drivers/staging/rtl8188eu/hal/odm_RTL8188E.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #include "odm_precomp.h"
  22
  23 static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
  24 {
  25         struct adapter *adapter = dm_odm->Adapter;
  26         u32     value32;
  27
  28         if (*(dm_odm->mp_mode) == 1) {
  29                 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
  30                 PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /*  disable HW AntDiv */
  31                 PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);  /*  1:CG, 0:CS */
  32                 return;
  33         }
  34         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n"));
  35
  36         /* MAC Setting */
  37         value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
  38         PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
  39         /* Pin Settings */
  40         PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0     antsel antselb by HW */
  41         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);       /* Reg864[10]=1'b0      antsel2 by HW */
  42         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);        /* Regb2c[22]=1'b0      disable CS/CG switch */
  43         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);        /* Regb2c[31]=1'b1      output at CG only */
  44         /* OFDM Settings */
  45         PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
  46         /* CCK Settings */
  47         PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */
  48         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
  49         ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
  50         PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);        /* antenna mapping table */
  51 }
  52
  53 static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
  54 {
  55         struct adapter *adapter = dm_odm->Adapter;
  56         u32     value32;
  57
  58         if (*(dm_odm->mp_mode) == 1) {
  59                 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
  60                 PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /*  disable HW AntDiv */
  61                 PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); /* Default RX   (0/1) */
  62                 return;
  63         }
  64         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n"));
  65
  66         /* MAC Setting */
  67         value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
  68         PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
  69         /* Pin Settings */
  70         PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0             antsel antselb by HW */
  71         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);       /* Reg864[10]=1'b0      antsel2 by HW */
  72         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0);        /* Regb2c[22]=1'b0      disable CS/CG switch */
  73         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);        /* Regb2c[31]=1'b1      output at CG only */
  74         /* OFDM Settings */
  75         PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
  76         /* CCK Settings */
  77         PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */
  78         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
  79         /* Tx Settings */
  80         PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0            from TX Reg */
  81         ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
  82
  83         /* antenna mapping table */
  84         if (!dm_odm->bIsMPChip) { /* testchip */
  85                 PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1);    /* Reg858[10:8]=3'b001 */
  86                 PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2);  /* Reg858[13:11]=3'b010 */
  87         } else { /* MPchip */
  88                 PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201);    /* Reg914=3'b010, Reg915=3'b001 */
  89         }
  90 }
  91
  92 static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
  93 {
  94         struct adapter *adapter = dm_odm->Adapter;
  95         u32     value32, i;
  96         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
  97         u32     AntCombination = 2;
  98
  99         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n"));
 100
 101         if (*(dm_odm->mp_mode) == 1) {
 102                 ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("dm_odm->AntDivType: %d\n", dm_odm->AntDivType));
 103                 return;
 104         }
 105
 106         for (i = 0; i < 6; i++) {
 107                 dm_fat_tbl->Bssid[i] = 0;
 108                 dm_fat_tbl->antSumRSSI[i] = 0;
 109                 dm_fat_tbl->antRSSIcnt[i] = 0;
 110                 dm_fat_tbl->antAveRSSI[i] = 0;
 111         }
 112         dm_fat_tbl->TrainIdx = 0;
 113         dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
 114
 115         /* MAC Setting */
 116         value32 = PHY_QueryBBReg(adapter, 0x4c, bMaskDWord);
 117         PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
 118         value32 = PHY_QueryBBReg(adapter,  0x7B4, bMaskDWord);
 119         PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
 120
 121         /* Match MAC ADDR */
 122         PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
 123         PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
 124
 125         PHY_SetBBReg(adapter, 0x870, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0            antsel antselb by HW */
 126         PHY_SetBBReg(adapter, 0x864, BIT10, 0); /* Reg864[10]=1'b0      antsel2 by HW */
 127         PHY_SetBBReg(adapter, 0xb2c, BIT22, 0); /* Regb2c[22]=1'b0      disable CS/CG switch */
 128         PHY_SetBBReg(adapter, 0xb2c, BIT31, 1); /* Regb2c[31]=1'b1      output at CG only */
 129         PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
 130
 131         /* antenna mapping table */
 132         if (AntCombination == 2) {
 133                 if (!dm_odm->bIsMPChip) { /* testchip */
 134                         PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 1);       /* Reg858[10:8]=3'b001 */
 135                         PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 2);     /* Reg858[13:11]=3'b010 */
 136                 } else { /* MPchip */
 137                         PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
 138                         PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
 139                 }
 140         } else if (AntCombination == 7) {
 141                 if (!dm_odm->bIsMPChip) { /* testchip */
 142                         PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 0);       /* Reg858[10:8]=3'b000 */
 143                         PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 1);     /* Reg858[13:11]=3'b001 */
 144                         PHY_SetBBReg(adapter, 0x878, BIT16, 0);
 145                         PHY_SetBBReg(adapter, 0x858, BIT15|BIT14, 2);   /* Reg878[0],Reg858[14:15])=3'b010 */
 146                         PHY_SetBBReg(adapter, 0x878, BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */
 147                         PHY_SetBBReg(adapter, 0x878, BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */
 148                         PHY_SetBBReg(adapter, 0x878, BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */
 149                         PHY_SetBBReg(adapter, 0x878, BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */
 150                         PHY_SetBBReg(adapter, 0x878, BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */
 151                 } else { /* MPchip */
 152                         PHY_SetBBReg(adapter, 0x914, bMaskByte0, 0);
 153                         PHY_SetBBReg(adapter, 0x914, bMaskByte1, 1);
 154                         PHY_SetBBReg(adapter, 0x914, bMaskByte2, 2);
 155                         PHY_SetBBReg(adapter, 0x914, bMaskByte3, 3);
 156                         PHY_SetBBReg(adapter, 0x918, bMaskByte0, 4);
 157                         PHY_SetBBReg(adapter, 0x918, bMaskByte1, 5);
 158                         PHY_SetBBReg(adapter, 0x918, bMaskByte2, 6);
 159                         PHY_SetBBReg(adapter, 0x918, bMaskByte3, 7);
 160                 }
 161         }
 162
 163         /* Default Ant Setting when no fast training */
 164         PHY_SetBBReg(adapter, 0x80c, BIT21, 1); /* Reg80c[21]=1'b1              from TX Info */
 165         PHY_SetBBReg(adapter, 0x864, BIT5|BIT4|BIT3, 0);        /* Default RX */
 166         PHY_SetBBReg(adapter, 0x864, BIT8|BIT7|BIT6, 1);        /* Optional RX */
 167
 168         /* Enter Traing state */
 169         PHY_SetBBReg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1));       /* Reg864[2:0]=3'd6     ant combination=reg864[2:0]+1 */
 170         PHY_SetBBReg(adapter, 0xc50, BIT7, 1);  /* RegC50[7]=1'b1               enable HW AntDiv */
 171 }
 172
 173 void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
 174 {
 175         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType));
 176         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false")));
 177
 178         if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
 179                 odm_RX_HWAntDivInit(dm_odm);
 180         else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 181                 odm_TRX_HWAntDivInit(dm_odm);
 182         else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
 183                 odm_FastAntTrainingInit(dm_odm);
 184 }
 185
 186 void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
 187 {
 188         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 189         struct adapter *adapter = dm_odm->Adapter;
 190         u32     DefaultAnt, OptionalAnt;
 191
 192         if (dm_fat_tbl->RxIdleAnt != Ant) {
 193                 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n"));
 194                 if (Ant == MAIN_ANT) {
 195                         DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
 196                         OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
 197                 } else {
 198                         DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
 199                         OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
 200                 }
 201
 202                 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
 203                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt);     /* Default RX */
 204                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt);            /* Optional RX */
 205                         PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, DefaultAnt);  /* Default TX */
 206                         PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT6|BIT7, DefaultAnt);      /* Resp Tx */
 207                 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
 208                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt);     /* Default RX */
 209                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt);            /* Optional RX */
 210                 }
 211         }
 212         dm_fat_tbl->RxIdleAnt = Ant;
 213         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
 214         pr_info("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 215 }
 216
 217 static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
 218 {
 219         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 220         u8      TargetAnt;
 221
 222         if (Ant == MAIN_ANT)
 223                 TargetAnt = MAIN_ANT_CG_TRX;
 224         else
 225                 TargetAnt = AUX_ANT_CG_TRX;
 226         dm_fat_tbl->antsel_a[MacId] = TargetAnt&BIT0;
 227         dm_fat_tbl->antsel_b[MacId] = (TargetAnt&BIT1)>>1;
 228         dm_fat_tbl->antsel_c[MacId] = (TargetAnt&BIT2)>>2;
 229
 230         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 231                      ("Tx from TxInfo, TargetAnt=%s\n",
 232                      (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
 233         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 234                      ("antsel_tr_mux=3'b%d%d%d\n",
 235                      dm_fat_tbl->antsel_c[MacId], dm_fat_tbl->antsel_b[MacId], dm_fat_tbl->antsel_a[MacId]));
 236 }
 237
 238 void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId)
 239 {
 240         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 241
 242         if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
 243                 SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]);
 244                 SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]);
 245                 SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]);
 246         }
 247 }
 248
 249 void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll)
 250 {
 251         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 252         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
 253                 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
 254                         dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
 255                         dm_fat_tbl->MainAnt_Cnt[MacId]++;
 256                 } else {
 257                         dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
 258                         dm_fat_tbl->AuxAnt_Cnt[MacId]++;
 259                 }
 260         } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
 261                 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
 262                         dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
 263                         dm_fat_tbl->MainAnt_Cnt[MacId]++;
 264                 } else {
 265                         dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
 266                         dm_fat_tbl->AuxAnt_Cnt[MacId]++;
 267                 }
 268         }
 269 }
 270
 271 static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
 272 {
 273         u32     i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI;
 274         u32     Main_RSSI, Aux_RSSI;
 275         u8      RxIdleAnt = 0, TargetAnt = 7;
 276         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 277         struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
 278         struct sta_info *pEntry;
 279
 280         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 281                 pEntry = dm_odm->pODM_StaInfo[i];
 282                 if (IS_STA_VALID(pEntry)) {
 283                         /* 2 Caculate RSSI per Antenna */
 284                         Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0;
 285                         Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
 286                         TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT;
 287                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 288                                      ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n",
 289                                      i, dm_fat_tbl->MainAnt_Sum[i],
 290                                      dm_fat_tbl->MainAnt_Cnt[i]));
 291                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 292                                      ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",
 293                                      i, dm_fat_tbl->AuxAnt_Sum[i], dm_fat_tbl->AuxAnt_Cnt[i]));
 294                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 295                                      ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n",
 296                                      i, Main_RSSI, Aux_RSSI));
 297                         /* 2 Select MaxRSSI for DIG */
 298                         LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI;
 299                         if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
 300                                 AntDivMaxRSSI = LocalMaxRSSI;
 301                         if (LocalMaxRSSI > MaxRSSI)
 302                                 MaxRSSI = LocalMaxRSSI;
 303
 304                         /* 2 Select RX Idle Antenna */
 305                         if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
 306                                 Main_RSSI = Aux_RSSI;
 307                         else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
 308                                 Aux_RSSI = Main_RSSI;
 309
 310                         LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI;
 311                         if (LocalMinRSSI < MinRSSI) {
 312                                 MinRSSI = LocalMinRSSI;
 313                                 RxIdleAnt = TargetAnt;
 314                         }
 315                         /* 2 Select TRX Antenna */
 316                         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 317                                 odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i);
 318                 }
 319                 dm_fat_tbl->MainAnt_Sum[i] = 0;
 320                 dm_fat_tbl->AuxAnt_Sum[i] = 0;
 321                 dm_fat_tbl->MainAnt_Cnt[i] = 0;
 322                 dm_fat_tbl->AuxAnt_Cnt[i] = 0;
 323         }
 324
 325         /* 2 Set RX Idle Antenna */
 326         ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
 327
 328         pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
 329         pDM_DigTable->RSSI_max = MaxRSSI;
 330 }
 331
 332 void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
 333 {
 334         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 335         struct adapter *adapter = dm_odm->Adapter;
 336
 337         if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
 338                 return;
 339         if (!dm_odm->bLinked) {
 340                 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n"));
 341                 if (dm_fat_tbl->bBecomeLinked) {
 342                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
 343                         PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);      /* RegC50[7]=1'b1               enable HW AntDiv */
 344                         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0); /* Enable CCK AntDiv */
 345                         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 346                                 PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0            from TX Reg */
 347                         dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
 348                 }
 349                 return;
 350         } else {
 351                 if (!dm_fat_tbl->bBecomeLinked) {
 352                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
 353                         /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
 354                         PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 1);      /* RegC50[7]=1'b1               enable HW AntDiv */
 355                         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1); /* Enable CCK AntDiv */
 356                         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 357                                 PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* Reg80c[21]=1'b1            from TX Info */
 358                         dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
 359                 }
 360         }
 361         if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
 362                 odm_HWAntDiv(dm_odm);
 363 }
 364
 365 /* 3============================================================ */
 366 /* 3 Dynamic Primary CCA */
 367 /* 3============================================================ */
 368
 369 void odm_PrimaryCCA_Init(struct odm_dm_struct *dm_odm)
 370 {
 371         struct dyn_primary_cca *PrimaryCCA = &(dm_odm->DM_PriCCA);
 372
 373         PrimaryCCA->DupRTS_flag = 0;
 374         PrimaryCCA->intf_flag = 0;
 375         PrimaryCCA->intf_type = 0;
 376         PrimaryCCA->Monitor_flag = 0;
 377         PrimaryCCA->PriCCA_flag = 0;
 378 }