drivers/staging/rtl8188eu/hal/odm_RTL8188E.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #include "odm_precomp.h"
  22
  23 void ODM_DIG_LowerBound_88E(struct odm_dm_struct *dm_odm)
  24 {
  25         struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
  26
  27         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
  28                 pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max;
  29                 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
  30                              ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d\n", pDM_DigTable->AntDiv_RSSI_max));
  31         }
  32         /* If only one Entry connected */
  33 }
  34
  35 static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
  36 {
  37         struct adapter *adapter = dm_odm->Adapter;
  38         u32     value32;
  39
  40         if (*(dm_odm->mp_mode) == 1) {
  41                 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
  42                 PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /*  disable HW AntDiv */
  43                 PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);  /*  1:CG, 0:CS */
  44                 return;
  45         }
  46         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n"));
  47
  48         /* MAC Setting */
  49         value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
  50         PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
  51         /* Pin Settings */
  52         PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0     antsel antselb by HW */
  53         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);       /* Reg864[10]=1'b0      antsel2 by HW */
  54         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);        /* Regb2c[22]=1'b0      disable CS/CG switch */
  55         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);        /* Regb2c[31]=1'b1      output at CG only */
  56         /* OFDM Settings */
  57         PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
  58         /* CCK Settings */
  59         PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */
  60         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
  61         ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
  62         PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);        /* antenna mapping table */
  63 }
  64
  65 static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
  66 {
  67         struct adapter *adapter = dm_odm->Adapter;
  68         u32     value32;
  69
  70         if (*(dm_odm->mp_mode) == 1) {
  71                 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
  72                 PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /*  disable HW AntDiv */
  73                 PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); /* Default RX   (0/1) */
  74                 return;
  75         }
  76         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n"));
  77
  78         /* MAC Setting */
  79         value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
  80         PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
  81         /* Pin Settings */
  82         PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0             antsel antselb by HW */
  83         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);       /* Reg864[10]=1'b0      antsel2 by HW */
  84         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0);        /* Regb2c[22]=1'b0      disable CS/CG switch */
  85         PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);        /* Regb2c[31]=1'b1      output at CG only */
  86         /* OFDM Settings */
  87         PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
  88         /* CCK Settings */
  89         PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */
  90         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
  91         /* Tx Settings */
  92         PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0            from TX Reg */
  93         ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
  94
  95         /* antenna mapping table */
  96         if (!dm_odm->bIsMPChip) { /* testchip */
  97                 PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1);    /* Reg858[10:8]=3'b001 */
  98                 PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2);  /* Reg858[13:11]=3'b010 */
  99         } else { /* MPchip */
 100                 PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201);    /* Reg914=3'b010, Reg915=3'b001 */
 101         }
 102 }
 103
 104 static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
 105 {
 106         struct adapter *adapter = dm_odm->Adapter;
 107         u32     value32, i;
 108         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 109         u32     AntCombination = 2;
 110
 111         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n"));
 112
 113         if (*(dm_odm->mp_mode) == 1) {
 114                 ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("dm_odm->AntDivType: %d\n", dm_odm->AntDivType));
 115                 return;
 116         }
 117
 118         for (i = 0; i < 6; i++) {
 119                 dm_fat_tbl->Bssid[i] = 0;
 120                 dm_fat_tbl->antSumRSSI[i] = 0;
 121                 dm_fat_tbl->antRSSIcnt[i] = 0;
 122                 dm_fat_tbl->antAveRSSI[i] = 0;
 123         }
 124         dm_fat_tbl->TrainIdx = 0;
 125         dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
 126
 127         /* MAC Setting */
 128         value32 = PHY_QueryBBReg(adapter, 0x4c, bMaskDWord);
 129         PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
 130         value32 = PHY_QueryBBReg(adapter,  0x7B4, bMaskDWord);
 131         PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
 132
 133         /* Match MAC ADDR */
 134         PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
 135         PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
 136
 137         PHY_SetBBReg(adapter, 0x870, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0            antsel antselb by HW */
 138         PHY_SetBBReg(adapter, 0x864, BIT10, 0); /* Reg864[10]=1'b0      antsel2 by HW */
 139         PHY_SetBBReg(adapter, 0xb2c, BIT22, 0); /* Regb2c[22]=1'b0      disable CS/CG switch */
 140         PHY_SetBBReg(adapter, 0xb2c, BIT31, 1); /* Regb2c[31]=1'b1      output at CG only */
 141         PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
 142
 143         /* antenna mapping table */
 144         if (AntCombination == 2) {
 145                 if (!dm_odm->bIsMPChip) { /* testchip */
 146                         PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 1);       /* Reg858[10:8]=3'b001 */
 147                         PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 2);     /* Reg858[13:11]=3'b010 */
 148                 } else { /* MPchip */
 149                         PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
 150                         PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
 151                 }
 152         } else if (AntCombination == 7) {
 153                 if (!dm_odm->bIsMPChip) { /* testchip */
 154                         PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 0);       /* Reg858[10:8]=3'b000 */
 155                         PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 1);     /* Reg858[13:11]=3'b001 */
 156                         PHY_SetBBReg(adapter, 0x878, BIT16, 0);
 157                         PHY_SetBBReg(adapter, 0x858, BIT15|BIT14, 2);   /* Reg878[0],Reg858[14:15])=3'b010 */
 158                         PHY_SetBBReg(adapter, 0x878, BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */
 159                         PHY_SetBBReg(adapter, 0x878, BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */
 160                         PHY_SetBBReg(adapter, 0x878, BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */
 161                         PHY_SetBBReg(adapter, 0x878, BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */
 162                         PHY_SetBBReg(adapter, 0x878, BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */
 163                 } else { /* MPchip */
 164                         PHY_SetBBReg(adapter, 0x914, bMaskByte0, 0);
 165                         PHY_SetBBReg(adapter, 0x914, bMaskByte1, 1);
 166                         PHY_SetBBReg(adapter, 0x914, bMaskByte2, 2);
 167                         PHY_SetBBReg(adapter, 0x914, bMaskByte3, 3);
 168                         PHY_SetBBReg(adapter, 0x918, bMaskByte0, 4);
 169                         PHY_SetBBReg(adapter, 0x918, bMaskByte1, 5);
 170                         PHY_SetBBReg(adapter, 0x918, bMaskByte2, 6);
 171                         PHY_SetBBReg(adapter, 0x918, bMaskByte3, 7);
 172                 }
 173         }
 174
 175         /* Default Ant Setting when no fast training */
 176         PHY_SetBBReg(adapter, 0x80c, BIT21, 1); /* Reg80c[21]=1'b1              from TX Info */
 177         PHY_SetBBReg(adapter, 0x864, BIT5|BIT4|BIT3, 0);        /* Default RX */
 178         PHY_SetBBReg(adapter, 0x864, BIT8|BIT7|BIT6, 1);        /* Optional RX */
 179
 180         /* Enter Traing state */
 181         PHY_SetBBReg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1));       /* Reg864[2:0]=3'd6     ant combination=reg864[2:0]+1 */
 182         PHY_SetBBReg(adapter, 0xc50, BIT7, 1);  /* RegC50[7]=1'b1               enable HW AntDiv */
 183 }
 184
 185 void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
 186 {
 187         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType));
 188         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false")));
 189
 190         if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
 191                 odm_RX_HWAntDivInit(dm_odm);
 192         else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 193                 odm_TRX_HWAntDivInit(dm_odm);
 194         else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
 195                 odm_FastAntTrainingInit(dm_odm);
 196 }
 197
 198 void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
 199 {
 200         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 201         struct adapter *adapter = dm_odm->Adapter;
 202         u32     DefaultAnt, OptionalAnt;
 203
 204         if (dm_fat_tbl->RxIdleAnt != Ant) {
 205                 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n"));
 206                 if (Ant == MAIN_ANT) {
 207                         DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
 208                         OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
 209                 } else {
 210                         DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
 211                         OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
 212                 }
 213
 214                 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
 215                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt);     /* Default RX */
 216                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt);            /* Optional RX */
 217                         PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, DefaultAnt);  /* Default TX */
 218                         PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT6|BIT7, DefaultAnt);      /* Resp Tx */
 219                 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
 220                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt);     /* Default RX */
 221                         PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt);            /* Optional RX */
 222                 }
 223         }
 224         dm_fat_tbl->RxIdleAnt = Ant;
 225         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
 226         pr_info("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 227 }
 228
 229 static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
 230 {
 231         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 232         u8      TargetAnt;
 233
 234         if (Ant == MAIN_ANT)
 235                 TargetAnt = MAIN_ANT_CG_TRX;
 236         else
 237                 TargetAnt = AUX_ANT_CG_TRX;
 238         dm_fat_tbl->antsel_a[MacId] = TargetAnt&BIT0;
 239         dm_fat_tbl->antsel_b[MacId] = (TargetAnt&BIT1)>>1;
 240         dm_fat_tbl->antsel_c[MacId] = (TargetAnt&BIT2)>>2;
 241
 242         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 243                      ("Tx from TxInfo, TargetAnt=%s\n",
 244                      (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
 245         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 246                      ("antsel_tr_mux=3'b%d%d%d\n",
 247                      dm_fat_tbl->antsel_c[MacId], dm_fat_tbl->antsel_b[MacId], dm_fat_tbl->antsel_a[MacId]));
 248 }
 249
 250 void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId)
 251 {
 252         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 253
 254         if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
 255                 SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]);
 256                 SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]);
 257                 SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]);
 258         }
 259 }
 260
 261 void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll)
 262 {
 263         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 264         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
 265                 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
 266                         dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
 267                         dm_fat_tbl->MainAnt_Cnt[MacId]++;
 268                 } else {
 269                         dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
 270                         dm_fat_tbl->AuxAnt_Cnt[MacId]++;
 271                 }
 272         } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
 273                 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
 274                         dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
 275                         dm_fat_tbl->MainAnt_Cnt[MacId]++;
 276                 } else {
 277                         dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
 278                         dm_fat_tbl->AuxAnt_Cnt[MacId]++;
 279                 }
 280         }
 281 }
 282
 283 static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
 284 {
 285         u32     i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI;
 286         u32     Main_RSSI, Aux_RSSI;
 287         u8      RxIdleAnt = 0, TargetAnt = 7;
 288         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 289         struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
 290         struct sta_info *pEntry;
 291
 292         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 293                 pEntry = dm_odm->pODM_StaInfo[i];
 294                 if (IS_STA_VALID(pEntry)) {
 295                         /* 2 Caculate RSSI per Antenna */
 296                         Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0;
 297                         Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
 298                         TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT;
 299                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 300                                      ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n",
 301                                      i, dm_fat_tbl->MainAnt_Sum[i],
 302                                      dm_fat_tbl->MainAnt_Cnt[i]));
 303                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 304                                      ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",
 305                                      i, dm_fat_tbl->AuxAnt_Sum[i], dm_fat_tbl->AuxAnt_Cnt[i]));
 306                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 307                                      ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n",
 308                                      i, Main_RSSI, Aux_RSSI));
 309                         /* 2 Select MaxRSSI for DIG */
 310                         LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI;
 311                         if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
 312                                 AntDivMaxRSSI = LocalMaxRSSI;
 313                         if (LocalMaxRSSI > MaxRSSI)
 314                                 MaxRSSI = LocalMaxRSSI;
 315
 316                         /* 2 Select RX Idle Antenna */
 317                         if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
 318                                 Main_RSSI = Aux_RSSI;
 319                         else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
 320                                 Aux_RSSI = Main_RSSI;
 321
 322                         LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI;
 323                         if (LocalMinRSSI < MinRSSI) {
 324                                 MinRSSI = LocalMinRSSI;
 325                                 RxIdleAnt = TargetAnt;
 326                         }
 327                         /* 2 Select TRX Antenna */
 328                         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 329                                 odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i);
 330                 }
 331                 dm_fat_tbl->MainAnt_Sum[i] = 0;
 332                 dm_fat_tbl->AuxAnt_Sum[i] = 0;
 333                 dm_fat_tbl->MainAnt_Cnt[i] = 0;
 334                 dm_fat_tbl->AuxAnt_Cnt[i] = 0;
 335         }
 336
 337         /* 2 Set RX Idle Antenna */
 338         ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
 339
 340         pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
 341         pDM_DigTable->RSSI_max = MaxRSSI;
 342 }
 343
 344 void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
 345 {
 346         struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
 347         struct adapter *adapter = dm_odm->Adapter;
 348
 349         if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
 350                 return;
 351         if (!dm_odm->bLinked) {
 352                 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n"));
 353                 if (dm_fat_tbl->bBecomeLinked) {
 354                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
 355                         PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);      /* RegC50[7]=1'b1               enable HW AntDiv */
 356                         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0); /* Enable CCK AntDiv */
 357                         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 358                                 PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0            from TX Reg */
 359                         dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
 360                 }
 361                 return;
 362         } else {
 363                 if (!dm_fat_tbl->bBecomeLinked) {
 364                         ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
 365                         /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
 366                         PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 1);      /* RegC50[7]=1'b1               enable HW AntDiv */
 367                         PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1); /* Enable CCK AntDiv */
 368                         if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
 369                                 PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* Reg80c[21]=1'b1            from TX Info */
 370                         dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
 371                 }
 372         }
 373         if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
 374                 odm_HWAntDiv(dm_odm);
 375 }
 376
 377 /* 3============================================================ */
 378 /* 3 Dynamic Primary CCA */
 379 /* 3============================================================ */
 380
 381 void odm_PrimaryCCA_Init(struct odm_dm_struct *dm_odm)
 382 {
 383         struct dyn_primary_cca *PrimaryCCA = &(dm_odm->DM_PriCCA);
 384
 385         PrimaryCCA->DupRTS_flag = 0;
 386         PrimaryCCA->intf_flag = 0;
 387         PrimaryCCA->intf_type = 0;
 388         PrimaryCCA->Monitor_flag = 0;
 389         PrimaryCCA->PriCCA_flag = 0;
 390 }
 391
 392 bool ODM_DynamicPrimaryCCA_DupRTS(struct odm_dm_struct *dm_odm)
 393 {
 394         struct dyn_primary_cca *PrimaryCCA = &(dm_odm->DM_PriCCA);
 395
 396         return  PrimaryCCA->DupRTS_flag;
 397 }
 398
 399 void odm_DynamicPrimaryCCA(struct odm_dm_struct *dm_odm)
 400 {
 401         return;
 402 }