1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "odm_precomp.h"
23 void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
24 u32 Data, enum ODM_RF_RADIO_PATH RF_PATH,
29 } else if (Addr == 0xfd) {
31 } else if (Addr == 0xfc) {
33 } else if (Addr == 0xfb) {
35 } else if (Addr == 0xfa) {
37 } else if (Addr == 0xf9) {
40 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
41 /* Add 1us delay between BB/RF register setting. */
46 void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
48 u32 content = 0x1000; /* RF_Content: radioa_txt */
49 u32 maskforPhySet = (u32)(content&0xE000);
51 odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
52 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
55 void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
57 u32 content = 0x1001; /* RF_Content: radiob_txt */
58 u32 maskforPhySet = (u32)(content&0xE000);
60 odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
62 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
65 void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)
67 ODM_Write1Byte(pDM_Odm, Addr, Data);
68 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
71 void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
73 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
74 /* Add 1us delay between BB/RF register setting. */
77 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
78 ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n",
82 void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
83 u32 Bitmask, u32 Data)
87 } else if (Addr == 0xfd) {
89 } else if (Addr == 0xfc) {
91 } else if (Addr == 0xfb) {
93 } else if (Addr == 0xfa) {
95 } else if (Addr == 0xf9) {
98 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
99 ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n",
100 Addr, Bitmask, Data));
101 storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
105 void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
109 } else if (Addr == 0xfd) {
111 } else if (Addr == 0xfc) {
113 } else if (Addr == 0xfb) {
115 } else if (Addr == 0xfa) {
117 } else if (Addr == 0xf9) {
121 pDM_Odm->RFCalibrateInfo.RegA24 = Data;
122 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
124 /* Add 1us delay between BB/RF register setting. */
126 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
127 ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n",