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staging: rtl8188eu: remove PWR_BASEADDR_* macro definitions and "base" member of...
[karo-tx-linux.git] / drivers / staging / rtl8188eu / hal / pwrseqcmd.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  ******************************************************************************/
19
20 #include <pwrseqcmd.h>
21 #include <usb_ops_linux.h>
22
23 /* This routine deals with the Power Configuration CMDs parsing
24  * for RTL8723/RTL8188E Series IC.
25  */
26 u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers,
27                             struct wl_pwr_cfg pwrseqcmd[])
28 {
29         struct wl_pwr_cfg pwrcfgcmd = {0};
30         u8 poll_bit = false;
31         u32 aryidx = 0;
32         u8 value = 0;
33         u32 offset = 0;
34         u32 poll_count = 0; /*  polling autoload done. */
35         u32 max_poll_count = 5000;
36
37         do {
38                 pwrcfgcmd = pwrseqcmd[aryidx];
39
40                 RT_TRACE(_module_hal_init_c_, _drv_info_,
41                          ("rtl88eu_pwrseqcmdparsing: offset(%#x) cut_msk(%#x)"
42                           " cmd(%#x)"
43                           "msk(%#x) value(%#x)\n",
44                          GET_PWR_CFG_OFFSET(pwrcfgcmd),
45                          GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
46                          GET_PWR_CFG_CMD(pwrcfgcmd),
47                          GET_PWR_CFG_MASK(pwrcfgcmd),
48                          GET_PWR_CFG_VALUE(pwrcfgcmd)));
49
50                 /* Only Handle the command whose CUT is matched */
51                 if (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) {
52                         switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
53                         case PWR_CMD_READ:
54                                 RT_TRACE(_module_hal_init_c_, _drv_info_,
55                                          ("rtl88eu_pwrseqcmdparsing: PWR_CMD_READ\n"));
56                                 break;
57                         case PWR_CMD_WRITE:
58                                 RT_TRACE(_module_hal_init_c_, _drv_info_,
59                                          ("rtl88eu_pwrseqcmdparsing: PWR_CMD_WRITE\n"));
60                                 offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
61
62                                 /*  Read the value from system register */
63                                 value = usb_read8(padapter, offset);
64
65                                 value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
66                                 value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) &
67                                           GET_PWR_CFG_MASK(pwrcfgcmd));
68
69                                 /*  Write the value back to system register */
70                                 usb_write8(padapter, offset, value);
71                                 break;
72                         case PWR_CMD_POLLING:
73                                 RT_TRACE(_module_hal_init_c_, _drv_info_,
74                                          ("rtl88eu_pwrseqcmdparsing: PWR_CMD_POLLING\n"));
75
76                                 poll_bit = false;
77                                 offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
78                                 do {
79                                         value = usb_read8(padapter, offset);
80                                         value &= GET_PWR_CFG_MASK(pwrcfgcmd);
81
82                                         if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) &
83                                                       GET_PWR_CFG_MASK(pwrcfgcmd)))
84                                                 poll_bit = true;
85                                         else
86                                                 udelay(10);
87
88                                         if (poll_count++ > max_poll_count) {
89                                                 DBG_88E("Fail to polling Offset[%#x]\n", offset);
90                                                 return false;
91                                         }
92                                 } while (!poll_bit);
93                                 break;
94                         case PWR_CMD_DELAY:
95                                 RT_TRACE(_module_hal_init_c_, _drv_info_,
96                                          ("rtl88eu_pwrseqcmdparsing: PWR_CMD_DELAY\n"));
97                                 if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
98                                         udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));
99                                 else
100                                         udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
101                                 break;
102                         case PWR_CMD_END:
103                                 /* When this command is parsed, end the process */
104                                 RT_TRACE(_module_hal_init_c_, _drv_info_,
105                                          ("rtl88eu_pwrseqcmdparsing: PWR_CMD_END\n"));
106                                 return true;
107                         default:
108                                 RT_TRACE(_module_hal_init_c_, _drv_err_,
109                                          ("rtl88eu_pwrseqcmdparsing: Unknown CMD!!\n"));
110                                 break;
111                         }
112                 }
113
114                 aryidx++;/* Add Array Index */
115         } while (1);
116         return true;
117 }