1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #define _RTL8188E_PHYCFG_C_
22 #include <osdep_service.h>
23 #include <drv_types.h>
25 #include <rtl8188e_hal.h>
27 /*---------------------------Define Local Constant---------------------------*/
28 /* Channel switch:The size of command tables for switch channel*/
29 #define MAX_PRECMD_CNT 16
30 #define MAX_RFDEPENDCMD_CNT 16
31 #define MAX_POSTCMD_CNT 16
33 #define MAX_DOZE_WAITING_TIMES_9x 64
35 /*---------------------------Define Local Constant---------------------------*/
38 /*------------------------Define global variable-----------------------------*/
40 /*------------------------Define local variable------------------------------*/
43 /*--------------------Define export function prototype-----------------------*/
44 /* Please refer to header file */
45 /*--------------------Define export function prototype-----------------------*/
47 /*----------------------------Function Body----------------------------------*/
49 /* 1. BB register R/W API */
53 * Function: phy_CalculateBitShift
55 * OverView: Get shifted position of the BitMask
61 * Return: u32 Return the shift bit bit position of the mask
63 static u32 phy_CalculateBitShift(u32 BitMask)
67 for (i = 0; i <= 31; i++) {
68 if (((BitMask>>i) & 0x1) == 1)
75 * Function: PHY_QueryBBReg
77 * OverView: Read "sepcific bits" from BB register
80 * struct adapter *Adapter,
81 * u32 RegAddr, The target address to be readback
82 * u32 BitMask The target bit position in the target address
85 * Return: u32 Data The readback register value
86 * Note: This function is equal to "GetRegSetting" in PHY programming guide
89 rtl8188e_PHY_QueryBBReg(
90 struct adapter *Adapter,
95 u32 ReturnValue = 0, OriginalValue, BitShift;
97 OriginalValue = rtw_read32(Adapter, RegAddr);
98 BitShift = phy_CalculateBitShift(BitMask);
99 ReturnValue = (OriginalValue & BitMask) >> BitShift;
105 * Function: PHY_SetBBReg
107 * OverView: Write "Specific bits" to BB register (page 8~)
110 * struct adapter *Adapter,
111 * u32 RegAddr, The target address to be modified
112 * u32 BitMask The target bit position in the target address
114 * u32 Data The new register value in the target bit position
115 * of the target address
119 * Note: This function is equal to "PutRegSetting" in PHY programming guide
122 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
124 u32 OriginalValue, BitShift;
126 if (BitMask != bMaskDWord) { /* if not "double word" write */
127 OriginalValue = rtw_read32(Adapter, RegAddr);
128 BitShift = phy_CalculateBitShift(BitMask);
129 Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
132 rtw_write32(Adapter, RegAddr, Data);
137 /* 2. RF register R/W API */
140 * Function: phy_RFSerialRead
142 * OverView: Read regster from RF chips
145 * struct adapter *Adapter,
146 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
147 * u32 Offset, The target address to be read
150 * Return: u32 reback value
151 * Note: Threre are three types of serial operations:
152 * 1. Software serial write
153 * 2. Hardware LSSI-Low Speed Serial Interface
154 * 3. Hardware HSSI-High speed
155 * serial write. Driver need to implement (1) and (2).
156 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
160 struct adapter *Adapter,
161 enum rf_radio_path eRFPath,
166 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
167 struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
169 u32 tmplong, tmplong2;
172 /* Make sure RF register offset is correct */
177 /* Switch page for 8256 RF IC */
181 /* For 92S LSSI Read RFLSSIRead */
182 /* For RF A/B write 0x824/82c(does not work in the future) */
183 /* We must use 0x824 for RF A and B to execute read trigger */
184 tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
185 if (eRFPath == RF_PATH_A)
188 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
190 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
192 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
193 udelay(10);/* PlatformStallExecution(10); */
195 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
196 udelay(100);/* PlatformStallExecution(100); */
198 udelay(10);/* PlatformStallExecution(10); */
200 if (eRFPath == RF_PATH_A)
201 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
202 else if (eRFPath == RF_PATH_B)
203 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
205 if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
206 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
207 } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
208 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
214 * Function: phy_RFSerialWrite
216 * OverView: Write data to RF register (page 8~)
219 * struct adapter *Adapter,
220 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
221 * u32 Offset, The target address to be read
222 * u32 Data The new register Data in the target bit position
223 * of the target to be read
227 * Note: Threre are three types of serial operations:
228 * 1. Software serial write
229 * 2. Hardware LSSI-Low Speed Serial Interface
230 * 3. Hardware HSSI-High speed
231 * serial write. Driver need to implement (1) and (2).
232 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
234 * Note: For RF8256 only
235 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
236 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
237 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
238 * programming guide" for more details.
239 * Thus, we define a sub-finction for RTL8526 register address conversion
240 * ===========================================================
241 * Register Mode RegCTL[1] RegCTL[0] Note
242 * (Reg00[12]) (Reg00[10])
243 * ===========================================================
244 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
245 * ------------------------------------------------------------------
246 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
247 * ------------------------------------------------------------------
248 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
249 * ------------------------------------------------------------------
251 * 2008/09/02 MH Add 92S RF definition
258 struct adapter *Adapter,
259 enum rf_radio_path eRFPath,
265 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
266 struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
270 /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */
275 /* Switch page for 8256 RF IC */
280 /* Put write addr in [5:0] and write data in [31:16] */
282 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */
285 /* Write Operation */
287 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
291 * Function: PHY_QueryRFReg
293 * OverView: Query "Specific bits" to RF register (page 8~)
296 * struct adapter *Adapter,
297 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
298 * u32 RegAddr, The target address to be read
299 * u32 BitMask The target bit position in the target address
303 * Return: u32 Readback value
304 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
306 u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, enum rf_radio_path eRFPath,
307 u32 RegAddr, u32 BitMask)
309 u32 Original_Value, Readback_Value, BitShift;
311 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
313 BitShift = phy_CalculateBitShift(BitMask);
314 Readback_Value = (Original_Value & BitMask) >> BitShift;
315 return Readback_Value;
319 * Function: PHY_SetRFReg
321 * OverView: Write "Specific bits" to RF register (page 8~)
324 * struct adapter *Adapter,
325 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
326 * u32 RegAddr, The target address to be modified
327 * u32 BitMask The target bit position in the target address
329 * u32 Data The new register Data in the target bit position
330 * of the target address
334 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
337 rtl8188e_PHY_SetRFReg(
338 struct adapter *Adapter,
339 enum rf_radio_path eRFPath,
345 u32 Original_Value, BitShift;
347 /* RF data is 12 bits only */
348 if (BitMask != bRFRegOffsetMask) {
349 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
350 BitShift = phy_CalculateBitShift(BitMask);
351 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
354 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
358 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
361 /*-----------------------------------------------------------------------------
362 * Function: PHY_MACConfig8192C
364 * Overview: Condig MAC by header file or parameter file.
374 * 08/12/2008 MHC Create Version 0.
376 *---------------------------------------------------------------------------*/
377 s32 PHY_MACConfig8188E(struct adapter *Adapter)
379 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
380 int rtStatus = _SUCCESS;
385 if (HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
388 /* 2010.07.13 AMPDU aggregation number B */
389 rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
395 * Function: phy_InitBBRFRegisterDefinition
397 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
400 * struct adapter *Adapter,
404 * Note: The initialization value is constant and it should never be changes
407 phy_InitBBRFRegisterDefinition(
408 struct adapter *Adapter
411 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
413 /* RF Interface Sowrtware Control */
414 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
415 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
416 pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 LSBs if read 32-bit from 0x874 */
417 pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
419 /* RF Interface Readback Value */
420 pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */
421 pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
422 pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 LSBs if read 32-bit from 0x8E4 */
423 pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
425 /* RF Interface Output (and Enable) */
426 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
427 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
429 /* RF Interface (Output and) Enable */
430 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
431 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
433 /* Addr of LSSI. Wirte RF register by driver */
434 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
435 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
438 pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */
439 pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
440 pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
441 pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
443 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
444 pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
445 pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
446 pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
447 pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
449 /* Tranceiver A~D HSSI Parameter-1 */
450 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */
451 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; /* wire control parameter1 */
453 /* Tranceiver A~D HSSI Parameter-2 */
454 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
455 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
457 /* RF switch Control */
458 pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */
459 pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
460 pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
461 pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
464 pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
465 pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
466 pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
467 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
470 pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
471 pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
472 pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
473 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
475 /* RX AFE control 1 */
476 pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
477 pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
478 pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
479 pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
481 /* RX AFE control 1 */
482 pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
483 pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
484 pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
485 pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
487 /* Tx AFE control 1 */
488 pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
489 pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
490 pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
491 pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
493 /* Tx AFE control 2 */
494 pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
495 pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
496 pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
497 pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
499 /* Tranceiver LSSI Readback SI mode */
500 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
501 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
502 pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
503 pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
505 /* Tranceiver LSSI Readback PI mode */
506 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
507 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
510 void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
512 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
514 if (RegAddr == rTxAGC_A_Rate18_06)
515 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
516 if (RegAddr == rTxAGC_A_Rate54_24)
517 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
518 if (RegAddr == rTxAGC_A_CCK1_Mcs32)
519 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
520 if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
521 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
522 if (RegAddr == rTxAGC_A_Mcs03_Mcs00)
523 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
524 if (RegAddr == rTxAGC_A_Mcs07_Mcs04)
525 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
526 if (RegAddr == rTxAGC_A_Mcs11_Mcs08)
527 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
528 if (RegAddr == rTxAGC_A_Mcs15_Mcs12) {
529 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
530 if (pHalData->rf_type == RF_1T1R)
531 pHalData->pwrGroupCnt++;
533 if (RegAddr == rTxAGC_B_Rate18_06)
534 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
535 if (RegAddr == rTxAGC_B_Rate54_24)
536 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
537 if (RegAddr == rTxAGC_B_CCK1_55_Mcs32)
538 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
539 if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
540 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
541 if (RegAddr == rTxAGC_B_Mcs03_Mcs00)
542 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
543 if (RegAddr == rTxAGC_B_Mcs07_Mcs04)
544 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
545 if (RegAddr == rTxAGC_B_Mcs11_Mcs08)
546 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
547 if (RegAddr == rTxAGC_B_Mcs15_Mcs12) {
548 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
549 if (pHalData->rf_type != RF_1T1R)
550 pHalData->pwrGroupCnt++;
554 static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter)
556 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
557 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
558 int rtStatus = _SUCCESS;
561 /* 1. Read PHY_REG.TXT BB INIT!! */
562 /* We will separate as 88C / 92C according to chip version */
564 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
566 if (rtStatus != _SUCCESS)
567 goto phy_BB8190_Config_ParaFile_Fail;
569 /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
570 if (!pEEPROM->bautoload_fail_flag) {
571 pHalData->pwrGroupCnt = 0;
573 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
577 if (rtStatus != _SUCCESS)
578 goto phy_BB8190_Config_ParaFile_Fail;
580 /* 3. BB AGC table Initialization */
581 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
584 if (rtStatus != _SUCCESS)
585 goto phy_BB8190_Config_ParaFile_Fail;
587 phy_BB8190_Config_ParaFile_Fail:
594 struct adapter *Adapter
597 int rtStatus = _SUCCESS;
598 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
602 phy_InitBBRFRegisterDefinition(Adapter);
605 /* Enable BB and RF */
606 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
607 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
609 /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
611 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
613 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
615 /* Config BB and AGC */
616 rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
618 /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
619 CrystalCap = pHalData->CrystalCap & 0x3F;
620 PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
625 int PHY_RFConfig8188E(struct adapter *Adapter)
627 int rtStatus = _SUCCESS;
630 rtStatus = PHY_RF6052_Config8188E(Adapter);
634 static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
635 u8 *ofdmPowerLevel, u8 *BW20PowerLevel,
638 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
639 u8 index = (channel - 1);
640 u8 TxCount = 0, path_nums;
642 if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R == pHalData->rf_type))
647 for (TxCount = 0; TxCount < path_nums; TxCount++) {
648 if (TxCount == RF_PATH_A) {
650 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
652 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
653 pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A];
655 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
656 pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];
658 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
659 } else if (TxCount == RF_PATH_B) {
661 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
663 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
664 pHalData->BW20_24G_Diff[RF_PATH_A][index]+
665 pHalData->BW20_24G_Diff[TxCount][index];
667 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
668 pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]+
669 pHalData->BW20_24G_Diff[TxCount][index];
671 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
672 } else if (TxCount == RF_PATH_C) {
674 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
676 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
677 pHalData->BW20_24G_Diff[RF_PATH_A][index]+
678 pHalData->BW20_24G_Diff[RF_PATH_B][index]+
679 pHalData->BW20_24G_Diff[TxCount][index];
681 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
682 pHalData->BW20_24G_Diff[RF_PATH_A][index]+
683 pHalData->BW20_24G_Diff[RF_PATH_B][index]+
684 pHalData->BW20_24G_Diff[TxCount][index];
686 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
687 } else if (TxCount == RF_PATH_D) {
689 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
691 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
692 pHalData->BW20_24G_Diff[RF_PATH_A][index]+
693 pHalData->BW20_24G_Diff[RF_PATH_B][index]+
694 pHalData->BW20_24G_Diff[RF_PATH_C][index]+
695 pHalData->BW20_24G_Diff[TxCount][index];
698 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
699 pHalData->BW20_24G_Diff[RF_PATH_A][index]+
700 pHalData->BW20_24G_Diff[RF_PATH_B][index]+
701 pHalData->BW20_24G_Diff[RF_PATH_C][index]+
702 pHalData->BW20_24G_Diff[TxCount][index];
705 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
710 static void phy_PowerIndexCheck88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
711 u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel)
713 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
715 pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
716 pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
717 pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
718 pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
721 /*-----------------------------------------------------------------------------
722 * Function: SetTxPowerLevel8190()
724 * Overview: This function is export to "HalCommon" moudule
725 * We must consider RF path later!!!!!!!
727 * Input: struct adapter *Adapter
733 * 2008/11/04 MHC We remove EEPROM_93C56.
734 * We need to move CCX relative code to independet file.
735 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
737 *---------------------------------------------------------------------------*/
739 PHY_SetTxPowerLevel8188E(
740 struct adapter *Adapter,
744 u8 cckPowerLevel[MAX_TX_COUNT] = {0};
745 u8 ofdmPowerLevel[MAX_TX_COUNT] = {0};/* [0]:RF-A, [1]:RF-B */
746 u8 BW20PowerLevel[MAX_TX_COUNT] = {0};
747 u8 BW40PowerLevel[MAX_TX_COUNT] = {0};
749 getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
751 phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
753 rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
754 rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel);
757 /*-----------------------------------------------------------------------------
758 * Function: PHY_SetBWModeCallback8192C()
760 * Overview: Timer callback function for SetSetBWMode
762 * Input: PRT_TIMER pTimer
768 * Note: (1) We do not take j mode into consideration now
769 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
771 *---------------------------------------------------------------------------*/
774 struct adapter *Adapter
777 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
781 if (pHalData->rf_chip == RF_PSEUDO_11N)
784 /* There is no 40MHz mode in RF_8225. */
785 if (pHalData->rf_chip == RF_8225)
788 if (Adapter->bDriverStopped)
792 /* 3<1>Set MAC register */
795 regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
796 regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
798 switch (pHalData->CurrentChannelBW) {
799 case HT_CHANNEL_WIDTH_20:
800 regBwOpMode |= BW_OPMODE_20MHZ;
801 /* 2007/02/07 Mark by Emily because we have not verify whether this register works */
802 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
804 case HT_CHANNEL_WIDTH_40:
805 regBwOpMode &= ~BW_OPMODE_20MHZ;
806 /* 2007/02/07 Mark by Emily because we have not verify whether this register works */
807 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
808 regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5);
809 rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
816 /* 3 <2>Set PHY related register */
818 switch (pHalData->CurrentChannelBW) {
820 case HT_CHANNEL_WIDTH_20:
821 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
822 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
825 case HT_CHANNEL_WIDTH_40:
826 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
827 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
828 /* Set Control channel to upper or lower. These settings are required only for 40MHz */
829 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
830 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
831 PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27),
832 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
837 /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
839 /* 3<3>Set RF related register */
840 switch (pHalData->rf_chip) {
844 /* Please implement this function in Hal8190PciPhy8256.c */
847 /* Please implement this function in Hal8190PciPhy8258.c */
852 rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
859 /*-----------------------------------------------------------------------------
860 * Function: SetBWMode8190Pci()
862 * Overview: This function is export to "HalCommon" moudule
864 * Input: struct adapter *Adapter
865 * enum ht_channel_width Bandwidth 20M or 40M
871 * Note: We do not take j mode into consideration now
872 *---------------------------------------------------------------------------*/
873 void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */
874 unsigned char Offset) /* Upper, Lower, or Don't care */
876 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
877 enum ht_channel_width tmpBW = pHalData->CurrentChannelBW;
879 pHalData->CurrentChannelBW = Bandwidth;
881 pHalData->nCur40MhzPrimeSC = Offset;
883 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
884 _PHY_SetBWMode92C(Adapter);
886 pHalData->CurrentChannelBW = tmpBW;
889 static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
893 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
895 if (Adapter->bNotifyChannelChange)
896 DBG_88E("[%s] ch = %d\n", __func__, channel);
898 /* s1. pre common command - CmdID_SetTxPowerLevel */
899 PHY_SetTxPowerLevel8188E(Adapter, channel);
901 /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
904 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
905 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
906 PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
910 void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
912 /* Call after initialization */
913 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
914 u8 tmpchannel = pHalData->CurrentChannel;
917 if (pHalData->rf_chip == RF_PSEUDO_11N)
918 return; /* return immediately if it is peudo-phy */
923 pHalData->CurrentChannel = channel;
925 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
926 _PHY_SwChnl8192C(Adapter, channel);
931 pHalData->CurrentChannel = tmpchannel;
934 pHalData->CurrentChannel = tmpchannel;