1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __INC_HAL8188EPHYREG_H__
21 #define __INC_HAL8188EPHYREG_H__
22 /*--------------------------Define Parameters-------------------------------*/
24 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
25 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
26 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
27 /* 3. RF register 0x00-2E */
28 /* 4. Bit Mask for BB/RF register */
29 /* 5. Other defintion for BB/RF R/W */
34 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
37 #define rPMAC_Reset 0x100
38 #define rPMAC_TxStart 0x104
39 #define rPMAC_TxLegacySIG 0x108
40 #define rPMAC_TxHTSIG1 0x10c
41 #define rPMAC_TxHTSIG2 0x110
42 #define rPMAC_PHYDebug 0x114
43 #define rPMAC_TxPacketNum 0x118
44 #define rPMAC_TxIdle 0x11c
45 #define rPMAC_TxMACHeader0 0x120
46 #define rPMAC_TxMACHeader1 0x124
47 #define rPMAC_TxMACHeader2 0x128
48 #define rPMAC_TxMACHeader3 0x12c
49 #define rPMAC_TxMACHeader4 0x130
50 #define rPMAC_TxMACHeader5 0x134
51 #define rPMAC_TxDataType 0x138
52 #define rPMAC_TxRandomSeed 0x13c
53 #define rPMAC_CCKPLCPPreamble 0x140
54 #define rPMAC_CCKPLCPHeader 0x144
55 #define rPMAC_CCKCRC16 0x148
56 #define rPMAC_OFDMRxCRC32OK 0x170
57 #define rPMAC_OFDMRxCRC32Er 0x174
58 #define rPMAC_OFDMRxParityEr 0x178
59 #define rPMAC_OFDMRxCRC8Er 0x17c
60 #define rPMAC_CCKCRxRC16Er 0x180
61 #define rPMAC_CCKCRxRC32Er 0x184
62 #define rPMAC_CCKCRxRC32OK 0x188
63 #define rPMAC_TxStatus 0x18c
66 /* The following two definition are only used for USB interface. */
67 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */
68 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */
71 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
73 #define rFPGA0_TxInfo 0x804 /* Status report?? */
74 #define rFPGA0_PSDFunction 0x808
76 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
78 #define rFPGA0_RFTiming1 0x810 /* Useless now */
79 #define rFPGA0_RFTiming2 0x814
81 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
82 #define rFPGA0_XA_HSSIParameter2 0x824
83 #define rFPGA0_XB_HSSIParameter1 0x828
84 #define rFPGA0_XB_HSSIParameter2 0x82c
86 #define rFPGA0_XA_LSSIParameter 0x840
87 #define rFPGA0_XB_LSSIParameter 0x844
89 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
90 #define rFPGA0_RFSleepUpParameter 0x854
92 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
93 #define rFPGA0_XCD_SwitchControl 0x85c
95 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
96 #define rFPGA0_XB_RFInterfaceOE 0x864
98 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */
99 #define rFPGA0_XCD_RFInterfaceSW 0x874
101 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
102 #define rFPGA0_XCD_RFParameter 0x87c
104 /* Crystal cap setting RF-R/W protection for parameter4?? */
105 #define rFPGA0_AnalogParameter1 0x880
106 #define rFPGA0_AnalogParameter2 0x884
107 #define rFPGA0_AnalogParameter3 0x888
108 /* enable ad/da clock1 for dual-phy */
109 #define rFPGA0_AdDaClockEn 0x888
110 #define rFPGA0_AnalogParameter4 0x88c
112 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
113 #define rFPGA0_XB_LSSIReadBack 0x8a4
114 #define rFPGA0_XC_LSSIReadBack 0x8a8
115 #define rFPGA0_XD_LSSIReadBack 0x8ac
117 #define rFPGA0_PSDReport 0x8b4 /* Useless now */
118 /* Transceiver A HSPI Readback */
119 #define TransceiverA_HSPI_Readback 0x8b8
120 /* Transceiver B HSPI Readback */
121 #define TransceiverB_HSPI_Readback 0x8bc
122 /* Useless now RF Interface Readback Value */
123 #define rFPGA0_XAB_RFInterfaceRB 0x8e0
124 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
126 /* 4. Page9(0x900) */
127 /* RF mode & OFDM TxSC RF BW Setting?? */
128 #define rFPGA1_RFMOD 0x900
130 #define rFPGA1_TxBlock 0x904 /* Useless now */
131 #define rFPGA1_DebugSelect 0x908 /* Useless now */
132 #define rFPGA1_TxInfo 0x90c /* Useless now Status report */
134 /* 5. PageA(0xA00) */
135 /* Set Control channel to upper or lower - required only for 40MHz */
136 #define rCCK0_System 0xa00
138 /* Disable init gain now Select RX path by RSSI */
139 #define rCCK0_AFESetting 0xa04
140 /* Disable init gain now Init gain */
141 #define rCCK0_CCA 0xa08
143 /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold,
144 * RX LNA Threshold useless now. Not the same as 90 series */
145 #define rCCK0_RxAGC1 0xa0c
146 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
148 #define rCCK0_RxHP 0xa14
150 /* Timing recovery & Channel estimation threshold */
151 #define rCCK0_DSPParameter1 0xa18
152 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
154 #define rCCK0_TxFilter1 0xa20
155 #define rCCK0_TxFilter2 0xa24
156 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
157 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now */
158 #define rCCK0_TRSSIReport 0xa50
159 #define rCCK0_RxReport 0xa54 /* 0xa57 */
160 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
161 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
166 #define rPdp_AntA 0xb00
167 #define rPdp_AntA_4 0xb04
168 #define rConfig_Pmpd_AntA 0xb28
169 #define rConfig_AntA 0xb68
170 #define rConfig_AntB 0xb6c
171 #define rPdp_AntB 0xb70
172 #define rPdp_AntB_4 0xb74
173 #define rConfig_Pmpd_AntB 0xb98
177 /* 6. PageC(0xC00) */
179 #define rOFDM0_LSTF 0xc00
181 #define rOFDM0_TRxPathEnable 0xc04
182 #define rOFDM0_TRMuxPar 0xc08
183 #define rOFDM0_TRSWIsolation 0xc0c
185 /* RxIQ DC offset, Rx digital filter, DC notch filter */
186 #define rOFDM0_XARxAFE 0xc10
187 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
188 #define rOFDM0_XBRxAFE 0xc18
189 #define rOFDM0_XBRxIQImbalance 0xc1c
190 #define rOFDM0_XCRxAFE 0xc20
191 #define rOFDM0_XCRxIQImbalance 0xc24
192 #define rOFDM0_XDRxAFE 0xc28
193 #define rOFDM0_XDRxIQImbalance 0xc2c
195 #define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/
196 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
197 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
198 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
200 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
201 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
202 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
203 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
205 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
206 #define rOFDM0_XAAGCCore2 0xc54
207 #define rOFDM0_XBAGCCore1 0xc58
208 #define rOFDM0_XBAGCCore2 0xc5c
209 #define rOFDM0_XCAGCCore1 0xc60
210 #define rOFDM0_XCAGCCore2 0xc64
211 #define rOFDM0_XDAGCCore1 0xc68
212 #define rOFDM0_XDAGCCore2 0xc6c
214 #define rOFDM0_AGCParameter1 0xc70
215 #define rOFDM0_AGCParameter2 0xc74
216 #define rOFDM0_AGCRSSITable 0xc78
217 #define rOFDM0_HTSTFAGC 0xc7c
219 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
220 #define rOFDM0_XATxAFE 0xc84
221 #define rOFDM0_XBTxIQImbalance 0xc88
222 #define rOFDM0_XBTxAFE 0xc8c
223 #define rOFDM0_XCTxIQImbalance 0xc90
224 #define rOFDM0_XCTxAFE 0xc94
225 #define rOFDM0_XDTxIQImbalance 0xc98
226 #define rOFDM0_XDTxAFE 0xc9c
228 #define rOFDM0_RxIQExtAnta 0xca0
229 #define rOFDM0_TxCoeff1 0xca4
230 #define rOFDM0_TxCoeff2 0xca8
231 #define rOFDM0_TxCoeff3 0xcac
232 #define rOFDM0_TxCoeff4 0xcb0
233 #define rOFDM0_TxCoeff5 0xcb4
234 #define rOFDM0_TxCoeff6 0xcb8
235 #define rOFDM0_RxHPParameter 0xce0
236 #define rOFDM0_TxPseudoNoiseWgt 0xce4
237 #define rOFDM0_FrameSync 0xcf0
238 #define rOFDM0_DFSReport 0xcf4
242 /* 7. PageD(0xD00) */
244 #define rOFDM1_LSTF 0xd00
245 #define rOFDM1_TRxPathEnable 0xd04
247 #define rOFDM1_CFO 0xd08 /* No setting now */
248 #define rOFDM1_CSI1 0xd10
249 #define rOFDM1_SBD 0xd14
250 #define rOFDM1_CSI2 0xd18
251 #define rOFDM1_CFOTracking 0xd2c
252 #define rOFDM1_TRxMesaure1 0xd34
253 #define rOFDM1_IntfDet 0xd3c
254 #define rOFDM1_PseudoNoiseStateAB 0xd50
255 #define rOFDM1_PseudoNoiseStateCD 0xd54
256 #define rOFDM1_RxPseudoNoiseWgt 0xd58
258 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
259 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
260 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
262 #define rOFDM_ShortCFOAB 0xdac /* No setting now */
263 #define rOFDM_ShortCFOCD 0xdb0
264 #define rOFDM_LongCFOAB 0xdb4
265 #define rOFDM_LongCFOCD 0xdb8
266 #define rOFDM_TailCFOAB 0xdbc
267 #define rOFDM_TailCFOCD 0xdc0
268 #define rOFDM_PWMeasure1 0xdc4
269 #define rOFDM_PWMeasure2 0xdc8
270 #define rOFDM_BWReport 0xdcc
271 #define rOFDM_AGCReport 0xdd0
272 #define rOFDM_RxSNR 0xdd4
273 #define rOFDM_RxEVMCSI 0xdd8
274 #define rOFDM_SIGReport 0xddc
278 /* 8. PageE(0xE00) */
280 #define rTxAGC_A_Rate18_06 0xe00
281 #define rTxAGC_A_Rate54_24 0xe04
282 #define rTxAGC_A_CCK1_Mcs32 0xe08
283 #define rTxAGC_A_Mcs03_Mcs00 0xe10
284 #define rTxAGC_A_Mcs07_Mcs04 0xe14
285 #define rTxAGC_A_Mcs11_Mcs08 0xe18
286 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
288 #define rTxAGC_B_Rate18_06 0x830
289 #define rTxAGC_B_Rate54_24 0x834
290 #define rTxAGC_B_CCK1_55_Mcs32 0x838
291 #define rTxAGC_B_Mcs03_Mcs00 0x83c
292 #define rTxAGC_B_Mcs07_Mcs04 0x848
293 #define rTxAGC_B_Mcs11_Mcs08 0x84c
294 #define rTxAGC_B_Mcs15_Mcs12 0x868
295 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
297 #define rFPGA0_IQK 0xe28
298 #define rTx_IQK_Tone_A 0xe30
299 #define rRx_IQK_Tone_A 0xe34
300 #define rTx_IQK_PI_A 0xe38
301 #define rRx_IQK_PI_A 0xe3c
303 #define rTx_IQK 0xe40
304 #define rRx_IQK 0xe44
305 #define rIQK_AGC_Pts 0xe48
306 #define rIQK_AGC_Rsp 0xe4c
307 #define rTx_IQK_Tone_B 0xe50
308 #define rRx_IQK_Tone_B 0xe54
309 #define rTx_IQK_PI_B 0xe58
310 #define rRx_IQK_PI_B 0xe5c
311 #define rIQK_AGC_Cont 0xe60
313 #define rBlue_Tooth 0xe6c
314 #define rRx_Wait_CCA 0xe70
315 #define rTx_CCK_RFON 0xe74
316 #define rTx_CCK_BBON 0xe78
317 #define rTx_OFDM_RFON 0xe7c
318 #define rTx_OFDM_BBON 0xe80
319 #define rTx_To_Rx 0xe84
320 #define rTx_To_Tx 0xe88
321 #define rRx_CCK 0xe8c
323 #define rTx_Power_Before_IQK_A 0xe94
324 #define rTx_Power_After_IQK_A 0xe9c
326 #define rRx_Power_Before_IQK_A 0xea0
327 #define rRx_Power_Before_IQK_A_2 0xea4
328 #define rRx_Power_After_IQK_A 0xea8
329 #define rRx_Power_After_IQK_A_2 0xeac
331 #define rTx_Power_Before_IQK_B 0xeb4
332 #define rTx_Power_After_IQK_B 0xebc
334 #define rRx_Power_Before_IQK_B 0xec0
335 #define rRx_Power_Before_IQK_B_2 0xec4
336 #define rRx_Power_After_IQK_B 0xec8
337 #define rRx_Power_After_IQK_B_2 0xecc
339 #define rRx_OFDM 0xed0
340 #define rRx_Wait_RIFS 0xed4
341 #define rRx_TO_Rx 0xed8
342 #define rStandby 0xedc
344 #define rPMPD_ANAEN 0xeec
347 /* 7. RF Register 0x00-0x2E (RF 8256) */
348 /* RF-0222D 0x00-3F */
351 #define rZebra1_HSSIEnable 0x0 /* Useless now */
352 #define rZebra1_TRxEnable1 0x1
353 #define rZebra1_TRxEnable2 0x2
354 #define rZebra1_AGC 0x4
355 #define rZebra1_ChargePump 0x5
356 #define rZebra1_Channel 0x7 /* RF channel switch */
359 #define rZebra1_TxGain 0x8 /* Useless now */
360 #define rZebra1_TxLPF 0x9
361 #define rZebra1_RxLPF 0xb
362 #define rZebra1_RxHPFCorner 0xc
365 #define rGlobalCtrl 0 /* Useless now */
366 #define rRTL8256_TxLPF 19
367 #define rRTL8256_RxLPF 11
370 #define rRTL8258_TxLPF 0x11 /* Useless now */
371 #define rRTL8258_RxLPF 0x13
372 #define rRTL8258_RSSILPF 0xa
375 /* RL6052 Register definition */
377 #define RF_AC 0x00 /* */
379 #define RF_IQADJ_G1 0x01 /* */
380 #define RF_IQADJ_G2 0x02 /* */
382 #define RF_POW_TRSW 0x05 /* */
384 #define RF_GAIN_RX 0x06 /* */
385 #define RF_GAIN_TX 0x07 /* */
387 #define RF_TXM_IDAC 0x08 /* */
388 #define RF_IPA_G 0x09 /* */
389 #define RF_TXBIAS_G 0x0A
390 #define RF_TXPA_AG 0x0B
391 #define RF_IPA_A 0x0C /* */
392 #define RF_TXBIAS_A 0x0D
393 #define RF_BS_PA_APSET_G9_G11 0x0E
394 #define RF_BS_IQGEN 0x0F /* */
396 #define RF_MODE1 0x10 /* */
397 #define RF_MODE2 0x11 /* */
399 #define RF_RX_AGC_HP 0x12 /* */
400 #define RF_TX_AGC 0x13 /* */
401 #define RF_BIAS 0x14 /* */
402 #define RF_IPA 0x15 /* */
403 #define RF_TXBIAS 0x16
404 #define RF_POW_ABILITY 0x17 /* */
405 #define RF_CHNLBW 0x18 /* RF channel and BW switch */
406 #define RF_TOP 0x19 /* */
408 #define RF_RX_G1 0x1A /* */
409 #define RF_RX_G2 0x1B /* */
411 #define RF_RX_BB2 0x1C /* */
412 #define RF_RX_BB1 0x1D /* */
414 #define RF_RCK1 0x1E /* */
415 #define RF_RCK2 0x1F /* */
417 #define RF_TX_G1 0x20 /* */
418 #define RF_TX_G2 0x21 /* */
419 #define RF_TX_G3 0x22 /* */
421 #define RF_TX_BB1 0x23 /* */
423 #define RF_T_METER_92D 0x42 /* */
424 #define RF_T_METER_88E 0x42 /* */
425 #define RF_T_METER 0x24 /* */
427 #define RF_SYN_G1 0x25 /* RF TX Power control */
428 #define RF_SYN_G2 0x26 /* RF TX Power control */
429 #define RF_SYN_G3 0x27 /* RF TX Power control */
430 #define RF_SYN_G4 0x28 /* RF TX Power control */
431 #define RF_SYN_G5 0x29 /* RF TX Power control */
432 #define RF_SYN_G6 0x2A /* RF TX Power control */
433 #define RF_SYN_G7 0x2B /* RF TX Power control */
434 #define RF_SYN_G8 0x2C /* RF TX Power control */
436 #define RF_RCK_OS 0x30 /* RF TX PA control */
437 #define RF_TXPA_G1 0x31 /* RF TX PA control */
438 #define RF_TXPA_G2 0x32 /* RF TX PA control */
439 #define RF_TXPA_G3 0x33 /* RF TX PA control */
440 #define RF_TX_BIAS_A 0x35
441 #define RF_TX_BIAS_D 0x36
442 #define RF_LOBF_9 0x38
443 #define RF_RXRF_A3 0x3C /* */
446 #define RF_TXRF_A2 0x41
447 #define RF_TXPA_G4 0x46
448 #define RF_TXPA_A4 0x4B
450 #define RF_WE_LUT 0xEF
456 /* 1. Page1(0x100) */
457 #define bBBResetB 0x100 /* Useless now? */
458 #define bGlobalResetB 0x200
459 #define bOFDMTxStart 0x4
460 #define bCCKTxStart 0x8
461 #define bCRC32Debug 0x100
462 #define bPMACLoopback 0x10
463 #define bTxLSIG 0xffffff
464 #define bOFDMTxRate 0xf
465 #define bOFDMTxReserved 0x10
466 #define bOFDMTxLength 0x1ffe0
467 #define bOFDMTxParity 0x20000
468 #define bTxHTSIG1 0xffffff
469 #define bTxHTMCSRate 0x7f
471 #define bTxHTLength 0xffff00
472 #define bTxHTSIG2 0xffffff
473 #define bTxHTSmoothing 0x1
474 #define bTxHTSounding 0x2
475 #define bTxHTReserved 0x4
476 #define bTxHTAggreation 0x8
477 #define bTxHTSTBC 0x30
478 #define bTxHTAdvanceCoding 0x40
479 #define bTxHTShortGI 0x80
480 #define bTxHTNumberHT_LTF 0x300
481 #define bTxHTCRC8 0x3fc00
482 #define bCounterReset 0x10000
483 #define bNumOfOFDMTx 0xffff
484 #define bNumOfCCKTx 0xffff0000
485 #define bTxIdleInterval 0xffff
486 #define bOFDMService 0xffff0000
487 #define bTxMACHeader 0xffffffff
488 #define bTxDataInit 0xff
489 #define bTxHTMode 0x100
490 #define bTxDataType 0x30000
491 #define bTxRandomSeed 0xffffffff
492 #define bCCKTxPreamble 0x1
493 #define bCCKTxSFD 0xffff0000
494 #define bCCKTxSIG 0xff
495 #define bCCKTxService 0xff00
496 #define bCCKLengthExt 0x8000
497 #define bCCKTxLength 0xffff0000
498 #define bCCKTxCRC16 0xffff
499 #define bCCKTxStatus 0x1
500 #define bOFDMTxStatus 0x2
502 #define IS_BB_REG_OFFSET_92S(_Offset) \
503 ((_Offset >= 0x800) && (_Offset <= 0xfff))
505 /* 2. Page8(0x800) */
506 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
507 #define bJapanMode 0x2
508 #define bCCKTxSC 0x30
509 #define bCCKEn 0x1000000
510 #define bOFDMEn 0x2000000
512 #define bOFDMRxADCPhase 0x10000 /* Useless now */
513 #define bOFDMTxDACPhase 0x40000
514 #define bXATxAGC 0x3f
516 #define bAntennaSelect 0x0300
518 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
519 #define bXCTxAGC 0xf000
520 #define bXDTxAGC 0xf0000
522 #define bPAStart 0xf0000000 /* Useless now */
523 #define bTRStart 0x00f00000
524 #define bRFStart 0x0000f000
525 #define bBBStart 0x000000f0
526 #define bBBCCKStart 0x0000000f
527 #define bPAEnd 0xf /* Reg0x814 */
528 #define bTREnd 0x0f000000
529 #define bRFEnd 0x000f0000
530 #define bCCAMask 0x000000f0 /* T2R */
531 #define bR2RCCAMask 0x00000f00
532 #define bHSSI_R2TDelay 0xf8000000
533 #define bHSSI_T2RDelay 0xf80000
534 #define bContTxHSSI 0x400 /* change gain at continue Tx */
535 #define bIGFromCCK 0x200
536 #define bAGCAddress 0x3f
537 #define bRxHPTx 0x7000
538 #define bRxHPT2R 0x38000
539 #define bRxHPCCKIni 0xc0000
540 #define bAGCTxCode 0xc00000
541 #define bAGCRxCode 0x300000
543 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
544 #define b3WireDataLength 0x800
545 #define b3WireAddressLength 0x400
547 #define b3WireRFPowerDown 0x1 /* Useless now */
548 #define b5GPAPEPolarity 0x40000000
549 #define b2GPAPEPolarity 0x80000000
550 #define bRFSW_TxDefaultAnt 0x3
551 #define bRFSW_TxOptionAnt 0x30
552 #define bRFSW_RxDefaultAnt 0x300
553 #define bRFSW_RxOptionAnt 0x3000
554 #define bRFSI_3WireData 0x1
555 #define bRFSI_3WireClock 0x2
556 #define bRFSI_3WireLoad 0x4
557 #define bRFSI_3WireRW 0x8
558 #define bRFSI_3Wire 0xf
560 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
562 #define bRFSI_TRSW 0x20 /* Useless now */
563 #define bRFSI_TRSWB 0x40
564 #define bRFSI_ANTSW 0x100
565 #define bRFSI_ANTSWB 0x200
566 #define bRFSI_PAPE 0x400
567 #define bRFSI_PAPE5G 0x800
568 #define bBandSelect 0x1
569 #define bHTSIG2_GI 0x80
570 #define bHTSIG2_Smoothing 0x01
571 #define bHTSIG2_Sounding 0x02
572 #define bHTSIG2_Aggreaton 0x08
573 #define bHTSIG2_STBC 0x30
574 #define bHTSIG2_AdvCoding 0x40
575 #define bHTSIG2_NumOfHTLTF 0x300
576 #define bHTSIG2_CRC8 0x3fc
577 #define bHTSIG1_MCS 0x7f
578 #define bHTSIG1_BandWidth 0x80
579 #define bHTSIG1_HTLength 0xffff
580 #define bLSIG_Rate 0xf
581 #define bLSIG_Reserved 0x10
582 #define bLSIG_Length 0x1fffe
583 #define bLSIG_Parity 0x20
584 #define bCCKRxPhase 0x4
586 #define bLSSIReadAddress 0x7f800000 /* T65 RF */
588 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
590 #define bLSSIReadBackData 0xfffff /* T65 RF */
592 #define bLSSIReadOKFlag 0x1000 /* Useless now */
593 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
594 #define bRegulator0Standby 0x1
595 #define bRegulatorPLLStandby 0x2
596 #define bRegulator1Standby 0x4
597 #define bPLLPowerUp 0x8
598 #define bDPLLPowerUp 0x10
599 #define bDA10PowerUp 0x20
600 #define bAD7PowerUp 0x200
601 #define bDA6PowerUp 0x2000
602 #define bXtalPowerUp 0x4000
603 #define b40MDClkPowerUP 0x8000
604 #define bDA6DebugMode 0x20000
605 #define bDA6Swing 0x380000
607 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
608 #define bADClkPhase 0x4000000
610 #define b80MClkDelay 0x18000000 /* Useless */
611 #define bAFEWatchDogEnable 0x20000000
613 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
614 #define bXtalCap01 0xc0000000
615 #define bXtalCap23 0x3
616 #define bXtalCap92x 0x0f000000
617 #define bXtalCap 0x0f000000
619 #define bIntDifClkEnable 0x400 /* Useless */
620 #define bExtSigClkEnable 0x800
621 #define bBandgapMbiasPowerUp 0x10000
622 #define bAD11SHGain 0xc0000
623 #define bAD11InputRange 0x700000
624 #define bAD11OPCurrent 0x3800000
625 #define bIPathLoopback 0x4000000
626 #define bQPathLoopback 0x8000000
627 #define bAFELoopback 0x10000000
628 #define bDA10Swing 0x7e0
629 #define bDA10Reverse 0x800
630 #define bDAClkSource 0x1000
631 #define bAD7InputRange 0x6000
632 #define bAD7Gain 0x38000
633 #define bAD7OutputCMMode 0x40000
634 #define bAD7InputCMMode 0x380000
635 #define bAD7Current 0xc00000
636 #define bRegulatorAdjust 0x7000000
637 #define bAD11PowerUpAtTx 0x1
638 #define bDA10PSAtTx 0x10
639 #define bAD11PowerUpAtRx 0x100
640 #define bDA10PSAtRx 0x1000
641 #define bCCKRxAGCFormat 0x200
642 #define bPSDFFTSamplepPoint 0xc000
643 #define bPSDAverageNum 0x3000
644 #define bIQPathControl 0xc00
645 #define bPSDFreq 0x3ff
646 #define bPSDAntennaPath 0x30
647 #define bPSDIQSwitch 0x40
648 #define bPSDRxTrigger 0x400000
649 #define bPSDTxTrigger 0x80000000
650 #define bPSDSineToneScale 0x7f000000
651 #define bPSDReport 0xffff
653 /* 3. Page9(0x900) */
654 #define bOFDMTxSC 0x30000000 /* Useless */
656 #define bOFDMTxOn 0x2
657 #define bDebugPage 0xfff /* reset debug page and HWord, LWord */
658 #define bDebugItem 0xff /* reset debug page and LWord */
660 #define bAntNonHT 0x100
661 #define bAntHT1 0x1000
662 #define bAntHT2 0x10000
663 #define bAntHT1S1 0x100000
664 #define bAntNonHTS1 0x1000000
666 /* 4. PageA(0xA00) */
667 #define bCCKBBMode 0x3 /* Useless */
668 #define bCCKTxPowerSaving 0x80
669 #define bCCKRxPowerSaving 0x40
671 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */
673 #define bCCKScramble 0x8 /* Useless */
674 #define bCCKAntDiversity 0x8000
675 #define bCCKCarrierRecovery 0x4000
676 #define bCCKTxRate 0x3000
677 #define bCCKDCCancel 0x0800
678 #define bCCKISICancel 0x0400
679 #define bCCKMatchFilter 0x0200
680 #define bCCKEqualizer 0x0100
681 #define bCCKPreambleDetect 0x800000
682 #define bCCKFastFalseCCA 0x400000
683 #define bCCKChEstStart 0x300000
684 #define bCCKCCACount 0x080000
685 #define bCCKcs_lim 0x070000
686 #define bCCKBistMode 0x80000000
687 #define bCCKCCAMask 0x40000000
688 #define bCCKTxDACPhase 0x4
689 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
690 #define bCCKr_cp_mode0 0x0100
691 #define bCCKTxDCOffset 0xf0
692 #define bCCKRxDCOffset 0xf
693 #define bCCKCCAMode 0xc000
694 #define bCCKFalseCS_lim 0x3f00
695 #define bCCKCS_ratio 0xc00000
696 #define bCCKCorgBit_sel 0x300000
697 #define bCCKPD_lim 0x0f0000
698 #define bCCKNewCCA 0x80000000
699 #define bCCKRxHPofIG 0x8000
700 #define bCCKRxIG 0x7f00
701 #define bCCKLNAPolarity 0x800000
702 #define bCCKRx1stGain 0x7f0000
703 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
704 #define bCCKRxAGCSatLevel 0x1f000000
705 #define bCCKRxAGCSatCount 0xe0
706 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
707 #define bCCKFixedRxAGC 0x8000
708 #define bCCKAntennaPolarity 0x2000
709 #define bCCKTxFilterType 0x0c00
710 #define bCCKRxAGCReportType 0x0300
711 #define bCCKRxDAGCEn 0x80000000
712 #define bCCKRxDAGCPeriod 0x20000000
713 #define bCCKRxDAGCSatLevel 0x1f000000
714 #define bCCKTimingRecovery 0x800000
715 #define bCCKTxC0 0x3f0000
716 #define bCCKTxC1 0x3f000000
717 #define bCCKTxC2 0x3f
718 #define bCCKTxC3 0x3f00
719 #define bCCKTxC4 0x3f0000
720 #define bCCKTxC5 0x3f000000
721 #define bCCKTxC6 0x3f
722 #define bCCKTxC7 0x3f00
723 #define bCCKDebugPort 0xff0000
724 #define bCCKDACDebug 0x0f000000
725 #define bCCKFalseAlarmEnable 0x8000
726 #define bCCKFalseAlarmRead 0x4000
727 #define bCCKTRSSI 0x7f
728 #define bCCKRxAGCReport 0xfe
729 #define bCCKRxReport_AntSel 0x80000000
730 #define bCCKRxReport_MFOff 0x40000000
731 #define bCCKRxRxReport_SQLoss 0x20000000
732 #define bCCKRxReport_Pktloss 0x10000000
733 #define bCCKRxReport_Lockedbit 0x08000000
734 #define bCCKRxReport_RateError 0x04000000
735 #define bCCKRxReport_RxRate 0x03000000
736 #define bCCKRxFACounterLower 0xff
737 #define bCCKRxFACounterUpper 0xff000000
738 #define bCCKRxHPAGCStart 0xe000
739 #define bCCKRxHPAGCFinal 0x1c00
740 #define bCCKRxFalseAlarmEnable 0x8000
741 #define bCCKFACounterFreeze 0x4000
742 #define bCCKTxPathSel 0x10000000
743 #define bCCKDefaultRxPath 0xc000000
744 #define bCCKOptionRxPath 0x3000000
746 /* 5. PageC(0xC00) */
747 #define bNumOfSTF 0x3 /* Useless */
748 #define bShift_L 0xc0
758 #define bTRSSIFreq 0x200
759 #define bADCBackoff 0x3000
760 #define bDFIRBackoff 0xc000
761 #define bTRSSILatchPhase 0x10000
762 #define bRxIDCOffset 0xff
763 #define bRxQDCOffset 0xff00
764 #define bRxDFIRMode 0x1800000
765 #define bRxDCNFType 0xe000000
766 #define bRXIQImb_A 0x3ff
767 #define bRXIQImb_B 0xfc00
768 #define bRXIQImb_C 0x3f0000
769 #define bRXIQImb_D 0xffc00000
770 #define bDC_dc_Notch 0x60000
771 #define bRxNBINotch 0x1f000000
773 #define bPD_TH_Opt2 0xc000
774 #define bPWED_TH 0x700
775 #define bIfMF_Win_L 0x800
776 #define bPD_Option 0x1000
777 #define bMF_Win_L 0xe000
778 #define bBW_Search_L 0x30000
779 #define bwin_enh_L 0xc0000
780 #define bBW_TH 0x700000
781 #define bED_TH2 0x3800000
782 #define bBW_option 0x4000000
783 #define bRatio_TH 0x18000000
784 #define bWindow_L 0xe0000000
785 #define bSBD_Option 0x1
786 #define bFrame_TH 0x1c
787 #define bFS_Option 0x60
788 #define bDC_Slope_check 0x80
789 #define bFGuard_Counter_DC_L 0xe00
790 #define bFrame_Weight_Short 0x7000
791 #define bSub_Tune 0xe00000
792 #define bFrame_DC_Length 0xe000000
793 #define bSBD_start_offset 0x30000000
794 #define bFrame_TH_2 0x7
795 #define bFrame_GI2_TH 0x38
796 #define bGI2_Sync_en 0x40
797 #define bSarch_Short_Early 0x300
798 #define bSarch_Short_Late 0xc00
799 #define bSarch_GI2_Late 0x70000
800 #define bCFOAntSum 0x1
802 #define bCFOStartOffset 0xc
803 #define bCFOLookBack 0x70
804 #define bCFOSumWeight 0x80
805 #define bDAGCEnable 0x10000
806 #define bTXIQImb_A 0x3ff
807 #define bTXIQImb_B 0xfc00
808 #define bTXIQImb_C 0x3f0000
809 #define bTXIQImb_D 0xffc00000
810 #define bTxIDCOffset 0xff
811 #define bTxQDCOffset 0xff00
812 #define bTxDFIRMode 0x10000
813 #define bTxPesudoNoiseOn 0x4000000
814 #define bTxPesudoNoise_A 0xff
815 #define bTxPesudoNoise_B 0xff00
816 #define bTxPesudoNoise_C 0xff0000
817 #define bTxPesudoNoise_D 0xff000000
818 #define bCCADropOption 0x20000
819 #define bCCADropThres 0xfff00000
821 #define bEDCCA_L 0xf0
822 #define bLambda_ED 0x300
823 #define bRxInitialGain 0x7f
824 #define bRxAntDivEn 0x80
825 #define bRxAGCAddressForLNA 0x7f00
826 #define bRxHighPowerFlow 0x8000
827 #define bRxAGCFreezeThres 0xc0000
828 #define bRxFreezeStep_AGC1 0x300000
829 #define bRxFreezeStep_AGC2 0xc00000
830 #define bRxFreezeStep_AGC3 0x3000000
831 #define bRxFreezeStep_AGC0 0xc000000
832 #define bRxRssi_Cmp_En 0x10000000
833 #define bRxQuickAGCEn 0x20000000
834 #define bRxAGCFreezeThresMode 0x40000000
835 #define bRxOverFlowCheckType 0x80000000
836 #define bRxAGCShift 0x7f
837 #define bTRSW_Tri_Only 0x80
838 #define bPowerThres 0x300
840 #define bRxAGCTogetherEn 0x2
841 #define bRxAGCMin 0x4
842 #define bRxHP_Ini 0x7
843 #define bRxHP_TRLNA 0x70
844 #define bRxHP_RSSI 0x700
845 #define bRxHP_BBP1 0x7000
846 #define bRxHP_BBP2 0x70000
847 #define bRxHP_BBP3 0x700000
848 #define bRSSI_H 0x7f0000 /* threshold for high power */
849 #define bRSSI_Gen 0x7f000000 /* threshold for ant diversity */
850 #define bRxSettle_TRSW 0x7
851 #define bRxSettle_LNA 0x38
852 #define bRxSettle_RSSI 0x1c0
853 #define bRxSettle_BBP 0xe00
854 #define bRxSettle_RxHP 0x7000
855 #define bRxSettle_AntSW_RSSI 0x38000
856 #define bRxSettle_AntSW 0xc0000
857 #define bRxProcessTime_DAGC 0x300000
858 #define bRxSettle_HSSI 0x400000
859 #define bRxProcessTime_BBPPW 0x800000
860 #define bRxAntennaPowerShift 0x3000000
861 #define bRSSITableSelect 0xc000000
862 #define bRxHP_Final 0x7000000
863 #define bRxHTSettle_BBP 0x7
864 #define bRxHTSettle_HSSI 0x8
865 #define bRxHTSettle_RxHP 0x70
866 #define bRxHTSettle_BBPPW 0x80
867 #define bRxHTSettle_Idle 0x300
868 #define bRxHTSettle_Reserved 0x1c00
869 #define bRxHTRxHPEn 0x8000
870 #define bRxHTAGCFreezeThres 0x30000
871 #define bRxHTAGCTogetherEn 0x40000
872 #define bRxHTAGCMin 0x80000
873 #define bRxHTAGCEn 0x100000
874 #define bRxHTDAGCEn 0x200000
875 #define bRxHTRxHP_BBP 0x1c00000
876 #define bRxHTRxHP_Final 0xe0000000
877 #define bRxPWRatioTH 0x3
878 #define bRxPWRatioEn 0x4
879 #define bRxMFHold 0x3800
880 #define bRxPD_Delay_TH1 0x38
881 #define bRxPD_Delay_TH2 0x1c0
882 #define bRxPD_DC_COUNT_MAX 0x600
883 #define bRxPD_Delay_TH 0x8000
884 #define bRxProcess_Delay 0xf0000
885 #define bRxSearchrange_GI2_Early 0x700000
886 #define bRxFrame_Guard_Counter_L 0x3800000
887 #define bRxSGI_Guard_L 0xc000000
888 #define bRxSGI_Search_L 0x30000000
889 #define bRxSGI_TH 0xc0000000
890 #define bDFSCnt0 0xff
891 #define bDFSCnt1 0xff00
892 #define bDFSFlag 0xf0000
893 #define bMFWeightSum 0x300000
894 #define bMinIdxTH 0x7f000000
895 #define bDAFormat 0x40000
896 #define bTxChEmuEnable 0x01000000
897 #define bTRSWIsolation_A 0x7f
898 #define bTRSWIsolation_B 0x7f00
899 #define bTRSWIsolation_C 0x7f0000
900 #define bTRSWIsolation_D 0x7f000000
901 #define bExtLNAGain 0x7c00
903 /* 6. PageE(0xE00) */
904 #define bSTBCEn 0x4 /* Useless */
905 #define bAntennaMapping 0x10
907 #define bCFOAntSumD 0x200
908 #define bPHYCounterReset 0x8000000
909 #define bCFOReportGet 0x4000000
910 #define bOFDMContinueTx 0x10000000
911 #define bOFDMSingleCarrier 0x20000000
912 #define bOFDMSingleTone 0x40000000
913 #define bHTDetect 0x100
914 #define bCFOEn 0x10000
915 #define bCFOValue 0xfff00000
916 #define bSigTone_Re 0x3f
917 #define bSigTone_Im 0x7f00
918 #define bCounter_CCA 0xffff
919 #define bCounter_ParityFail 0xffff0000
920 #define bCounter_RateIllegal 0xffff
921 #define bCounter_CRC8Fail 0xffff0000
922 #define bCounter_MCSNoSupport 0xffff
923 #define bCounter_FastSync 0xffff
924 #define bShortCFO 0xfff
925 #define bShortCFOTLength 12 /* total */
926 #define bShortCFOFLength 11 /* fraction */
927 #define bLongCFO 0x7ff
928 #define bLongCFOTLength 11
929 #define bLongCFOFLength 11
930 #define bTailCFO 0x1fff
931 #define bTailCFOTLength 13
932 #define bTailCFOFLength 12
933 #define bmax_en_pwdB 0xffff
934 #define bCC_power_dB 0xffff0000
935 #define bnoise_pwdB 0xffff
936 #define bPowerMeasTLength 10
937 #define bPowerMeasFLength 3
938 #define bRx_HT_BW 0x1
941 #define bNB_intf_det_on 0x1
942 #define bIntf_win_len_cfg 0x30
943 #define bNB_Intf_TH_cfg 0x1c0
945 #define bTableSel 0x40
947 #define bRxSNR_A 0xff
948 #define bRxSNR_B 0xff00
949 #define bRxSNR_C 0xff0000
950 #define bRxSNR_D 0xff000000
951 #define bSNREVMTLength 8
952 #define bSNREVMFLength 1
954 #define bCSI2nd 0xff00
955 #define bRxEVM1st 0xff0000
956 #define bRxEVM2nd 0xff000000
959 #define bSGIEN 0x10000
961 #define bSFactorQAM1 0xf /* Useless */
962 #define bSFactorQAM2 0xf0
963 #define bSFactorQAM3 0xf00
964 #define bSFactorQAM4 0xf000
965 #define bSFactorQAM5 0xf0000
966 #define bSFactorQAM6 0xf0000
967 #define bSFactorQAM7 0xf00000
968 #define bSFactorQAM8 0xf000000
969 #define bSFactorQAM9 0xf0000000
970 #define bCSIScheme 0x100000
972 #define bNoiseLvlTopSet 0x3 /* Useless */
973 #define bChSmooth 0x4
974 #define bChSmoothCfg1 0x38
975 #define bChSmoothCfg2 0x1c0
976 #define bChSmoothCfg3 0xe00
977 #define bChSmoothCfg4 0x7000
978 #define bMRCMode 0x800000
979 #define bTHEVMCfg 0x7000000
981 #define bLoopFitType 0x1 /* Useless */
983 #define bUpdCFOOffData 0x80
984 #define bAdvUpdCFO 0x100
985 #define bAdvTimeCtrl 0x800
986 #define bUpdClko 0x1000
988 #define bTrackingMode 0x8000
989 #define bPhCmpEnable 0x10000
990 #define bUpdClkoLTF 0x20000
991 #define bComChCFO 0x40000
992 #define bCSIEstiMode 0x80000
993 #define bAdvUpdEqz 0x100000
994 #define bUChCfg 0x7000000
995 #define bUpdEqz 0x8000000
997 /* Rx Pseduo noise */
998 #define bRxPesudoNoiseOn 0x20000000 /* Useless */
999 #define bRxPesudoNoise_A 0xff
1000 #define bRxPesudoNoise_B 0xff00
1001 #define bRxPesudoNoise_C 0xff0000
1002 #define bRxPesudoNoise_D 0xff000000
1003 #define bPesudoNoiseState_A 0xffff
1004 #define bPesudoNoiseState_B 0xffff0000
1005 #define bPesudoNoiseState_C 0xffff
1006 #define bPesudoNoiseState_D 0xffff0000
1008 /* 7. RF Register */
1010 #define bZebra1_HSSIEnable 0x8 /* Useless */
1011 #define bZebra1_TRxControl 0xc00
1012 #define bZebra1_TRxGainSetting 0x07f
1013 #define bZebra1_RxCorner 0xc00
1014 #define bZebra1_TxChargePump 0x38
1015 #define bZebra1_RxChargePump 0x7
1016 #define bZebra1_ChannelNum 0xf80
1017 #define bZebra1_TxLPFBW 0x400
1018 #define bZebra1_RxLPFBW 0x600
1021 #define bRTL8256RegModeCtrl1 0x100 /* Useless */
1022 #define bRTL8256RegModeCtrl0 0x40
1023 #define bRTL8256_TxLPFBW 0x18
1024 #define bRTL8256_RxLPFBW 0x600
1027 #define bRTL8258_TxLPFBW 0xc /* Useless */
1028 #define bRTL8258_RxLPFBW 0xc00
1029 #define bRTL8258_RSSILPFBW 0xc0
1033 /* Other Definition */
1036 /* byte endable for sb_write */
1037 #define bByte0 0x1 /* Useless */
1045 /* for PutRegsetting & GetRegSetting BitMask */
1046 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1047 #define bMaskByte1 0xff00
1048 #define bMaskByte2 0xff0000
1049 #define bMaskByte3 0xff000000
1050 #define bMaskHWord 0xffff0000
1051 #define bMaskLWord 0x0000ffff
1052 #define bMaskDWord 0xffffffff
1053 #define bMask12Bits 0xfff
1054 #define bMaskH4Bits 0xf0000000
1055 #define bMaskOFDM_D 0xffc00000
1056 #define bMaskCCK 0x3f3f3f3f
1058 /* for PutRFRegsetting & GetRFRegSetting BitMask */
1059 #define bRFRegOffsetMask 0xfffff
1061 #define bEnable 0x1 /* Useless */
1062 #define bDisable 0x0
1064 #define LeftAntenna 0x0 /* Useless */
1065 #define RightAntenna 0x1
1067 #define tCheckTxStatus 500 /* 500ms Useless */
1068 #define tUpdateRxCounter 100 /* 100ms */
1070 #define rateCCK 0 /* Useless */
1074 /* define Register-End */
1075 #define bPMAC_End 0x1ff /* Useless */
1076 #define bFPGAPHY0_End 0x8ff
1077 #define bFPGAPHY1_End 0x9ff
1078 #define bCCKPHY0_End 0xaff
1079 #define bOFDMPHY0_End 0xcff
1080 #define bOFDMPHY1_End 0xdff
1082 #define bPMACControl 0x0 /* Useless */
1083 #define bWMACControl 0x1
1084 #define bWNICControl 0x2
1086 #define PathA 0x0 /* Useless */
1091 /*--------------------------Define Parameters-------------------------------*/