1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
22 #ifndef __HALDMOUTSRC_H__
23 #define __HALDMOUTSRC_H__
26 /* Define all team support ability. */
28 /* Define for all teams. Please Define the constant in your precomp header. */
30 /* define DM_ODM_SUPPORT_AP 0 */
31 /* define DM_ODM_SUPPORT_ADSL 0 */
32 /* define DM_ODM_SUPPORT_CE 0 */
33 /* define DM_ODM_SUPPORT_MP 1 */
35 /* Define ODM SW team support flag. */
37 /* Antenna Switch Relative Definition. */
39 /* Add new function SwAntDivCheck8192C(). */
40 /* This is the main function of Antenna diversity function before link. */
41 /* Mainly, it just retains last scan result and scan again. */
42 /* After that, it compares the scan result to see which one gets better
43 * RSSI. It selects antenna with better receiving power and returns better
49 #define TRAFFIC_HIGH 1
51 /* 3 Tx Power Tracking */
52 /* 3============================================================ */
53 #define DPK_DELTA_MAPPING_NUM 13
54 #define index_mapping_HP_NUM 15
59 /* 3============================================================ */
61 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
62 #define MODE_40M 0 /* 0:20M, 1:40M */
64 #define PSD_CHM 20 /* Minimum channel number for BT AFH */
65 #define SIR_STEP_SIZE 3
66 #define Smooth_Size_1 5
68 #define Smooth_Size_2 10
70 #define Smooth_Size_3 20
72 #define Smooth_Step_Size 5
73 #define Adaptive_SIR 1
75 #define PSD_SCAN_INTERVAL 700 /* ms */
77 /* 8723A High Power IGI Setting */
78 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
79 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
80 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
83 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
84 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
85 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
86 #define RSSI_OFFSET_DIG 0x05;
89 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
90 #define ANTTESTA 0x01 /* Ant A will be Testing */
91 #define ANTTESTB 0x02 /* Ant B will be testing */
93 /* structure and define */
95 /* Add for AP/ADSLpseudo DM structuer requirement. */
96 /* We need to remove to other position??? */
97 struct rtl8192cd_priv {
103 u8 Dig_Ext_Port_Stage;
111 u8 CurSTAConnectState;
112 u8 PreSTAConnectState;
113 u8 CurMultiSTAConnectState;
120 s8 BackoffVal_range_max;
121 s8 BackoffVal_range_min;
122 u8 rx_gain_range_max;
123 u8 rx_gain_range_min;
135 u8 DIG_Dynamic_MIN_0;
136 u8 DIG_Dynamic_MIN_1;
137 bool bMediaConnect_0;
138 bool bMediaConnect_1;
154 u32 Reg874,RegC70,Reg85C,RegA74;
158 struct false_alarm_stats {
160 u32 Cnt_Rate_Illegal;
167 u32 Cnt_SB_Search_fail;
171 u32 Cnt_BW_USC; /* Gary */
172 u32 Cnt_BW_LSC; /* Gary */
175 struct dyn_primary_cca {
186 u8 PSD_bitmap_RXHP[80];
191 bool First_time_enter;
194 struct timer_list PSDTimer;
197 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
198 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
200 /* This indicates two different steps. */
201 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
202 * the signal on the air. */
203 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
204 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
207 #define SWAW_STEP_PEAK 0
208 #define SWAW_STEP_DETERMINE 1
212 #define TRAFFIC_LOW 0
213 #define TRAFFIC_HIGH 1
215 struct sw_ant_switch {
222 u8 bTriggerAntennaSwitch;
226 /* Before link Antenna Switch check */
227 u8 SWAS_NoLink_State;
228 u32 SWAS_NoLink_BK_Reg860;
229 bool ANTA_ON; /* To indicate Ant A is or not */
230 bool ANTB_ON; /* To indicate Ant B is on or not */
243 struct timer_list SwAntennaSwitchTimer;
244 /* Hybrid Antenna Diversity */
245 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
246 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
247 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
248 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
249 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
250 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
251 u8 TxAnt[ASSOCIATE_ENTRY_NUM];
258 bool bCurrentTurboEDCA;
260 u32 prv_traffic_idx; /* edca turbo */
263 struct odm_rate_adapt {
264 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
265 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
266 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
267 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
268 u32 LastRATR; /* RATR Register Content */
271 #define IQK_MAC_REG_NUM 4
272 #define IQK_ADDA_REG_NUM 16
273 #define IQK_BB_REG_NUM_MAX 10
274 #define IQK_BB_REG_NUM 9
275 #define HP_THERMAL_NUM 8
277 #define AVG_THERMAL_NUM 8
278 #define IQK_Matrix_REG_NUM 8
279 #define IQK_Matrix_Settings_NUM 1+24+21
281 #define DM_Type_ByFWi 0
282 #define DM_Type_ByDriver 1
284 /* Declare for common info */
286 #define MAX_PATH_NUM_92CS 2
288 struct odm_phy_status_info {
290 u8 SignalQuality; /* in 0-100 index. */
291 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
292 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
293 s8 RxPower; /* in dBm Translate from PWdB */
294 s8 RecvSignalPower;/* Real power in dBm for this packet, no
295 * beautification and aggregation. Keep this raw
296 * info to be used for the other procedures. */
297 u8 BTRxRSSIPercentage;
298 u8 SignalStrength; /* in 0-100 index. */
299 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
300 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
303 struct odm_phy_dbg_info {
304 /* ODM Write,debug info */
305 s8 RxSNRdB[MAX_PATH_NUM_92CS];
307 u64 NumQryPhyStatusCCK;
308 u64 NumQryPhyStatusOFDM;
310 s32 RxEVM[MAX_PATH_NUM_92CS];
313 struct odm_per_pkt_info {
316 bool bPacketMatchBSSID;
321 struct odm_mac_status_info {
327 ODM_DIG = 0x00000001,
328 ODM_HIGH_POWER = 0x00000002,
329 ODM_CCK_CCA_TH = 0x00000004,
330 ODM_FA_STATISTICS = 0x00000008,
331 ODM_RAMASK = 0x00000010,
332 ODM_RSSI_MONITOR = 0x00000020,
333 ODM_SW_ANTDIV = 0x00000040,
334 ODM_HW_ANTDIV = 0x00000080,
335 ODM_BB_PWRSV = 0x00000100,
336 ODM_2TPATHDIV = 0x00000200,
337 ODM_1TPATHDIV = 0x00000400,
338 ODM_PSD2AFH = 0x00000800
341 /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */
342 /* Please declare below ODM relative info in your STA info structure. */
344 struct odm_sta_info {
346 bool bUsed; /* record the sta status link or not? */
347 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
350 /* 1 PHY_STATUS_INFO */
351 u8 RSSI_Path[4]; /* */
357 /* 2011/10/20 MH Define Common info enum for all team. */
359 enum odm_common_info_def {
362 /* HOOK BEFORE REG INIT----------- */
363 ODM_CMNINFO_PLATFORM = 0,
364 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
365 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
366 ODM_CMNINFO_MP_TEST_CHIP,
367 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
368 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
369 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */
370 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
371 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
372 ODM_CMNINFO_EXT_LNA, /* true */
374 ODM_CMNINFO_EXT_TRSW,
375 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
376 ODM_CMNINFO_BINHCT_TEST,
377 ODM_CMNINFO_BWIFI_TEST,
378 ODM_CMNINFO_SMART_CONCURRENT,
379 /* HOOK BEFORE REG INIT----------- */
382 /* POINTER REFERENCE----------- */
383 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
386 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
387 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
388 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
389 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
390 ODM_CMNINFO_BW, /* ODM_BW_E */
393 ODM_CMNINFO_DMSP_GET_VALUE,
394 ODM_CMNINFO_BUDDY_ADAPTOR,
395 ODM_CMNINFO_DMSP_IS_MASTER,
397 ODM_CMNINFO_POWER_SAVING,
398 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
399 ODM_CMNINFO_DRV_STOP,
402 ODM_CMNINFO_ANT_TEST,
403 ODM_CMNINFO_NET_CLOSED,
405 /* POINTER REFERENCE----------- */
407 /* CALL BY VALUE------------- */
408 ODM_CMNINFO_WIFI_DIRECT,
409 ODM_CMNINFO_WIFI_DISPLAY,
411 ODM_CMNINFO_RSSI_MIN,
412 ODM_CMNINFO_DBG_COMP, /* u64 */
413 ODM_CMNINFO_DBG_LEVEL, /* u32 */
414 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
415 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
416 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
417 ODM_CMNINFO_BT_DISABLED,
418 ODM_CMNINFO_BT_OPERATION,
420 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
421 ODM_CMNINFO_BT_DISABLE_EDCA,
422 /* CALL BY VALUE-------------*/
424 /* Dynamic ptr array hook itms. */
425 ODM_CMNINFO_STA_STATUS,
426 ODM_CMNINFO_PHY_STATUS,
427 ODM_CMNINFO_MAC_STATUS,
431 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
433 enum odm_ability_def {
434 /* BB ODM section BIT 0-15 */
436 ODM_BB_RA_MASK = BIT1,
437 ODM_BB_DYNAMIC_TXPWR = BIT2,
438 ODM_BB_FA_CNT = BIT3,
439 ODM_BB_RSSI_MONITOR = BIT4,
440 ODM_BB_CCK_PD = BIT5,
441 ODM_BB_ANT_DIV = BIT6,
442 ODM_BB_PWR_SAVE = BIT7,
443 ODM_BB_PWR_TRA = BIT8,
444 ODM_BB_RATE_ADAPTIVE = BIT9,
445 ODM_BB_PATH_DIV = BIT10,
449 /* MAC DM section BIT 16-23 */
450 ODM_MAC_EDCA_TURBO = BIT16,
451 ODM_MAC_EARLY_MODE = BIT17,
453 /* RF ODM section BIT 24-31 */
454 ODM_RF_TX_PWR_TRACK = BIT24,
455 ODM_RF_RX_GAIN_TRACK = BIT25,
456 ODM_RF_CALIBRATION = BIT26,
459 /* ODM_CMNINFO_INTERFACE */
460 enum odm_interface_def {
467 /* ODM_CMNINFO_IC_TYPE */
478 #define ODM_IC_11N_SERIES \
479 (ODM_RTL8192S | ODM_RTL8192C | ODM_RTL8192D | \
480 ODM_RTL8723A | ODM_RTL8188E)
481 #define ODM_IC_11AC_SERIES (ODM_RTL8812)
483 /* ODM_CMNINFO_CUT_VER */
484 enum odm_cut_version {
494 /* ODM_CMNINFO_FAB_VER */
495 enum odm_fab_Version {
500 /* ODM_CMNINFO_RF_TYPE */
501 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
524 /* ODM Dynamic common info value definition */
526 enum odm_mac_phy_mode {
532 enum odm_bt_coexist {
539 /* ODM_CMNINFO_OP_MODE */
540 enum odm_operation_mode {
544 ODM_POWERSAVE = BIT3,
546 ODM_CLIENT_MODE = BIT5,
548 ODM_WIFI_DIRECT = BIT7,
549 ODM_WIFI_DISPLAY = BIT8,
552 /* ODM_CMNINFO_WM_MODE */
553 enum odm_wireless_mode {
564 /* ODM_CMNINFO_BAND */
566 ODM_BAND_2_4G = BIT0,
570 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
571 enum odm_sec_chnl_offset {
577 /* ODM_CMNINFO_SEC_MODE */
585 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
598 /* ODM_CMNINFO_BOARD_TYPE */
599 enum odm_board_type {
600 ODM_BOARD_NORMAL = 0,
601 ODM_BOARD_HIGHPWR = 1,
602 ODM_BOARD_MINICARD = 2,
607 /* ODM_CMNINFO_ONE_PATH_CCA */
635 u8 PTActive; /* on or off */
636 u8 PTTryState; /* 0 trying state, 1 for decision state */
637 u8 PTStage; /* 0~6 */
638 u8 PTStopCount; /* Stop PT counter */
639 u8 PTPreRate; /* if rate change do PT */
640 u8 PTPreRssi; /* if RSSI change 5% do PT */
641 u8 PTModeSS; /* decide whitch rate should do PT */
642 u8 RAstage; /* StageRA, decide how many times RA will be done
647 struct ijk_matrix_regs_set {
649 s32 Value[1][IQK_Matrix_REG_NUM];
653 /* for tx power tracking */
654 u32 RegA24; /* for TempCCK */
661 bool bTXPowerTrackingInit;
662 bool bTXPowerTracking;
663 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
666 u8 InternalPA5G[2]; /* pathA / pathB */
668 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
674 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
675 u8 ThermalValue_AVG_index;
676 u8 ThermalValue_RxGain;
677 u8 ThermalValue_Crystal;
678 u8 ThermalValue_DPKstore;
679 u8 ThermalValue_DPKtrack;
680 bool TxPowerTrackingInProgress;
683 bool bReloadtxpowerindex;
685 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
692 u8 ThermalValue_HP[HP_THERMAL_NUM];
693 u8 ThermalValue_HP_index;
694 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
709 bool bIQKInitialized;
711 bool bAntennaDetected;
712 u32 ADDA_backup[IQK_ADDA_REG_NUM];
713 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
714 u32 IQK_BB_backup_recover[9];
715 u32 IQK_BB_backup[IQK_BB_REG_NUM];
718 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
720 u8 bAPKThermalMeterIgnore;
726 /* ODM Dynamic common info value definition */
728 struct fast_ant_train {
738 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
739 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
740 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
741 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
742 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
743 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
744 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
750 FAT_NORMAL_STATE = 0,
751 FAT_TRAINING_STATE = 1,
756 CG_TRX_HW_ANTDIV = 0x01,
757 CGCS_RX_HW_ANTDIV = 0x02,
758 FIXED_HW_ANTDIV = 0x03,
759 CG_TRX_SMART_ANTDIV = 0x04,
760 CGCS_RX_SW_ANTDIV = 0x05,
763 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
764 struct odm_dm_struct {
765 /* Add for different team use temporarily */
766 struct adapter *Adapter; /* For CE/NIC team */
767 struct rtl8192cd_priv *priv; /* For AP/ADSL team */
768 /* WHen you use above pointers, they must be initialized. */
771 struct rtl8192cd_priv *fake_priv;
775 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
777 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
779 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
781 /* 1 COMMON INFORMATION */
783 /* HOOK BEFORE REG INIT----------- */
784 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
786 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
788 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
790 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
791 * other type = 1/2/3/... */
793 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
795 /* Fab Version TSMC/UMC = 0/1 */
797 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
799 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
801 /* with external LNA NO/Yes = 0/1 */
803 /* with external PA NO/Yes = 0/1 */
805 /* with external TRSW NO/Yes = 0/1 */
807 u8 PatchID; /* Customer ID */
811 bool bDualMacSmartConcurrent;
812 u32 BK_SupportAbility;
814 /* HOOK BEFORE REG INIT----------- */
817 /* POINTER REFERENCE----------- */
821 struct adapter *adapter_temp;
823 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
825 /* TX Unicast byte count */
826 u64 *pNumTxBytesUnicast;
827 /* RX Unicast byte count */
828 u64 *pNumRxBytesUnicast;
829 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
830 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
831 /* Frequence band 2.4G/5G = 0/1 */
833 /* Secondary channel offset don't_care/below/above = 0/1/2 */
835 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
837 /* BW info 20M/40M/80M = 0/1/2 */
839 /* Central channel location Ch1/Ch2/.... */
840 u8 *pChannel; /* central channel number */
841 /* Common info for 92D DMSP */
843 bool *pbGetValueFromOtherMac;
844 struct adapter **pBuddyAdapter;
845 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
846 /* Common info for Status */
847 bool *pbScanInProcess;
849 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
851 /* pMgntInfo->AntennaTest */
854 /* POINTER REFERENCE----------- */
856 /* CALL BY VALUE------------- */
861 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
864 /* Common info for BTDM */
865 bool bBtDisabled; /* BT is disabled */
866 bool bBtHsOperation; /* BT HS mode is under progress */
867 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
868 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the
870 bool bBtBusy; /* BT is busy. */
871 /* CALL BY VALUE------------- */
873 /* 2 Define STA info. */
875 /* For MP, we need to reduce one array pointer for default port.?? */
876 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
879 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
880 * array index. STA MacID=0,
881 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
883 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
884 /* We need to colelct all support abilit to a proper area. */
888 /* Define ........... */
890 /* Latest packet phy info (ODM write) */
891 struct odm_phy_dbg_info PhyDbgInfo;
893 /* Latest packet phy info (ODM write) */
894 struct odm_mac_status_info *pMacInfo;
896 /* Different Team independt structure?? */
899 struct fast_ant_train DM_FatTable;
900 struct rtw_dig DM_DigTable;
901 struct rtl_ps DM_PSTable;
902 struct dyn_primary_cca DM_PriCCA;
903 struct rx_hpc DM_RXHP_Table;
904 struct false_alarm_stats FalseAlmCnt;
905 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
906 struct sw_ant_switch DM_SWAT_Table;
909 struct edca_turbo DM_EDCA_Table;
911 /* Copy from SD4 structure */
913 /* ================================================== */
916 bool *pbDriverStopped;
917 bool *pbDriverIsGoingToPnpSetPowerSleep;
918 bool *pinit_adpt_in_progress;
921 bool bUserAssignLevel;
922 struct timer_list PSDTimer;
923 u8 RSSI_BT; /* come from BT */
925 bool bDMInitialGainEnable;
927 /* for rate adaptive, in fact, 88c/92c fw will handle this */
930 struct odm_rate_adapt RateAdaptive;
932 struct odm_rf_cal RFCalibrateInfo;
934 /* TX power tracking */
936 u8 BbSwingIdxOfdmCurrent;
937 u8 BbSwingIdxOfdmBase;
938 bool BbSwingFlagOfdm;
940 u8 BbSwingIdxCckCurrent;
941 u8 BbSwingIdxCckBase;
944 /* ODM system resource. */
946 /* ODM relative time. */
947 struct timer_list PathDivSwitchTimer;
948 /* 2011.09.27 add for Path Diversity */
949 struct timer_list CCKPathDiversityTimer;
950 struct timer_list FastAntTrainingTimer;
951 }; /* DM_Dynamic_Mechanism_Structure */
953 #define ODM_RF_PATH_MAX 2
955 enum ODM_RF_RADIO_PATH {
956 ODM_RF_PATH_A = 0, /* Radio Path A */
957 ODM_RF_PATH_B = 1, /* Radio Path B */
958 ODM_RF_PATH_C = 2, /* Radio Path C */
959 ODM_RF_PATH_D = 3, /* Radio Path D */
962 enum ODM_RF_CONTENT {
963 odm_radioa_txt = 0x1000,
964 odm_radiob_txt = 0x1001,
965 odm_radioc_txt = 0x1002,
966 odm_radiod_txt = 0x1003
969 enum odm_bb_config_type {
972 CONFIG_BB_AGC_TAB_2G,
973 CONFIG_BB_AGC_TAB_5G,
974 CONFIG_BB_PHY_REG_PG,
983 RT_STATUS_INVALID_CONTEXT,
984 RT_STATUS_INVALID_PARAMETER,
985 RT_STATUS_NOT_SUPPORT,
986 RT_STATUS_OS_API_FAILED,
989 /* 3=========================================================== */
991 /* 3=========================================================== */
994 RT_TYPE_THRESH_HIGH = 0,
995 RT_TYPE_THRESH_LOW = 1,
997 RT_TYPE_RX_GAIN_MIN = 3,
998 RT_TYPE_RX_GAIN_MAX = 4,
1000 RT_TYPE_DISABLE = 6,
1004 #define DM_DIG_THRESH_HIGH 40
1005 #define DM_DIG_THRESH_LOW 35
1007 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
1010 #define DM_false_ALARM_THRESH_LOW 400
1011 #define DM_false_ALARM_THRESH_HIGH 1000
1013 #define DM_DIG_MAX_NIC 0x4e
1014 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
1016 #define DM_DIG_MAX_AP 0x32
1017 #define DM_DIG_MIN_AP 0x20
1019 #define DM_DIG_MAX_NIC_HP 0x46
1020 #define DM_DIG_MIN_NIC_HP 0x2e
1022 #define DM_DIG_MAX_AP_HP 0x42
1023 #define DM_DIG_MIN_AP_HP 0x30
1025 /* vivi 92c&92d has different definition, 20110504 */
1026 /* this is for 92c */
1027 #define DM_DIG_FA_TH0 0x200/* 0x20 */
1028 #define DM_DIG_FA_TH1 0x300/* 0x100 */
1029 #define DM_DIG_FA_TH2 0x400/* 0x200 */
1030 /* this is for 92d */
1031 #define DM_DIG_FA_TH0_92D 0x100
1032 #define DM_DIG_FA_TH1_92D 0x400
1033 #define DM_DIG_FA_TH2_92D 0x600
1035 #define DM_DIG_BACKOFF_MAX 12
1036 #define DM_DIG_BACKOFF_MIN -4
1037 #define DM_DIG_BACKOFF_DEFAULT 10
1039 /* 3=========================================================== */
1040 /* 3 AGC RX High Power Mode */
1041 /* 3=========================================================== */
1042 #define LNA_Low_Gain_1 0x64
1043 #define LNA_Low_Gain_2 0x5A
1044 #define LNA_Low_Gain_3 0x58
1046 #define FA_RXHP_TH1 5000
1047 #define FA_RXHP_TH2 1500
1048 #define FA_RXHP_TH3 800
1049 #define FA_RXHP_TH4 600
1050 #define FA_RXHP_TH5 500
1052 /* 3=========================================================== */
1054 /* 3=========================================================== */
1056 /* 3=========================================================== */
1057 /* 3 Dynamic Tx Power */
1058 /* 3=========================================================== */
1059 /* Dynamic Tx Power Control Threshold */
1060 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1061 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1062 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
1064 #define TxHighPwrLevel_Normal 0
1065 #define TxHighPwrLevel_Level1 1
1066 #define TxHighPwrLevel_Level2 2
1067 #define TxHighPwrLevel_BT1 3
1068 #define TxHighPwrLevel_BT2 4
1069 #define TxHighPwrLevel_15 5
1070 #define TxHighPwrLevel_35 6
1071 #define TxHighPwrLevel_50 7
1072 #define TxHighPwrLevel_70 8
1073 #define TxHighPwrLevel_100 9
1075 /* 3=========================================================== */
1076 /* 3 Rate Adaptive */
1077 /* 3=========================================================== */
1078 #define DM_RATR_STA_INIT 0
1079 #define DM_RATR_STA_HIGH 1
1080 #define DM_RATR_STA_MIDDLE 2
1081 #define DM_RATR_STA_LOW 3
1083 /* 3=========================================================== */
1084 /* 3 BB Power Save */
1085 /* 3=========================================================== */
1100 /* 3=========================================================== */
1101 /* 3 Antenna Diversity */
1102 /* 3=========================================================== */
1109 /* Maximal number of antenna detection mechanism needs to perform. */
1110 #define MAX_ANTENNA_DETECTION_CNT 10
1112 /* Extern Global Variables. */
1113 #define OFDM_TABLE_SIZE_92C 37
1114 #define OFDM_TABLE_SIZE_92D 43
1115 #define CCK_TABLE_SIZE 33
1117 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1118 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1119 extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
1121 /* check Sta pointer valid or not */
1122 #define IS_STA_VALID(pSta) (pSta)
1123 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1124 /* This indicates two different the steps. */
1125 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1126 * signal on the air. */
1127 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1129 /* with original RSSI to determine if it is necessary to switch antenna. */
1130 #define SWAW_STEP_PEAK 0
1131 #define SWAW_STEP_DETERMINE 1
1133 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1134 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1136 void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna);
1139 #define dm_RF_Saving ODM_RF_Saving
1140 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1142 #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
1143 void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm);
1145 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1146 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1148 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1149 bool bForceUpdate, u8 *pRATRState);
1151 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
1152 void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID,
1153 struct odm_phy_status_info *pPhyInfo);
1155 u32 ConvertTo_dB(u32 Value);
1157 u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point,
1158 u8 initial_gain_psd);
1160 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1162 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1163 u32 ra_mask, u8 rssi_level);
1165 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1167 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1169 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1170 enum odm_common_info_def CmnInfo, u32 Value);
1172 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1173 enum odm_common_info_def CmnInfo, void *pValue);
1175 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1176 enum odm_common_info_def CmnInfo,
1177 u16 Index, void *pValue);
1179 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1181 void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm);
1183 void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm);
1185 void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm);
1187 void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm);
1189 void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId,
1190 u32 PWDBAll, bool isCCKrate);
1192 void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm);
1194 bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode);
1196 void odm_dtc(struct odm_dm_struct *pDM_Odm);