drivers/staging/rtl8188eu/include/pwrseq.h

   1
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  18  *
  19  *
  20  ******************************************************************************/
  21
  22 #ifndef __HAL8188EPWRSEQ_H__
  23 #define __HAL8188EPWRSEQ_H__
  24
  25 #include "pwrseqcmd.h"
  26
  27 /*
  28         Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
  29         There are 6 HW Power States:
  30         0: POFF--Power Off
  31         1: PDN--Power Down
  32         2: CARDEMU--Card Emulation
  33         3: ACT--Active Mode
  34         4: LPS--Low Power State
  35         5: SUS--Suspend
  36
  37         The transision from different states are defined below
  38         TRANS_CARDEMU_TO_ACT
  39         TRANS_ACT_TO_CARDEMU
  40         TRANS_CARDEMU_TO_SUS
  41         TRANS_SUS_TO_CARDEMU
  42         TRANS_CARDEMU_TO_PDN
  43         TRANS_ACT_TO_LPS
  44         TRANS_LPS_TO_ACT
  45
  46         TRANS_END
  47
  48     PWR SEQ Version: rtl8188E_PwrSeq_V09.h
  49 */
  50 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS     10
  51 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS     10
  52 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS     10
  53 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS     10
  54 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS     10
  55 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS     10
  56 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS         15
  57 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS         15
  58 #define RTL8188E_TRANS_END_STEPS                1
  59
  60
  61 #define RTL8188E_TRANS_CARDEMU_TO_ACT                                   \
  62         /* format
  63          * { offset, cut_msk, interface_msk, base|cmd, msk, value
  64          * },
  65          * comment here
  66          */                                                             \
  67         {0x0006, PWR_CUT_ALL_MSK, \
  68         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},             \
  69         /* wait till 0x04[17] = 1    power ready*/      \
  70         {0x0002, PWR_CUT_ALL_MSK, \
  71         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0},           \
  72         /* 0x02[1:0] = 0        reset BB*/                              \
  73         {0x0026, PWR_CUT_ALL_MSK, \
  74         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
  75         /*0x24[23] = 2b'01 schmit trigger */                            \
  76         {0x0005, PWR_CUT_ALL_MSK, \
  77         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                    \
  78         /* 0x04[15] = 0 disable HWPDN (control by DRV)*/                \
  79         {0x0005, PWR_CUT_ALL_MSK, \
  80         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0},           \
  81         /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
  82         {0x0005, PWR_CUT_ALL_MSK, \
  83         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},               \
  84         /*0x04[8] = 1 polling until return 0*/                          \
  85         {0x0005, PWR_CUT_ALL_MSK, \
  86         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},                  \
  87         /*wait till 0x04[8] = 0*/                                       \
  88         {0x0023, PWR_CUT_ALL_MSK, \
  89         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
  90         /*LDO normal mode*/
  91
  92 #define RTL8188E_TRANS_ACT_TO_CARDEMU                                   \
  93         /* format
  94          * { offset, cut_msk, interface_msk, base|cmd, msk, value
  95          * },
  96          * comments here
  97          */                                                             \
  98         {0x001F, PWR_CUT_ALL_MSK, \
  99         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},                      \
 100         /*0x1F[7:0] = 0 turn off RF*/                                   \
 101         {0x0023, PWR_CUT_ALL_MSK, \
 102         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
 103         /*LDO Sleep mode*/                                              \
 104         {0x0005, PWR_CUT_ALL_MSK, \
 105         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
 106         /*0x04[9] = 1 turn off MAC by HW state machine*/                \
 107         {0x0005, PWR_CUT_ALL_MSK, \
 108         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},                  \
 109         /*wait till 0x04[9] = 0 polling until return 0 to disable*/
 110
 111 #define RTL8188E_TRANS_CARDEMU_TO_SUS                                   \
 112         /* format
 113          * { offset, cut_msk, interface_msk, base|cmd, msk,
 114          * value },
 115          * comments here
 116          */                                                             \
 117         {0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 118         PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},                        \
 119         /* 0x04[12:11] = 2b'01enable WL suspend */                      \
 120         {0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 121         PWR_CMD_WRITE, 0xFF, BIT(7)},                                   \
 122         /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 123         {0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 124         PWR_CMD_WRITE, BIT(4), 0},                                      \
 125         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 126         {0xfe10, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 127         PWR_CMD_WRITE, BIT(4), BIT(4)},                                 \
 128         /*Set USB suspend enable local register  0xfe10[4]=1 */
 129
 130 #define RTL8188E_TRANS_SUS_TO_CARDEMU                                   \
 131         /* format
 132          * { offset, cut_msk, interface_msk, base|cmd, msk,
 133          * value },
 134          * comments here
 135          */                                                             \
 136         {0x0005, PWR_CUT_ALL_MSK, \
 137         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0},           \
 138         /*0x04[12:11] = 2b'01enable WL suspend*/
 139
 140 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS                               \
 141         /* format
 142          * { offset, cut_msk, interface_msk, base|cmd, msk,
 143          * value },
 144          * comments here
 145          */                                                             \
 146         {0x0026, PWR_CUT_ALL_MSK, \
 147         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
 148         /*0x24[23] = 2b'01 schmit trigger */                            \
 149         {0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 150         PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},                        \
 151         /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
 152         {0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 153         PWR_CMD_WRITE, 0xFF, 0},                                        \
 154         /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 155         {0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,             \
 156         PWR_CMD_WRITE, BIT(4), 0},                                      \
 157         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 158         {0xfe10, PWR_CUT_ALL_MSK,       \
 159         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
 160         /*Set USB suspend enable local register  0xfe10[4]=1 */
 161
 162 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU                               \
 163         /* format
 164          * { offset, cut_msk, interface_msk, base|cmd, msk,
 165          * value },
 166          * comments here
 167          */                                                             \
 168         {0x0005, PWR_CUT_ALL_MSK, \
 169         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0},           \
 170         /*0x04[12:11] = 2b'01enable WL suspend*/
 171
 172 #define RTL8188E_TRANS_CARDEMU_TO_PDN                                   \
 173         /* format
 174          * { offset, cut_msk, interface_msk, base|cmd, msk,
 175          * value },
 176          * comments here
 177          */                                                             \
 178         {0x0006, PWR_CUT_ALL_MSK, \
 179         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                    \
 180         /* 0x04[16] = 0*/                                               \
 181         {0x0005, PWR_CUT_ALL_MSK, \
 182         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
 183         /* 0x04[15] = 1*/
 184
 185 #define RTL8188E_TRANS_PDN_TO_CARDEMU                                   \
 186         /* format
 187          * { offset, cut_msk, interface_msk, base|cmd, msk,
 188          * value },
 189          * comments here
 190          */                                                             \
 191         {0x0005, PWR_CUT_ALL_MSK, \
 192         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                    \
 193         /* 0x04[15] = 0*/
 194
 195 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
 196 #define RTL8188E_TRANS_ACT_TO_LPS                                       \
 197         /* format
 198          * { offset, cut_msk, interface_msk, base|cmd, msk,
 199          * value },
 200          * comments here
 201          */                                                             \
 202         {0x0522, PWR_CUT_ALL_MSK, \
 203         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/       \
 204         {0x05F8, PWR_CUT_ALL_MSK, \
 205         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 206         /*Should be zero if no packet is transmitting*/                 \
 207         {0x05F9, PWR_CUT_ALL_MSK, \
 208         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 209         /*Should be zero if no packet is transmitting*/                 \
 210         {0x05FA, PWR_CUT_ALL_MSK, \
 211         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 212         /*Should be zero if no packet is transmitting*/                 \
 213         {0x05FB, PWR_CUT_ALL_MSK, \
 214         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 215         /*Should be zero if no packet is transmitting*/                 \
 216         {0x0002, PWR_CUT_ALL_MSK, \
 217         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                    \
 218         /*CCK and OFDM are disabled,and clock are gated*/               \
 219         {0x0002, PWR_CUT_ALL_MSK, \
 220         PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0,                             \
 221         PWRSEQ_DELAY_US},/*Delay 1us*/                                  \
 222         {0x0100, PWR_CUT_ALL_MSK, \
 223         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/  \
 224         {0x0101, PWR_CUT_ALL_MSK, \
 225         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\
 226         {0x0553, PWR_CUT_ALL_MSK, \
 227         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},               \
 228         /*Respond TxOK to scheduler*/
 229
 230
 231 #define RTL8188E_TRANS_LPS_TO_ACT                                       \
 232         /* format
 233          * { offset, cut_msk, interface_msk, base|cmd, msk,
 234          * value },
 235          * comments here
 236          */                                                             \
 237         {0xFE58, PWR_CUT_ALL_MSK, \
 238         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/      \
 239         {0x0002, PWR_CUT_ALL_MSK, \
 240         PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
 241         {0x0008, PWR_CUT_ALL_MSK, \
 242         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 243         /* 0x08[4] = 0 switch TSF to 40M */                             \
 244         {0x0109, PWR_CUT_ALL_MSK, \
 245         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},                  \
 246         /* Polling 0x109[7]=0  TSF in 40M */                            \
 247         {0x0029, PWR_CUT_ALL_MSK, \
 248         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0},           \
 249         /* 0x29[7:6] = 2b'00  enable BB clock */                        \
 250         {0x0101, PWR_CUT_ALL_MSK, \
 251         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
 252         /* 0x101[1] = 1 */                                              \
 253         {0x0100, PWR_CUT_ALL_MSK, \
 254         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                   \
 255         /* 0x100[7:0] = 0xFF enable WMAC TRX */                         \
 256         {0x0002, PWR_CUT_ALL_MSK, \
 257         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
 258         /* 0x02[1:0] = 2b'11 enable BB macro */                         \
 259         {0x0522, PWR_CUT_ALL_MSK, \
 260         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.  0x522 = 0*/
 261
 262 #define RTL8188E_TRANS_END                                              \
 263         /* format
 264          * { offset, cut_msk, interface_msk, base|cmd, msk,
 265          * value },
 266          * comments here
 267          */                                                             \
 268         {0xFFFF, PWR_CUT_ALL_MSK, 0,    \
 269         PWR_CMD_END, 0, 0},
 270
 271
 272 extern struct wl_pwr_cfg rtl8188E_power_on_flow
 273                 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
 274 extern struct wl_pwr_cfg rtl8188E_radio_off_flow
 275                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
 276 extern struct wl_pwr_cfg rtl8188E_card_disable_flow
 277                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 278                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 279                 RTL8188E_TRANS_END_STEPS];
 280 extern struct wl_pwr_cfg rtl8188E_card_enable_flow
 281                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 282                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 283                 RTL8188E_TRANS_END_STEPS];
 284 extern struct wl_pwr_cfg rtl8188E_suspend_flow[
 285                 RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 286                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 287                 RTL8188E_TRANS_END_STEPS];
 288 extern struct wl_pwr_cfg rtl8188E_resume_flow
 289                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 290                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 291                 RTL8188E_TRANS_END_STEPS];
 292 extern struct wl_pwr_cfg rtl8188E_hwpdn_flow
 293                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 294                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
 295 extern struct wl_pwr_cfg rtl8188E_enter_lps_flow
 296                 [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
 297 extern struct wl_pwr_cfg rtl8188E_leave_lps_flow
 298                 [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
 299
 300 #endif /* __HAL8188EPWRSEQ_H__ */