3 #include "r819xE_phyreg.h"
4 #include "r8190_rtl8256.h"
5 #include "r819xE_phy.h"
8 #include "ieee80211/dot11d.h"
10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
28 static u32 Rtl8192PciEMACPHY_Array[] = {
29 0x03c,0xffff0000,0x00000f0f,
30 0x340,0xffffffff,0x161a1a1a,
31 0x344,0xffffffff,0x12121416,
32 0x348,0x0000ffff,0x00001818,
33 0x12c,0xffffffff,0x04000802,
34 0x318,0x00000fff,0x00000100,
36 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
37 0x03c,0xffff0000,0x00000f0f,
38 0xe00,0xffffffff,0x06090909,
39 0xe04,0xffffffff,0x00030306,
40 0xe08,0x0000ff00,0x00000000,
41 0xe10,0xffffffff,0x0a0c0d0f,
42 0xe14,0xffffffff,0x06070809,
43 0xe18,0xffffffff,0x0a0c0d0f,
44 0xe1c,0xffffffff,0x06070809,
45 0x12c,0xffffffff,0x04000802,
46 0x318,0x00000fff,0x00000800,
48 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
242 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
244 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
394 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
519 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
560 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
562 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
565 /*************************Define local function prototype**********************/
567 static u32 phy_FwRFSerialRead(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset);
568 static void phy_FwRFSerialWrite(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
570 /*************************Define local function prototype**********************/
571 /******************************************************************************
572 *function: This function read BB parameters from Header file we gen,
573 * and do register read/write
574 * input: u32 dwBitMask //taget bit pos in the addr to be modified
576 * return: u32 return the shift bit bit position of the mask
577 * ****************************************************************************/
578 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
581 for (i=0; i<=31; i++)
583 if (((dwBitMask>>i)&0x1) == 1)
588 /******************************************************************************
589 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
592 * return: 0(illegal, false), 1(legal,true)
593 * ***************************************************************************/
594 u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath)
598 if (priv->rf_type == RF_2T4R)
600 else if (priv->rf_type == RF_1T2R)
602 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
604 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
610 /******************************************************************************
611 *function: This function set specific bits to BB register
612 * input: net_device dev
613 * u32 dwRegAddr //target addr to be modified
614 * u32 dwBitMask //taget bit pos in the addr to be modified
615 * u32 dwData //value to be write
619 * ****************************************************************************/
620 void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
622 u32 OriginalValue, BitShift, NewValue;
624 if(dwBitMask!= bMaskDWord)
625 {//if not "double word" write
626 OriginalValue = read_nic_dword(priv, dwRegAddr);
627 BitShift = rtl8192_CalculateBitShift(dwBitMask);
628 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
629 write_nic_dword(priv, dwRegAddr, NewValue);
631 write_nic_dword(priv, dwRegAddr, dwData);
633 /******************************************************************************
634 *function: This function reads specific bits from BB register
635 * input: net_device dev
636 * u32 dwRegAddr //target addr to be readback
637 * u32 dwBitMask //taget bit pos in the addr to be readback
639 * return: u32 Data //the readback register value
641 * ****************************************************************************/
642 u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask)
644 u32 OriginalValue, BitShift;
646 OriginalValue = read_nic_dword(priv, dwRegAddr);
647 BitShift = rtl8192_CalculateBitShift(dwBitMask);
648 return (OriginalValue & dwBitMask) >> BitShift;
650 /******************************************************************************
651 *function: This function read register from RF chip
652 * input: net_device dev
653 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
654 * u32 Offset //target address to be read
656 * return: u32 readback value
657 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
658 * ****************************************************************************/
659 static u32 rtl8192_phy_RFSerialRead(struct r8192_priv *priv,
660 RF90_RADIO_PATH_E eRFPath, u32 Offset)
664 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
665 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
666 //make sure RF register offset is correct
669 //switch page for 8256 RF IC
670 //analog to digital off, for protection
671 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
674 priv->RfReg0Value[eRFPath] |= 0x140;
675 //Switch to Reg_Mode2 for Reg 31-45
676 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
678 NewOffset = Offset -30;
680 else if (Offset >= 16)
682 priv->RfReg0Value[eRFPath] |= 0x100;
683 priv->RfReg0Value[eRFPath] &= (~0x40);
684 //Switch to Reg_Mode 1 for Reg16-30
685 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
687 NewOffset = Offset - 15;
692 //put desired read addr to LSSI control Register
693 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
694 //Issue a posedge trigger
696 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
697 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
700 // TODO: we should not delay such a long time. Ask help from SD3
703 ret = rtl8192_QueryBBReg(priv, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
706 // Switch back to Reg_Mode0;
707 priv->RfReg0Value[eRFPath] &= 0xebf;
711 pPhyReg->rf3wireOffset,
713 (priv->RfReg0Value[eRFPath] << 16));
715 //analog to digital on
716 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
721 /******************************************************************************
722 *function: This function write data to RF register
723 * input: net_device dev
724 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
725 * u32 Offset //target address to be written
726 * u32 Data //The new register data to be written
729 * notice: For RF8256 only.
730 ===========================================================
731 *Reg Mode RegCTL[1] RegCTL[0] Note
732 * (Reg00[12]) (Reg00[10])
733 *===========================================================
734 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
735 *------------------------------------------------------------------
736 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
737 *------------------------------------------------------------------
738 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
739 *------------------------------------------------------------------
740 * ****************************************************************************/
741 static void rtl8192_phy_RFSerialWrite(struct r8192_priv *priv,
742 RF90_RADIO_PATH_E eRFPath, u32 Offset,
745 u32 DataAndAddr = 0, NewOffset = 0;
746 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
750 //analog to digital off, for protection
751 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
755 priv->RfReg0Value[eRFPath] |= 0x140;
756 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
757 NewOffset = Offset - 30;
759 else if (Offset >= 16)
761 priv->RfReg0Value[eRFPath] |= 0x100;
762 priv->RfReg0Value[eRFPath] &= (~0x40);
763 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
764 NewOffset = Offset - 15;
769 // Put write addr in [5:0] and write data in [31:16]
770 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
773 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
777 priv->RfReg0Value[eRFPath] = Data;
779 // Switch back to Reg_Mode0;
782 priv->RfReg0Value[eRFPath] &= 0xebf;
785 pPhyReg->rf3wireOffset,
787 (priv->RfReg0Value[eRFPath] << 16));
789 //analog to digital on
790 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
793 /******************************************************************************
794 *function: This function set specific bits to RF register
795 * input: RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
796 * u32 RegAddr //target addr to be modified
797 * u32 BitMask //taget bit pos in the addr to be modified
798 * u32 Data //value to be write
802 * ****************************************************************************/
803 void rtl8192_phy_SetRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath,
804 u32 RegAddr, u32 BitMask, u32 Data)
806 u32 Original_Value, BitShift, New_Value;
809 if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
811 if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter)
813 //down(&priv->rf_sem);
815 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
816 if (priv->Rf_Mode == RF_OP_By_FW)
818 if (BitMask != bMask12Bits) // RF data is 12 bits only
820 Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr);
821 BitShift = rtl8192_CalculateBitShift(BitMask);
822 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
824 phy_FwRFSerialWrite(priv, eRFPath, RegAddr, New_Value);
826 phy_FwRFSerialWrite(priv, eRFPath, RegAddr, Data);
832 if (BitMask != bMask12Bits) // RF data is 12 bits only
834 Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr);
835 BitShift = rtl8192_CalculateBitShift(BitMask);
836 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
838 rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, New_Value);
840 rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, Data);
845 /******************************************************************************
846 *function: This function reads specific bits from RF register
847 * input: net_device dev
848 * u32 RegAddr //target addr to be readback
849 * u32 BitMask //taget bit pos in the addr to be readback
851 * return: u32 Data //the readback register value
853 * ****************************************************************************/
854 u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath,
855 u32 RegAddr, u32 BitMask)
857 u32 Original_Value, Readback_Value, BitShift;
859 if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
861 if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter)
864 if (priv->Rf_Mode == RF_OP_By_FW)
866 Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr);
871 Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr);
874 BitShift = rtl8192_CalculateBitShift(BitMask);
875 Readback_Value = (Original_Value & BitMask) >> BitShift;
878 return Readback_Value;
881 /******************************************************************************
882 *function: We support firmware to execute RF-R/W.
887 * ***************************************************************************/
888 static u32 phy_FwRFSerialRead(struct r8192_priv *priv,
889 RF90_RADIO_PATH_E eRFPath, u32 Offset)
893 //DbgPrint("FW RF CTRL\n\r");
894 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
895 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
896 much time. This is only for site survey. */
897 // 1. Read operation need not insert data. bit 0-11
898 //Data &= bMask12Bits;
899 // 2. Write RF register address. Bit 12-19
900 Data |= ((Offset&0xFF)<<12);
901 // 3. Write RF path. bit 20-21
902 Data |= ((eRFPath&0x3)<<20);
903 // 4. Set RF read indicator. bit 22=0
905 // 5. Trigger Fw to operate the command. bit 31
907 // 6. We can not execute read operation if bit 31 is 1.
908 while (read_nic_dword(priv, QPNR)&0x80000000)
910 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
913 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
919 // 7. Execute read operation.
920 write_nic_dword(priv, QPNR, Data);
921 // 8. Check if firmawre send back RF content.
922 while (read_nic_dword(priv, QPNR)&0x80000000)
924 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
927 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
933 return read_nic_dword(priv, RF_DATA);
936 /******************************************************************************
937 *function: We support firmware to execute RF-R/W.
942 * ***************************************************************************/
943 static void phy_FwRFSerialWrite(struct r8192_priv *priv,
944 RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
948 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
949 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
950 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
951 much time. This is only for site survey. */
953 // 1. Set driver write bit and 12 bit data. bit 0-11
954 //Data &= bMask12Bits; // Done by uper layer.
955 // 2. Write RF register address. bit 12-19
956 Data |= ((Offset&0xFF)<<12);
957 // 3. Write RF path. bit 20-21
958 Data |= ((eRFPath&0x3)<<20);
959 // 4. Set RF write indicator. bit 22=1
961 // 5. Trigger Fw to operate the command. bit 31=1
964 // 6. Write operation. We can not write if bit 31 is 1.
965 while (read_nic_dword(priv, QPNR)&0x80000000)
967 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
970 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
976 // 7. No matter check bit. We always force the write. Because FW will
977 // not accept the command.
978 write_nic_dword(priv, QPNR, Data);
979 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
980 to finish RF write operation. */
981 /* 2008/01/17 MH We support delay in firmware side now. */
987 /******************************************************************************
988 *function: This function read BB parameters from Header file we gen,
989 * and do register read/write
993 * notice: BB parameters may change all the time, so please make
994 * sure it has been synced with the newest.
995 * ***************************************************************************/
996 void rtl8192_phy_configmac(struct r8192_priv *priv)
998 u32 dwArrayLen = 0, i = 0;
999 u32* pdwArray = NULL;
1001 if(Adapter->bInHctTest)
1003 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1004 dwArrayLen = MACPHY_ArrayLengthDTM;
1005 pdwArray = Rtl819XMACPHY_ArrayDTM;
1007 else if(priv->bTXPowerDataReadFromEEPORM)
1009 if(priv->bTXPowerDataReadFromEEPORM)
1011 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1012 dwArrayLen = MACPHY_Array_PGLength;
1013 pdwArray = Rtl819XMACPHY_Array_PG;
1018 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1019 dwArrayLen = MACPHY_ArrayLength;
1020 pdwArray = Rtl819XMACPHY_Array;
1022 for(i = 0; i<dwArrayLen; i=i+3){
1023 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1024 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1025 if(pdwArray[i] == 0x318)
1027 pdwArray[i+2] = 0x00000800;
1028 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1029 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1031 rtl8192_setBBreg(priv, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1035 /******************************************************************************
1036 *function: This function do dirty work
1040 * notice: BB parameters may change all the time, so please make
1041 * sure it has been synced with the newest.
1042 * ***************************************************************************/
1044 void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType)
1048 u32* Rtl819XPHY_REGArray_Table = NULL;
1049 u32* Rtl819XAGCTAB_Array_Table = NULL;
1050 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1052 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1053 if(Adapter->bInHctTest)
1055 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1056 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1058 if(priv->RF_Type == RF_2T4R)
1060 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1061 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1063 else if (priv->RF_Type == RF_1T2R)
1065 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1066 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1072 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1073 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1074 if(priv->rf_type == RF_2T4R)
1076 PHY_REGArrayLen = PHY_REGArrayLength;
1077 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
1079 else if (priv->rf_type == RF_1T2R)
1081 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
1082 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
1086 if (ConfigType == BaseBand_Config_PHY_REG)
1088 for (i=0; i<PHY_REGArrayLen; i+=2)
1090 rtl8192_setBBreg(priv, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1091 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1094 else if (ConfigType == BaseBand_Config_AGC_TAB)
1096 for (i=0; i<AGCTAB_ArrayLen; i+=2)
1098 rtl8192_setBBreg(priv, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1099 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
1103 /******************************************************************************
1104 *function: This function initialize Register definition offset for Radio Path
1106 * input: net_device dev
1109 * notice: Initialization value here is constant and it should never be changed
1110 * ***************************************************************************/
1111 static void rtl8192_InitBBRFRegDef(struct r8192_priv *priv)
1113 // RF Interface Sowrtware Control
1114 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1115 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1116 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1117 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1119 // RF Interface Readback Value
1120 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1121 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1122 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1123 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1125 // RF Interface Output (and Enable)
1126 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1127 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1128 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1129 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1131 // RF Interface (Output and) Enable
1132 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1133 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1134 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1135 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1137 //Addr of LSSI. Wirte RF register by driver
1138 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1139 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1140 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1141 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1144 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
1145 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1146 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1147 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1149 // Tx AGC Gain Stage (same for all path. Should we remove this?)
1150 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1151 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1152 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1153 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1155 // Tranceiver A~D HSSI Parameter-1
1156 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
1157 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
1158 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
1159 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
1161 // Tranceiver A~D HSSI Parameter-2
1162 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
1163 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
1164 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
1165 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
1167 // RF switch Control
1168 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1169 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1170 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1171 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1174 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1175 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1176 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1177 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1180 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1181 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1182 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1183 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1186 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1187 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1188 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1189 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1192 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1193 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1194 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1195 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1198 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1199 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1200 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1201 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1204 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1205 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1206 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1207 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1209 // Tranceiver LSSI Readback
1210 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1211 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1212 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1213 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1216 /******************************************************************************
1217 *function: This function is to write register and then readback to make sure whether BB and RF is OK
1218 * input: net_device dev
1219 * HW90_BLOCK_E CheckBlock
1220 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
1222 * return: return whether BB and RF is ok(0:OK; 1:Fail)
1223 * notice: This function may be removed in the ASIC
1224 * ***************************************************************************/
1225 RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv,
1226 HW90_BLOCK_E CheckBlock,
1227 RF90_RADIO_PATH_E eRFPath)
1229 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1230 RT_STATUS ret = RT_STATUS_SUCCESS;
1231 u32 i, CheckTimes = 4, dwRegRead = 0;
1233 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1234 // Initialize register address offset to be checked
1235 WriteAddr[HW90_BLOCK_MAC] = 0x100;
1236 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1237 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1238 WriteAddr[HW90_BLOCK_RF] = 0x3;
1239 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
1240 for(i=0 ; i < CheckTimes ; i++)
1244 // Write Data to register and readback
1248 case HW90_BLOCK_MAC:
1249 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1252 case HW90_BLOCK_PHY0:
1253 case HW90_BLOCK_PHY1:
1254 write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
1255 dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
1259 WriteData[i] &= 0xfff;
1260 rtl8192_phy_SetRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
1261 // TODO: we should not delay for such a long time. Ask SD3
1263 dwRegRead = rtl8192_phy_QueryRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1268 ret = RT_STATUS_FAILURE;
1274 // Check whether readback data is correct
1276 if(dwRegRead != WriteData[i])
1278 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x\n", dwRegRead, WriteData[i]);
1279 ret = RT_STATUS_FAILURE;
1288 /******************************************************************************
1289 *function: This function initialize BB&RF
1290 * input: net_device dev
1293 * notice: Initialization value may change all the time, so please make
1294 * sure it has been synced with the newest.
1295 * ***************************************************************************/
1296 static RT_STATUS rtl8192_BB_Config_ParaFile(struct r8192_priv *priv)
1298 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1300 u8 bRegValue = 0, eCheckItem = 0;
1302 /**************************************
1303 //<1>Initialize BaseBand
1304 **************************************/
1306 /*--set BB Global Reset--*/
1307 bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
1308 write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
1310 /*---set BB reset Active---*/
1311 dwRegValue = read_nic_dword(priv, CPU_GEN);
1312 write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
1314 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
1315 // TODO: this function should be removed on ASIC , Emily 2007.2.2
1316 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
1318 rtStatus = rtl8192_phy_checkBBAndRF(priv, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
1319 if(rtStatus != RT_STATUS_SUCCESS)
1321 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
1325 /*---- Set CCK and OFDM Block "OFF"----*/
1326 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
1327 /*----BB Register Initilazation----*/
1328 //==m==>Set PHY REG From Header<==m==
1329 rtl8192_phyConfigBB(priv, BaseBand_Config_PHY_REG);
1331 /*----Set BB reset de-Active----*/
1332 dwRegValue = read_nic_dword(priv, CPU_GEN);
1333 write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
1335 /*----BB AGC table Initialization----*/
1336 //==m==>Set PHY REG From Header<==m==
1337 rtl8192_phyConfigBB(priv, BaseBand_Config_AGC_TAB);
1339 if (priv->card_8192_version > VERSION_8190_BD)
1341 if(priv->rf_type == RF_2T4R)
1343 // Antenna gain offset from B/C/D to A
1344 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1345 priv->AntennaTxPwDiff[1]<<4 |
1346 priv->AntennaTxPwDiff[0]);
1349 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
1350 rtl8192_setBBreg(priv, rFPGA0_TxGainStage,
1351 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
1355 dwRegValue = priv->CrystalCap;
1356 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
1359 // Check if the CCK HighPower is turned ON.
1360 // This is used to calculate PWDB.
1361 // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1364 /******************************************************************************
1365 *function: This function initialize BB&RF
1366 * input: net_device dev
1369 * notice: Initialization value may change all the time, so please make
1370 * sure it has been synced with the newest.
1371 * ***************************************************************************/
1372 RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv)
1374 rtl8192_InitBBRFRegDef(priv);
1375 //config BB&RF. As hardCode based initialization has not been well
1376 //implemented, so use file first.FIXME:should implement it for hardcode?
1377 return rtl8192_BB_Config_ParaFile(priv);
1380 /******************************************************************************
1381 *function: This function obtains the initialization value of Tx power Level offset
1382 * input: net_device dev
1385 * ***************************************************************************/
1386 void rtl8192_phy_getTxPower(struct r8192_priv *priv)
1388 priv->MCSTxPowerLevelOriginalOffset[0] =
1389 read_nic_dword(priv, rTxAGC_Rate18_06);
1390 priv->MCSTxPowerLevelOriginalOffset[1] =
1391 read_nic_dword(priv, rTxAGC_Rate54_24);
1392 priv->MCSTxPowerLevelOriginalOffset[2] =
1393 read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
1394 priv->MCSTxPowerLevelOriginalOffset[3] =
1395 read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
1396 priv->MCSTxPowerLevelOriginalOffset[4] =
1397 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
1398 priv->MCSTxPowerLevelOriginalOffset[5] =
1399 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
1401 // read rx initial gain
1402 priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
1403 priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
1404 priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
1405 priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
1406 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1407 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1408 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1411 priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
1412 priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
1413 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
1414 rOFDM0_RxDetector3, priv->framesync);
1415 // read SIFS (save the value read fome MACPHY_REG.txt)
1416 priv->SifsTime = read_nic_word(priv, SIFS);
1419 /******************************************************************************
1420 *function: This function obtains the initialization value of Tx power Level offset
1421 * input: net_device dev
1424 * ***************************************************************************/
1425 void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel)
1427 u8 powerlevel = 0,powerlevelOFDM24G = 0;
1431 if(priv->epromtype == EPROM_93c46)
1433 powerlevel = priv->TxPowerLevelCCK[channel-1];
1434 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1436 else if(priv->epromtype == EPROM_93c56)
1438 if(priv->rf_type == RF_1T2R)
1440 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
1441 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
1443 else if(priv->rf_type == RF_2T4R)
1445 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
1446 // Power must be calculated by the antenna diff.
1447 // So we have to rewrite Antenna gain offset register here.
1448 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
1449 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
1451 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
1452 -priv->TxPowerLevelOFDM24G_A[channel-1];
1453 ant_pwr_diff &= 0xf;
1455 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
1456 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
1457 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
1459 // Antenna gain offset from B/C/D to A
1460 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1461 priv->AntennaTxPwDiff[1]<<4 |
1462 priv->AntennaTxPwDiff[0]);
1464 rtl8192_setBBreg(priv, rFPGA0_TxGainStage,
1465 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1470 // CCX 2 S31, AP control of client transmit power:
1471 // 1. We shall not exceed Cell Power Limit as possible as we can.
1472 // 2. Tolerance is +/- 5dB.
1473 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
1476 // 1. 802.11h power contraint
1478 // 071011, by rcnjko.
1480 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
1481 pMgntInfo->bWithCcxCellPwr &&
1482 channel == pMgntInfo->dot11CurrentChannelNumber)
1484 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
1485 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
1486 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
1488 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1489 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1490 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
1491 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1492 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1493 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1496 if(powerlevel > CckCellPwrIdx)
1497 powerlevel = CckCellPwrIdx;
1498 // Legacy OFDM, HT OFDM
1499 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
1501 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
1503 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
1507 LegacyOfdmCellPwrIdx = 0;
1511 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1512 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1513 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1516 pHalData->CurrentCckTxPwrIdx = powerlevel;
1517 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1519 PHY_SetRF8256CCKTxPower(priv, powerlevel); //need further implement
1520 PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G);
1523 /******************************************************************************
1524 *function: This function check Rf chip to do RF config
1525 * input: net_device dev
1527 * return: only 8256 is supported
1528 * ***************************************************************************/
1529 RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv)
1531 return PHY_RF8256_Config(priv);
1534 /******************************************************************************
1535 *function: This function update Initial gain
1536 * input: net_device dev
1538 * return: As Windows has not implemented this, wait for complement
1539 * ***************************************************************************/
1540 void rtl8192_phy_updateInitGain(struct r8192_priv *priv)
1544 /******************************************************************************
1545 *function: This function read RF parameters from general head file, and do RF 3-wire
1546 * input: net_device dev
1548 * return: return code show if RF configuration is successful(0:pass, 1:fail)
1549 * Note: Delay may be required for RF configuration
1550 * ***************************************************************************/
1551 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv,
1552 RF90_RADIO_PATH_E eRFPath)
1561 for(i = 0;i<RadioA_ArrayLength; i=i+2){
1563 if(Rtl819XRadioA_Array[i] == 0xfe){
1567 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
1573 for(i = 0;i<RadioB_ArrayLength; i=i+2){
1575 if(Rtl819XRadioB_Array[i] == 0xfe){
1579 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
1585 for(i = 0;i<RadioC_ArrayLength; i=i+2){
1587 if(Rtl819XRadioC_Array[i] == 0xfe){
1591 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
1597 for(i = 0;i<RadioD_ArrayLength; i=i+2){
1599 if(Rtl819XRadioD_Array[i] == 0xfe){
1603 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
1615 /******************************************************************************
1616 *function: This function set Tx Power of the channel
1617 * input: struct net_device *dev
1622 * ***************************************************************************/
1623 static void rtl8192_SetTxPowerLevel(struct r8192_priv *priv, u8 channel)
1625 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1626 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1628 PHY_SetRF8256CCKTxPower(priv, powerlevel);
1629 PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G);
1632 /****************************************************************************************
1633 *function: This function set command table variable(struct SwChnlCmd).
1634 * input: SwChnlCmd* CmdTable //table to be set.
1635 * u32 CmdTableIdx //variable index in table to be set
1636 * u32 CmdTableSz //table size.
1637 * SwChnlCmdID CmdID //command ID to set.
1642 * return: true if finished, false otherwise
1644 * ************************************************************************************/
1645 static u8 rtl8192_phy_SetSwChnlCmdArray(
1646 SwChnlCmd* CmdTable,
1657 if(CmdTable == NULL)
1659 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1662 if(CmdTableIdx >= CmdTableSz)
1664 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1665 CmdTableIdx, CmdTableSz);
1669 pCmd = CmdTable + CmdTableIdx;
1670 pCmd->CmdID = CmdID;
1671 pCmd->Para1 = Para1;
1672 pCmd->Para2 = Para2;
1673 pCmd->msDelay = msDelay;
1677 /******************************************************************************
1678 *function: This function set channel step by step
1679 * input: struct net_device *dev
1681 * u8* stage //3 stages
1683 * u32* delay //whether need to delay
1684 * output: store new stage, step and delay for next step(combine with function above)
1685 * return: true if finished, false otherwise
1686 * Note: Wait for simpler function to replace it //wb
1687 * ***************************************************************************/
1688 static u8 rtl8192_phy_SwChnlStepByStep(struct r8192_priv *priv, u8 channel,
1689 u8* stage, u8* step, u32* delay)
1691 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1692 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1693 u32 PreCommonCmdCnt;
1694 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1695 u32 PostCommonCmdCnt;
1696 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1698 SwChnlCmd *CurrentCmd = NULL;
1699 //RF90_RADIO_PATH_E eRFPath;
1704 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1705 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1707 #ifdef ENABLE_DOT11D
1708 if (!IsLegalChannel(priv->ieee80211, channel))
1710 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1711 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1715 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1716 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1718 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1720 // <1> Fill up pre common command.
1721 PreCommonCmdCnt = 0;
1722 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1723 CmdID_SetTxPowerLevel, 0, 0, 0);
1724 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1725 CmdID_End, 0, 0, 0);
1727 // <2> Fill up post common command.
1728 PostCommonCmdCnt = 0;
1730 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1731 CmdID_End, 0, 0, 0);
1733 // <3> Fill up RF dependent command.
1736 // TEST!! This is not the table for 8256!!
1737 if (!(channel >= 1 && channel <= 14))
1739 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1742 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1743 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1744 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1745 CmdID_End, 0, 0, 0);
1751 CurrentCmd=&PreCommonCmd[*step];
1754 CurrentCmd=&RfDependCmd[*step];
1757 CurrentCmd=&PostCommonCmd[*step];
1761 if(CurrentCmd->CmdID==CmdID_End)
1775 switch(CurrentCmd->CmdID)
1777 case CmdID_SetTxPowerLevel:
1778 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
1779 rtl8192_SetTxPowerLevel(priv, channel);
1781 case CmdID_WritePortUlong:
1782 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
1784 case CmdID_WritePortUshort:
1785 write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1787 case CmdID_WritePortUchar:
1788 write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1790 case CmdID_RF_WriteReg:
1791 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
1792 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
1800 }/*for(Number of RF paths)*/
1802 (*delay)=CurrentCmd->msDelay;
1807 /******************************************************************************
1808 *function: This function does acturally set channel work
1809 * input: struct net_device *dev
1813 * Note: We should not call this function directly
1814 * ***************************************************************************/
1815 static void rtl8192_phy_FinishSwChnlNow(struct r8192_priv *priv, u8 channel)
1819 while (!rtl8192_phy_SwChnlStepByStep(priv, channel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
1822 msleep(delay);//or mdelay? need further consideration
1827 /******************************************************************************
1828 *function: Callback routine of the work item for switch channel.
1833 * ***************************************************************************/
1834 void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv)
1836 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1838 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
1840 rtl8192_phy_FinishSwChnlNow(priv, priv->chan);
1842 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1845 /******************************************************************************
1846 *function: This function scheduled actural workitem to set channel
1847 * input: net_device dev
1848 * u8 channel //channel to set
1850 * return: return code show if workitem is scheduled(1:pass, 0:fail)
1851 * Note: Delay may be required for RF configuration
1852 * ***************************************************************************/
1853 u8 rtl8192_phy_SwChnl(struct ieee80211_device *ieee80211, u8 channel)
1855 struct r8192_priv *priv = ieee80211_priv(ieee80211->dev);
1857 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
1860 if(priv->SwChnlInProgress)
1863 // if(pHalData->SetBWModeInProgress)
1866 //--------------------------------------------
1867 switch(priv->ieee80211->mode)
1869 case WIRELESS_MODE_A:
1870 case WIRELESS_MODE_N_5G:
1872 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1876 case WIRELESS_MODE_B:
1878 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1882 case WIRELESS_MODE_G:
1883 case WIRELESS_MODE_N_24G:
1885 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1890 //--------------------------------------------
1892 priv->SwChnlInProgress = true;
1898 priv->SwChnlStage=0;
1901 rtl8192_SwChnl_WorkItem(priv);
1903 priv->SwChnlInProgress = false;
1907 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct r8192_priv *priv)
1909 switch(priv->CurrentChannelBW)
1912 case HT_CHANNEL_WIDTH_20:
1913 //added by vivi, cck,tx power track, 20080703
1914 priv->CCKPresentAttentuation =
1915 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
1917 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1918 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1919 if(priv->CCKPresentAttentuation < 0)
1920 priv->CCKPresentAttentuation = 0;
1922 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1924 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
1926 priv->bcck_in_ch14 = TRUE;
1927 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1929 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1931 priv->bcck_in_ch14 = FALSE;
1932 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1935 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1939 case HT_CHANNEL_WIDTH_20_40:
1940 //added by vivi, cck,tx power track, 20080703
1941 priv->CCKPresentAttentuation =
1942 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
1944 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1945 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1946 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1947 if(priv->CCKPresentAttentuation < 0)
1948 priv->CCKPresentAttentuation = 0;
1950 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1952 priv->bcck_in_ch14 = TRUE;
1953 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1955 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1957 priv->bcck_in_ch14 = FALSE;
1958 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1961 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1966 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct r8192_priv *priv)
1968 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1969 priv->bcck_in_ch14 = TRUE;
1970 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1971 priv->bcck_in_ch14 = FALSE;
1973 //write to default index and tx power track will be done in dm.
1974 switch(priv->CurrentChannelBW)
1977 case HT_CHANNEL_WIDTH_20:
1978 if(priv->Record_CCK_20Mindex == 0)
1979 priv->Record_CCK_20Mindex = 6; //set default value.
1980 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
1981 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
1985 case HT_CHANNEL_WIDTH_20_40:
1986 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
1987 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
1990 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1993 static void CCK_Tx_Power_Track_BW_Switch(struct r8192_priv *priv)
1996 //if(pHalData->bDcut == TRUE)
1997 if(priv->IC_Cut >= IC_VersionCut_D)
1998 CCK_Tx_Power_Track_BW_Switch_TSSI(priv);
2000 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(priv);
2005 /******************************************************************************
2006 *function: Callback routine of the work item for set bandwidth mode.
2007 * input: struct net_device *dev
2008 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2009 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
2012 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2013 * test whether current work in the queue or not.//do I?
2014 * ***************************************************************************/
2015 void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv)
2019 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
2020 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
2025 priv->SetBWModeInProgress= false;
2028 //<1>Set MAC register
2029 regBwOpMode = read_nic_byte(priv, BW_OPMODE);
2031 switch(priv->CurrentChannelBW)
2033 case HT_CHANNEL_WIDTH_20:
2034 regBwOpMode |= BW_OPMODE_20MHZ;
2035 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2036 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2039 case HT_CHANNEL_WIDTH_20_40:
2040 regBwOpMode &= ~BW_OPMODE_20MHZ;
2041 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2042 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2046 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2050 //<2>Set PHY related register
2051 switch(priv->CurrentChannelBW)
2053 case HT_CHANNEL_WIDTH_20:
2054 // Add by Vivi 20071119
2055 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x0);
2056 rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x0);
2057 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
2059 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
2060 // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2061 // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2062 // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2063 if(!priv->btxpower_tracking)
2065 write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
2066 write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
2067 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
2070 CCK_Tx_Power_Track_BW_Switch(priv);
2072 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 1);
2074 case HT_CHANNEL_WIDTH_20_40:
2075 // Add by Vivi 20071119
2076 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x1);
2077 rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x1);
2078 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2079 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
2080 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2082 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2083 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2084 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2085 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2086 if(!priv->btxpower_tracking)
2088 write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
2089 write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
2090 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
2093 CCK_Tx_Power_Track_BW_Switch(priv);
2095 // Set Control channel to upper or lower. These settings are required only for 40MHz
2096 rtl8192_setBBreg(priv, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2097 rtl8192_setBBreg(priv, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2100 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 0);
2103 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
2107 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2109 //<3>Set RF related register
2110 PHY_SetRF8256Bandwidth(priv, priv->CurrentChannelBW);
2112 atomic_dec(&(priv->ieee80211->atm_swbw));
2113 priv->SetBWModeInProgress= false;
2115 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()\n");
2118 /******************************************************************************
2119 *function: This function schedules bandwith switch work.
2120 * input: struct net_device *dev
2121 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2122 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
2125 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2126 * test whether current work in the queue or not.//do I?
2127 * ***************************************************************************/
2128 void rtl8192_SetBWMode(struct ieee80211_device *ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2130 struct r8192_priv *priv = ieee80211_priv(ieee->dev);
2133 if(priv->SetBWModeInProgress)
2136 atomic_inc(&(priv->ieee80211->atm_swbw));
2137 priv->SetBWModeInProgress= true;
2139 priv->CurrentChannelBW = Bandwidth;
2141 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2142 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2143 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2144 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2146 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2148 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
2149 // schedule_work(&(priv->SetBWModeWorkItem));
2150 rtl8192_SetBWModeWorkItem(priv);
2155 void InitialGain819xPci(struct ieee80211_device *ieee, u8 Operation)
2157 #define SCAN_RX_INITIAL_GAIN 0x17
2158 #define POWER_DETECTION_TH 0x08
2159 struct r8192_priv *priv = ieee80211_priv(ieee->dev);
2168 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
2169 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
2170 BitMask = bMaskByte0;
2171 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2172 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2173 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XAAGCCore1, BitMask);
2174 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XBAGCCore1, BitMask);
2175 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XCAGCCore1, BitMask);
2176 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XDAGCCore1, BitMask);
2177 BitMask = bMaskByte2;
2178 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(priv, rCCK0_CCA, BitMask);
2180 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2181 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2182 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2183 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2184 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
2186 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
2187 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
2188 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
2189 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
2190 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
2191 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
2192 write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
2195 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
2196 BitMask = 0x7f; //Bit0~ Bit6
2197 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2198 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2200 rtl8192_setBBreg(priv, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
2201 rtl8192_setBBreg(priv, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
2202 rtl8192_setBBreg(priv, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
2203 rtl8192_setBBreg(priv, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
2204 BitMask = bMaskByte2;
2205 rtl8192_setBBreg(priv, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
2207 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2208 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2209 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2210 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2211 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
2213 rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel);
2216 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2217 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // FW DIG ON
2220 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");