3 #include "r819xE_phyreg.h"
4 #include "r8190_rtl8256.h"
5 #include "r819xE_phy.h"
8 #include "ieee80211/dot11d.h"
10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
28 u32 Rtl8190PciMACPHY_Array[] = {
29 0x03c,0xffff0000,0x00000f0f,
30 0x340,0xffffffff,0x161a1a1a,
31 0x344,0xffffffff,0x12121416,
32 0x348,0x0000ffff,0x00001818,
33 0x12c,0xffffffff,0x04000802,
34 0x318,0x00000fff,0x00000800,
36 u32 Rtl8190PciMACPHY_Array_PG[] = {
37 0x03c,0xffff0000,0x00000f0f,
38 0x340,0xffffffff,0x0a0c0d0f,
39 0x344,0xffffffff,0x06070809,
40 0x344,0xffffffff,0x06070809,
41 0x348,0x0000ffff,0x00000000,
42 0x12c,0xffffffff,0x04000802,
43 0x318,0x00000fff,0x00000800,
46 u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
241 u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
383 u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
526 u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
651 u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
692 u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
817 u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
860 static u32 Rtl8192PciEMACPHY_Array[] = {
861 0x03c,0xffff0000,0x00000f0f,
862 0x340,0xffffffff,0x161a1a1a,
863 0x344,0xffffffff,0x12121416,
864 0x348,0x0000ffff,0x00001818,
865 0x12c,0xffffffff,0x04000802,
866 0x318,0x00000fff,0x00000100,
868 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
869 0x03c,0xffff0000,0x00000f0f,
870 0xe00,0xffffffff,0x06090909,
871 0xe04,0xffffffff,0x00030306,
872 0xe08,0x0000ff00,0x00000000,
873 0xe10,0xffffffff,0x0a0c0d0f,
874 0xe14,0xffffffff,0x06070809,
875 0xe18,0xffffffff,0x0a0c0d0f,
876 0xe1c,0xffffffff,0x06070809,
877 0x12c,0xffffffff,0x04000802,
878 0x318,0x00000fff,0x00000800,
880 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
1074 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
1076 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
1226 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
1351 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
1392 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
1394 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
1398 /*************************Define local function prototype**********************/
1400 static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
1401 static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
1402 /*************************Define local function prototype**********************/
1403 /******************************************************************************
1404 *function: This function read BB parameters from Header file we gen,
1405 * and do register read/write
1406 * input: u32 dwBitMask //taget bit pos in the addr to be modified
1408 * return: u32 return the shift bit bit position of the mask
1409 * ****************************************************************************/
1410 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
1413 for (i=0; i<=31; i++)
1415 if (((dwBitMask>>i)&0x1) == 1)
1420 /******************************************************************************
1421 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
1424 * return: 0(illegal, false), 1(legal,true)
1425 * ***************************************************************************/
1426 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1429 struct r8192_priv *priv = ieee80211_priv(dev);
1431 if(priv->rf_type == RF_2T4R)
1435 else if (priv->rf_type == RF_1T2R)
1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1439 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1444 if (priv->rf_type == RF_2T4R)
1446 else if (priv->rf_type == RF_1T2R)
1448 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1450 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1457 /******************************************************************************
1458 *function: This function set specific bits to BB register
1459 * input: net_device dev
1460 * u32 dwRegAddr //target addr to be modified
1461 * u32 dwBitMask //taget bit pos in the addr to be modified
1462 * u32 dwData //value to be write
1466 * ****************************************************************************/
1467 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
1470 u32 OriginalValue, BitShift, NewValue;
1472 if(dwBitMask!= bMaskDWord)
1473 {//if not "double word" write
1474 OriginalValue = read_nic_dword(dev, dwRegAddr);
1475 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1476 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
1477 write_nic_dword(dev, dwRegAddr, NewValue);
1479 write_nic_dword(dev, dwRegAddr, dwData);
1482 /******************************************************************************
1483 *function: This function reads specific bits from BB register
1484 * input: net_device dev
1485 * u32 dwRegAddr //target addr to be readback
1486 * u32 dwBitMask //taget bit pos in the addr to be readback
1488 * return: u32 Data //the readback register value
1490 * ****************************************************************************/
1491 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
1493 u32 Ret = 0, OriginalValue, BitShift;
1495 OriginalValue = read_nic_dword(dev, dwRegAddr);
1496 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1497 Ret = (OriginalValue & dwBitMask) >> BitShift;
1501 /******************************************************************************
1502 *function: This function read register from RF chip
1503 * input: net_device dev
1504 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1505 * u32 Offset //target address to be read
1507 * return: u32 readback value
1508 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
1509 * ****************************************************************************/
1510 static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
1512 struct r8192_priv *priv = ieee80211_priv(dev);
1515 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
1516 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
1517 //make sure RF register offset is correct
1520 //switch page for 8256 RF IC
1521 if (priv->rf_chip == RF_8256)
1524 //analog to digital off, for protection
1525 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1528 //analog to digital off, for protection
1529 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1534 priv->RfReg0Value[eRFPath] |= 0x140;
1535 //Switch to Reg_Mode2 for Reg 31-45
1536 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1538 NewOffset = Offset -30;
1540 else if (Offset >= 16)
1542 priv->RfReg0Value[eRFPath] |= 0x100;
1543 priv->RfReg0Value[eRFPath] &= (~0x40);
1544 //Switch to Reg_Mode 1 for Reg16-30
1545 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1547 NewOffset = Offset - 15;
1554 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1557 //put desired read addr to LSSI control Register
1558 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
1559 //Issue a posedge trigger
1561 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
1562 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
1565 // TODO: we should not delay such a long time. Ask help from SD3
1568 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1571 // Switch back to Reg_Mode0;
1572 if(priv->rf_chip == RF_8256)
1574 priv->RfReg0Value[eRFPath] &= 0xebf;
1578 pPhyReg->rf3wireOffset,
1580 (priv->RfReg0Value[eRFPath] << 16));
1583 if(priv->rf_type == RF_2T4R)
1585 //analog to digital on
1586 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1588 else if(priv->rf_type == RF_1T2R)
1590 //analog to digital on
1591 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1595 //analog to digital on
1596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1606 /******************************************************************************
1607 *function: This function write data to RF register
1608 * input: net_device dev
1609 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1610 * u32 Offset //target address to be written
1611 * u32 Data //The new register data to be written
1614 * notice: For RF8256 only.
1615 ===========================================================
1616 *Reg Mode RegCTL[1] RegCTL[0] Note
1617 * (Reg00[12]) (Reg00[10])
1618 *===========================================================
1619 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
1620 *------------------------------------------------------------------
1621 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
1622 *------------------------------------------------------------------
1623 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
1624 *------------------------------------------------------------------
1625 * ****************************************************************************/
1626 static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
1628 struct r8192_priv *priv = ieee80211_priv(dev);
1629 u32 DataAndAddr = 0, NewOffset = 0;
1630 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1633 if (priv->rf_chip == RF_8256)
1637 //analog to digital off, for protection
1638 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1641 //analog to digital off, for protection
1642 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1648 priv->RfReg0Value[eRFPath] |= 0x140;
1649 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
1650 NewOffset = Offset - 30;
1652 else if (Offset >= 16)
1654 priv->RfReg0Value[eRFPath] |= 0x100;
1655 priv->RfReg0Value[eRFPath] &= (~0x40);
1656 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
1657 NewOffset = Offset - 15;
1664 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1668 // Put write addr in [5:0] and write data in [31:16]
1669 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1672 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1676 priv->RfReg0Value[eRFPath] = Data;
1678 // Switch back to Reg_Mode0;
1679 if(priv->rf_chip == RF_8256)
1683 priv->RfReg0Value[eRFPath] &= 0xebf;
1686 pPhyReg->rf3wireOffset,
1688 (priv->RfReg0Value[eRFPath] << 16));
1691 if(priv->rf_type == RF_2T4R)
1693 //analog to digital on
1694 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1696 else if(priv->rf_type == RF_1T2R)
1698 //analog to digital on
1699 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1703 //analog to digital on
1704 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1712 /******************************************************************************
1713 *function: This function set specific bits to RF register
1714 * input: net_device dev
1715 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1716 * u32 RegAddr //target addr to be modified
1717 * u32 BitMask //taget bit pos in the addr to be modified
1718 * u32 Data //value to be write
1722 * ****************************************************************************/
1723 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
1725 struct r8192_priv *priv = ieee80211_priv(dev);
1726 u32 Original_Value, BitShift, New_Value;
1729 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1732 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1735 //spin_lock_irqsave(&priv->rf_lock, flags);
1736 //down(&priv->rf_sem);
1738 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
1739 if (priv->Rf_Mode == RF_OP_By_FW)
1741 if (BitMask != bMask12Bits) // RF data is 12 bits only
1743 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1744 BitShift = rtl8192_CalculateBitShift(BitMask);
1745 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1747 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1749 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
1755 if (BitMask != bMask12Bits) // RF data is 12 bits only
1757 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1758 BitShift = rtl8192_CalculateBitShift(BitMask);
1759 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1761 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1763 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
1765 //spin_unlock_irqrestore(&priv->rf_lock, flags);
1766 //up(&priv->rf_sem);
1770 /******************************************************************************
1771 *function: This function reads specific bits from RF register
1772 * input: net_device dev
1773 * u32 RegAddr //target addr to be readback
1774 * u32 BitMask //taget bit pos in the addr to be readback
1776 * return: u32 Data //the readback register value
1778 * ****************************************************************************/
1779 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
1781 u32 Original_Value, Readback_Value, BitShift;
1782 struct r8192_priv *priv = ieee80211_priv(dev);
1783 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1786 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1789 down(&priv->rf_sem);
1790 if (priv->Rf_Mode == RF_OP_By_FW)
1792 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1797 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1800 BitShift = rtl8192_CalculateBitShift(BitMask);
1801 Readback_Value = (Original_Value & BitMask) >> BitShift;
1804 return (Readback_Value);
1807 /******************************************************************************
1808 *function: We support firmware to execute RF-R/W.
1813 * ***************************************************************************/
1814 static u32 phy_FwRFSerialRead(
1815 struct net_device* dev,
1816 RF90_RADIO_PATH_E eRFPath,
1822 //DbgPrint("FW RF CTRL\n\r");
1823 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1824 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1825 much time. This is only for site survey. */
1826 // 1. Read operation need not insert data. bit 0-11
1827 //Data &= bMask12Bits;
1828 // 2. Write RF register address. Bit 12-19
1829 Data |= ((Offset&0xFF)<<12);
1830 // 3. Write RF path. bit 20-21
1831 Data |= ((eRFPath&0x3)<<20);
1832 // 4. Set RF read indicator. bit 22=0
1834 // 5. Trigger Fw to operate the command. bit 31
1836 // 6. We can not execute read operation if bit 31 is 1.
1837 while (read_nic_dword(dev, QPNR)&0x80000000)
1839 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1842 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
1848 // 7. Execute read operation.
1849 write_nic_dword(dev, QPNR, Data);
1850 // 8. Check if firmawre send back RF content.
1851 while (read_nic_dword(dev, QPNR)&0x80000000)
1853 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1856 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1862 retValue = read_nic_dword(dev, RF_DATA);
1866 } /* phy_FwRFSerialRead */
1868 /******************************************************************************
1869 *function: We support firmware to execute RF-R/W.
1874 * ***************************************************************************/
1876 phy_FwRFSerialWrite(
1877 struct net_device* dev,
1878 RF90_RADIO_PATH_E eRFPath,
1884 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
1885 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1886 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1887 much time. This is only for site survey. */
1889 // 1. Set driver write bit and 12 bit data. bit 0-11
1890 //Data &= bMask12Bits; // Done by uper layer.
1891 // 2. Write RF register address. bit 12-19
1892 Data |= ((Offset&0xFF)<<12);
1893 // 3. Write RF path. bit 20-21
1894 Data |= ((eRFPath&0x3)<<20);
1895 // 4. Set RF write indicator. bit 22=1
1897 // 5. Trigger Fw to operate the command. bit 31=1
1900 // 6. Write operation. We can not write if bit 31 is 1.
1901 while (read_nic_dword(dev, QPNR)&0x80000000)
1903 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1906 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1912 // 7. No matter check bit. We always force the write. Because FW will
1913 // not accept the command.
1914 write_nic_dword(dev, QPNR, Data);
1915 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1916 to finish RF write operation. */
1917 /* 2008/01/17 MH We support delay in firmware side now. */
1920 } /* phy_FwRFSerialWrite */
1923 /******************************************************************************
1924 *function: This function read BB parameters from Header file we gen,
1925 * and do register read/write
1929 * notice: BB parameters may change all the time, so please make
1930 * sure it has been synced with the newest.
1931 * ***************************************************************************/
1932 void rtl8192_phy_configmac(struct net_device* dev)
1934 u32 dwArrayLen = 0, i = 0;
1935 u32* pdwArray = NULL;
1936 struct r8192_priv *priv = ieee80211_priv(dev);
1938 if(Adapter->bInHctTest)
1940 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1941 dwArrayLen = MACPHY_ArrayLengthDTM;
1942 pdwArray = Rtl819XMACPHY_ArrayDTM;
1944 else if(priv->bTXPowerDataReadFromEEPORM)
1946 if(priv->bTXPowerDataReadFromEEPORM)
1948 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1949 dwArrayLen = MACPHY_Array_PGLength;
1950 pdwArray = Rtl819XMACPHY_Array_PG;
1955 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1956 dwArrayLen = MACPHY_ArrayLength;
1957 pdwArray = Rtl819XMACPHY_Array;
1959 for(i = 0; i<dwArrayLen; i=i+3){
1960 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1961 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1962 if(pdwArray[i] == 0x318)
1964 pdwArray[i+2] = 0x00000800;
1965 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1966 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1968 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1974 /******************************************************************************
1975 *function: This function do dirty work
1979 * notice: BB parameters may change all the time, so please make
1980 * sure it has been synced with the newest.
1981 * ***************************************************************************/
1983 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1987 u32* Rtl819XPHY_REGArray_Table = NULL;
1988 u32* Rtl819XAGCTAB_Array_Table = NULL;
1989 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1990 struct r8192_priv *priv = ieee80211_priv(dev);
1992 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1993 if(Adapter->bInHctTest)
1995 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1996 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1998 if(priv->RF_Type == RF_2T4R)
2000 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
2001 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
2003 else if (priv->RF_Type == RF_1T2R)
2005 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
2006 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
2012 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
2013 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
2014 if(priv->rf_type == RF_2T4R)
2016 PHY_REGArrayLen = PHY_REGArrayLength;
2017 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
2019 else if (priv->rf_type == RF_1T2R)
2021 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
2022 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
2026 if (ConfigType == BaseBand_Config_PHY_REG)
2028 for (i=0; i<PHY_REGArrayLen; i+=2)
2030 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
2031 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
2034 else if (ConfigType == BaseBand_Config_AGC_TAB)
2036 for (i=0; i<AGCTAB_ArrayLen; i+=2)
2038 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
2039 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
2046 /******************************************************************************
2047 *function: This function initialize Register definition offset for Radio Path
2049 * input: net_device dev
2052 * notice: Initialization value here is constant and it should never be changed
2053 * ***************************************************************************/
2054 static void rtl8192_InitBBRFRegDef(struct net_device* dev)
2056 struct r8192_priv *priv = ieee80211_priv(dev);
2057 // RF Interface Sowrtware Control
2058 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2059 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2060 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2061 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2063 // RF Interface Readback Value
2064 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2065 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2066 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2067 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2069 // RF Interface Output (and Enable)
2070 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2071 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2072 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2073 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2075 // RF Interface (Output and) Enable
2076 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2077 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2078 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2079 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2081 //Addr of LSSI. Wirte RF register by driver
2082 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2083 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2084 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2085 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2088 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
2089 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2090 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2091 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2093 // Tx AGC Gain Stage (same for all path. Should we remove this?)
2094 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2095 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2096 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2097 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2099 // Tranceiver A~D HSSI Parameter-1
2100 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
2101 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
2102 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
2103 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
2105 // Tranceiver A~D HSSI Parameter-2
2106 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
2107 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
2108 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
2109 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
2111 // RF switch Control
2112 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2113 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2114 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2115 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2118 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2119 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2120 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2121 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2124 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2125 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2126 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2127 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2130 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2131 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2132 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2133 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2136 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2137 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2138 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2139 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2142 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2143 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2144 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2145 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2148 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2149 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2150 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2151 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2153 // Tranceiver LSSI Readback
2154 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2155 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2156 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2157 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2160 /******************************************************************************
2161 *function: This function is to write register and then readback to make sure whether BB and RF is OK
2162 * input: net_device dev
2163 * HW90_BLOCK_E CheckBlock
2164 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
2166 * return: return whether BB and RF is ok(0:OK; 1:Fail)
2167 * notice: This function may be removed in the ASIC
2168 * ***************************************************************************/
2169 RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
2171 //struct r8192_priv *priv = ieee80211_priv(dev);
2172 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
2173 RT_STATUS ret = RT_STATUS_SUCCESS;
2174 u32 i, CheckTimes = 4, dwRegRead = 0;
2176 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2177 // Initialize register address offset to be checked
2178 WriteAddr[HW90_BLOCK_MAC] = 0x100;
2179 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2180 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2181 WriteAddr[HW90_BLOCK_RF] = 0x3;
2182 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
2183 for(i=0 ; i < CheckTimes ; i++)
2187 // Write Data to register and readback
2191 case HW90_BLOCK_MAC:
2192 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
2195 case HW90_BLOCK_PHY0:
2196 case HW90_BLOCK_PHY1:
2197 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2198 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2202 WriteData[i] &= 0xfff;
2203 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
2204 // TODO: we should not delay for such a long time. Ask SD3
2206 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2211 ret = RT_STATUS_FAILURE;
2217 // Check whether readback data is correct
2219 if(dwRegRead != WriteData[i])
2221 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
2222 ret = RT_STATUS_FAILURE;
2231 /******************************************************************************
2232 *function: This function initialize BB&RF
2233 * input: net_device dev
2236 * notice: Initialization value may change all the time, so please make
2237 * sure it has been synced with the newest.
2238 * ***************************************************************************/
2239 static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2241 struct r8192_priv *priv = ieee80211_priv(dev);
2242 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2243 u8 bRegValue = 0, eCheckItem = 0;
2245 /**************************************
2246 //<1>Initialize BaseBand
2247 **************************************/
2249 /*--set BB Global Reset--*/
2250 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
2251 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
2253 /*---set BB reset Active---*/
2254 dwRegValue = read_nic_dword(dev, CPU_GEN);
2255 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
2257 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
2258 // TODO: this function should be removed on ASIC , Emily 2007.2.2
2259 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
2261 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
2262 if(rtStatus != RT_STATUS_SUCCESS)
2264 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
2268 /*---- Set CCK and OFDM Block "OFF"----*/
2269 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
2270 /*----BB Register Initilazation----*/
2271 //==m==>Set PHY REG From Header<==m==
2272 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
2274 /*----Set BB reset de-Active----*/
2275 dwRegValue = read_nic_dword(dev, CPU_GEN);
2276 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
2278 /*----BB AGC table Initialization----*/
2279 //==m==>Set PHY REG From Header<==m==
2280 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
2282 if (priv->card_8192_version > VERSION_8190_BD)
2284 if(priv->rf_type == RF_2T4R)
2286 // Antenna gain offset from B/C/D to A
2287 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2288 priv->AntennaTxPwDiff[1]<<4 |
2289 priv->AntennaTxPwDiff[0]);
2292 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
2293 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2294 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2299 dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap
2300 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
2301 dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
2302 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
2305 dwRegValue = priv->CrystalCap;
2306 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
2312 // Check if the CCK HighPower is turned ON.
2313 // This is used to calculate PWDB.
2314 // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
2317 /******************************************************************************
2318 *function: This function initialize BB&RF
2319 * input: net_device dev
2322 * notice: Initialization value may change all the time, so please make
2323 * sure it has been synced with the newest.
2324 * ***************************************************************************/
2325 RT_STATUS rtl8192_BBConfig(struct net_device* dev)
2327 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2328 rtl8192_InitBBRFRegDef(dev);
2329 //config BB&RF. As hardCode based initialization has not been well
2330 //implemented, so use file first.FIXME:should implement it for hardcode?
2331 rtStatus = rtl8192_BB_Config_ParaFile(dev);
2335 /******************************************************************************
2336 *function: This function obtains the initialization value of Tx power Level offset
2337 * input: net_device dev
2340 * ***************************************************************************/
2341 void rtl8192_phy_getTxPower(struct net_device* dev)
2343 struct r8192_priv *priv = ieee80211_priv(dev);
2345 priv->MCSTxPowerLevelOriginalOffset[0] =
2346 read_nic_dword(dev, MCS_TXAGC);
2347 priv->MCSTxPowerLevelOriginalOffset[1] =
2348 read_nic_dword(dev, (MCS_TXAGC+4));
2349 priv->CCKTxPowerLevelOriginalOffset =
2350 read_nic_dword(dev, CCK_TXAGC);
2353 priv->MCSTxPowerLevelOriginalOffset[0] =
2354 read_nic_dword(dev, rTxAGC_Rate18_06);
2355 priv->MCSTxPowerLevelOriginalOffset[1] =
2356 read_nic_dword(dev, rTxAGC_Rate54_24);
2357 priv->MCSTxPowerLevelOriginalOffset[2] =
2358 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
2359 priv->MCSTxPowerLevelOriginalOffset[3] =
2360 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
2361 priv->MCSTxPowerLevelOriginalOffset[4] =
2362 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
2363 priv->MCSTxPowerLevelOriginalOffset[5] =
2364 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
2368 // read rx initial gain
2369 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
2370 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
2371 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
2372 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
2373 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2374 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2375 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2378 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
2379 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
2380 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2381 rOFDM0_RxDetector3, priv->framesync);
2382 // read SIFS (save the value read fome MACPHY_REG.txt)
2383 priv->SifsTime = read_nic_word(dev, SIFS);
2387 /******************************************************************************
2388 *function: This function obtains the initialization value of Tx power Level offset
2389 * input: net_device dev
2392 * ***************************************************************************/
2393 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
2395 struct r8192_priv *priv = ieee80211_priv(dev);
2396 u8 powerlevel = 0,powerlevelOFDM24G = 0;
2400 if(priv->epromtype == EPROM_93c46)
2402 powerlevel = priv->TxPowerLevelCCK[channel-1];
2403 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2405 else if(priv->epromtype == EPROM_93c56)
2407 if(priv->rf_type == RF_1T2R)
2409 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
2410 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
2412 else if(priv->rf_type == RF_2T4R)
2414 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
2415 // Power must be calculated by the antenna diff.
2416 // So we have to rewrite Antenna gain offset register here.
2417 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
2418 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
2420 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
2421 -priv->TxPowerLevelOFDM24G_A[channel-1];
2422 ant_pwr_diff &= 0xf;
2423 //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
2424 priv->RF_C_TxPwDiff = ant_pwr_diff;
2426 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2427 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
2428 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
2430 // Antenna gain offset from B/C/D to A
2431 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2432 priv->AntennaTxPwDiff[1]<<4 |
2433 priv->AntennaTxPwDiff[0]);
2435 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2436 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2441 // CCX 2 S31, AP control of client transmit power:
2442 // 1. We shall not exceed Cell Power Limit as possible as we can.
2443 // 2. Tolerance is +/- 5dB.
2444 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2447 // 1. 802.11h power contraint
2449 // 071011, by rcnjko.
2451 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
2452 pMgntInfo->bWithCcxCellPwr &&
2453 channel == pMgntInfo->dot11CurrentChannelNumber)
2455 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
2456 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
2457 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
2459 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2460 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2461 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2462 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2463 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2464 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2467 if(powerlevel > CckCellPwrIdx)
2468 powerlevel = CckCellPwrIdx;
2469 // Legacy OFDM, HT OFDM
2470 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
2472 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
2474 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
2478 LegacyOfdmCellPwrIdx = 0;
2482 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2483 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2484 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2487 pHalData->CurrentCckTxPwrIdx = powerlevel;
2488 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2490 switch(priv->rf_chip)
2493 // PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2494 // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2497 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
2498 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2503 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
2509 /******************************************************************************
2510 *function: This function check Rf chip to do RF config
2511 * input: net_device dev
2513 * return: only 8256 is supported
2514 * ***************************************************************************/
2515 RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
2517 struct r8192_priv *priv = ieee80211_priv(dev);
2518 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2519 switch(priv->rf_chip)
2522 // rtStatus = PHY_RF8225_Config(Adapter);
2525 rtStatus = PHY_RF8256_Config(dev);
2531 //rtStatus = PHY_RF8225_Config(Adapter);
2535 RT_TRACE(COMP_ERR, "error chip id\n");
2541 /******************************************************************************
2542 *function: This function update Initial gain
2543 * input: net_device dev
2545 * return: As Windows has not implemented this, wait for complement
2546 * ***************************************************************************/
2547 void rtl8192_phy_updateInitGain(struct net_device* dev)
2552 /******************************************************************************
2553 *function: This function read RF parameters from general head file, and do RF 3-wire
2554 * input: net_device dev
2556 * return: return code show if RF configuration is successful(0:pass, 1:fail)
2557 * Note: Delay may be required for RF configuration
2558 * ***************************************************************************/
2559 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
2568 for(i = 0;i<RadioA_ArrayLength; i=i+2){
2570 if(Rtl819XRadioA_Array[i] == 0xfe){
2574 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
2580 for(i = 0;i<RadioB_ArrayLength; i=i+2){
2582 if(Rtl819XRadioB_Array[i] == 0xfe){
2586 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
2592 for(i = 0;i<RadioC_ArrayLength; i=i+2){
2594 if(Rtl819XRadioC_Array[i] == 0xfe){
2598 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
2604 for(i = 0;i<RadioD_ArrayLength; i=i+2){
2606 if(Rtl819XRadioD_Array[i] == 0xfe){
2610 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
2622 /******************************************************************************
2623 *function: This function set Tx Power of the channel
2624 * input: struct net_device *dev
2629 * ***************************************************************************/
2630 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
2632 struct r8192_priv *priv = ieee80211_priv(dev);
2633 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
2634 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2636 switch(priv->rf_chip)
2640 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2641 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2646 PHY_SetRF8256CCKTxPower(dev, powerlevel);
2647 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2653 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
2658 /****************************************************************************************
2659 *function: This function set command table variable(struct SwChnlCmd).
2660 * input: SwChnlCmd* CmdTable //table to be set.
2661 * u32 CmdTableIdx //variable index in table to be set
2662 * u32 CmdTableSz //table size.
2663 * SwChnlCmdID CmdID //command ID to set.
2668 * return: true if finished, false otherwise
2670 * ************************************************************************************/
2671 static u8 rtl8192_phy_SetSwChnlCmdArray(
2672 SwChnlCmd* CmdTable,
2683 if(CmdTable == NULL)
2685 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
2688 if(CmdTableIdx >= CmdTableSz)
2690 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2691 CmdTableIdx, CmdTableSz);
2695 pCmd = CmdTable + CmdTableIdx;
2696 pCmd->CmdID = CmdID;
2697 pCmd->Para1 = Para1;
2698 pCmd->Para2 = Para2;
2699 pCmd->msDelay = msDelay;
2703 /******************************************************************************
2704 *function: This function set channel step by step
2705 * input: struct net_device *dev
2707 * u8* stage //3 stages
2709 * u32* delay //whether need to delay
2710 * output: store new stage, step and delay for next step(combine with function above)
2711 * return: true if finished, false otherwise
2712 * Note: Wait for simpler function to replace it //wb
2713 * ***************************************************************************/
2714 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
2716 struct r8192_priv *priv = ieee80211_priv(dev);
2717 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
2718 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2719 u32 PreCommonCmdCnt;
2720 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2721 u32 PostCommonCmdCnt;
2722 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2724 SwChnlCmd *CurrentCmd = NULL;
2725 //RF90_RADIO_PATH_E eRFPath;
2730 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
2731 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
2733 #ifdef ENABLE_DOT11D
2734 if (!IsLegalChannel(priv->ieee80211, channel))
2736 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2737 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2741 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
2742 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
2744 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2746 // <1> Fill up pre common command.
2747 PreCommonCmdCnt = 0;
2748 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2749 CmdID_SetTxPowerLevel, 0, 0, 0);
2750 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2751 CmdID_End, 0, 0, 0);
2753 // <2> Fill up post common command.
2754 PostCommonCmdCnt = 0;
2756 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2757 CmdID_End, 0, 0, 0);
2759 // <3> Fill up RF dependent command.
2761 switch( priv->rf_chip )
2764 if (!(channel >= 1 && channel <= 14))
2766 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
2769 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2770 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
2771 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2772 CmdID_End, 0, 0, 0);
2776 // TEST!! This is not the table for 8256!!
2777 if (!(channel >= 1 && channel <= 14))
2779 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
2782 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2783 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
2784 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2785 CmdID_End, 0, 0, 0);
2792 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
2802 CurrentCmd=&PreCommonCmd[*step];
2805 CurrentCmd=&RfDependCmd[*step];
2808 CurrentCmd=&PostCommonCmd[*step];
2812 if(CurrentCmd->CmdID==CmdID_End)
2826 switch(CurrentCmd->CmdID)
2828 case CmdID_SetTxPowerLevel:
2829 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
2830 rtl8192_SetTxPowerLevel(dev,channel);
2832 case CmdID_WritePortUlong:
2833 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2835 case CmdID_WritePortUshort:
2836 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2838 case CmdID_WritePortUchar:
2839 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2841 case CmdID_RF_WriteReg:
2842 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2843 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
2851 }/*for(Number of RF paths)*/
2853 (*delay)=CurrentCmd->msDelay;
2858 /******************************************************************************
2859 *function: This function does acturally set channel work
2860 * input: struct net_device *dev
2864 * Note: We should not call this function directly
2865 * ***************************************************************************/
2866 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
2868 struct r8192_priv *priv = ieee80211_priv(dev);
2871 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2874 msleep(delay);//or mdelay? need further consideration
2879 /******************************************************************************
2880 *function: Callback routine of the work item for switch channel.
2885 * ***************************************************************************/
2886 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
2889 struct r8192_priv *priv = ieee80211_priv(dev);
2891 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
2893 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
2895 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
2897 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
2900 /******************************************************************************
2901 *function: This function scheduled actural workitem to set channel
2902 * input: net_device dev
2903 * u8 channel //channel to set
2905 * return: return code show if workitem is scheduled(1:pass, 0:fail)
2906 * Note: Delay may be required for RF configuration
2907 * ***************************************************************************/
2908 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2910 struct r8192_priv *priv = ieee80211_priv(dev);
2911 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
2914 if(priv->SwChnlInProgress)
2917 // if(pHalData->SetBWModeInProgress)
2920 //--------------------------------------------
2921 switch(priv->ieee80211->mode)
2923 case WIRELESS_MODE_A:
2924 case WIRELESS_MODE_N_5G:
2926 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2930 case WIRELESS_MODE_B:
2932 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2936 case WIRELESS_MODE_G:
2937 case WIRELESS_MODE_N_24G:
2939 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2944 //--------------------------------------------
2946 priv->SwChnlInProgress = true;
2952 priv->SwChnlStage=0;
2954 // schedule_work(&(priv->SwChnlWorkItem));
2955 // rtl8192_SwChnl_WorkItem(dev);
2957 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
2958 rtl8192_SwChnl_WorkItem(dev);
2960 priv->SwChnlInProgress = false;
2964 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
2966 struct r8192_priv *priv = ieee80211_priv(dev);
2968 switch(priv->CurrentChannelBW)
2971 case HT_CHANNEL_WIDTH_20:
2972 //added by vivi, cck,tx power track, 20080703
2973 priv->CCKPresentAttentuation =
2974 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
2976 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2977 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2978 if(priv->CCKPresentAttentuation < 0)
2979 priv->CCKPresentAttentuation = 0;
2981 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2983 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
2985 priv->bcck_in_ch14 = TRUE;
2986 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2988 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2990 priv->bcck_in_ch14 = FALSE;
2991 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2994 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2998 case HT_CHANNEL_WIDTH_20_40:
2999 //added by vivi, cck,tx power track, 20080703
3000 priv->CCKPresentAttentuation =
3001 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
3003 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
3004 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
3005 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
3006 if(priv->CCKPresentAttentuation < 0)
3007 priv->CCKPresentAttentuation = 0;
3009 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3011 priv->bcck_in_ch14 = TRUE;
3012 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3014 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3016 priv->bcck_in_ch14 = FALSE;
3017 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3020 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3026 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3028 struct r8192_priv *priv = ieee80211_priv(dev);
3030 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3031 priv->bcck_in_ch14 = TRUE;
3032 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3033 priv->bcck_in_ch14 = FALSE;
3035 //write to default index and tx power track will be done in dm.
3036 switch(priv->CurrentChannelBW)
3039 case HT_CHANNEL_WIDTH_20:
3040 if(priv->Record_CCK_20Mindex == 0)
3041 priv->Record_CCK_20Mindex = 6; //set default value.
3042 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
3043 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
3047 case HT_CHANNEL_WIDTH_20_40:
3048 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
3049 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
3052 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
3056 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
3059 struct r8192_priv *priv = ieee80211_priv(dev);
3063 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3065 //if(pHalData->bDcut == TRUE)
3066 if(priv->IC_Cut >= IC_VersionCut_D)
3067 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3069 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
3075 /******************************************************************************
3076 *function: Callback routine of the work item for set bandwidth mode.
3077 * input: struct net_device *dev
3078 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3079 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3082 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3083 * test whether current work in the queue or not.//do I?
3084 * ***************************************************************************/
3085 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3088 struct r8192_priv *priv = ieee80211_priv(dev);
3091 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \
3092 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
3095 if(priv->rf_chip== RF_PSEUDO_11N)
3097 priv->SetBWModeInProgress= false;
3102 priv->SetBWModeInProgress= false;
3105 //<1>Set MAC register
3106 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3108 switch(priv->CurrentChannelBW)
3110 case HT_CHANNEL_WIDTH_20:
3111 regBwOpMode |= BW_OPMODE_20MHZ;
3112 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3113 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3116 case HT_CHANNEL_WIDTH_20_40:
3117 regBwOpMode &= ~BW_OPMODE_20MHZ;
3118 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3119 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3123 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3127 //<2>Set PHY related register
3128 switch(priv->CurrentChannelBW)
3130 case HT_CHANNEL_WIDTH_20:
3131 // Add by Vivi 20071119
3132 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3133 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3134 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3136 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
3137 // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3138 // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3139 // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3140 if(!priv->btxpower_tracking)
3142 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3143 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3144 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3147 CCK_Tx_Power_Track_BW_Switch(dev);
3150 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
3151 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily
3154 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3159 case HT_CHANNEL_WIDTH_20_40:
3160 // Add by Vivi 20071119
3161 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3162 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3163 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3164 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3165 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3167 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3168 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3169 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3170 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3171 if(!priv->btxpower_tracking)
3173 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3174 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3175 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3178 CCK_Tx_Power_Track_BW_Switch(dev);
3180 // Set Control channel to upper or lower. These settings are required only for 40MHz
3181 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3182 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3186 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3187 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily
3189 // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
3190 // It is set in Tx descriptor for 8192x series
3191 if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3193 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
3194 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3196 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
3201 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3206 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
3210 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3213 //<3>Set RF related register
3214 switch( priv->rf_chip )
3218 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
3223 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3227 // PHY_SetRF8258Bandwidth();
3235 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
3239 atomic_dec(&(priv->ieee80211->atm_swbw));
3240 priv->SetBWModeInProgress= false;
3242 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
3245 /******************************************************************************
3246 *function: This function schedules bandwith switch work.
3247 * input: struct net_device *dev
3248 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3249 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3252 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3253 * test whether current work in the queue or not.//do I?
3254 * ***************************************************************************/
3255 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3257 struct r8192_priv *priv = ieee80211_priv(dev);
3260 if(priv->SetBWModeInProgress)
3263 atomic_inc(&(priv->ieee80211->atm_swbw));
3264 priv->SetBWModeInProgress= true;
3266 priv->CurrentChannelBW = Bandwidth;
3268 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3269 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3270 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3271 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3273 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3275 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
3276 // schedule_work(&(priv->SetBWModeWorkItem));
3277 rtl8192_SetBWModeWorkItem(dev);
3282 void InitialGain819xPci(struct net_device *dev, u8 Operation)
3284 #define SCAN_RX_INITIAL_GAIN 0x17
3285 #define POWER_DETECTION_TH 0x08
3286 struct r8192_priv *priv = ieee80211_priv(dev);
3295 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3296 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
3297 BitMask = bMaskByte0;
3298 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3299 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3300 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3301 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3302 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3303 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3304 BitMask = bMaskByte2;
3305 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3307 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3308 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3309 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3310 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3311 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3313 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3314 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3315 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3316 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3317 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3318 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3319 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3322 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3323 BitMask = 0x7f; //Bit0~ Bit6
3324 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3325 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3327 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3328 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3329 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3330 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3331 BitMask = bMaskByte2;
3332 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3334 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3335 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3336 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3337 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3338 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3340 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3343 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3344 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3347 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");