drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * Based on the r8180 driver, which is:
   5  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  18  *
  19  * The full GNU General Public License is included in this distribution in the
  20  * file called LICENSE.
  21  *
  22  * Contact Information:
  23  * wlanfae <wlanfae@realtek.com>
  24 ******************************************************************************/
  25 #include "rtl_core.h"
  26 #include "r8192E_phy.h"
  27 #include "r8192E_phyreg.h"
  28 #include "r8190P_rtl8256.h"
  29 #include "r8192E_cmdpkt.h"
  30 #include "rtl_dm.h"
  31 #include "rtl_wx.h"
  32
  33 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI, EDCAPARA_VO};
  34
  35 void rtl8192e_start_beacon(struct net_device *dev)
  36 {
  37         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
  38         struct rtllib_network *net = &priv->rtllib->current_network;
  39         u16 BcnTimeCfg = 0;
  40         u16 BcnCW = 6;
  41         u16 BcnIFS = 0xf;
  42
  43         DMESG("Enabling beacon TX");
  44         rtl8192_irq_disable(dev);
  45
  46         write_nic_word(dev, ATIMWND, 2);
  47
  48         write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
  49         write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
  50         write_nic_word(dev, BCN_DMATIME, 256);
  51
  52         write_nic_byte(dev, BCN_ERR_THRESH, 100);
  53
  54         BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
  55         BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
  56         write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
  57         rtl8192_irq_enable(dev);
  58 }
  59
  60 static void rtl8192e_update_msr(struct net_device *dev)
  61 {
  62         struct r8192_priv *priv = rtllib_priv(dev);
  63         u8 msr;
  64         enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
  65
  66         msr  = read_nic_byte(dev, MSR);
  67         msr &= ~MSR_LINK_MASK;
  68
  69         switch (priv->rtllib->iw_mode) {
  70         case IW_MODE_INFRA:
  71                 if (priv->rtllib->state == RTLLIB_LINKED)
  72                         msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
  73                 else
  74                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  75                 LedAction = LED_CTL_LINK;
  76                 break;
  77         case IW_MODE_ADHOC:
  78                 if (priv->rtllib->state == RTLLIB_LINKED)
  79                         msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
  80                 else
  81                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  82                 break;
  83         case IW_MODE_MASTER:
  84                 if (priv->rtllib->state == RTLLIB_LINKED)
  85                         msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
  86                 else
  87                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  88                 break;
  89         default:
  90                 break;
  91         }
  92
  93         write_nic_byte(dev, MSR, msr);
  94         if (priv->rtllib->LedControlHandler)
  95                 priv->rtllib->LedControlHandler(dev, LedAction);
  96 }
  97
  98 void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val)
  99 {
 100         struct r8192_priv *priv = rtllib_priv(dev);
 101
 102         switch (variable) {
 103         case HW_VAR_BSSID:
 104                 write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]);
 105                 write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
 106                 break;
 107
 108         case HW_VAR_MEDIA_STATUS:
 109         {
 110                 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
 111                 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
 112                 u8              btMsr = read_nic_byte(dev, MSR);
 113
 114                 btMsr &= 0xfc;
 115
 116                 switch (OpMode) {
 117                 case RT_OP_MODE_INFRASTRUCTURE:
 118                         btMsr |= MSR_INFRA;
 119                         LedAction = LED_CTL_LINK;
 120                         break;
 121
 122                 case RT_OP_MODE_IBSS:
 123                         btMsr |= MSR_ADHOC;
 124                         break;
 125
 126                 case RT_OP_MODE_AP:
 127                         btMsr |= MSR_AP;
 128                         LedAction = LED_CTL_LINK;
 129                         break;
 130
 131                 default:
 132                         btMsr |= MSR_NOLINK;
 133                         break;
 134                 }
 135
 136                 write_nic_byte(dev, MSR, btMsr);
 137
 138         }
 139         break;
 140
 141         case HW_VAR_CECHK_BSSID:
 142         {
 143                 u32     RegRCR, Type;
 144
 145                 Type = ((u8 *)(val))[0];
 146                 RegRCR = read_nic_dword(dev, RCR);
 147                 priv->ReceiveConfig = RegRCR;
 148
 149                 if (Type == true)
 150                         RegRCR |= (RCR_CBSSID);
 151                 else if (Type == false)
 152                         RegRCR &= (~RCR_CBSSID);
 153
 154                 write_nic_dword(dev, RCR, RegRCR);
 155                 priv->ReceiveConfig = RegRCR;
 156
 157         }
 158         break;
 159
 160         case HW_VAR_SLOT_TIME:
 161
 162                 priv->slot_time = val[0];
 163                 write_nic_byte(dev, SLOT_TIME, val[0]);
 164
 165                 break;
 166
 167         case HW_VAR_ACK_PREAMBLE:
 168         {
 169                 u32 regTmp;
 170
 171                 priv->short_preamble = (bool)(*(u8 *)val);
 172                 regTmp = priv->basic_rate;
 173                 if (priv->short_preamble)
 174                         regTmp |= BRSR_AckShortPmb;
 175                 write_nic_dword(dev, RRSR, regTmp);
 176                 break;
 177         }
 178
 179         case HW_VAR_CPU_RST:
 180                 write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]);
 181                 break;
 182
 183         case HW_VAR_AC_PARAM:
 184         {
 185                 u8      pAcParam = *((u8 *)val);
 186                 u32     eACI = pAcParam;
 187                 u8              u1bAIFS;
 188                 u32             u4bAcParam;
 189                 u8 mode = priv->rtllib->mode;
 190                 struct rtllib_qos_parameters *qos_parameters =
 191                          &priv->rtllib->current_network.qos_data.parameters;
 192
 193                 u1bAIFS = qos_parameters->aifs[pAcParam] *
 194                           ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
 195
 196                 dm_init_edca_turbo(dev);
 197
 198                 u4bAcParam = (((le16_to_cpu(
 199                                         qos_parameters->tx_op_limit[pAcParam])) <<
 200                              AC_PARAM_TXOP_LIMIT_OFFSET) |
 201                              ((le16_to_cpu(qos_parameters->cw_max[pAcParam])) <<
 202                              AC_PARAM_ECW_MAX_OFFSET) |
 203                              ((le16_to_cpu(qos_parameters->cw_min[pAcParam])) <<
 204                              AC_PARAM_ECW_MIN_OFFSET) |
 205                              (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
 206
 207                 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
 208                          __func__, eACI, u4bAcParam);
 209                 switch (eACI) {
 210                 case AC1_BK:
 211                         write_nic_dword(dev, EDCAPARA_BK, u4bAcParam);
 212                         break;
 213
 214                 case AC0_BE:
 215                         write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
 216                         break;
 217
 218                 case AC2_VI:
 219                         write_nic_dword(dev, EDCAPARA_VI, u4bAcParam);
 220                         break;
 221
 222                 case AC3_VO:
 223                         write_nic_dword(dev, EDCAPARA_VO, u4bAcParam);
 224                         break;
 225
 226                 default:
 227                         printk(KERN_INFO "SetHwReg8185(): invalid ACI: %d !\n",
 228                                eACI);
 229                         break;
 230                 }
 231                 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
 232                                               (u8 *)(&pAcParam));
 233                 break;
 234         }
 235
 236         case HW_VAR_ACM_CTRL:
 237         {
 238                 struct rtllib_qos_parameters *qos_parameters =
 239                          &priv->rtllib->current_network.qos_data.parameters;
 240                 u8 pAcParam = *((u8 *)val);
 241                 u32 eACI = pAcParam;
 242                 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
 243                                               (qos_parameters->aifs[0]);
 244                 u8 acm = pAciAifsn->f.acm;
 245                 u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
 246
 247                 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
 248                          __func__, eACI);
 249                 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
 250
 251                 if (acm) {
 252                         switch (eACI) {
 253                         case AC0_BE:
 254                                 AcmCtrl |= AcmHw_BeqEn;
 255                                 break;
 256
 257                         case AC2_VI:
 258                                 AcmCtrl |= AcmHw_ViqEn;
 259                                 break;
 260
 261                         case AC3_VO:
 262                                 AcmCtrl |= AcmHw_VoqEn;
 263                                 break;
 264
 265                         default:
 266                                 RT_TRACE(COMP_QOS, "SetHwReg8185(): [HW_VAR_"
 267                                          "ACM_CTRL] acm set failed: eACI is "
 268                                          "%d\n", eACI);
 269                                 break;
 270                         }
 271                 } else {
 272                         switch (eACI) {
 273                         case AC0_BE:
 274                                 AcmCtrl &= (~AcmHw_BeqEn);
 275                                 break;
 276
 277                         case AC2_VI:
 278                                 AcmCtrl &= (~AcmHw_ViqEn);
 279                                 break;
 280
 281                         case AC3_VO:
 282                                 AcmCtrl &= (~AcmHw_BeqEn);
 283                                 break;
 284
 285                         default:
 286                                 break;
 287                         }
 288                 }
 289
 290                 RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write"
 291                          " 0x%X\n", AcmCtrl);
 292                 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
 293                 break;
 294         }
 295
 296         case HW_VAR_SIFS:
 297                 write_nic_byte(dev, SIFS, val[0]);
 298                 write_nic_byte(dev, SIFS+1, val[0]);
 299                 break;
 300
 301         case HW_VAR_RF_TIMING:
 302         {
 303                 u8 Rf_Timing = *((u8 *)val);
 304
 305                 write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing);
 306                 break;
 307         }
 308
 309         default:
 310                 break;
 311         }
 312
 313 }
 314
 315 static void rtl8192_read_eeprom_info(struct net_device *dev)
 316 {
 317         struct r8192_priv *priv = rtllib_priv(dev);
 318
 319         u8 tempval;
 320         u8 ICVer8192, ICVer8256;
 321         u16 i, usValue, IC_Version;
 322         u16 EEPROMId;
 323         u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
 324
 325         RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
 326
 327         EEPROMId = eprom_read(dev, 0);
 328         if (EEPROMId != RTL8190_EEPROM_ID) {
 329                 RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n",
 330                          EEPROMId, RTL8190_EEPROM_ID);
 331                 priv->AutoloadFailFlag = true;
 332         } else {
 333                 priv->AutoloadFailFlag = false;
 334         }
 335
 336         if (!priv->AutoloadFailFlag) {
 337                 priv->eeprom_vid = eprom_read(dev, (EEPROM_VID >> 1));
 338                 priv->eeprom_did = eprom_read(dev, (EEPROM_DID >> 1));
 339
 340                 usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8;
 341                 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
 342                 usValue = eprom_read(dev, (EEPROM_ICVersion_ChannelPlan>>1));
 343                 priv->eeprom_ChannelPlan = usValue&0xff;
 344                 IC_Version = ((usValue&0xff00)>>8);
 345
 346                 ICVer8192 = (IC_Version&0xf);
 347                 ICVer8256 = ((IC_Version&0xf0)>>4);
 348                 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
 349                 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
 350                 if (ICVer8192 == 0x2) {
 351                         if (ICVer8256 == 0x5)
 352                                 priv->card_8192_version = VERSION_8190_BE;
 353                 }
 354                 switch (priv->card_8192_version) {
 355                 case VERSION_8190_BD:
 356                 case VERSION_8190_BE:
 357                         break;
 358                 default:
 359                         priv->card_8192_version = VERSION_8190_BD;
 360                         break;
 361                 }
 362                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
 363                           priv->card_8192_version);
 364         } else {
 365                 priv->card_8192_version = VERSION_8190_BD;
 366                 priv->eeprom_vid = 0;
 367                 priv->eeprom_did = 0;
 368                 priv->eeprom_CustomerID = 0;
 369                 priv->eeprom_ChannelPlan = 0;
 370                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
 371         }
 372
 373         RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
 374         RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
 375         RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
 376                  priv->eeprom_CustomerID);
 377
 378         if (!priv->AutoloadFailFlag) {
 379                 for (i = 0; i < 6; i += 2) {
 380                         usValue = eprom_read(dev,
 381                                  (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
 382                         *(u16 *)(&dev->dev_addr[i]) = usValue;
 383                 }
 384         } else {
 385                 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
 386         }
 387
 388         RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
 389                  dev->dev_addr);
 390
 391         if (priv->card_8192_version > VERSION_8190_BD)
 392                 priv->bTXPowerDataReadFromEEPORM = true;
 393         else
 394                 priv->bTXPowerDataReadFromEEPORM = false;
 395
 396         priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
 397
 398         if (priv->card_8192_version > VERSION_8190_BD) {
 399                 if (!priv->AutoloadFailFlag) {
 400                         tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >>
 401                                               1))) & 0xff;
 402                         priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
 403
 404                         if (tempval&0x80)
 405                                 priv->rf_type = RF_1T2R;
 406                         else
 407                                 priv->rf_type = RF_2T4R;
 408                 } else {
 409                         priv->EEPROMLegacyHTTxPowerDiff = 0x04;
 410                 }
 411                 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
 412                         priv->EEPROMLegacyHTTxPowerDiff);
 413
 414                 if (!priv->AutoloadFailFlag)
 415                         priv->EEPROMThermalMeter = (u8)(((eprom_read(dev,
 416                                                    (EEPROM_ThermalMeter>>1))) &
 417                                                    0xff00)>>8);
 418                 else
 419                         priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
 420                 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
 421                          priv->EEPROMThermalMeter);
 422                 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
 423
 424                 if (priv->epromtype == EEPROM_93C46) {
 425                         if (!priv->AutoloadFailFlag) {
 426                                 usValue = eprom_read(dev,
 427                                           (EEPROM_TxPwDiff_CrystalCap >> 1));
 428                                 priv->EEPROMAntPwDiff = (usValue&0x0fff);
 429                                 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
 430                                                          >> 12);
 431                         } else {
 432                                 priv->EEPROMAntPwDiff =
 433                                          EEPROM_Default_AntTxPowerDiff;
 434                                 priv->EEPROMCrystalCap =
 435                                          EEPROM_Default_TxPwDiff_CrystalCap;
 436                         }
 437                         RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
 438                                  priv->EEPROMAntPwDiff);
 439                         RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
 440                                  priv->EEPROMCrystalCap);
 441
 442                         for (i = 0; i < 14; i += 2) {
 443                                 if (!priv->AutoloadFailFlag)
 444                                         usValue = eprom_read(dev,
 445                                                   (u16)((EEPROM_TxPwIndex_CCK +
 446                                                   i) >> 1));
 447                                 else
 448                                         usValue = EEPROM_Default_TxPower;
 449                                 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
 450                                                                  usValue;
 451                                 RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index"
 452                                          " %d = 0x%02x\n", i,
 453                                          priv->EEPROMTxPowerLevelCCK[i]);
 454                                 RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index"
 455                                          " %d = 0x%02x\n", i+1,
 456                                          priv->EEPROMTxPowerLevelCCK[i+1]);
 457                         }
 458                         for (i = 0; i < 14; i += 2) {
 459                                 if (!priv->AutoloadFailFlag)
 460                                         usValue = eprom_read(dev,
 461                                                 (u16)((EEPROM_TxPwIndex_OFDM_24G
 462                                                 + i) >> 1));
 463                                 else
 464                                         usValue = EEPROM_Default_TxPower;
 465                                 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
 466                                                          = usValue;
 467                                 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level,"
 468                                          " Index %d = 0x%02x\n", i,
 469                                          priv->EEPROMTxPowerLevelOFDM24G[i]);
 470                                 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level,"
 471                                          " Index %d = 0x%02x\n", i + 1,
 472                                          priv->EEPROMTxPowerLevelOFDM24G[i+1]);
 473                         }
 474                 }
 475                 if (priv->epromtype == EEPROM_93C46) {
 476                         for (i = 0; i < 14; i++) {
 477                                 priv->TxPowerLevelCCK[i] =
 478                                          priv->EEPROMTxPowerLevelCCK[i];
 479                                 priv->TxPowerLevelOFDM24G[i] =
 480                                          priv->EEPROMTxPowerLevelOFDM24G[i];
 481                         }
 482                         priv->LegacyHTTxPowerDiff =
 483                                          priv->EEPROMLegacyHTTxPowerDiff;
 484                         priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
 485                                                     0xf);
 486                         priv->AntennaTxPwDiff[1] = ((priv->EEPROMAntPwDiff &
 487                                                     0xf0)>>4);
 488                         priv->AntennaTxPwDiff[2] = ((priv->EEPROMAntPwDiff &
 489                                                     0xf00)>>8);
 490                         priv->CrystalCap = priv->EEPROMCrystalCap;
 491                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 492                                                  0xf);
 493                         priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter &
 494                                                  0xf0)>>4);
 495                 } else if (priv->epromtype == EEPROM_93C56) {
 496
 497                         for (i = 0; i < 3; i++) {
 498                                 priv->TxPowerLevelCCK_A[i] =
 499                                          priv->EEPROMRfACCKChnl1TxPwLevel[0];
 500                                 priv->TxPowerLevelOFDM24G_A[i] =
 501                                          priv->EEPROMRfAOfdmChnlTxPwLevel[0];
 502                                 priv->TxPowerLevelCCK_C[i] =
 503                                          priv->EEPROMRfCCCKChnl1TxPwLevel[0];
 504                                 priv->TxPowerLevelOFDM24G_C[i] =
 505                                          priv->EEPROMRfCOfdmChnlTxPwLevel[0];
 506                         }
 507                         for (i = 3; i < 9; i++) {
 508                                 priv->TxPowerLevelCCK_A[i]  =
 509                                          priv->EEPROMRfACCKChnl1TxPwLevel[1];
 510                                 priv->TxPowerLevelOFDM24G_A[i] =
 511                                          priv->EEPROMRfAOfdmChnlTxPwLevel[1];
 512                                 priv->TxPowerLevelCCK_C[i] =
 513                                          priv->EEPROMRfCCCKChnl1TxPwLevel[1];
 514                                 priv->TxPowerLevelOFDM24G_C[i] =
 515                                          priv->EEPROMRfCOfdmChnlTxPwLevel[1];
 516                         }
 517                         for (i = 9; i < 14; i++) {
 518                                 priv->TxPowerLevelCCK_A[i]  =
 519                                          priv->EEPROMRfACCKChnl1TxPwLevel[2];
 520                                 priv->TxPowerLevelOFDM24G_A[i] =
 521                                          priv->EEPROMRfAOfdmChnlTxPwLevel[2];
 522                                 priv->TxPowerLevelCCK_C[i] =
 523                                          priv->EEPROMRfCCCKChnl1TxPwLevel[2];
 524                                 priv->TxPowerLevelOFDM24G_C[i] =
 525                                          priv->EEPROMRfCOfdmChnlTxPwLevel[2];
 526                         }
 527                         for (i = 0; i < 14; i++)
 528                                 RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_A"
 529                                          "[%d] = 0x%x\n", i,
 530                                          priv->TxPowerLevelCCK_A[i]);
 531                         for (i = 0; i < 14; i++)
 532                                 RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM"
 533                                          "24G_A[%d] = 0x%x\n", i,
 534                                          priv->TxPowerLevelOFDM24G_A[i]);
 535                         for (i = 0; i < 14; i++)
 536                                 RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_C"
 537                                          "[%d] = 0x%x\n", i,
 538                                          priv->TxPowerLevelCCK_C[i]);
 539                         for (i = 0; i < 14; i++)
 540                                 RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM"
 541                                          "24G_C[%d] = 0x%x\n", i,
 542                                          priv->TxPowerLevelOFDM24G_C[i]);
 543                         priv->LegacyHTTxPowerDiff =
 544                                  priv->EEPROMLegacyHTTxPowerDiff;
 545                         priv->AntennaTxPwDiff[0] = 0;
 546                         priv->AntennaTxPwDiff[1] = 0;
 547                         priv->AntennaTxPwDiff[2] = 0;
 548                         priv->CrystalCap = priv->EEPROMCrystalCap;
 549                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 550                                                  0xf);
 551                         priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter &
 552                                                  0xf0)>>4);
 553                 }
 554         }
 555
 556         if (priv->rf_type == RF_1T2R) {
 557                 /* no matter what checkpatch says, the braces are needed */
 558                 RT_TRACE(COMP_INIT, "\n1T2R config\n");
 559         } else if (priv->rf_type == RF_2T4R) {
 560                 RT_TRACE(COMP_INIT, "\n2T4R config\n");
 561         }
 562
 563         init_rate_adaptive(dev);
 564
 565         priv->rf_chip = RF_8256;
 566
 567         if (priv->RegChannelPlan == 0xf)
 568                 priv->ChannelPlan = priv->eeprom_ChannelPlan;
 569         else
 570                 priv->ChannelPlan = priv->RegChannelPlan;
 571
 572         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 573                 priv->CustomerID =  RT_CID_DLINK;
 574
 575         switch (priv->eeprom_CustomerID) {
 576         case EEPROM_CID_DEFAULT:
 577                 priv->CustomerID = RT_CID_DEFAULT;
 578                 break;
 579         case EEPROM_CID_CAMEO:
 580                 priv->CustomerID = RT_CID_819x_CAMEO;
 581                 break;
 582         case  EEPROM_CID_RUNTOP:
 583                 priv->CustomerID = RT_CID_819x_RUNTOP;
 584                 break;
 585         case EEPROM_CID_NetCore:
 586                 priv->CustomerID = RT_CID_819x_Netcore;
 587                 break;
 588         case EEPROM_CID_TOSHIBA:
 589                 priv->CustomerID = RT_CID_TOSHIBA;
 590                 if (priv->eeprom_ChannelPlan&0x80)
 591                         priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
 592                 else
 593                         priv->ChannelPlan = 0x0;
 594                 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
 595                         priv->ChannelPlan);
 596                 break;
 597         case EEPROM_CID_Nettronix:
 598                 priv->ScanDelay = 100;
 599                 priv->CustomerID = RT_CID_Nettronix;
 600                 break;
 601         case EEPROM_CID_Pronet:
 602                 priv->CustomerID = RT_CID_PRONET;
 603                 break;
 604         case EEPROM_CID_DLINK:
 605                 priv->CustomerID = RT_CID_DLINK;
 606                 break;
 607
 608         case EEPROM_CID_WHQL:
 609                 break;
 610         default:
 611                 break;
 612         }
 613
 614         if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
 615                 priv->ChannelPlan = 0;
 616         priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
 617
 618         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 619                 priv->rtllib->bSupportRemoteWakeUp = true;
 620         else
 621                 priv->rtllib->bSupportRemoteWakeUp = false;
 622
 623         RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
 624         RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
 625         RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
 626 }
 627
 628 void rtl8192_get_eeprom_size(struct net_device *dev)
 629 {
 630         u16 curCR;
 631         struct r8192_priv *priv = rtllib_priv(dev);
 632
 633         RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
 634         curCR = read_nic_dword(dev, EPROM_CMD);
 635         RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
 636                  curCR);
 637         priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
 638                           EEPROM_93C46;
 639         RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
 640                  priv->epromtype);
 641         rtl8192_read_eeprom_info(dev);
 642 }
 643
 644 static void rtl8192_hwconfig(struct net_device *dev)
 645 {
 646         u32 regRATR = 0, regRRSR = 0;
 647         u8 regBwOpMode = 0, regTmp = 0;
 648         struct r8192_priv *priv = rtllib_priv(dev);
 649
 650         switch (priv->rtllib->mode) {
 651         case WIRELESS_MODE_B:
 652                 regBwOpMode = BW_OPMODE_20MHZ;
 653                 regRATR = RATE_ALL_CCK;
 654                 regRRSR = RATE_ALL_CCK;
 655                 break;
 656         case WIRELESS_MODE_A:
 657                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 658                 regRATR = RATE_ALL_OFDM_AG;
 659                 regRRSR = RATE_ALL_OFDM_AG;
 660                 break;
 661         case WIRELESS_MODE_G:
 662                 regBwOpMode = BW_OPMODE_20MHZ;
 663                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 664                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 665                 break;
 666         case WIRELESS_MODE_AUTO:
 667         case WIRELESS_MODE_N_24G:
 668                 regBwOpMode = BW_OPMODE_20MHZ;
 669                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 670                                   RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 671                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 672                 break;
 673         case WIRELESS_MODE_N_5G:
 674                 regBwOpMode = BW_OPMODE_5G;
 675                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 676                           RATE_ALL_OFDM_2SS;
 677                 regRRSR = RATE_ALL_OFDM_AG;
 678                 break;
 679         default:
 680                 regBwOpMode = BW_OPMODE_20MHZ;
 681                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 682                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 683                 break;
 684         }
 685
 686         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
 687         {
 688                 u32 ratr_value = 0;
 689
 690                 ratr_value = regRATR;
 691                 if (priv->rf_type == RF_1T2R)
 692                         ratr_value &= ~(RATE_ALL_OFDM_2SS);
 693                 write_nic_dword(dev, RATR0, ratr_value);
 694                 write_nic_byte(dev, UFWP, 1);
 695         }
 696         regTmp = read_nic_byte(dev, 0x313);
 697         regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
 698         write_nic_dword(dev, RRSR, regRRSR);
 699
 700         write_nic_word(dev, RETRY_LIMIT,
 701                         priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
 702                         priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
 703 }
 704
 705 bool rtl8192_adapter_start(struct net_device *dev)
 706 {
 707         struct r8192_priv *priv = rtllib_priv(dev);
 708         u32 ulRegRead;
 709         bool rtStatus = true;
 710         u8 tmpvalue;
 711         u8 ICVersion, SwitchingRegulatorOutput;
 712         bool bfirmwareok = true;
 713         u32 tmpRegA, tmpRegC, TempCCk;
 714         int i = 0;
 715         u32 retry_times = 0;
 716
 717         RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
 718         priv->being_init_adapter = true;
 719
 720 start:
 721         rtl8192_pci_resetdescring(dev);
 722         priv->Rf_Mode = RF_OP_By_SW_3wire;
 723         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 724                 write_nic_byte(dev, ANAPAR, 0x37);
 725                 mdelay(500);
 726         }
 727         priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
 728
 729         if (priv->RegRfOff)
 730                 priv->rtllib->eRFPowerState = eRfOff;
 731
 732         ulRegRead = read_nic_dword(dev, CPU_GEN);
 733         if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
 734                 ulRegRead |= CPU_GEN_SYSTEM_RESET;
 735         else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
 736                 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
 737         else
 738                 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)"
 739                          "\n", __func__,   priv->pFirmware->firmware_status);
 740
 741         write_nic_dword(dev, CPU_GEN, ulRegRead);
 742
 743         ICVersion = read_nic_byte(dev, IC_VERRSION);
 744         if (ICVersion >= 0x4) {
 745                 SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
 746                 if (SwitchingRegulatorOutput  != 0xb8) {
 747                         write_nic_byte(dev, SWREGULATOR, 0xa8);
 748                         mdelay(1);
 749                         write_nic_byte(dev, SWREGULATOR, 0xb8);
 750                 }
 751         }
 752         RT_TRACE(COMP_INIT, "BB Config Start!\n");
 753         rtStatus = rtl8192_BBConfig(dev);
 754         if (!rtStatus) {
 755                 RT_TRACE(COMP_ERR, "BB Config failed\n");
 756                 return rtStatus;
 757         }
 758         RT_TRACE(COMP_INIT, "BB Config Finished!\n");
 759
 760         priv->LoopbackMode = RTL819X_NO_LOOPBACK;
 761         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 762                 ulRegRead = read_nic_dword(dev, CPU_GEN);
 763                 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
 764                         ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
 765                                      CPU_GEN_NO_LOOPBACK_SET);
 766                 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
 767                         ulRegRead |= CPU_CCK_LOOPBACK;
 768                 else
 769                         RT_TRACE(COMP_ERR, "Serious error: wrong loopback"
 770                                  " mode setting\n");
 771
 772                 write_nic_dword(dev, CPU_GEN, ulRegRead);
 773
 774                 udelay(500);
 775         }
 776         rtl8192_hwconfig(dev);
 777         write_nic_byte(dev, CMDR, CR_RE | CR_TE);
 778
 779         write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
 780                        (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
 781         write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
 782         write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
 783         write_nic_dword(dev, RCR, priv->ReceiveConfig);
 784
 785         write_nic_dword(dev, RQPN1,  NUM_OF_PAGE_IN_FW_QUEUE_BK <<
 786                         RSVD_FW_QUEUE_PAGE_BK_SHIFT |
 787                         NUM_OF_PAGE_IN_FW_QUEUE_BE <<
 788                         RSVD_FW_QUEUE_PAGE_BE_SHIFT |
 789                         NUM_OF_PAGE_IN_FW_QUEUE_VI <<
 790                         RSVD_FW_QUEUE_PAGE_VI_SHIFT |
 791                         NUM_OF_PAGE_IN_FW_QUEUE_VO <<
 792                         RSVD_FW_QUEUE_PAGE_VO_SHIFT);
 793         write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
 794                         RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
 795         write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
 796                         NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
 797                         RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
 798                         NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
 799                         RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
 800
 801         rtl8192_tx_enable(dev);
 802         rtl8192_rx_enable(dev);
 803         ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR))  |
 804                      RATE_ALL_OFDM_AG | RATE_ALL_CCK;
 805         write_nic_dword(dev, RRSR, ulRegRead);
 806         write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
 807
 808         write_nic_byte(dev, ACK_TIMEOUT, 0x30);
 809
 810         if (priv->ResetProgress == RESET_TYPE_NORESET)
 811                 rtl8192_SetWirelessMode(dev, priv->rtllib->mode);
 812         CamResetAllEntry(dev);
 813         {
 814                 u8 SECR_value = 0x0;
 815
 816                 SECR_value |= SCR_TxEncEnable;
 817                 SECR_value |= SCR_RxDecEnable;
 818                 SECR_value |= SCR_NoSKMC;
 819                 write_nic_byte(dev, SECR, SECR_value);
 820         }
 821         write_nic_word(dev, ATIMWND, 2);
 822         write_nic_word(dev, BCN_INTERVAL, 100);
 823         {
 824                 int i;
 825
 826                 for (i = 0; i < QOS_QUEUE_NUM; i++)
 827                         write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
 828         }
 829         write_nic_byte(dev, 0xbe, 0xc0);
 830
 831         rtl8192_phy_configmac(dev);
 832
 833         if (priv->card_8192_version > (u8) VERSION_8190_BD) {
 834                 rtl8192_phy_getTxPower(dev);
 835                 rtl8192_phy_setTxPower(dev, priv->chan);
 836         }
 837
 838         tmpvalue = read_nic_byte(dev, IC_VERRSION);
 839         priv->IC_Cut = tmpvalue;
 840         RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
 841         if (priv->IC_Cut >= IC_VersionCut_D) {
 842                 if (priv->IC_Cut == IC_VersionCut_D) {
 843                         /* no matter what checkpatch says, braces are needed */
 844                         RT_TRACE(COMP_INIT, "D-cut\n");
 845                 } else if (priv->IC_Cut == IC_VersionCut_E) {
 846                         RT_TRACE(COMP_INIT, "E-cut\n");
 847                 }
 848         } else {
 849                 RT_TRACE(COMP_INIT, "Before C-cut\n");
 850         }
 851
 852         RT_TRACE(COMP_INIT, "Load Firmware!\n");
 853         bfirmwareok = init_firmware(dev);
 854         if (!bfirmwareok) {
 855                 if (retry_times < 10) {
 856                         retry_times++;
 857                         goto start;
 858                 } else {
 859                         rtStatus = false;
 860                         goto end;
 861                 }
 862         }
 863         RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
 864         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 865                 RT_TRACE(COMP_INIT, "RF Config Started!\n");
 866                 rtStatus = rtl8192_phy_RFConfig(dev);
 867                 if (!rtStatus) {
 868                         RT_TRACE(COMP_ERR, "RF Config failed\n");
 869                         return rtStatus;
 870                 }
 871                 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
 872         }
 873         rtl8192_phy_updateInitGain(dev);
 874
 875         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
 876         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
 877
 878         write_nic_byte(dev, 0x87, 0x0);
 879
 880         if (priv->RegRfOff) {
 881                 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
 882                           "%s(): Turn off RF for RegRfOff ----------\n",
 883                           __func__);
 884                 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true);
 885         } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
 886                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for"
 887                          " RfOffReason(%d) ----------\n", __func__,
 888                          priv->rtllib->RfOffReason);
 889                 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
 890                                     true);
 891         } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
 892                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for"
 893                          " RfOffReason(%d) ----------\n", __func__,
 894                          priv->rtllib->RfOffReason);
 895                 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
 896                                     true);
 897         } else {
 898                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
 899                           __func__);
 900                 priv->rtllib->eRFPowerState = eRfOn;
 901                 priv->rtllib->RfOffReason = 0;
 902         }
 903
 904         if (priv->rtllib->FwRWRF)
 905                 priv->Rf_Mode = RF_OP_By_FW;
 906         else
 907                 priv->Rf_Mode = RF_OP_By_SW_3wire;
 908
 909         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 910                 dm_initialize_txpower_tracking(dev);
 911
 912                 if (priv->IC_Cut >= IC_VersionCut_D) {
 913                         tmpRegA = rtl8192_QueryBBReg(dev,
 914                                   rOFDM0_XATxIQImbalance, bMaskDWord);
 915                         tmpRegC = rtl8192_QueryBBReg(dev,
 916                                   rOFDM0_XCTxIQImbalance, bMaskDWord);
 917                         for (i = 0; i < TxBBGainTableLength; i++) {
 918                                 if (tmpRegA ==
 919                                     priv->txbbgain_table[i].txbbgain_value) {
 920                                         priv->rfa_txpowertrackingindex = (u8)i;
 921                                         priv->rfa_txpowertrackingindex_real =
 922                                                  (u8)i;
 923                                         priv->rfa_txpowertracking_default =
 924                                                  priv->rfa_txpowertrackingindex;
 925                                         break;
 926                                 }
 927                         }
 928
 929                         TempCCk = rtl8192_QueryBBReg(dev,
 930                                   rCCK0_TxFilter1, bMaskByte2);
 931
 932                         for (i = 0; i < CCKTxBBGainTableLength; i++) {
 933                                 if (TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0]) {
 934                                         priv->CCKPresentAttentuation_20Mdefault = (u8)i;
 935                                         break;
 936                                 }
 937                         }
 938                         priv->CCKPresentAttentuation_40Mdefault = 0;
 939                         priv->CCKPresentAttentuation_difference = 0;
 940                         priv->CCKPresentAttentuation =
 941                                   priv->CCKPresentAttentuation_20Mdefault;
 942                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower"
 943                                  "trackingindex_initial = %d\n",
 944                                  priv->rfa_txpowertrackingindex);
 945                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower"
 946                                  "trackingindex_real__initial = %d\n",
 947                                  priv->rfa_txpowertrackingindex_real);
 948                         RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent"
 949                                  "Attentuation_difference_initial = %d\n",
 950                                   priv->CCKPresentAttentuation_difference);
 951                         RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent"
 952                                  "Attentuation_initial = %d\n",
 953                                  priv->CCKPresentAttentuation);
 954                         priv->btxpower_tracking = false;
 955                 }
 956         }
 957         rtl8192_irq_enable(dev);
 958 end:
 959         priv->being_init_adapter = false;
 960         return rtStatus;
 961 }
 962
 963 static void rtl8192_net_update(struct net_device *dev)
 964 {
 965
 966         struct r8192_priv *priv = rtllib_priv(dev);
 967         struct rtllib_network *net;
 968         u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
 969         u16 rate_config = 0;
 970
 971         net = &priv->rtllib->current_network;
 972         rtl8192_config_rate(dev, &rate_config);
 973         priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
 974          priv->basic_rate = rate_config &= 0x15f;
 975         write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
 976         write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
 977
 978         if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
 979                 write_nic_word(dev, ATIMWND, 2);
 980                 write_nic_word(dev, BCN_DMATIME, 256);
 981                 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
 982                 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
 983                 write_nic_byte(dev, BCN_ERR_THRESH, 100);
 984
 985                 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
 986                 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
 987
 988                 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
 989         }
 990 }
 991
 992 void rtl8192_link_change(struct net_device *dev)
 993 {
 994         struct r8192_priv *priv = rtllib_priv(dev);
 995         struct rtllib_device *ieee = priv->rtllib;
 996
 997         if (!priv->up)
 998                 return;
 999
1000         if (ieee->state == RTLLIB_LINKED) {
1001                 rtl8192_net_update(dev);
1002                 priv->ops->update_ratr_table(dev);
1003                 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
1004                     (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
1005                         EnableHWSecurityConfig8192(dev);
1006         } else {
1007                 write_nic_byte(dev, 0x173, 0);
1008         }
1009         rtl8192e_update_msr(dev);
1010
1011         if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1012                 u32 reg = 0;
1013
1014                 reg = read_nic_dword(dev, RCR);
1015                 if (priv->rtllib->state == RTLLIB_LINKED) {
1016                         if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1017                                 ;
1018                         else
1019                                 priv->ReceiveConfig = reg |= RCR_CBSSID;
1020                 } else
1021                         priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1022
1023                 write_nic_dword(dev, RCR, reg);
1024         }
1025 }
1026
1027 void rtl8192_AllowAllDestAddr(struct net_device *dev,
1028                               bool bAllowAllDA, bool WriteIntoReg)
1029 {
1030         struct r8192_priv *priv = rtllib_priv(dev);
1031
1032         if (bAllowAllDA)
1033                 priv->ReceiveConfig |= RCR_AAP;
1034         else
1035                 priv->ReceiveConfig &= ~RCR_AAP;
1036
1037         if (WriteIntoReg)
1038                 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1039 }
1040
1041 static u8 MRateToHwRate8190Pci(u8 rate)
1042 {
1043         u8  ret = DESC90_RATE1M;
1044
1045         switch (rate) {
1046         case MGN_1M:
1047                 ret = DESC90_RATE1M;
1048                 break;
1049         case MGN_2M:
1050                 ret = DESC90_RATE2M;
1051                 break;
1052         case MGN_5_5M:
1053                 ret = DESC90_RATE5_5M;
1054                 break;
1055         case MGN_11M:
1056                 ret = DESC90_RATE11M;
1057                 break;
1058         case MGN_6M:
1059                 ret = DESC90_RATE6M;
1060                 break;
1061         case MGN_9M:
1062                 ret = DESC90_RATE9M;
1063                 break;
1064         case MGN_12M:
1065                 ret = DESC90_RATE12M;
1066                 break;
1067         case MGN_18M:
1068                 ret = DESC90_RATE18M;
1069                 break;
1070         case MGN_24M:
1071                 ret = DESC90_RATE24M;
1072                 break;
1073         case MGN_36M:
1074                 ret = DESC90_RATE36M;
1075                 break;
1076         case MGN_48M:
1077                 ret = DESC90_RATE48M;
1078                 break;
1079         case MGN_54M:
1080                 ret = DESC90_RATE54M;
1081                 break;
1082         case MGN_MCS0:
1083                 ret = DESC90_RATEMCS0;
1084                 break;
1085         case MGN_MCS1:
1086                 ret = DESC90_RATEMCS1;
1087                 break;
1088         case MGN_MCS2:
1089                 ret = DESC90_RATEMCS2;
1090                 break;
1091         case MGN_MCS3:
1092                 ret = DESC90_RATEMCS3;
1093                 break;
1094         case MGN_MCS4:
1095                 ret = DESC90_RATEMCS4;
1096                 break;
1097         case MGN_MCS5:
1098                 ret = DESC90_RATEMCS5;
1099                 break;
1100         case MGN_MCS6:
1101                 ret = DESC90_RATEMCS6;
1102                 break;
1103         case MGN_MCS7:
1104                 ret = DESC90_RATEMCS7;
1105                 break;
1106         case MGN_MCS8:
1107                 ret = DESC90_RATEMCS8;
1108                 break;
1109         case MGN_MCS9:
1110                 ret = DESC90_RATEMCS9;
1111                 break;
1112         case MGN_MCS10:
1113                 ret = DESC90_RATEMCS10;
1114                 break;
1115         case MGN_MCS11:
1116                 ret = DESC90_RATEMCS11;
1117                 break;
1118         case MGN_MCS12:
1119                 ret = DESC90_RATEMCS12;
1120                 break;
1121         case MGN_MCS13:
1122                 ret = DESC90_RATEMCS13;
1123                 break;
1124         case MGN_MCS14:
1125                 ret = DESC90_RATEMCS14;
1126                 break;
1127         case MGN_MCS15:
1128                 ret = DESC90_RATEMCS15;
1129                 break;
1130         case (0x80|0x20):
1131                 ret = DESC90_RATEMCS32;
1132                 break;
1133         default:
1134                 break;
1135         }
1136         return ret;
1137 }
1138
1139 static u8 rtl8192_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority)
1140 {
1141         u8 QueueSelect = 0x0;
1142
1143         switch (QueueID) {
1144         case BE_QUEUE:
1145                 QueueSelect = QSLT_BE;
1146                 break;
1147
1148         case BK_QUEUE:
1149                 QueueSelect = QSLT_BK;
1150                 break;
1151
1152         case VO_QUEUE:
1153                 QueueSelect = QSLT_VO;
1154                 break;
1155
1156         case VI_QUEUE:
1157                 QueueSelect = QSLT_VI;
1158                 break;
1159         case MGNT_QUEUE:
1160                 QueueSelect = QSLT_MGNT;
1161                 break;
1162         case BEACON_QUEUE:
1163                 QueueSelect = QSLT_BEACON;
1164                 break;
1165         case TXCMD_QUEUE:
1166                 QueueSelect = QSLT_CMD;
1167                 break;
1168         case HIGH_QUEUE:
1169                 QueueSelect = QSLT_HIGH;
1170                 break;
1171         default:
1172                 RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection:"
1173                          " %d\n", QueueID);
1174                 break;
1175         }
1176         return QueueSelect;
1177 }
1178
1179 void  rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc,
1180                            struct cb_desc *cb_desc, struct sk_buff *skb)
1181 {
1182         struct r8192_priv *priv = rtllib_priv(dev);
1183         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1184                          PCI_DMA_TODEVICE);
1185         struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1186
1187         pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1188         memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1189         pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1190         pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1191         pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1192         pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1193                                                 pTxFwInfo->TxRate,
1194                                                 cb_desc);
1195
1196         if (pci_dma_mapping_error(priv->pdev, mapping))
1197                 RT_TRACE(COMP_ERR, "DMA Mapping error\n");
1198         if (cb_desc->bAMPDUEnable) {
1199                 pTxFwInfo->AllowAggregation = 1;
1200                 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1201                 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1202         } else {
1203                 pTxFwInfo->AllowAggregation = 0;
1204                 pTxFwInfo->RxMF = 0;
1205                 pTxFwInfo->RxAMD = 0;
1206         }
1207
1208         pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1209         pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1210         pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1211         pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1212         pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1213         pTxFwInfo->RtsBandwidth = 0;
1214         pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1215         pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1216                           (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1217                           (cb_desc->bRTSUseShortGI ? 1 : 0);
1218         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1219                 if (cb_desc->bPacketBW) {
1220                         pTxFwInfo->TxBandwidth = 1;
1221                         pTxFwInfo->TxSubCarrier = 0;
1222                 } else {
1223                         pTxFwInfo->TxBandwidth = 0;
1224                         pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1225                 }
1226         } else {
1227                 pTxFwInfo->TxBandwidth = 0;
1228                 pTxFwInfo->TxSubCarrier = 0;
1229         }
1230
1231         memset((u8 *)pdesc, 0, 12);
1232         pdesc->LINIP = 0;
1233         pdesc->CmdInit = 1;
1234         pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1235         pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1236
1237         pdesc->SecCAMID = 0;
1238         pdesc->RATid = cb_desc->RATRIndex;
1239
1240
1241         pdesc->NoEnc = 1;
1242         pdesc->SecType = 0x0;
1243         if (cb_desc->bHwSec) {
1244                 static u8 tmp;
1245
1246                 if (!tmp) {
1247                         RT_TRACE(COMP_DBG, "==>================hw sec\n");
1248                         tmp = 1;
1249                 }
1250                 switch (priv->rtllib->pairwise_key_type) {
1251                 case KEY_TYPE_WEP40:
1252                 case KEY_TYPE_WEP104:
1253                         pdesc->SecType = 0x1;
1254                         pdesc->NoEnc = 0;
1255                         break;
1256                 case KEY_TYPE_TKIP:
1257                         pdesc->SecType = 0x2;
1258                         pdesc->NoEnc = 0;
1259                         break;
1260                 case KEY_TYPE_CCMP:
1261                         pdesc->SecType = 0x3;
1262                         pdesc->NoEnc = 0;
1263                         break;
1264                 case KEY_TYPE_NA:
1265                         pdesc->SecType = 0x0;
1266                         pdesc->NoEnc = 1;
1267                         break;
1268                 }
1269         }
1270
1271         pdesc->PktId = 0x0;
1272
1273         pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(
1274                                                 cb_desc->queue_index,
1275                                                 cb_desc->priority);
1276         pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1277
1278         pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1279         pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1280
1281         pdesc->FirstSeg = 1;
1282         pdesc->LastSeg = 1;
1283         pdesc->TxBufferSize = skb->len;
1284
1285         pdesc->TxBuffAddr = mapping;
1286 }
1287
1288 void  rtl8192_tx_fill_cmd_desc(struct net_device *dev,
1289                                struct tx_desc_cmd *entry,
1290                                struct cb_desc *cb_desc, struct sk_buff *skb)
1291 {
1292         struct r8192_priv *priv = rtllib_priv(dev);
1293         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1294                          PCI_DMA_TODEVICE);
1295
1296         if (pci_dma_mapping_error(priv->pdev, mapping))
1297                 RT_TRACE(COMP_ERR, "DMA Mapping error\n");
1298         memset(entry, 0, 12);
1299         entry->LINIP = cb_desc->bLastIniPkt;
1300         entry->FirstSeg = 1;
1301         entry->LastSeg = 1;
1302         if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1303                 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1304         } else {
1305                 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1306
1307                 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1308                 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1309                 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1310                                       entry_tmp->Offset);
1311                 entry_tmp->QueueSelect = QSLT_CMD;
1312                 entry_tmp->TxFWInfoSize = 0x08;
1313                 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1314         }
1315         entry->TxBufferSize = skb->len;
1316         entry->TxBuffAddr = mapping;
1317         entry->OWN = 1;
1318 }
1319
1320 static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1321 {
1322         u8  ret_rate = 0x02;
1323
1324         if (!bIsHT) {
1325                 switch (rate) {
1326                 case DESC90_RATE1M:
1327                         ret_rate = MGN_1M;
1328                         break;
1329                 case DESC90_RATE2M:
1330                         ret_rate = MGN_2M;
1331                         break;
1332                 case DESC90_RATE5_5M:
1333                         ret_rate = MGN_5_5M;
1334                         break;
1335                 case DESC90_RATE11M:
1336                         ret_rate = MGN_11M;
1337                         break;
1338                 case DESC90_RATE6M:
1339                         ret_rate = MGN_6M;
1340                         break;
1341                 case DESC90_RATE9M:
1342                         ret_rate = MGN_9M;
1343                         break;
1344                 case DESC90_RATE12M:
1345                         ret_rate = MGN_12M;
1346                         break;
1347                 case DESC90_RATE18M:
1348                         ret_rate = MGN_18M;
1349                         break;
1350                 case DESC90_RATE24M:
1351                         ret_rate = MGN_24M;
1352                         break;
1353                 case DESC90_RATE36M:
1354                         ret_rate = MGN_36M;
1355                         break;
1356                 case DESC90_RATE48M:
1357                         ret_rate = MGN_48M;
1358                         break;
1359                 case DESC90_RATE54M:
1360                         ret_rate = MGN_54M;
1361                         break;
1362
1363                 default:
1364                         RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported"
1365                                  "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
1366                                                   break;
1367                 }
1368
1369         } else {
1370                 switch (rate) {
1371                 case DESC90_RATEMCS0:
1372                         ret_rate = MGN_MCS0;
1373                         break;
1374                 case DESC90_RATEMCS1:
1375                         ret_rate = MGN_MCS1;
1376                         break;
1377                 case DESC90_RATEMCS2:
1378                         ret_rate = MGN_MCS2;
1379                         break;
1380                 case DESC90_RATEMCS3:
1381                         ret_rate = MGN_MCS3;
1382                         break;
1383                 case DESC90_RATEMCS4:
1384                         ret_rate = MGN_MCS4;
1385                         break;
1386                 case DESC90_RATEMCS5:
1387                         ret_rate = MGN_MCS5;
1388                         break;
1389                 case DESC90_RATEMCS6:
1390                         ret_rate = MGN_MCS6;
1391                         break;
1392                 case DESC90_RATEMCS7:
1393                         ret_rate = MGN_MCS7;
1394                         break;
1395                 case DESC90_RATEMCS8:
1396                         ret_rate = MGN_MCS8;
1397                         break;
1398                 case DESC90_RATEMCS9:
1399                         ret_rate = MGN_MCS9;
1400                         break;
1401                 case DESC90_RATEMCS10:
1402                         ret_rate = MGN_MCS10;
1403                         break;
1404                 case DESC90_RATEMCS11:
1405                         ret_rate = MGN_MCS11;
1406                         break;
1407                 case DESC90_RATEMCS12:
1408                         ret_rate = MGN_MCS12;
1409                         break;
1410                 case DESC90_RATEMCS13:
1411                         ret_rate = MGN_MCS13;
1412                         break;
1413                 case DESC90_RATEMCS14:
1414                         ret_rate = MGN_MCS14;
1415                         break;
1416                 case DESC90_RATEMCS15:
1417                         ret_rate = MGN_MCS15;
1418                         break;
1419                 case DESC90_RATEMCS32:
1420                         ret_rate = (0x80|0x20);
1421                         break;
1422
1423                 default:
1424                         RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported "
1425                                  "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
1426                         break;
1427                 }
1428         }
1429
1430         return ret_rate;
1431 }
1432
1433 static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1434 {
1435         long retsig;
1436
1437         if (currsig >= 61 && currsig <= 100)
1438                 retsig = 90 + ((currsig - 60) / 4);
1439         else if (currsig >= 41 && currsig <= 60)
1440                 retsig = 78 + ((currsig - 40) / 2);
1441         else if (currsig >= 31 && currsig <= 40)
1442                 retsig = 66 + (currsig - 30);
1443         else if (currsig >= 21 && currsig <= 30)
1444                 retsig = 54 + (currsig - 20);
1445         else if (currsig >= 5 && currsig <= 20)
1446                 retsig = 42 + (((currsig - 5) * 2) / 3);
1447         else if (currsig == 4)
1448                 retsig = 36;
1449         else if (currsig == 3)
1450                 retsig = 27;
1451         else if (currsig == 2)
1452                 retsig = 18;
1453         else if (currsig == 1)
1454                 retsig = 9;
1455         else
1456                 retsig = currsig;
1457
1458         return retsig;
1459 }
1460
1461
1462 #define  rx_hal_is_cck_rate(_pdrvinfo)\
1463                         ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1464                         _pdrvinfo->RxRate == DESC90_RATE2M ||\
1465                         _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1466                         _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1467                         !_pdrvinfo->RxHT)
1468
1469 static void rtl8192_query_rxphystatus(
1470         struct r8192_priv *priv,
1471         struct rtllib_rx_stats *pstats,
1472         struct rx_desc  *pdesc,
1473         struct rx_fwinfo   *pdrvinfo,
1474         struct rtllib_rx_stats *precord_stats,
1475         bool bpacket_match_bssid,
1476         bool bpacket_toself,
1477         bool bPacketBeacon,
1478         bool bToSelfBA
1479         )
1480 {
1481         struct phy_sts_ofdm_819xpci *pofdm_buf;
1482         struct phy_sts_cck_819xpci *pcck_buf;
1483         struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1484         u8 *prxpkt;
1485         u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1486         char rx_pwr[4], rx_pwr_all = 0;
1487         char rx_snrX, rx_evmX;
1488         u8 evm, pwdb_all;
1489         u32 RSSI, total_rssi = 0;
1490         u8 is_cck_rate = 0;
1491         u8 rf_rx_num = 0;
1492         static  u8 check_reg824;
1493         static  u32 reg824_bit9;
1494
1495         priv->stats.numqry_phystatus++;
1496
1497         is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1498         memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1499         pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1500                                     bpacket_match_bssid;
1501         pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1502         pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1503         pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1504         pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1505         if (check_reg824 == 0) {
1506                 reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev,
1507                               rFPGA0_XA_HSSIParameter2, 0x200);
1508                 check_reg824 = 1;
1509         }
1510
1511
1512         prxpkt = (u8 *)pdrvinfo;
1513
1514         prxpkt += sizeof(struct rx_fwinfo);
1515
1516         pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1517         pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1518
1519         pstats->RxMIMOSignalQuality[0] = -1;
1520         pstats->RxMIMOSignalQuality[1] = -1;
1521         precord_stats->RxMIMOSignalQuality[0] = -1;
1522         precord_stats->RxMIMOSignalQuality[1] = -1;
1523
1524         if (is_cck_rate) {
1525                 u8 report;
1526
1527                 priv->stats.numqry_phystatusCCK++;
1528                 if (!reg824_bit9) {
1529                         report = pcck_buf->cck_agc_rpt & 0xc0;
1530                         report = report>>6;
1531                         switch (report) {
1532                         case 0x3:
1533                                 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1534                                              0x3e);
1535                                 break;
1536                         case 0x2:
1537                                 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1538                                              0x3e);
1539                                 break;
1540                         case 0x1:
1541                                 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1542                                              0x3e);
1543                                 break;
1544                         case 0x0:
1545                                 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1546                                 break;
1547                         }
1548                 } else {
1549                         report = pcck_buf->cck_agc_rpt & 0x60;
1550                         report = report>>5;
1551                         switch (report) {
1552                         case 0x3:
1553                                 rx_pwr_all = -35 -
1554                                         ((pcck_buf->cck_agc_rpt &
1555                                         0x1f) << 1);
1556                                 break;
1557                         case 0x2:
1558                                 rx_pwr_all = -23 -
1559                                         ((pcck_buf->cck_agc_rpt &
1560                                          0x1f) << 1);
1561                                 break;
1562                         case 0x1:
1563                                 rx_pwr_all = -11 -
1564                                          ((pcck_buf->cck_agc_rpt &
1565                                          0x1f) << 1);
1566                                 break;
1567                         case 0x0:
1568                                 rx_pwr_all = -8 -
1569                                          ((pcck_buf->cck_agc_rpt &
1570                                          0x1f) << 1);
1571                                 break;
1572                         }
1573                 }
1574
1575                 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1576                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1577                 pstats->RecvSignalPower = rx_pwr_all;
1578
1579                 if (bpacket_match_bssid) {
1580                         u8      sq;
1581
1582                         if (pstats->RxPWDBAll > 40) {
1583                                 sq = 100;
1584                         } else {
1585                                 sq = pcck_buf->sq_rpt;
1586
1587                                 if (pcck_buf->sq_rpt > 64)
1588                                         sq = 0;
1589                                 else if (pcck_buf->sq_rpt < 20)
1590                                         sq = 100;
1591                                 else
1592                                         sq = ((64-sq) * 100) / 44;
1593                         }
1594                         pstats->SignalQuality = sq;
1595                         precord_stats->SignalQuality = sq;
1596                         pstats->RxMIMOSignalQuality[0] = sq;
1597                         precord_stats->RxMIMOSignalQuality[0] = sq;
1598                         pstats->RxMIMOSignalQuality[1] = -1;
1599                         precord_stats->RxMIMOSignalQuality[1] = -1;
1600                 }
1601         } else {
1602                 priv->stats.numqry_phystatusHT++;
1603                 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1604                         if (priv->brfpath_rxenable[i])
1605                                 rf_rx_num++;
1606
1607                         rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1608                                      2) - 110;
1609
1610                         tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1611                         rx_snrX = (char)(tmp_rxsnr);
1612                         rx_snrX /= 2;
1613                         priv->stats.rxSNRdB[i] = (long)rx_snrX;
1614
1615                         RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
1616                         if (priv->brfpath_rxenable[i])
1617                                 total_rssi += RSSI;
1618
1619                         if (bpacket_match_bssid) {
1620                                 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1621                                 precord_stats->RxMIMOSignalStrength[i] =
1622                                                                 (u8) RSSI;
1623                         }
1624                 }
1625
1626
1627                 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1628                 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1629
1630                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1631                 pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1632                 pstats->RecvSignalPower = rx_pwr_all;
1633                 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1634                     pdrvinfo->RxRate <= DESC90_RATEMCS15)
1635                         max_spatial_stream = 2;
1636                 else
1637                         max_spatial_stream = 1;
1638
1639                 for (i = 0; i < max_spatial_stream; i++) {
1640                         tmp_rxevm = pofdm_buf->rxevm_X[i];
1641                         rx_evmX = (char)(tmp_rxevm);
1642
1643                         rx_evmX /= 2;
1644
1645                         evm = rtl819x_evm_dbtopercentage(rx_evmX);
1646                         if (bpacket_match_bssid) {
1647                                 if (i == 0) {
1648                                         pstats->SignalQuality = (u8)(evm &
1649                                                                  0xff);
1650                                         precord_stats->SignalQuality = (u8)(evm
1651                                                                         & 0xff);
1652                                 }
1653                                 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1654                                                                  0xff);
1655                                 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1656                                                                         & 0xff);
1657                         }
1658                 }
1659
1660
1661                 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1662                 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1663                         &rxsc_sgien_exflg;
1664                 if (pdrvinfo->BW)
1665                         priv->stats.received_bwtype[1+prxsc->rxsc]++;
1666                 else
1667                         priv->stats.received_bwtype[0]++;
1668         }
1669
1670         if (is_cck_rate) {
1671                 pstats->SignalStrength = precord_stats->SignalStrength =
1672                                          (u8)(rtl8192_signal_scale_mapping(priv,
1673                                          (long)pwdb_all));
1674
1675         } else {
1676                 if (rf_rx_num != 0)
1677                         pstats->SignalStrength = precord_stats->SignalStrength =
1678                                          (u8)(rtl8192_signal_scale_mapping(priv,
1679                                          (long)(total_rssi /= rf_rx_num)));
1680         }
1681 }
1682
1683 static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1684                                     struct rtllib_rx_stats *prev_st,
1685                                     struct rtllib_rx_stats *curr_st)
1686 {
1687         bool bcheck = false;
1688         u8      rfpath;
1689         u32 ij, tmp_val;
1690         static u32 slide_rssi_index, slide_rssi_statistics;
1691         static u32 slide_evm_index, slide_evm_statistics;
1692         static u32 last_rssi, last_evm;
1693         static u32 slide_beacon_adc_pwdb_index;
1694         static u32 slide_beacon_adc_pwdb_statistics;
1695         static u32 last_beacon_adc_pwdb;
1696         struct rtllib_hdr_3addr *hdr;
1697         u16 sc;
1698         unsigned int frag, seq;
1699
1700         hdr = (struct rtllib_hdr_3addr *)buffer;
1701         sc = le16_to_cpu(hdr->seq_ctl);
1702         frag = WLAN_GET_SEQ_FRAG(sc);
1703         seq = WLAN_GET_SEQ_SEQ(sc);
1704         curr_st->Seq_Num = seq;
1705         if (!prev_st->bIsAMPDU)
1706                 bcheck = true;
1707
1708         if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1709                 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1710                 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1711                 priv->stats.slide_rssi_total -= last_rssi;
1712         }
1713         priv->stats.slide_rssi_total += prev_st->SignalStrength;
1714
1715         priv->stats.slide_signal_strength[slide_rssi_index++] =
1716                                          prev_st->SignalStrength;
1717         if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1718                 slide_rssi_index = 0;
1719
1720         tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1721         priv->stats.signal_strength = rtl819x_translate_todbm(priv,
1722                                       (u8)tmp_val);
1723         curr_st->rssi = priv->stats.signal_strength;
1724         if (!prev_st->bPacketMatchBSSID) {
1725                 if (!prev_st->bToSelfBA)
1726                         return;
1727         }
1728
1729         if (!bcheck)
1730                 return;
1731
1732         rtl819x_process_cck_rxpathsel(priv, prev_st);
1733
1734         priv->stats.num_process_phyinfo++;
1735         if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1736                 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1737                         if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev,
1738                             rfpath))
1739                                 continue;
1740                         RT_TRACE(COMP_DBG, "Jacken -> pPreviousstats->RxMIMO"
1741                                  "SignalStrength[rfpath]  = %d\n",
1742                                  prev_st->RxMIMOSignalStrength[rfpath]);
1743                         if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1744                                 priv->stats.rx_rssi_percentage[rfpath] =
1745                                          prev_st->RxMIMOSignalStrength[rfpath];
1746                         }
1747                         if (prev_st->RxMIMOSignalStrength[rfpath]  >
1748                             priv->stats.rx_rssi_percentage[rfpath]) {
1749                                 priv->stats.rx_rssi_percentage[rfpath] =
1750                                         ((priv->stats.rx_rssi_percentage[rfpath]
1751                                         * (RX_SMOOTH - 1)) +
1752                                         (prev_st->RxMIMOSignalStrength
1753                                         [rfpath])) / (RX_SMOOTH);
1754                                 priv->stats.rx_rssi_percentage[rfpath] =
1755                                          priv->stats.rx_rssi_percentage[rfpath]
1756                                          + 1;
1757                         } else {
1758                                 priv->stats.rx_rssi_percentage[rfpath] =
1759                                    ((priv->stats.rx_rssi_percentage[rfpath] *
1760                                    (RX_SMOOTH-1)) +
1761                                    (prev_st->RxMIMOSignalStrength[rfpath])) /
1762                                    (RX_SMOOTH);
1763                         }
1764                         RT_TRACE(COMP_DBG, "Jacken -> priv->RxStats.RxRSSI"
1765                                  "Percentage[rfPath]  = %d\n",
1766                                  priv->stats.rx_rssi_percentage[rfpath]);
1767                 }
1768         }
1769
1770
1771         if (prev_st->bPacketBeacon) {
1772                 if (slide_beacon_adc_pwdb_statistics++ >=
1773                     PHY_Beacon_RSSI_SLID_WIN_MAX) {
1774                         slide_beacon_adc_pwdb_statistics =
1775                                          PHY_Beacon_RSSI_SLID_WIN_MAX;
1776                         last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1777                                                [slide_beacon_adc_pwdb_index];
1778                         priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1779                 }
1780                 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1781                 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1782                                                          prev_st->RxPWDBAll;
1783                 slide_beacon_adc_pwdb_index++;
1784                 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1785                         slide_beacon_adc_pwdb_index = 0;
1786                 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1787                                      slide_beacon_adc_pwdb_statistics;
1788                 if (prev_st->RxPWDBAll >= 3)
1789                         prev_st->RxPWDBAll -= 3;
1790         }
1791
1792         RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1793                                 prev_st->bIsCCK ? "CCK" : "OFDM",
1794                                 prev_st->RxPWDBAll);
1795
1796         if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1797             prev_st->bToSelfBA) {
1798                 if (priv->undecorated_smoothed_pwdb < 0)
1799                         priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1800                 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1801                         priv->undecorated_smoothed_pwdb =
1802                                         (((priv->undecorated_smoothed_pwdb) *
1803                                         (RX_SMOOTH-1)) +
1804                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1805                         priv->undecorated_smoothed_pwdb =
1806                                          priv->undecorated_smoothed_pwdb + 1;
1807                 } else {
1808                         priv->undecorated_smoothed_pwdb =
1809                                         (((priv->undecorated_smoothed_pwdb) *
1810                                         (RX_SMOOTH-1)) +
1811                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1812                 }
1813                 rtl819x_update_rxsignalstatistics8190pci(priv, prev_st);
1814         }
1815
1816         if (prev_st->SignalQuality != 0) {
1817                 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1818                     prev_st->bToSelfBA) {
1819                         if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1820                                 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1821                                 last_evm =
1822                                          priv->stats.slide_evm[slide_evm_index];
1823                                 priv->stats.slide_evm_total -= last_evm;
1824                         }
1825
1826                         priv->stats.slide_evm_total += prev_st->SignalQuality;
1827
1828                         priv->stats.slide_evm[slide_evm_index++] =
1829                                                  prev_st->SignalQuality;
1830                         if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1831                                 slide_evm_index = 0;
1832
1833                         tmp_val = priv->stats.slide_evm_total /
1834                                   slide_evm_statistics;
1835                         priv->stats.signal_quality = tmp_val;
1836                         priv->stats.last_signal_strength_inpercent = tmp_val;
1837                 }
1838
1839                 if (prev_st->bPacketToSelf ||
1840                     prev_st->bPacketBeacon ||
1841                     prev_st->bToSelfBA) {
1842                         for (ij = 0; ij < 2; ij++) {
1843                                 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1844                                         if (priv->stats.rx_evm_percentage[ij] == 0)
1845                                                 priv->stats.rx_evm_percentage[ij] =
1846                                                    prev_st->RxMIMOSignalQuality[ij];
1847                                         priv->stats.rx_evm_percentage[ij] =
1848                                           ((priv->stats.rx_evm_percentage[ij] *
1849                                           (RX_SMOOTH - 1)) +
1850                                           (prev_st->RxMIMOSignalQuality[ij])) /
1851                                           (RX_SMOOTH);
1852                                 }
1853                         }
1854                 }
1855         }
1856 }
1857
1858 static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1859                                            struct sk_buff *skb,
1860                                            struct rtllib_rx_stats *pstats,
1861                                            struct rx_desc *pdesc,
1862                                            struct rx_fwinfo *pdrvinfo)
1863 {
1864         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1865         bool bpacket_match_bssid, bpacket_toself;
1866         bool bPacketBeacon = false;
1867         struct rtllib_hdr_3addr *hdr;
1868         bool bToSelfBA = false;
1869         static struct rtllib_rx_stats  previous_stats;
1870         u16 fc, type;
1871         u8 *tmp_buf;
1872         u8 *praddr;
1873
1874         tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1875
1876         hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1877         fc = le16_to_cpu(hdr->frame_ctl);
1878         type = WLAN_FC_GET_TYPE(fc);
1879         praddr = hdr->addr1;
1880
1881         bpacket_match_bssid =
1882                 ((RTLLIB_FTYPE_CTL != type) &&
1883                  ether_addr_equal(priv->rtllib->current_network.bssid,
1884                                   (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1885                                   (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1886                                   hdr->addr3) &&
1887                  (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1888         bpacket_toself = bpacket_match_bssid &&         /* check this */
1889                          ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1890         if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1891                 bPacketBeacon = true;
1892         if (bpacket_match_bssid)
1893                 priv->stats.numpacket_matchbssid++;
1894         if (bpacket_toself)
1895                 priv->stats.numpacket_toself++;
1896         rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1897         rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1898                                   &previous_stats, bpacket_match_bssid,
1899                                   bpacket_toself, bPacketBeacon, bToSelfBA);
1900         rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
1901 }
1902
1903 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1904                                            struct net_device *dev,
1905                                            struct rtllib_rx_stats *pstats)
1906 {
1907         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1908         u32 rcvType = 1;
1909         u32 rateIndex;
1910         u32 preamble_guardinterval;
1911
1912         if (pstats->bCRC)
1913                 rcvType = 2;
1914         else if (pstats->bICV)
1915                 rcvType = 3;
1916
1917         if (pstats->bShortPreamble)
1918                 preamble_guardinterval = 1;
1919         else
1920                 preamble_guardinterval = 0;
1921
1922         switch (pstats->rate) {
1923         case MGN_1M:
1924                 rateIndex = 0;
1925                 break;
1926         case MGN_2M:
1927                 rateIndex = 1;
1928                  break;
1929         case MGN_5_5M:
1930                 rateIndex = 2;
1931                 break;
1932         case MGN_11M:
1933                 rateIndex = 3;
1934                 break;
1935         case MGN_6M:
1936                 rateIndex = 4;
1937                 break;
1938         case MGN_9M:
1939                 rateIndex = 5;
1940                 break;
1941         case MGN_12M:
1942                 rateIndex = 6;
1943                 break;
1944         case MGN_18M:
1945                 rateIndex = 7;
1946                  break;
1947         case MGN_24M:
1948                 rateIndex = 8;
1949                 break;
1950         case MGN_36M:
1951                 rateIndex = 9;
1952                 break;
1953         case MGN_48M:
1954                 rateIndex = 10;
1955                 break;
1956         case MGN_54M:
1957                 rateIndex = 11;
1958                 break;
1959         case MGN_MCS0:
1960                 rateIndex = 12;
1961                 break;
1962         case MGN_MCS1:
1963                 rateIndex = 13;
1964                 break;
1965         case MGN_MCS2:
1966                 rateIndex = 14;
1967                 break;
1968         case MGN_MCS3:
1969                 rateIndex = 15;
1970                 break;
1971         case MGN_MCS4:
1972                 rateIndex = 16;
1973                 break;
1974         case MGN_MCS5:
1975                 rateIndex = 17;
1976                 break;
1977         case MGN_MCS6:
1978                 rateIndex = 18;
1979                 break;
1980         case MGN_MCS7:
1981                 rateIndex = 19;
1982                 break;
1983         case MGN_MCS8:
1984                 rateIndex = 20;
1985                 break;
1986         case MGN_MCS9:
1987                 rateIndex = 21;
1988                 break;
1989         case MGN_MCS10:
1990                 rateIndex = 22;
1991                 break;
1992         case MGN_MCS11:
1993                 rateIndex = 23;
1994                 break;
1995         case MGN_MCS12:
1996                 rateIndex = 24;
1997                 break;
1998         case MGN_MCS13:
1999                 rateIndex = 25;
2000                 break;
2001         case MGN_MCS14:
2002                 rateIndex = 26;
2003                 break;
2004         case MGN_MCS15:
2005                 rateIndex = 27;
2006                 break;
2007         default:
2008                 rateIndex = 28;
2009                 break;
2010         }
2011         priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2012         priv->stats.received_rate_histogram[0][rateIndex]++;
2013         priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2014 }
2015
2016 bool rtl8192_rx_query_status_desc(struct net_device *dev,
2017                                   struct rtllib_rx_stats *stats,
2018                                   struct rx_desc *pdesc,
2019                                   struct sk_buff *skb)
2020 {
2021         struct r8192_priv *priv = rtllib_priv(dev);
2022
2023         stats->bICV = pdesc->ICV;
2024         stats->bCRC = pdesc->CRC32;
2025         stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2026
2027         stats->Length = pdesc->Length;
2028         if (stats->Length < 24)
2029                 stats->bHwError |= 1;
2030
2031         if (stats->bHwError) {
2032                 stats->bShift = false;
2033
2034                 if (pdesc->CRC32) {
2035                         if (pdesc->Length < 500)
2036                                 priv->stats.rxcrcerrmin++;
2037                         else if (pdesc->Length > 1000)
2038                                 priv->stats.rxcrcerrmax++;
2039                         else
2040                                 priv->stats.rxcrcerrmid++;
2041                 }
2042                 return false;
2043         } else {
2044                 struct rx_fwinfo *pDrvInfo = NULL;
2045
2046                 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2047                 stats->RxBufShift = ((pdesc->Shift)&0x03);
2048                 stats->Decrypted = !pdesc->SWDec;
2049
2050                 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2051
2052                 stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2053                                              (u8)pDrvInfo->RxRate);
2054                 stats->bShortPreamble = pDrvInfo->SPLCP;
2055
2056                 rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2057
2058                 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2059                 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2060                                     (pDrvInfo->FirstAGGR == 1);
2061
2062                 stats->TimeStampLow = pDrvInfo->TSFL;
2063                 stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
2064
2065                 rtl819x_UpdateRxPktTimeStamp(dev, stats);
2066
2067                 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2068                         stats->bShift = 1;
2069
2070                 stats->RxIs40MHzPacket = pDrvInfo->BW;
2071
2072                 rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2073                                                pDrvInfo);
2074
2075                 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2076                         RT_TRACE(COMP_RXDESC, "pDrvInfo->FirstAGGR = %d,"
2077                                  " pDrvInfo->PartAggr = %d\n",
2078                                  pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2079                 skb_trim(skb, skb->len - 4/*sCrcLng*/);
2080
2081
2082                 stats->packetlength = stats->Length-4;
2083                 stats->fraglength = stats->packetlength;
2084                 stats->fragoffset = 0;
2085                 stats->ntotalfrag = 1;
2086                 return true;
2087         }
2088 }
2089
2090 void rtl8192_halt_adapter(struct net_device *dev, bool reset)
2091 {
2092         struct r8192_priv *priv = rtllib_priv(dev);
2093         int i;
2094         u8      OpMode;
2095         u8      u1bTmp;
2096         u32     ulRegRead;
2097
2098         OpMode = RT_OP_MODE_NO_LINK;
2099         priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2100
2101         if (!priv->rtllib->bSupportRemoteWakeUp) {
2102                 u1bTmp = 0x0;
2103                 write_nic_byte(dev, CMDR, u1bTmp);
2104         }
2105
2106         mdelay(20);
2107
2108         if (!reset) {
2109                 mdelay(150);
2110
2111                 priv->bHwRfOffAction = 2;
2112
2113                 if (!priv->rtllib->bSupportRemoteWakeUp) {
2114                         PHY_SetRtl8192eRfOff(dev);
2115                         ulRegRead = read_nic_dword(dev, CPU_GEN);
2116                         ulRegRead |= CPU_GEN_SYSTEM_RESET;
2117                         write_nic_dword(dev, CPU_GEN, ulRegRead);
2118                 } else {
2119                         write_nic_dword(dev, WFCRC0, 0xffffffff);
2120                         write_nic_dword(dev, WFCRC1, 0xffffffff);
2121                         write_nic_dword(dev, WFCRC2, 0xffffffff);
2122
2123
2124                         write_nic_byte(dev, PMR, 0x5);
2125                         write_nic_byte(dev, MacBlkCtrl, 0xa);
2126                 }
2127         }
2128
2129         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2130                 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2131         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2132                 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2133
2134         skb_queue_purge(&priv->skb_queue);
2135         return;
2136 }
2137
2138 void rtl8192_update_ratr_table(struct net_device *dev)
2139 {
2140         struct r8192_priv *priv = rtllib_priv(dev);
2141         struct rtllib_device *ieee = priv->rtllib;
2142         u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2143         u32 ratr_value = 0;
2144         u16 rate_config = 0;
2145         u8 rate_index = 0;
2146
2147         rtl8192_config_rate(dev, &rate_config);
2148         ratr_value = rate_config | *pMcsRate << 12;
2149         switch (ieee->mode) {
2150         case IEEE_A:
2151                 ratr_value &= 0x00000FF0;
2152                 break;
2153         case IEEE_B:
2154                 ratr_value &= 0x0000000F;
2155                 break;
2156         case IEEE_G:
2157         case IEEE_G|IEEE_B:
2158                 ratr_value &= 0x00000FF7;
2159                 break;
2160         case IEEE_N_24G:
2161         case IEEE_N_5G:
2162                 if (ieee->pHTInfo->PeerMimoPs == 0) {
2163                         ratr_value &= 0x0007F007;
2164                 } else {
2165                         if (priv->rf_type == RF_1T2R)
2166                                 ratr_value &= 0x000FF007;
2167                         else
2168                                 ratr_value &= 0x0F81F007;
2169                 }
2170                 break;
2171         default:
2172                 break;
2173         }
2174         ratr_value &= 0x0FFFFFFF;
2175         if (ieee->pHTInfo->bCurTxBW40MHz &&
2176             ieee->pHTInfo->bCurShortGI40MHz)
2177                 ratr_value |= 0x80000000;
2178         else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2179                   ieee->pHTInfo->bCurShortGI20MHz)
2180                 ratr_value |= 0x80000000;
2181         write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
2182         write_nic_byte(dev, UFWP, 1);
2183 }
2184
2185 void
2186 rtl8192_InitializeVariables(struct net_device  *dev)
2187 {
2188         struct r8192_priv *priv = rtllib_priv(dev);
2189
2190         strcpy(priv->nick, "rtl8192E");
2191
2192         priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2193                 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2194                 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE /* |
2195                 IEEE_SOFTMAC_BEACONS*/;
2196
2197         priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2198
2199         priv->ShortRetryLimit = 0x30;
2200         priv->LongRetryLimit = 0x30;
2201
2202         priv->EarlyRxThreshold = 7;
2203         priv->pwrGroupCnt = 0;
2204
2205         priv->bIgnoreSilentReset = false;
2206         priv->enable_gpio0 = 0;
2207
2208         priv->TransmitConfig = 0;
2209
2210         priv->ReceiveConfig = RCR_ADD3  |
2211                 RCR_AMF | RCR_ADF |
2212                 RCR_AICV |
2213                 RCR_AB | RCR_AM | RCR_APM |
2214                 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2215                 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2216
2217         priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2218                             IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2219                             IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2220                             IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2221                             IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2222                             IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2223
2224
2225         priv->MidHighPwrTHR_L1 = 0x3B;
2226         priv->MidHighPwrTHR_L2 = 0x40;
2227         priv->PwrDomainProtect = false;
2228
2229         priv->bfirst_after_down = false;
2230 }
2231
2232 void rtl8192_EnableInterrupt(struct net_device *dev)
2233 {
2234         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2235
2236         priv->irq_enabled = 1;
2237
2238         write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]);
2239
2240 }
2241
2242 void rtl8192_DisableInterrupt(struct net_device *dev)
2243 {
2244         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2245
2246         write_nic_dword(dev, INTA_MASK, 0);
2247
2248         priv->irq_enabled = 0;
2249 }
2250
2251 void rtl8192_ClearInterrupt(struct net_device *dev)
2252 {
2253         u32 tmp = 0;
2254
2255         tmp = read_nic_dword(dev, ISR);
2256         write_nic_dword(dev, ISR, tmp);
2257 }
2258
2259
2260 void rtl8192_enable_rx(struct net_device *dev)
2261 {
2262         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2263
2264         write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2265 }
2266
2267 static const u32 TX_DESC_BASE[] = {
2268         BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2269 };
2270
2271 void rtl8192_enable_tx(struct net_device *dev)
2272 {
2273         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2274         u32 i;
2275
2276         for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2277                 write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2278 }
2279
2280
2281 void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta,
2282                                   u32 *p_intb)
2283 {
2284         *p_inta = read_nic_dword(dev, ISR);
2285         write_nic_dword(dev, ISR, *p_inta);
2286 }
2287
2288 bool rtl8192_HalRxCheckStuck(struct net_device *dev)
2289 {
2290         struct r8192_priv *priv = rtllib_priv(dev);
2291         u16               RegRxCounter = read_nic_word(dev, 0x130);
2292         bool              bStuck = false;
2293         static u8         rx_chk_cnt;
2294         u32             SlotIndex = 0, TotalRxStuckCount = 0;
2295         u8              i;
2296         u8              SilentResetRxSoltNum = 4;
2297
2298         RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2299                  __func__, RegRxCounter, priv->RxCounter);
2300
2301         rx_chk_cnt++;
2302         if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2303                 rx_chk_cnt = 0;
2304         } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2305           && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2306           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2307           || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2308           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2309                 if (rx_chk_cnt < 2)
2310                         return bStuck;
2311                 else
2312                         rx_chk_cnt = 0;
2313         } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2314                   (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2315                 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2316                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2317                 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2318                 if (rx_chk_cnt < 4)
2319                         return bStuck;
2320                 else
2321                         rx_chk_cnt = 0;
2322         } else {
2323                 if (rx_chk_cnt < 8)
2324                         return bStuck;
2325                 else
2326                         rx_chk_cnt = 0;
2327         }
2328
2329
2330         SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2331
2332         if (priv->RxCounter == RegRxCounter) {
2333                 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2334
2335                 for (i = 0; i < SilentResetRxSoltNum; i++)
2336                         TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2337
2338                 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2339                         bStuck = true;
2340                         for (i = 0; i < SilentResetRxSoltNum; i++)
2341                                 TotalRxStuckCount +=
2342                                          priv->SilentResetRxStuckEvent[i];
2343                 }
2344
2345
2346         } else {
2347                 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2348         }
2349
2350         priv->RxCounter = RegRxCounter;
2351
2352         return bStuck;
2353 }
2354
2355 bool rtl8192_HalTxCheckStuck(struct net_device *dev)
2356 {
2357         struct r8192_priv *priv = rtllib_priv(dev);
2358         bool    bStuck = false;
2359         u16     RegTxCounter = read_nic_word(dev, 0x128);
2360
2361         RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2362                  __func__, RegTxCounter, priv->TxCounter);
2363
2364         if (priv->TxCounter == RegTxCounter)
2365                 bStuck = true;
2366
2367         priv->TxCounter = RegTxCounter;
2368
2369         return bStuck;
2370 }
2371
2372 bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev)
2373 {
2374         struct r8192_priv *priv = rtllib_priv(dev);
2375         struct rtllib_device *ieee = priv->rtllib;
2376
2377         if (ieee->rtllib_ap_sec_type &&
2378            (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2379                                      SEC_ALG_TKIP))) {
2380                 return false;
2381         } else {
2382                 return true;
2383         }
2384 }
2385
2386 bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev)
2387 {
2388         bool Reval;
2389         struct r8192_priv *priv = rtllib_priv(dev);
2390         struct rtllib_device *ieee = priv->rtllib;
2391
2392         if (ieee->bHalfWirelessN24GMode == true)
2393                 Reval = true;
2394         else
2395                 Reval =  false;
2396
2397         return Reval;
2398 }
2399
2400 u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
2401 {
2402         u8   tmp_Short;
2403
2404         tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
2405                         ((tcb_desc->bUseShortPreamble) ? 1 : 0);
2406         if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
2407                 tmp_Short = 0;
2408
2409         return tmp_Short;
2410 }
2411
2412 void ActUpdateChannelAccessSetting(struct net_device *dev,
2413         enum wireless_mode WirelessMode,
2414         struct channel_access_setting *ChnlAccessSetting)
2415 {
2416         return;
2417 }