1 /*****************************************************************************
2 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved.
4 * Module: __INC_HAL8192SEREG_H
7 * Note: 1. Define Mac register address and corresponding bit mask map
9 * 3. Backward compatible register with useless address.
10 * 4. Define 92SU required register address and definition.
13 * Export: Constants, macro, functions(API), global variables(None).
19 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
20 * 2. Reorganize code architecture.
22 *****************************************************************************/
26 typedef enum _VERSION_8192S{
30 }VERSION_8192S,*PVERSION_8192S;
33 typedef enum _VERSION_8192SUsb{
34 VERSION_8192SU_A, //A-Cut
35 VERSION_8192SU_B, //B-Cut
36 VERSION_8192SU_C, //C-Cut
37 }VERSION_8192SUsb, *PVERSION_8192SUsb;
39 typedef enum _VERSION_819xU{
40 VERSION_819xU_A, // A-cut
41 VERSION_819xU_B, // B-cut
42 VERSION_819xU_C,// C-cut
43 }VERSION_819xU,*PVERSION_819xU;
46 /* 2007/11/15 MH Define different RF type. */
47 typedef enum _RT_RF_TYPE_DEFINITION
62 typedef enum _BaseBand_Config_Type{
63 BaseBand_Config_PHY_REG = 0, //Radio Path A
64 BaseBand_Config_AGC_TAB = 1, //Radio Path B
65 }BaseBand_Config_Type, *PBaseBand_Config_Type;
68 typedef enum _RT_RF_TYPE_819xU{
74 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
77 #define RTL8187_REQT_READ 0xc0
78 #define RTL8187_REQT_WRITE 0x40
79 #define RTL8187_REQ_GET_REGS 0x05
80 #define RTL8187_REQ_SET_REGS 0x05
85 #define R8180_MAX_RETRY 255
86 //#define MAX_RX_NORMAL_URB 3
87 //#define MAX_RX_COMMAND_URB 2
88 #define RX_URB_SIZE 9100
90 #define BB_ANTATTEN_CHAN14 0x0c
91 #define BB_ANTENNA_B 0x40
93 #define BB_HOST_BANG (1<<30)
94 #define BB_HOST_BANG_EN (1<<2)
95 #define BB_HOST_BANG_CLK (1<<1)
96 #define BB_HOST_BANG_RW (1<<3)
97 #define BB_HOST_BANG_DATA 1
100 //============================================================
101 // 8192S Regsiter bit
102 //============================================================
103 #define BB_GLOBAL_RESET_BIT 0x1
108 #define CR_MulRW 0x01
110 #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
111 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
113 #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
114 #define RX_FIFO_THRESHOLD_SHIFT 13
115 #define RX_FIFO_THRESHOLD_128 3
116 #define RX_FIFO_THRESHOLD_256 4
117 #define RX_FIFO_THRESHOLD_512 5
118 #define RX_FIFO_THRESHOLD_1024 6
119 #define RX_FIFO_THRESHOLD_NONE 7
121 #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
123 //----------------------------------------------------------------------------
124 // 8190 CPU General Register (offset 0x100, 4 byte)
125 //----------------------------------------------------------------------------
126 #define CPU_CCK_LOOPBACK 0x00030000
127 #define CPU_GEN_SYSTEM_RESET 0x00000001
128 #define CPU_GEN_FIRMWARE_RESET 0x00000008
129 #define CPU_GEN_BOOT_RDY 0x00000010
130 #define CPU_GEN_FIRM_RDY 0x00000020
131 #define CPU_GEN_PUT_CODE_OK 0x00000080
132 #define CPU_GEN_BB_RST 0x00000100
133 #define CPU_GEN_PWR_STB_CPU 0x00000004
134 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
135 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
136 //----------------------------------------------------------------------------
138 //// 8190 AcmHwCtrl bits (offset 0x171, 1 byte)
139 ////----------------------------------------------------------------------------
140 #define MSR_LINK_MASK ((1<<0)|(1<<1))
141 #define MSR_LINK_MANAGED 2
142 #define MSR_LINK_NONE 0
143 #define MSR_LINK_SHIFT 0
144 #define MSR_LINK_ADHOC 1
145 #define MSR_LINK_MASTER 3
146 #define MSR_LINK_ENEDCA (1<<4)
149 //#define Cmd9346CR_9356SEL (1<<4)
150 #define EPROM_CMD_RESERVED_MASK (1<<5)
151 #define EPROM_CMD_OPERATING_MODE_SHIFT 6
152 #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
153 #define EPROM_CMD_CONFIG 0x3
154 #define EPROM_CMD_NORMAL 0
155 #define EPROM_CMD_LOAD 1
156 #define EPROM_CMD_PROGRAM 2
157 #define EPROM_CS_SHIFT 3
158 #define EPROM_CK_SHIFT 2
159 #define EPROM_W_SHIFT 1
160 #define EPROM_R_SHIFT 0
162 //#define MAC0 0x000,
163 //#define MAC1 0x001,
164 //#define MAC2 0x002,
165 //#define MAC3 0x003,
166 //#define MAC4 0x004,
167 //#define MAC5 0x005,
169 //============================================================
170 // 8192S Regsiter offset definition
171 //============================================================
174 // MAC register 0x0 - 0x5xx
175 // 1. System configuration registers.
176 // 2. Command Control Registers
177 // 3. MACID Setting Registers
178 // 4. Timing Control Registers
179 // 5. FIFO Control Registers
180 // 6. Adaptive Control Registers
181 // 7. EDCA Setting Registers
182 // 8. WMAC, BA and CCX related Register.
183 // 9. Security Control Registers
184 // 10. Power Save Control Registers
185 // 11. General Purpose Registers
186 // 12. Host Interrupt Status Registers
187 // 13. Test Mode and Debug Control Registers
188 // 14. PCIE config register
193 // 1. System Configuration Registers (Offset: 0x0000 - 0x003F)
195 #define SYS_ISO_CTRL 0x0000 // System Isolation Interface Control.
196 #define SYS_FUNC_EN 0x0002 // System Function Enable.
197 #define PMC_FSM 0x0004 // Power Sequence Control.
198 #define SYS_CLKR 0x0008 // System Clock.
199 #define EPROM_CMD 0x000A // 93C46/93C56 Command Register. (win CR93C46)
200 #define EE_VPD 0x000C // EEPROM VPD Data.
201 #define AFE_MISC 0x0010 // AFE Misc.
202 #define SPS0_CTRL 0x0011 // Switching Power Supply 0 Control.
203 #define SPS1_CTRL 0x0018 // Switching Power Supply 1 Control.
204 #define RF_CTRL 0x001F // RF Block Control.
205 #define LDOA15_CTRL 0x0020 // V15 Digital LDO Control.
206 #define LDOV12D_CTRL 0x0021 // V12 Digital LDO Control.
207 #define LDOHCI12_CTRL 0x0022 // V12 Digital LDO Control.
208 #define LDO_USB_SDIO 0x0023 // LDO USB Control.
209 #define LPLDO_CTRL 0x0024 // Low Power LDO Control.
210 #define AFE_XTAL_CTRL 0x0026 // AFE Crystal Control.
211 #define AFE_PLL_CTRL 0x0028 // System Function Enable.
212 #define EFUSE_CTRL 0x0030 // E-Fuse Control.
213 #define EFUSE_TEST 0x0034 // E-Fuse Test.
214 #define PWR_DATA 0x0038 // Power on date.
215 #define DBG_PORT 0x003A // MAC debug port select
216 #define DPS_TIMER 0x003C // Deep Power Save Timer Register.
217 #define RCLK_MON 0x003E // Retention Clock Monitor.
220 // 2. Command Control Registers (Offset: 0x0040 - 0x004F)
222 #define CMDR 0x0040 // MAC Command Register.
223 #define TXPAUSE 0x0042 // Transmission Pause Register.
224 #define LBKMD_SEL 0x0043 // Loopback Mode Select Register.
225 #define TCR 0x0044 // Transmit Configuration Register
226 #define RCR 0x0048 // Receive Configuration Register
227 #define MSR 0x004C // Media Status register
228 #define SYSF_CFG 0x004D // System Function Configuration.
229 #define RX_PKY_LIMIT 0x004E // RX packet length limit
230 #define MBIDCTRL 0x004F // MBSSID Control.
233 // 3. MACID Setting Registers (Offset: 0x0050 - 0x007F)
235 #define MACIDR 0x0050 // MAC ID Register, Offset 0x0050-0x0055
236 #define MACIDR0 0x0050 // MAC ID Register, Offset 0x0050-0x0053
237 #define MACIDR4 0x0054 // MAC ID Register, Offset 0x0054-0x0055
238 #define BSSIDR 0x0058 // BSSID Register, Offset 0x0058-0x005D
239 #define HWVID 0x005E // HW Version ID.
240 #define MAR 0x0060 // Multicase Address.
241 #define MBIDCAMCONTENT 0x0068 // MBSSID CAM Content.
242 #define MBIDCAMCFG 0x0070 // MBSSID CAM Configuration.
243 #define BUILDTIME 0x0074 // Build Time Register.
244 #define BUILDUSER 0x0078 // Build User Register.
246 // Redifine MACID register, to compatible prior ICs.
251 // 4. Timing Control Registers (Offset: 0x0080 - 0x009F)
253 #define TSFR 0x0080 // Timing Sync Function Timer Register.
254 #define SLOT_TIME 0x0089 // Slot Time Register, in us.
255 #define USTIME 0x008A // EDCA/TSF clock unit time us unit.
256 #define SIFS_CCK 0x008C // SIFS for CCK, in us.
257 #define SIFS_OFDM 0x008E // SIFS for OFDM, in us.
258 #define PIFS_TIME 0x0090 // PIFS time register.
259 #define ACK_TIMEOUT 0x0091 // Ack Timeout Register
260 #define EIFSTR 0x0092 // EIFS time regiser.
261 #define BCN_INTERVAL 0x0094 // Beacon Interval, in TU.
262 #define ATIMWND 0x0096 // ATIM Window width, in TU.
263 #define BCN_DRV_EARLY_INT 0x0098 // Driver Early Interrupt.
264 #define BCN_DMATIME 0x009A // Beacon DMA and ATIM INT Time.
265 #define BCN_ERR_THRESH 0x009C // Beacon Error Threshold.
266 #define MLT 0x009D // MSDU Lifetime.
267 #define RSVD_MAC_TUNE_US 0x009E // MAC Internal USE.
270 // 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F)
273 #define RQPN1 0x00A0 // Reserved Queue Page Number for BK
274 #define RQPN2 0x00A1 // Reserved Queue Page Number for BE
275 #define RQPN3 0x00A2 // Reserved Queue Page Number for VI
276 #define RQPN4 0x00A3 // Reserved Queue Page Number for VO
277 #define RQPN5 0x00A4 // Reserved Queue Page Number for HCCA
278 #define RQPN6 0x00A5 // Reserved Queue Page Number for CMD
279 #define RQPN7 0x00A6 // Reserved Queue Page Number for MGNT
280 #define RQPN8 0x00A7 // Reserved Queue Page Number for HIGH
281 #define RQPN9 0x00A8 // Reserved Queue Page Number for Beacon
282 #define RQPN10 0x00A9 // Reserved Queue Page Number for Public
283 #define LD_RQPN 0x00AB //
284 #define RXFF_BNDY 0x00AC //
285 #define RXRPT_BNDY 0x00B0 //
286 #define TXPKTBUF_PGBNDY 0x00B4 //
287 #define PBP 0x00B5 //
288 #define RXDRVINFO_SZ 0x00B6 //
289 #define TXFF_STATUS 0x00B7 //
290 #define RXFF_STATUS 0x00B8 //
291 #define TXFF_EMPTY_TH 0x00B9 //
292 #define SDIO_RX_BLKSZ 0x00BC //
293 #define RXDMA 0x00BD //
294 #define RXPKT_NUM 0x00BE //
295 #define C2HCMD_UDT_SIZE 0x00C0 //
296 #define C2HCMD_UDT_ADDR 0x00C2 //
297 #define FIFOPAGE1 0x00C4 // Available public queue page number
298 #define FIFOPAGE2 0x00C8 //
299 #define FIFOPAGE3 0x00CC //
300 #define FIFOPAGE4 0x00D0 //
301 #define FIFOPAGE5 0x00D4 //
302 #define FW_RSVD_PG_CRTL 0x00D8 //
303 #define RXDMA_AGG_PG_TH 0x00D9 //
304 #define TXRPTFF_RDPTR 0x00E0 //
305 #define TXRPTFF_WTPTR 0x00E4 //
306 #define C2HFF_RDPTR 0x00E8 //FIFO Read pointer register.
307 #define C2HFF_WTPTR 0x00EC //FIFO Write pointer register.
308 #define RXFF0_RDPTR 0x00F0 //
309 #define RXFF0_WTPTR 0x00F4 //
310 #define RXFF1_RDPTR 0x00F8 //
311 #define RXFF1_WTPTR 0x00FC //
312 #define RXRPT0_RDPTR 0x0100 //
313 #define RXRPT0_WTPTR 0x0104 //
314 #define RXRPT1_RDPTR 0x0108 //
315 #define RXRPT1_WTPTR 0x010C //
316 #define RX0_UDT_SIZE 0x0110 //
317 #define RX1PKTNUM 0x0114 //
318 #define RXFILTERMAP 0x0116 //
319 #define RXFILTERMAP_GP1 0x0118 //
320 #define RXFILTERMAP_GP2 0x011A //
321 #define RXFILTERMAP_GP3 0x011C //
322 #define BCNQ_CTRL 0x0120 //
323 #define MGTQ_CTRL 0x0124 //
324 #define HIQ_CTRL 0x0128 //
325 #define VOTID7_CTRL 0x012c //
326 #define VOTID6_CTRL 0x0130 //
327 #define VITID5_CTRL 0x0134 //
328 #define VITID4_CTRL 0x0138 //
329 #define BETID3_CTRL 0x013c //
330 #define BETID0_CTRL 0x0140 //
331 #define BKTID2_CTRL 0x0144 //
332 #define BKTID1_CTRL 0x0148 //
333 #define CMDQ_CTRL 0x014c //
334 #define TXPKT_NUM_CTRL 0x0150 //
335 #define TXQ_PGADD 0x0152 //
336 #define TXFF_PG_NUM 0x0154 //
337 #define TRXDMA_STATUS 0x0156 //
340 // 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF)
342 #define INIMCS_SEL 0x0160 // Init MCSrate for 32 MACID 0x160-17f
343 #define TX_RATE_REG INIMCS_SEL //Current Tx rate register
344 #define INIRTSMCS_SEL 0x0180 // Init RTSMCSrate
345 #define RRSR 0x0181 // Response rate setting.
346 #define ARFR0 0x0184 // Auto Rate Fallback 0 Register.
347 #define ARFR1 0x0188 //
348 #define ARFR2 0x018C //
349 #define ARFR3 0x0190 //
350 #define ARFR4 0x0194 //
351 #define ARFR5 0x0198 //
352 #define ARFR6 0x019C //
353 #define ARFR7 0x01A0 //
354 #define AGGLEN_LMT_H 0x01A7 // Aggregation Length Limit for High-MCS
355 #define AGGLEN_LMT_L 0x01A8 // Aggregation Length Limit for Low-MCS.
356 #define DARFRC 0x01B0 // Data Auto Rate Fallback Retry Count.
357 #define RARFRC 0x01B8 // Response Auto Rate Fallback Count.
358 #define MCS_TXAGC 0x01C0
359 #define CCK_TXAGC 0x01C8
362 // 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF)
364 #define EDCAPARA_VO 0x01D0 // EDCA Parameter Register for VO queue.
365 #define EDCAPARA_VI 0x01D4 // EDCA Parameter Register for VI queue.
366 #define EDCAPARA_BE 0x01D8 // EDCA Parameter Register for BE queue.
367 #define EDCAPARA_BK 0x01DC // EDCA Parameter Register for BK queue.
368 #define BCNTCFG 0x01E0 // Beacon Time Configuration Register.
369 #define CWRR 0x01E2 // Contention Window Report Register.
370 #define ACMAVG 0x01E4 // ACM Average Register.
371 #define AcmHwCtrl 0x01E7
372 #define VO_ADMTM 0x01E8 // Admission Time Register.
373 #define VI_ADMTM 0x01EC
374 #define BE_ADMTM 0x01F0
375 #define RETRY_LIMIT 0x01F4 // Retry Limit Registers[15:8]-short, [7:0]-long
376 #define SG_RATE 0x01F6 // Max MCS Rate Available Register, which we Set the hightst SG rate.
379 // 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F)
381 #define NAV_CTRL 0x0200
382 #define BW_OPMODE 0x0203
383 #define BACAMCMD 0x0204
384 #define BACAMCONTENT 0x0208 // Block ACK CAM R/W Register.
386 // Roger had defined the 0x2xx register WMAC definition
387 #define LBDLY 0x0210 // Loopback Delay Register.
388 #define FWDLY 0x0211 // FW Delay Register.
389 #define HWPC_RX_CTRL 0x0218 // HW Packet Conversion RX Control Reg
390 #define MQIR 0x0220 // Mesh Qos Type Indication Register.
391 #define MAIR 0x0222 // Mesh ACK.
392 #define MSIR 0x0224 // Mesh HW Security Requirement Indication Reg
393 #define CLM_RESULT 0x0227 // CCA Busy Fraction(Channel Load)
394 #define NHM_RPI_CNT 0x0228 // Noise Histogram Measurement (NHM) RPI Report.
395 #define RXERR_RPT 0x0230 // Rx Error Report.
396 #define NAV_PROT_LEN 0x0234 // NAV Protection Length.
397 #define CFEND_TH 0x0236 // CF-End Threshold.
398 #define AMPDU_MIN_SPACE 0x0237 // AMPDU Min Space.
399 #define TXOP_STALL_CTRL 0x0238
402 // 9. Security Control Registers (Offset: 0x0240 - 0x025F)
404 #define RWCAM 0x0240 //IN 8190 Data Sheet is called CAMcmd
405 #define WCAMI 0x0244 // Software write CAM input content
406 #define RCAMO 0x0248 // Software read/write CAM config
407 #define CAMDBG 0x024C
408 #define SECR 0x0250 //Security Configuration Register
411 // 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF)
413 #define WOW_CTRL 0x0260 //Wake On WLAN Control.
414 #define PSSTATUS 0x0261 // Power Save Status.
415 #define PSSWITCH 0x0262 // Power Save Switch.
416 #define MIMOPS_WAIT_PERIOD 0x0263
417 #define LPNAV_CTRL 0x0264
418 #define WFM0 0x0270 // Wakeup Frame Mask.
419 #define WFM1 0x0280 //
420 #define WFM2 0x0290 //
421 #define WFM3 0x02A0 //
422 #define WFM4 0x02B0 //
423 #define WFM5 0x02C0 // FW Control register.
424 #define WFCRC 0x02D0 // Wakeup Frame CRC.
425 #define RPWM 0x02DC // Host Request Power Mode.
426 #define CPWM 0x02DD // Current Power Mode.
427 #define FW_RPT_REG 0x02c4
430 // 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)
432 #define PSTIME 0x02E0 // Power Save Timer Register
433 #define TIMER0 0x02E4 //
434 #define TIMER1 0x02E8 //
435 #define GPIO_CTRL 0x02EC // GPIO Control Register
436 #define GPIO_IN 0x02EC // GPIO pins input value
437 #define GPIO_OUT 0x02ED // GPIO pins output value
438 #define GPIO_IO_SEL 0x02EE // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
439 #define GPIO_MOD 0x02EF //
440 #define GPIO_INTCTRL 0x02F0 // GPIO Interrupt Control Register[7:0]
441 #define MAC_PINMUX_CFG 0x02F1 // MAC PINMUX Configuration Reg[7:0]
442 #define LEDCFG 0x02F2 // System PINMUX Configuration Reg[7:0]
443 #define PHY_REG 0x02F3 // RPT: PHY REG Access Report Reg[7:0]
444 #define PHY_REG_DATA 0x02F4 // PHY REG Read DATA Register [31:0]
445 #define EFUSE_CLK 0x02F8 // CTRL: E-FUSE Clock Control Reg[7:0]
446 //#define GPIO_INTCTRL 0x02F9 // GPIO Interrupt Control Register[7:0]
449 // 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F)
451 #define IMR 0x0300 // Interrupt Mask Register
452 #define ISR 0x0308 // Interrupt Status Register
455 // 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F)
457 #define DBG_PORT_SWITCH 0x003A
458 #define BIST 0x0310 // Bist reg definition
459 #define DBS 0x0314 // Debug Select ???
460 #define CPUINST 0x0318 // CPU Instruction Read Register
461 #define CPUCAUSE 0x031C // CPU Cause Register
462 #define LBUS_ERR_ADDR 0x0320 // Lexra Bus Error Address Register
463 #define LBUS_ERR_CMD 0x0324 // Lexra Bus Error Command Register
464 #define LBUS_ERR_DATA_L 0x0328 // Lexra Bus Error Data Low DW Register
465 #define LBUS_ERR_DATA_H 0x032C //
466 #define LX_EXCEPTION_ADDR 0x0330 // Lexra Bus Exception Address Register
467 #define WDG_CTRL 0x0334 // Watch Dog Control Register
468 #define INTMTU 0x0338 // Interrupt Mitigation Time Unit Reg
469 #define INTM 0x033A // Interrupt Mitigation Register
470 #define FDLOCKTURN0 0x033C // FW/DRV Lock Turn 0 Register
471 #define FDLOCKTURN1 0x033D // FW/DRV Lock Turn 1 Register
472 #define TRXPKTBUF_DBG_DATA 0x0340 // TRX Packet Buffer Debug Data Register
473 #define TRXPKTBUF_DBG_CTRL 0x0348 // TRX Packet Buffer Debug Control Reg
474 #define DPLL 0x034A // DPLL Monitor Register [15:0]
475 #define CBUS_ERR_ADDR 0x0350 // CPU Bus Error Address Register
476 #define CBUS_ERR_CMD 0x0354 // CPU Bus Error Command Register
477 #define CBUS_ERR_DATA_L 0x0358 // CPU Bus Error Data Low DW Register
478 #define CBUS_ERR_DATA_H 0x035C //
479 #define USB_SIE_INTF_ADDR 0x0360 // USB SIE Access Interface Address Reg
480 #define USB_SIE_INTF_WD 0x0361 // USB SIE Access Interface WData Reg
481 #define USB_SIE_INTF_RD 0x0362 // USB SIE Access Interface RData Reg
482 #define USB_SIE_INTF_CTRL 0x0363 // USB SIE Access Interface Control Reg
487 // 14. PCIE config register (Offset 0x500-)
489 #define TPPoll 0x0500 // Transmit Polling
490 #define PM_CTRL 0x0502 // PCIE power management control Register
491 #define PCIF 0x0503 // PCI Function Register 0x0009h~0x000bh
493 #define THPDA 0x0514 // Transmit High Priority Desc Addr
494 #define TMDA 0x0518 // Transmit Management Desc Addr
495 #define TCDA 0x051C // Transmit Command Desc Addr
496 #define HDA 0x0520 // HCCA Desc Addr
497 #define TVODA 0x0524 // Transmit VO Desc Addr
498 #define TVIDA 0x0528 // Transmit VI Desc Addr
499 #define TBEDA 0x052C // Transmit BE Desc Addr
500 #define TBKDA 0x0530 // Transmit BK Desc Addr
501 #define TBDA 0x0534 // Transmit Beacon Desc Addr
502 #define RCDA 0x0538 // Receive Command Desc Addr
503 #define RDSA 0x053C // Receive Desc Starting Addr
504 #define DBI_WDATA 0x0540 // DBI write data Register
505 #define DBI_RDATA 0x0544 // DBI read data Register
506 #define DBI_CTRL 0x0548 // PCIE DBI control Register
507 #define MDIO_DATA 0x0550 // PCIE MDIO data Register
508 #define MDIO_CTRL 0x0554 // PCIE MDIO control Register
509 #define PCI_RPWM 0x0561 // PCIE RPWM register
510 #define PCI_CPWM 0x0563 // Current Power Mode.
513 // Config register (Offset 0x800-)
515 #define PHY_CCA 0x803 // CCA related register
517 //============================================================================
518 // 8192S USB specific Regsiter Offset and Content definition,
519 // 2008.08.28, added by Roger.
520 //============================================================================
521 // Rx Aggregation time-out reg.
522 #define USB_RX_AGG_TIMEOUT 0xFE5B
524 // Firware reserved Tx page control.
525 #define FW_OFFLOAD_EN BIT7
527 // Min Spacing related settings.
528 #define MAX_MSS_DENSITY 0x13
529 #define MAX_MSS_DENSITY_2T 0x13
530 #define MAX_MSS_DENSITY_1T 0x0A
532 // Rx DMA Control related settings
533 #define RXDMA_AGG_EN BIT7
535 // USB Rx Aggregation TimeOut settings
536 #define RXDMA_AGG_TIMEOUT_DISABLE 0x00
537 #define RXDMA_AGG_TIMEOUT_17MS 0x01
538 #define RXDMA_AGG_TIMEOUT_17_2_MS 0x02
539 #define RXDMA_AGG_TIMEOUT_17_4_MS 0x04
540 #define RXDMA_AGG_TIMEOUT_17_10_MS 0x0A
542 #define USB_RPWM 0xFE58
544 //FIXLZM SVN_BRACH NOT MOD HERE, IF MOD RX IS LITTLE LOW
545 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==PCI_INTERFACE))
546 //#define RPWM PCI_RPWM
547 //#elif ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
548 //#define RPWM USB_RPWM
552 //============================================================================
553 // 8190 Regsiter offset definition
554 //============================================================================
555 #if 1 // Delete the register later
556 #define AFR 0x010 // AutoLoad Function Register
557 #define BCN_TCFG 0x062 // Beacon Time Configuration
558 #define RATR0 0x320 // Rate Adaptive Table register1
560 // TODO: Remove unused register, We must declare backward compatiable
561 //Undefined register set in 8192S. 0x320/350 DW is useless
562 #define UnusedRegister 0x0320
563 #define PSR UnusedRegister // Page Select Register
565 #define DCAM UnusedRegister // Debug CAM Interface
566 //PHY Configuration related
567 #define BBAddr UnusedRegister // Phy register address register
568 #define PhyDataR UnusedRegister // Phy register data read
569 #define UFWP UnusedRegister
572 //============================================================================
573 // 8192S Regsiter Bit and Content definition
574 //============================================================================
577 // 1. System Configuration Registers (Offset: 0x0000 - 0x003F)
579 //----------------------------------------------------------------------------
580 // 8192S SYS_ISO_CTRL bits (Offset 0x0, 16bit)
581 //----------------------------------------------------------------------------
582 #define ISO_MD2PP BIT0 // MACTOP/BB/PCIe Digital to Power On.
583 #define ISO_PA2PCIE BIT3 // PCIe Analog 1.2V to PCIe 3.3V
584 #define ISO_PLL2MD BIT4 // AFE PLL to MACTOP/BB/PCIe Digital.
585 #define ISO_PWC_DV2RP BIT11 // Digital Vdd to Retention Path
586 #define ISO_PWC_RV2RP BIT12 // LPLDOR12 to Retenrion Path, 1: isolation, 0: attach.
588 //----------------------------------------------------------------------------
589 // 8192S SYS_FUNC_EN bits (Offset 0x2, 16bit)
590 //----------------------------------------------------------------------------
591 #define FEN_MREGEN BIT15 // MAC I/O Registers Enable.
592 #define FEN_DCORE BIT11 // Enable Core Digital.
593 #define FEN_CPUEN BIT10 // Enable CPU Core Digital.
594 // 8192S PMC_FSM bits (Offset 0x4, 32bit)
595 //----------------------------------------------------------------------------
596 #define PAD_HWPD_IDN BIT22 // HWPDN PAD status Indicator
598 //----------------------------------------------------------------------------
600 //----------------------------------------------------------------------------
601 // 8192S SYS_CLKR bits (Offset 0x8, 16bit)
602 //----------------------------------------------------------------------------
603 #define SYS_CLKSEL_80M BIT0 // System Clock 80MHz
604 #define SYS_PS_CLKSEL BIT1 //System power save clock select.
605 #define SYS_CPU_CLKSEL BIT2 // System Clock select, 1: AFE source, 0: System clock(L-Bus)
606 #define SYS_MAC_CLK_EN BIT11 // MAC Clock Enable.
607 #define SYS_SWHW_SEL BIT14 // Load done, control path seitch.
608 #define SYS_FWHW_SEL BIT15 // Sleep exit, control path swith.
611 //----------------------------------------------------------------------------
612 // 8192S Cmd9346CR bits (Offset 0xA, 16bit)
613 //----------------------------------------------------------------------------
614 #define CmdEEPROM_En BIT5 // EEPROM enable when set 1
615 #define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
616 #define Cmd9346CR_9356SEL BIT4
617 #define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
618 #define AutoLoadEFUSE CmdEEPROM_En
621 //----------------------------------------------------------------------------
622 // 8192S AFE_MISC bits AFE Misc (Offset 0x10, 8bits)
623 //----------------------------------------------------------------------------
624 #define AFE_MBEN BIT1 // Enable AFE Macro Block's Mbias.
625 #define AFE_BGEN BIT0 // Enable AFE Macro Block's Bandgap.
627 //----------------------------------------------------------------------------
628 // 8192S SPS1_CTRL bits (Offset 0x18-1E, 56bits)
629 //----------------------------------------------------------------------------
630 #define SPS1_SWEN BIT1 // Enable vsps18 SW Macro Block.
631 #define SPS1_LDEN BIT0 // Enable VSPS12 LDO Macro block.
633 //----------------------------------------------------------------------------
634 // 8192S RF_CTRL bits (Offset 0x1F, 8bits)
635 //----------------------------------------------------------------------------
636 #define RF_EN BIT0 // Enable RF module.
637 #define RF_RSTB BIT1 // Reset RF module.
638 #define RF_SDMRSTB BIT2 // Reset RF SDM module.
640 //----------------------------------------------------------------------------
641 // 8192S LDOA15_CTRL bits (Offset 0x20, 8bits)
642 //----------------------------------------------------------------------------
643 #define LDA15_EN BIT0 // Enable LDOA15 Macro Block
645 //----------------------------------------------------------------------------
646 // 8192S LDOV12D_CTRL bits (Offset 0x21, 8bits)
647 //----------------------------------------------------------------------------
648 #define LDV12_EN BIT0 // Enable LDOVD12 Macro Block
649 #define LDV12_SDBY BIT1 // LDOVD12 standby mode
651 //----------------------------------------------------------------------------
652 // 8192S AFE_XTAL_CTRL bits AFE Crystal Control. (Offset 0x26,16bits)
653 //----------------------------------------------------------------------------
654 #define XTAL_GATE_AFE BIT10
655 // Gated Control. 1: AFE Clock source gated, 0: Clock enable.
657 //----------------------------------------------------------------------------
658 // 8192S AFE_PLL_CTRL bits System Function Enable (Offset 0x28,64bits)
659 //----------------------------------------------------------------------------
660 #define APLL_EN BIT0 // Enable AFE PLL Macro Block.
662 // Find which card bus type
663 #define AFR_CardBEn BIT0
664 #define AFR_CLKRUN_SEL BIT1
665 #define AFR_FuncRegEn BIT2
668 // 2. Command Control Registers (Offset: 0x0040 - 0x004F)
670 //----------------------------------------------------------------------------
671 // 8192S (CMD) command register bits (Offset 0x40, 16 bits)
672 //----------------------------------------------------------------------------
673 #define APSDOFF_STATUS BIT15 //
674 #define APSDOFF BIT14 //
675 #define BBRSTn BIT13 //Enable OFDM/CCK
676 #define BB_GLB_RSTn BIT12 //Enable BB
677 #define SCHEDULE_EN BIT10 //Enable MAC scheduler
678 #define MACRXEN BIT9 //
679 #define MACTXEN BIT8 //
680 #define DDMA_EN BIT7 //FW off load function enable
681 #define FW2HW_EN BIT6 //MAC every module reset as below
682 #define RXDMA_EN BIT5 //
683 #define TXDMA_EN BIT4 //
684 #define HCI_RXDMA_EN BIT3 //
685 #define HCI_TXDMA_EN BIT2 //
687 //----------------------------------------------------------------------------
688 // 8192S (TXPAUSE) transmission pause (Offset 0x42, 8 bits)
689 //----------------------------------------------------------------------------
690 #define StopHCCA BIT6
691 #define StopHigh BIT5
698 //----------------------------------------------------------------------------
699 // 8192S (LBKMD) LoopBack Mode Select (Offset 0x43, 8 bits)
700 //----------------------------------------------------------------------------
702 // [3] no buffer, 1: no delay, 0: delay; [2] dmalbk, [1] no_txphy, [0] diglbk.
704 // 1011: MAC loopback (involving CPU)
705 // 0011: MAC Delay Loopback
706 // 0001: PHY loopback (not yet implemented)
707 // 0111: DMA loopback (only uses TxPktBuffer and DMA engine)
708 // All other combinations are reserved.
711 #define LBK_NORMAL 0x00
712 #define LBK_MAC_LB (BIT0|BIT1|BIT3)
713 #define LBK_MAC_DLB (BIT0|BIT1)
714 #define LBK_DMA_LB (BIT0|BIT1|BIT2)
716 //----------------------------------------------------------------------------
717 // 8192S (TCR) transmission Configuration Register (Offset 0x44, 32 bits)
718 //----------------------------------------------------------------------------
719 #define TCP_OFDL_EN BIT25 //For CE packet conversion
720 #define HWPC_TX_EN BIT24 //""
721 #define TXDMAPRE2FULL BIT23 //TXDMA enable pre2full sync
722 #define DISCW BIT20 //CW disable
723 #define TCRICV BIT19 //Append ICV or not
724 #define CfendForm BIT17 //AP mode
725 #define TCRCRC BIT16 //Append CRC32
726 #define FAKE_IMEM_EN BIT15 //
727 #define TSFRST BIT9 //
728 #define TSFEN BIT8 //
729 // For TCR FW download ready --> write by FW Bit0-7 must all one
730 #define FWALLRDY (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7)
734 #define DMEM_CODE_DONE BIT4
735 #define EXT_IMEM_CHK_RPT BIT3
736 #define EXT_IMEM_CODE_DONE BIT2
737 #define IMEM_CHK_RPT BIT1
738 #define IMEM_CODE_DONE BIT0
739 // Copy fomr 92SU definition
740 #define IMEM_CODE_DONE BIT0
741 #define IMEM_CHK_RPT BIT1
742 #define EMEM_CODE_DONE BIT2
743 #define EMEM_CHK_RPT BIT3
744 #define DMEM_CODE_DONE BIT4
745 #define IMEM_RDY BIT5
748 #define LOAD_FW_READY (IMEM_CODE_DONE|IMEM_CHK_RPT|EMEM_CODE_DONE|\
749 EMEM_CHK_RPT|DMEM_CODE_DONE|IMEM_RDY|BASECHG|\
751 #define TCR_TSFEN BIT8 // TSF function on or off.
752 #define TCR_TSFRST BIT9 // Reset TSF function to zero.
753 #define TCR_FAKE_IMEM_EN BIT15
754 #define TCR_CRC BIT16
755 #define TCR_ICV BIT19 // Integrity Check Value.
756 #define TCR_DISCW BIT20 // Disable Contention Windows Backoff.
757 #define TCR_HWPC_TX_EN BIT24
758 #define TCR_TCP_OFDL_EN BIT25
759 #define TXDMA_INIT_VALUE (IMEM_CHK_RPT|EXT_IMEM_CHK_RPT)
760 //----------------------------------------------------------------------------
761 // 8192S (RCR) Receive Configuration Register (Offset 0x48, 32 bits)
762 //----------------------------------------------------------------------------
763 #define RCR_APPFCS BIT31 //WMAC append FCS after pauload
764 #define RCR_DIS_ENC_2BYTE BIT30 //HW encrypt 2 or 1 byte mode
765 #define RCR_DIS_AES_2BYTE BIT29 //
766 #define RCR_HTC_LOC_CTRL BIT28 //MFC<--HTC=1 MFC-->HTC=0
767 #define RCR_ENMBID BIT27 //Enable Multiple BssId.
768 #define RCR_RX_TCPOFDL_EN BIT26 //
769 #define RCR_APP_PHYST_RXFF BIT25 //
770 #define RCR_APP_PHYST_STAFF BIT24 //
771 #define RCR_CBSSID BIT23 //Accept BSSID match packet
772 #define RCR_APWRMGT BIT22 //Accept power management packet
773 #define RCR_ADD3 BIT21 //Accept address 3 match packet
774 #define RCR_AMF BIT20 //Accept management type frame
775 #define RCR_ACF BIT19 //Accept control type frame
776 #define RCR_ADF BIT18 //Accept data type frame
777 #define RCR_APP_MIC BIT17 //
778 #define RCR_APP_ICV BIT16 //
779 #define RCR_RXFTH BIT13 //Rx FIFO Threshold Bot 13 - 15
780 #define RCR_AICV BIT12 //Accept ICV error packet
781 #define RCR_RXDESC_LK_EN BIT11 //Accept to update rx desc length
782 #define RCR_APP_BA_SSN BIT6 //Accept BA SSN
783 #define RCR_ACRC32 BIT5 //Accept CRC32 error packet
784 #define RCR_RXSHFT_EN BIT4 //Accept broadcast packet
785 #define RCR_AB BIT3 //Accept broadcast packet
786 #define RCR_AM BIT2 //Accept multicast packet
787 #define RCR_APM BIT1 //Accept physical match packet
788 #define RCR_AAP BIT0 //Accept all unicast packet
789 #define RCR_MXDMA_OFFSET 8
790 #define RCR_FIFO_OFFSET 13
794 #define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
795 #define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2
796 #define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1
797 #define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames
799 //----------------------------------------------------------------------------
800 // 8192S (MSR) Media Status Register (Offset 0x4C, 8 bits)
801 //----------------------------------------------------------------------------
805 01: Link in ad hoc network
806 10: Link in infrastructure network
810 #define MSR_NOLINK 0x00
811 #define MSR_ADHOC 0x01
812 #define MSR_INFRA 0x02
815 //----------------------------------------------------------------------------
816 // 8192S (SYSF_CFG) system Fucntion Config Reg (Offset 0x4D, 8 bits)
817 //----------------------------------------------------------------------------
820 #define BTMODE (BIT2|BIT1)
823 //----------------------------------------------------------------------------
824 // 8192S (MBIDCTRL) MBSSID Control Register (Offset 0x4F, 8 bits)
825 //----------------------------------------------------------------------------
827 #define BCNUM (BIT6|BIT5|BIT4)
830 // 3. MACID Setting Registers (Offset: 0x0050 - 0x007F)
834 // 4. Timing Control Registers (Offset: 0x0080 - 0x009F)
836 //----------------------------------------------------------------------------
837 // 8192S (USTIME) US Time Tunning Register (Offset 0x8A, 16 bits)
838 //----------------------------------------------------------------------------
839 #define USTIME_EDCA 0xFF00
840 #define USTIME_TSF 0x00FF
842 //----------------------------------------------------------------------------
843 // 8192S (SIFS_CCK/OFDM) US Time Tunning Register (Offset 0x8C/8E,16 bits)
844 //----------------------------------------------------------------------------
845 #define SIFS_TRX 0xFF00
846 #define SIFS_CTX 0x00FF
848 //----------------------------------------------------------------------------
849 // 8192S (DRVERLYINT) Driver Early Interrupt Reg (Offset 0x98, 16bit)
850 //----------------------------------------------------------------------------
851 #define ENSWBCN BIT15
852 #define DRVERLY_TU 0x0FF0
853 #define DRVERLY_US 0x000F
854 #define BCN_TCFG_CW_SHIFT 8
855 #define BCN_TCFG_IFS 0
858 // 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F)
862 // 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF)
864 //----------------------------------------------------------------------------
865 // 8192S Response Rate Set Register (offset 0x181, 24bits)
866 //----------------------------------------------------------------------------
867 #define RRSR_RSC_OFFSET 21
868 #define RRSR_SHORT_OFFSET 23
869 #define RRSR_RSC_BW_40M 0x600000
870 #define RRSR_RSC_UPSUBCHNL 0x400000
871 #define RRSR_RSC_LOWSUBCHNL 0x200000
872 #define RRSR_SHORT 0x800000
875 #define RRSR_5_5M BIT2
876 #define RRSR_11M BIT3
879 #define RRSR_12M BIT6
880 #define RRSR_18M BIT7
881 #define RRSR_24M BIT8
882 #define RRSR_36M BIT9
883 #define RRSR_48M BIT10
884 #define RRSR_54M BIT11
885 #define RRSR_MCS0 BIT12
886 #define RRSR_MCS1 BIT13
887 #define RRSR_MCS2 BIT14
888 #define RRSR_MCS3 BIT15
889 #define RRSR_MCS4 BIT16
890 #define RRSR_MCS5 BIT17
891 #define RRSR_MCS6 BIT18
892 #define RRSR_MCS7 BIT19
893 #define BRSR_AckShortPmb BIT23
895 #define RRSR_RSC_UPSUBCHANL 0x200000
896 // CCK ACK: use Short Preamble or not
898 //----------------------------------------------------------------------------
899 // 8192S Rate Definition
900 //----------------------------------------------------------------------------
902 #define RATR_1M 0x00000001
903 #define RATR_2M 0x00000002
904 #define RATR_55M 0x00000004
905 #define RATR_11M 0x00000008
907 #define RATR_6M 0x00000010
908 #define RATR_9M 0x00000020
909 #define RATR_12M 0x00000040
910 #define RATR_18M 0x00000080
911 #define RATR_24M 0x00000100
912 #define RATR_36M 0x00000200
913 #define RATR_48M 0x00000400
914 #define RATR_54M 0x00000800
915 //MCS 1 Spatial Stream
916 #define RATR_MCS0 0x00001000
917 #define RATR_MCS1 0x00002000
918 #define RATR_MCS2 0x00004000
919 #define RATR_MCS3 0x00008000
920 #define RATR_MCS4 0x00010000
921 #define RATR_MCS5 0x00020000
922 #define RATR_MCS6 0x00040000
923 #define RATR_MCS7 0x00080000
924 //MCS 2 Spatial Stream
925 #define RATR_MCS8 0x00100000
926 #define RATR_MCS9 0x00200000
927 #define RATR_MCS10 0x00400000
928 #define RATR_MCS11 0x00800000
929 #define RATR_MCS12 0x01000000
930 #define RATR_MCS13 0x02000000
931 #define RATR_MCS14 0x04000000
932 #define RATR_MCS15 0x08000000
934 #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
935 #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
936 RATR_36M|RATR_48M|RATR_54M
937 #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
938 RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
939 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
940 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
943 // 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF)
945 //----------------------------------------------------------------------------
946 // 8192S EDCA Setting (offset 0x1D0-1DF, 4DW VO/VI/BE/BK)
947 //----------------------------------------------------------------------------
948 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
949 #define AC_PARAM_ECW_MAX_OFFSET 12
950 #define AC_PARAM_ECW_MIN_OFFSET 8
951 #define AC_PARAM_AIFS_OFFSET 0
953 //----------------------------------------------------------------------------
954 // 8192S AcmHwCtrl bits (offset 0x1E7, 1 byte)
955 //----------------------------------------------------------------------------
956 #define AcmHw_HwEn BIT0
957 #define AcmHw_BeqEn BIT1
958 #define AcmHw_ViqEn BIT2
959 #define AcmHw_VoqEn BIT3
960 #define AcmHw_BeqStatus BIT4
961 #define AcmHw_ViqStatus BIT5
962 #define AcmHw_VoqStatus BIT6
964 //----------------------------------------------------------------------------
965 // 8192S Retry Limit (Offset 0x1F4, 16bit)
966 //----------------------------------------------------------------------------
967 #define RETRY_LIMIT_SHORT_SHIFT 8
968 #define RETRY_LIMIT_LONG_SHIFT 0
971 // 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F)
973 //----------------------------------------------------------------------------
974 // 8192S NAV_CTRL bits (Offset 0x200, 24bit)
975 //----------------------------------------------------------------------------
976 #define NAV_UPPER_EN BIT16
977 #define NAV_UPPER 0xFF00
978 #define NAV_RTSRST 0xFF
979 //----------------------------------------------------------------------------
980 // 8192S BW_OPMODE bits (Offset 0x203, 8bit)
981 //----------------------------------------------------------------------------
982 #define BW_OPMODE_20MHZ BIT2
983 #define BW_OPMODE_5G BIT1
984 #define BW_OPMODE_11J BIT0
985 //----------------------------------------------------------------------------
986 // 8192S BW_OPMODE bits (Offset 0x230, 4 Byte)
987 //----------------------------------------------------------------------------
988 #define RXERR_RPT_RST BIT27 // Write "one" to set the counter to zero.
990 #define RXERR_OFDM_PPDU 0
991 #define RXERR_OFDM_FALSE_ALARM 1
992 #define RXERR_OFDM_MPDU_OK 2
993 #define RXERR_OFDM_MPDU_FAIL 3
994 #define RXERR_CCK_PPDU 4
995 #define RXERR_CCK_FALSE_ALARM 5
996 #define RXERR_CCK_MPDU_OK 6
997 #define RXERR_CCK_MPDU_FAIL 7
998 #define RXERR_HT_PPDU 8
999 #define RXERR_HT_FALSE_ALARM 9
1000 #define RXERR_HT_MPDU_TOTAL 10
1001 #define RXERR_HT_MPDU_OK 11
1002 #define RXERR_HT_MPDU_FAIL 12
1003 #define RXERR_RX_FULL_DROP 15
1006 // 9. Security Control Registers (Offset: 0x0240 - 0x025F)
1008 //----------------------------------------------------------------------------
1009 // 8192S RWCAM CAM Command Register (offset 0x240, 4 byte)
1010 //----------------------------------------------------------------------------
1011 #define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling
1012 #define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM
1013 #define CAM_CM_SecCAMWE BIT16 //Security CAM enable
1014 #define CAM_ADDR 0xFF //CAM Address Offset
1016 //----------------------------------------------------------------------------
1017 // 8192S CAMDBG Debug CAM Register (offset 0x24C, 4 byte)
1018 //----------------------------------------------------------------------------
1019 #define Dbg_CAM_TXSecCAMInfo BIT31 //Retrieve lastest Tx Info
1020 #define Dbg_CAM_SecKeyFound BIT30 //Security KEY Found
1023 //----------------------------------------------------------------------------
1024 // 8192S SECR Security Configuration Register (offset 0x250, 1 byte)
1025 //----------------------------------------------------------------------------
1026 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
1027 #define SCR_RxUseDK BIT1 //Force Rx Use Default Key
1028 #define SCR_TxEncEnable BIT2 //Enable Tx Encryption
1029 #define SCR_RxDecEnable BIT3 //Enable Rx Decryption
1030 #define SCR_SKByA2 BIT4 //Search kEY BY A2
1031 #define SCR_NoSKMC BIT5 //No Key Search Multicast
1032 //----------------------------------------------------------------------------
1033 // 8192S CAM Config Setting (offset 0x250, 1 byte)
1034 //----------------------------------------------------------------------------
1035 #define CAM_VALID BIT15
1036 #define CAM_NOTVALID 0x0000
1037 #define CAM_USEDK BIT5
1039 #define CAM_NONE 0x0
1040 #define CAM_WEP40 0x01
1041 #define CAM_TKIP 0x02
1042 #define CAM_AES 0x04
1043 #define CAM_WEP104 0x05
1045 #define TOTAL_CAM_ENTRY 32
1047 #define CAM_CONFIG_USEDK TRUE
1048 #define CAM_CONFIG_NO_USEDK FALSE
1050 #define CAM_WRITE BIT16
1051 #define CAM_READ 0x00000000
1052 #define CAM_POLLINIG BIT31
1054 #define SCR_UseDK 0x01
1055 #define SCR_TxSecEnable 0x02
1056 #define SCR_RxSecEnable 0x04
1059 // 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF)
1061 #define WOW_PMEN BIT0 // Power management Enable.
1062 #define WOW_WOMEN BIT1 // WoW function on or off.
1063 #define WOW_MAGIC BIT2 // Magic packet
1064 #define WOW_UWF BIT3 // Unicast Wakeup frame.
1067 // 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)
1068 // 8192S GPIO Config Setting (offset 0x2F1, 1 byte)
1069 //----------------------------------------------------------------------------
1070 #define GPIOMUX_EN BIT3 // When this bit is set to "1", GPIO PINs will switch to MAC GPIO Function
1071 #define GPIOSEL_GPIO 0 // UART or JTAG or pure GPIO
1072 #define GPIOSEL_PHYDBG 1 // PHYDBG
1073 #define GPIOSEL_BT 2 // BT_coex
1074 #define GPIOSEL_WLANDBG 3 // WLANDBG
1075 #define GPIOSEL_GPIO_MASK ~(BIT0|BIT1)
1077 //----------------------------------------------------------------------------
1079 //----------------------------------------------------------------------------
1080 // PHY REG Access Report Register definition
1081 //----------------------------------------------------------------------------
1082 #define HST_RDBUSY BIT0
1083 #define CPU_WTBUSY BIT1
1086 // 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F)
1088 //----------------------------------------------------------------------------
1089 // 8190 IMR/ISR bits (offset 0xfd, 8bits)
1090 //----------------------------------------------------------------------------
1091 #define IMR8190_DISABLED 0x0
1094 #define IMR_CPUERR BIT5 // CPU error interrupt
1095 #define IMR_ATIMEND BIT4 // ATIM Window End Interrupt
1096 #define IMR_TBDOK BIT3 // Transmit Beacon OK Interrupt
1097 #define IMR_TBDER BIT2 // Transmit Beacon Error Interrupt
1098 #define IMR_BCNDMAINT8 BIT1 // Beacon DMA Interrupt 8
1099 #define IMR_BCNDMAINT7 BIT0 // Beacon DMA Interrupt 7
1102 #define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6
1103 #define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5
1104 #define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4
1105 #define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3
1106 #define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2
1107 #define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1
1108 #define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8
1109 #define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7
1110 #define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6
1111 #define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5
1112 #define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4
1113 #define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3
1114 #define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2
1115 #define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1
1116 #define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
1117 #define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
1118 #define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
1119 #define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
1120 #define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
1121 #define IMR_RXFOVW BIT12 // Receive FIFO Overflow
1122 #define IMR_RDU BIT11 // Receive Descriptor Unavailable
1123 #define IMR_RXCMDOK BIT10 // Receive Command Packet OK
1124 #define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
1125 #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
1126 #define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt
1127 #define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
1128 #define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt
1129 #define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt
1130 #define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt
1131 #define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt
1132 #define IMR_VODOK BIT1 // AC_VO DMA Interrupt
1133 #define IMR_ROK BIT0 // Receive DMA OK Interrupt
1136 // 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F)
1140 // 14. PCIE config register (Offset 0x500-)
1142 //----------------------------------------------------------------------------
1143 // 8190 TPPool bits (offset 0xd9, 2 byte)
1144 //----------------------------------------------------------------------------
1145 #define TPPoll_BKQ BIT0 // BK queue polling
1146 #define TPPoll_BEQ BIT1 // BE queue polling
1147 #define TPPoll_VIQ BIT2 // VI queue polling
1148 #define TPPoll_VOQ BIT3 // VO queue polling
1149 #define TPPoll_BQ BIT4 // Beacon queue polling
1150 #define TPPoll_CQ BIT5 // Command queue polling
1151 #define TPPoll_MQ BIT6 // Management queue polling
1152 #define TPPoll_HQ BIT7 // High queue polling
1153 #define TPPoll_HCCAQ BIT8 // HCCA queue polling
1154 #define TPPoll_StopBK BIT9 // Stop BK queue
1155 #define TPPoll_StopBE BIT10 // Stop BE queue
1156 #define TPPoll_StopVI BIT11 // Stop VI queue
1157 #define TPPoll_StopVO BIT12 // Stop VO queue
1158 #define TPPoll_StopMgt BIT13 // Stop Mgnt queue
1159 #define TPPoll_StopHigh BIT14 // Stop High queue
1160 #define TPPoll_StopHCCA BIT15 // Stop HCCA queue
1161 #define TPPoll_SHIFT 8 // Queue ID mapping
1163 //----------------------------------------------------------------------------
1164 // 8192S PCIF (Offset 0x500, 32bit)
1165 //----------------------------------------------------------------------------
1166 #define MXDMA2_16bytes 0x000
1167 #define MXDMA2_32bytes 0x001
1168 #define MXDMA2_64bytes 0x010
1169 #define MXDMA2_128bytes 0x011
1170 #define MXDMA2_256bytes 0x100
1171 #define MXDMA2_512bytes 0x101
1172 #define MXDMA2_1024bytes 0x110
1173 #define MXDMA2_NoLimit 0x7
1175 #define MULRW_SHIFT 3
1176 #define MXDMA2_RX_SHIFT 4
1177 #define MXDMA2_TX_SHIFT 0
1179 //----------------------------------------------------------------------------
1180 // 8190 CCX_COMMAND_REG Setting (offset 0x25A, 1 byte)
1181 //----------------------------------------------------------------------------
1182 #define CCX_CMD_CLM_ENABLE BIT0 // Enable Channel Load
1183 #define CCX_CMD_NHM_ENABLE BIT1 // Enable Noise Histogram
1184 #define CCX_CMD_FUNCTION_ENABLE BIT8
1185 // CCX function (Channel Load/RPI/Noise Histogram).
1186 #define CCX_CMD_IGNORE_CCA BIT9
1187 // Treat CCA period as IDLE time for NHM.
1188 #define CCX_CMD_IGNORE_TXON BIT10
1189 // Treat TXON period as IDLE time for NHM.
1190 #define CCX_CLM_RESULT_READY BIT16
1191 // 1: Indicate the result of Channel Load is ready.
1192 #define CCX_NHM_RESULT_READY BIT16
1193 // 1: Indicate the result of Noise histogram is ready.
1194 #define CCX_CMD_RESET 0x0
1195 // Clear all the result of CCX measurement and disable the CCX function.
1198 //----------------------------------------------------------------------------
1200 //----------------------------------------------------------------------------
1201 //#define HWSET_MAX_SIZE_92S 128
1204 //----------------------------------------------------------------------------
1205 // 8192S EEPROM/EFUSE share register definition.
1206 //----------------------------------------------------------------------------
1210 // 2008/11/05 MH Redefine EEPROM address for 8192SE
1211 // 92SE/SU EEPROM definition seems not the same!!!!!!
1212 // EEPROM MAP REgister Definition!!!! Please refer to 8192SE EEPROM V0.5 2008/10/21
1213 // Update to 8192SE EEPROM V0.6 2008/11/11
1215 #define RTL8190_EEPROM_ID 0x8129 // 0-1
1216 #define EEPROM_HPON 0x02 // LDO settings.2-5
1217 #define EEPROM_CLK 0x06 // Clock settings.6-7
1218 #define EEPROM_TESTR 0x08 // SE Test mode.8
1220 #define EEPROM_VID 0x0A // SE Vendor ID.A-B
1221 #define EEPROM_DID 0x0C // SE Device ID. C-D
1222 #define EEPROM_SVID 0x0E // SE Vendor ID.E-F
1223 #define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11
1225 #define EEPROM_MAC_ADDR 0x12 // SEMAC Address. 12-17
1226 #define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address.
1228 #define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
1231 // 0x20 - 4B EPHY parameter!!!
1234 #define EEPROM_TxPowerBase 0x50 // Tx Power of serving station.
1235 #define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24//FIXLZM
1236 #define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24//FIXLZM
1237 #define EEPROM_TX_PWR_INDEX_RANGE 28 // CCK and OFDM 14 channel
1240 // 2009/01/21 MH Add for SD3 requirement
1241 #define EEPROM_TX_PWR_HT20_DIFF 0x62// HT20 Tx Power Index Difference
1242 #define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
1243 #define EEPROM_TX_PWR_OFDM_DIFF 0x65// OFDM Tx Power Index Difference
1244 #define EEPROM_TX_PWR_BAND_EDGE 0x67// TX Power offset at band-edge channel
1245 #define TX_PWR_BAND_EDGE_CHK 0x6D// Check if band-edge scheme is enabled
1247 // Oly old EEPROM format support the definition=============================
1249 #define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24
1250 #define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24
1251 #define EEPROM_HT2T_CH1_A 0x6c //HT 2T path A channel 1 Power Index.
1252 #define EEPROM_HT2T_CH7_A 0x6d //HT 2T path A channel 7 Power Index.
1253 #define EEPROM_HT2T_CH13_A 0x6e //HT 2T path A channel 13 Power Index.
1254 #define EEPROM_HT2T_CH1_B 0x6f //HT 2T path B channel 1 Power Index.
1255 #define EEPROM_HT2T_CH7_B 0x70 //HT 2T path B channel 7 Power Index.
1256 #define EEPROM_HT2T_CH13_B 0x71 //HT 2T path B channel 13 Power Index.
1258 #define EEPROM_TSSI_A 0x74 //TSSI value of path A.
1259 #define EEPROM_TSSI_B 0x75 //TSSI value of path B.
1261 #define EEPROM_RFInd_PowerDiff 0x76
1262 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1264 #define EEPROM_ThermalMeter 0x77 // Thermal meter default value.
1265 #define EEPROM_CrystalCap 0x79 // Crystal Cap.
1266 #define EEPROM_ChannelPlan 0x7B // Map of supported channels.
1267 #define EEPROM_Version 0x7C // The EEPROM content version
1268 #define EEPROM_CustomID 0x7A
1269 #define EEPROM_BoardType 0x7E
1270 // 0: 2x2 Green RTL8192GE miniCard (QFN68)
1271 // 1: 1x2 RTL8191SE miniCard (QFN64)
1272 // 2: 2x2 RTL8192SE miniCard (QFN68)
1273 // 3: 1x2 RTL8191SR minicCard(QFN64)
1276 // Default Value for EEPROM or EFUSE!!!
1278 #define EEPROM_Default_TSSI 0x0
1279 #define EEPROM_Default_TxPowerDiff 0x0
1280 #define EEPROM_Default_CrystalCap 0x5
1281 #define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SE(QFPN68)
1282 #define EEPROM_Default_TxPower 0x1010
1283 #define EEPROM_Default_HT2T_TxPwr 0x10
1285 #ifdef EEPROM_OLD_FORMAT_SUPPORT
1286 #define EEPROM_Default_TxPowerBase 0x0
1287 #define EEPROM_Default_ThermalMeter 0x12
1288 #define EEPROM_Default_PwDiff 0x4
1290 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1291 #define EEPROM_Default_ThermalMeter 0x12
1292 #define EEPROM_Default_AntTxPowerDiff 0x0
1293 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5
1294 #define EEPROM_Default_TxPowerLevel 0x22
1297 #define EEPROM_CHANNEL_PLAN_FCC 0x0
1298 #define EEPROM_CHANNEL_PLAN_IC 0x1
1299 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
1300 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
1301 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
1302 #define EEPROM_CHANNEL_PLAN_MKK 0x5
1303 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
1304 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
1305 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
1306 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
1307 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
1308 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
1311 #define EEPROM_CID_DEFAULT 0x0
1312 #define EEPROM_CID_TOSHIBA 0x4
1314 //----------------------------------------------------------------------------
1315 // 8192S EEROM and Compatible E-Fuse definition. Added by Roger, 2008.10.21.
1316 //----------------------------------------------------------------------------
1317 #define RTL8190_EEPROM_ID 0x8129
1318 #define EEPROM_HPON 0x02 // LDO settings.
1319 #define EEPROM_VID 0x08 // USB Vendor ID.
1320 #define EEPROM_PID 0x0A // USB Product ID.
1321 #define EEPROM_USB_OPTIONAL 0x0C // For optional function.
1322 #define EEPROM_USB_PHY_PARA1 0x0D // For fine tune USB PHY.
1323 #define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address.
1324 #define EEPROM_TxPowerDiff 0x1F
1326 #define EEPROM_Version 0x50
1327 #define EEPROM_ChannelPlan 0x51 // Map of supported channels.
1328 #define EEPROM_CustomID 0x52
1329 #define EEPROM_SubCustomID 0x53 // Reserved for customer use.
1332 // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22.
1333 #ifdef EEPROM_OLD_FORMAT_SUPPORT
1334 #define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
1335 #define EEPROM_ThermalMeter 0x55 // Thermal meter default value.
1336 #define EEPROM_Reserved 0x56 // Reserved.
1337 #define EEPROM_CrystalCap 0x57 // Crystal Cap.
1338 #define EEPROM_TxPowerBase 0x58 // Tx Power of serving station.
1339 #define EEPROM_TxPwIndex_CCK_24G 0x59 // 0x59~0x66
1340 #define EEPROM_TxPwIndex_OFDM_24G 0x67 // 0x67~0x74
1341 #define EEPROM_TSSI_A 0x75 //TSSI value of path A.
1342 #define EEPROM_TSSI_B 0x76 //TSSI value of path B.
1343 #define EEPROM_TxPwTkMode 0x77 //Tx Power tracking mode.
1344 #define EEPROM_HT2T_CH1_A 0x78 //HT 2T path A channel 1 Power Index.
1345 #define EEPROM_HT2T_CH7_A 0x79 //HT 2T path A channel 7 Power Index.
1346 #define EEPROM_HT2T_CH13_A 0x7a //HT 2T path A channel 13 Power Index.
1347 #define EEPROM_HT2T_CH1_B 0x7b //HT 2T path B channel 1 Power Index.
1348 #define EEPROM_HT2T_CH7_B 0x7c //HT 2T path B channel 7 Power Index.
1349 #define EEPROM_HT2T_CH13_B 0x7d //HT 2T path B channel 13 Power Index.
1350 #define EEPROM_BoardType 0x7e //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1352 #define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1353 #define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index.
1354 #define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM.
1355 #define EEPROM_ThermalMeter 0x68 // Thermal meter default value.
1356 #define EEPROM_CrystalCap 0x69 // Crystal Cap.
1357 #define EEPROM_TxPowerBase 0x6a // Tx Power of serving station.
1358 #define EEPROM_TSSI_A 0x6b //TSSI value of path A.
1359 #define EEPROM_TSSI_B 0x6c //TSSI value of path B.
1360 #define EEPROM_TxPwTkMode 0x6d //Tx Power tracking mode.
1361 //#define EEPROM_Reserved 0x6e //0x6e-0x7f, reserved.
1363 // 2009/02/09 Cosa Add for SD3 requirement
1364 #define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference
1365 #define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
1366 #define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
1367 #define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel
1368 #define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled
1370 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1371 #define EEPROM_USB_Default_OPTIONAL_FUNC 0x8
1372 #define EEPROM_USB_Default_PHY_PARAM 0x0
1373 #define EEPROM_Default_TSSI 0x0
1374 #define EEPROM_Default_TxPwrTkMode 0x0
1375 #define EEPROM_Default_TxPowerDiff 0x0
1376 #define EEPROM_Default_TxPowerBase 0x0
1377 #define EEPROM_Default_ThermalMeter 0x7
1378 #define EEPROM_Default_PwDiff 0x4
1379 #define EEPROM_Default_CrystalCap 0x5
1380 #define EEPROM_Default_TxPower 0x1010
1381 #define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SU(QFPN68)
1382 #define EEPROM_Default_HT2T_TxPwr 0x10
1383 #define EEPROM_USB_SN BIT0
1384 #define EEPROM_USB_REMOTE_WAKEUP BIT1
1385 #define EEPROM_USB_DEVICE_PWR BIT2
1386 #define EEPROM_EP_NUMBER (BIT3|BIT4)
1388 #define EEPROM_CHANNEL_PLAN_FCC 0x0
1389 #define EEPROM_CHANNEL_PLAN_IC 0x1
1390 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
1391 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
1392 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
1393 #define EEPROM_CHANNEL_PLAN_MKK 0x5
1394 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
1395 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
1396 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
1397 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
1398 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
1399 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
1401 #define EEPROM_CID_DEFAULT 0x0
1402 #define EEPROM_CID_ALPHA 0x1
1403 #define EEPROM_CID_CAMEO 0X8
1404 #define EEPROM_CID_SITECOM 0x9
1406 //#define EEPROM_CID_RUNTOP 0x2
1407 //#define EEPROM_CID_Senao 0x3
1408 //#define EEPROM_CID_TOSHIBA 0x4
1409 //#define EEPROM_CID_NetCore 0x5
1410 #define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
1413 //-----------------------------------------------------------------
1414 // 0x2c0 FW Command Control register definition, added by Roger, 2008.11.27.
1415 //-----------------------------------------------------------------
1416 #define FW_DIG_DISABLE 0xfd00cc00
1417 #define FW_DIG_ENABLE 0xfd000000
1418 #define FW_DIG_HALT 0xfd000001
1419 #define FW_DIG_RESUME 0xfd000002
1420 #define FW_HIGH_PWR_DISABLE 0xfd000008
1421 #define FW_HIGH_PWR_ENABLE 0xfd000009
1422 #define FW_TXPWR_TRACK_ENABLE 0xfd000017
1423 #define FW_TXPWR_TRACK_DISABLE 0xfd000018
1424 #define FW_RA_RESET 0xfd0000af
1425 #define FW_RA_ACTIVE 0xfd0000a6
1426 #define FW_RA_REFRESH 0xfd0000a0
1427 #define FW_RA_ENABLE_BG 0xfd0000ac
1428 #define FW_IQK_ENABLE 0xf0000020
1429 #define FW_IQK_SUCCESS 0x0000dddd
1430 #define FW_IQK_FAIL 0x0000ffff
1431 #define FW_OP_FAILURE 0xffffffff
1432 #define FW_DM_DISABLE 0xfd00aa00
1433 #define FW_BB_RESET_ENABLE 0xff00000d
1434 #define FW_BB_RESET_DISABLE 0xff00000e
1436 //----------------------------------------------------------------------------
1438 //----------------------------------------------------------------------------
1439 #define RTL8190_EEPROM_ID 0x8129
1440 //#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
1442 #define EEPROM_RFInd_PowerDiff 0x28
1443 #define EEPROM_ThermalMeter 0x29
1444 #define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B
1445 #define EEPROM_TxPwIndex_CCK 0x2C //0x2C~0x39
1446 #define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x3A~0x47
1447 #define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B
1449 //The following definition is for eeprom 93c56......modified 20080220
1450 #define EEPROM_C56_CrystalCap 0x17 //0x17
1451 #define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80
1452 #define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83
1453 #define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8
1454 #define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb
1455 #define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
1456 #define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChnlPlan,
1458 #define EEPROM_CRC 0x7E //0x7E~0x7F
1460 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
1461 #define EEPROM_Default_ThermalMeter 0x77
1462 #define EEPROM_Default_AntTxPowerDiff 0x0
1463 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5
1464 #define EEPROM_Default_TxPower 0x1010
1465 #define EEPROM_Default_TxPowerLevel 0x10
1468 // Define Different EEPROM type for customer
1470 #define EEPROM_CID_DEFAULT 0x0
1471 #define EEPROM_CID_CAMEO 0x1
1472 #define EEPROM_CID_RUNTOP 0x2
1473 #define EEPROM_CID_Senao 0x3
1474 #define EEPROM_CID_TOSHIBA 0x4
1475 #define EEPROM_CID_NetCore 0x5
1476 #define EEPROM_CID_Nettronix 0x6
1477 #define EEPROM_CID_Pronet 0x7
1482 //--------------92SU require delete or move to other place later
1489 // 2008/08/06 MH For share the same 92S source/header files, we copy some
1490 // definition to pass 92SU compiler. But we must delete thm later.
1494 //============================================================================
1495 // 819xUsb Regsiter offset definition
1496 //============================================================================
1498 //2 define it temp!!!
1499 #define RFPC 0x5F // Rx FIFO Packet Count
1500 #define RCR_9356SEL BIT6
1501 #define TCR_LRL_OFFSET 0
1502 #define TCR_SRL_OFFSET 8
1503 #define TCR_MXDMA_OFFSET 21
1504 #define TCR_MXDMA_2048 7
1505 #define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer
1506 #define RCR_MXDMA_OFFSET 8
1507 #define RCR_FIFO_OFFSET 13
1508 #define RCR_OnlyErlPkt BIT31 // Rx Early mode is performed for packet size greater than 1536
1509 #define CWR 0xDC // Contention window register
1510 #define RetryCTR 0xDE // Retry Count register
1513 // For backward compatible for 9xUSB
1514 #define LED1Cfg UnusedRegister // LED1 Configuration Register
1515 #define LED0Cfg UnusedRegister // LED0 Configuration Register
1516 #define GPI UnusedRegister // LED0 Configuration Register
1517 #define BRSR UnusedRegister // LED0 Configuration Register
1518 #define CPU_GEN UnusedRegister // LED0 Configuration Register
1519 #define SIFS UnusedRegister // LED0 Configuration Register
1521 //----------------------------------------------------------------------------
1522 // 8190 CPU General Register (offset 0x100, 4 byte)
1523 //----------------------------------------------------------------------------
1524 //#define CPU_CCK_LOOPBACK 0x00030000
1525 #define CPU_GEN_SYSTEM_RESET 0x00000001
1526 //#define CPU_GEN_FIRMWARE_RESET 0x00000008
1527 //#define CPU_GEN_BOOT_RDY 0x00000010
1528 //#define CPU_GEN_FIRM_RDY 0x00000020
1529 //#define CPU_GEN_PUT_CODE_OK 0x00000080
1530 //#define CPU_GEN_BB_RST 0x00000100
1531 //#define CPU_GEN_PWR_STB_CPU 0x00000004
1532 //#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
1533 //#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
1535 //----------------------------------------------------------------------------
1537 //----------------------------------------------------------------------------
1539 //#define RTL8190_EEPROM_ID 0x8129
1540 //#define EEPROM_VID 0x08
1541 //#define EEPROM_PID 0x0A
1542 //#define EEPROM_USB_OPTIONAL 0x0C
1543 //#define EEPROM_NODE_ADDRESS_BYTE_0 0x12
1545 //#define EEPROM_TxPowerDiff 0x1F
1546 //#define EEPROM_ThermalMeter 0x20
1547 //#define EEPROM_PwDiff 0x21 //0x21
1548 //#define EEPROM_CrystalCap 0x22 //0x22
1550 //#define EEPROM_TxPwIndex_CCK 0x23 //0x23
1551 //#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26
1552 #define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B
1553 #define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E
1554 #define EEPROM_TxPwIndex_Ver 0x27 //0x27
1556 //#define EEPROM_Default_TxPowerDiff 0x0
1557 //#define EEPROM_Default_ThermalMeter 0x7
1558 //#define EEPROM_Default_PwDiff 0x4
1559 //#define EEPROM_Default_CrystalCap 0x5
1560 //#define EEPROM_Default_TxPower 0x1010
1561 //#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
1562 //#define EEPROM_Version 0x50 // 0x50
1563 //#define EEPROM_CustomID 0x52
1564 //#define EEPROM_ChannelPlan 0x7c //0x7C
1565 //#define EEPROM_IC_VER 0x7d //0x7D
1566 //#define EEPROM_CRC 0x7e //0x7E~0x7F
1569 //#define EEPROM_CID_DEFAULT 0x0
1570 //#define EEPROM_CID_CAMEO 0x1
1571 //#define EEPROM_CID_RUNTOP 0x2
1572 //#define EEPROM_CID_Senao 0x3
1573 //#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31
1574 //#define EEPROM_CID_NetCore 0x5
1578 //--------------92SU require delete or move to other place later
1581 //============================================================
1582 // CCX Related Register
1583 //============================================================
1584 #define CCX_COMMAND_REG 0x890
1585 // CCX Measurement Command Register. 4 Bytes.
1586 // Bit[0]: R_CLM_En, 1=enable, 0=disable. Enable or disable "Channel Load
1587 // Measurement (CLM)".
1588 // Bit[1]: R_NHM_En, 1=enable, 0=disable. Enable or disalbe "Noise Histogram
1589 // Measurement (NHM)".
1590 // Bit[2~7]: Reserved
1591 // Bit[8]: R_CCX_En: 1=enable, 0=disable. Enable or disable CCX function.
1592 // Note: After clearing this bit, all the result of all NHM_Result and CLM_
1593 // Result are cleared concurrently.
1594 // Bit[9]: R_Ignore_CCA: 1=enable, 0=disable. Enable means that treat CCA
1595 // period as idle time for NHM.
1596 // Bit[10]: R_Ignore_TXON: 1=enable, 0=disable. Enable means that treat TXON
1597 // period as idle time for NHM.
1598 // Bit[11~31]: Reserved.
1599 #define CLM_PERIOD_REG 0x894
1600 // CCX Measurement Period Register, in unit of 4us. 2 Bytes.
1601 #define NHM_PERIOD_REG 0x896
1602 // Noise Histogram Measurement Period Register, in unit of 4us. 2Bytes.
1603 #define NHM_THRESHOLD0 0x898 // Noise Histogram Meashorement0
1604 #define NHM_THRESHOLD1 0x899 // Noise Histogram Meashorement1
1605 #define NHM_THRESHOLD2 0x89A // Noise Histogram Meashorement2
1606 #define NHM_THRESHOLD3 0x89B // Noise Histogram Meashorement3
1607 #define NHM_THRESHOLD4 0x89C // Noise Histogram Meashorement4
1608 #define NHM_THRESHOLD5 0x89D // Noise Histogram Meashorement5
1609 #define NHM_THRESHOLD6 0x89E // Noise Histogram Meashorement6
1610 #define CLM_RESULT_REG 0x8D0
1611 // Channel Load result register. 4 Bytes.
1612 // Bit[0~15]: Total measured duration of CLM. The CCA busy fraction is caculate
1613 // by CLM_RESULT_REG/CLM_PERIOD_REG.
1614 // Bit[16]: Indicate the CLM result is ready.
1615 // Bit[17~31]: Reserved.
1616 #define NHM_RESULT_REG 0x8D4
1617 // Noise Histogram result register. 4 Bytes.
1618 // Bit[0~15]: Total measured duration of NHM. If R_Ignore_CCA=1 or
1619 // R_Ignore_TXON=1, this value will be less than NHM_PERIOD_REG.
1620 // Bit[16]: Indicate the NHM result is ready.
1621 // Bit[17~31]: Reserved.
1622 #define NHM_RPI_COUNTER0 0x8D8
1623 // NHM RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
1624 #define NHM_RPI_COUNTER1 0x8D9
1625 // NHM RPI counter1, the fraction of signal stren in NHM_THRESH0, NHM_THRESH1
1626 #define NHM_RPI_COUNTER2 0x8DA
1627 // NHM RPI counter2, the fraction of signal stren in NHM_THRESH2, NHM_THRESH3
1628 #define NHM_RPI_COUNTER3 0x8DB
1629 // NHM RPI counter3, the fraction of signal stren in NHM_THRESH4, NHM_THRESH5
1630 #define NHM_RPI_COUNTER4 0x8DC
1631 // NHM RPI counter4, the fraction of signal stren in NHM_THRESH6, NHM_THRESH7
1632 #define NHM_RPI_COUNTER5 0x8DD
1633 // NHM RPI counter5, the fraction of signal stren in NHM_THRESH8, NHM_THRESH9
1634 #define NHM_RPI_COUNTER6 0x8DE
1635 // NHM RPI counter6, the fraction of signal stren in NHM_THRESH10, NHM_THRESH11
1636 #define NHM_RPI_COUNTER7 0x8DF
1637 // NHM RPI counter7, the fraction of signal stren in NHM_THRESH12, NHM_THRESH13
1639 #define HAL_RETRY_LIMIT_INFRA 48
1640 #define HAL_RETRY_LIMIT_AP_ADHOC 7
1642 // HW Readio OFF switch (GPIO BIT)
1643 #define HAL_8192S_HW_GPIO_OFF_BIT BIT3
1644 #define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
1645 #define HAL_8192S_HW_GPIO_WPS_BIT BIT4
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