2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
14 We want to tanks the Authors of those projects and the Ndiswrapper
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 //#include <linux/pci.h>
31 #include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
43 #include "ieee80211/ieee80211.h"
46 #include "r8192S_firmware.h"
48 #include "r819xU_firmware.h"
52 #define RTL819xU_MODULE_NAME "rtl819xU"
53 //added for HW security, john.0629
56 #define MAX_KEY_LEN 61
57 #define KEY_BUF_SIZE 5
59 #define BIT0 0x00000001
60 #define BIT1 0x00000002
61 #define BIT2 0x00000004
62 #define BIT3 0x00000008
63 #define BIT4 0x00000010
64 #define BIT5 0x00000020
65 #define BIT6 0x00000040
66 #define BIT7 0x00000080
67 #define BIT8 0x00000100
68 #define BIT9 0x00000200
69 #define BIT10 0x00000400
70 #define BIT11 0x00000800
71 #define BIT12 0x00001000
72 #define BIT13 0x00002000
73 #define BIT14 0x00004000
74 #define BIT15 0x00008000
75 #define BIT16 0x00010000
76 #define BIT17 0x00020000
77 #define BIT18 0x00040000
78 #define BIT19 0x00080000
79 #define BIT20 0x00100000
80 #define BIT21 0x00200000
81 #define BIT22 0x00400000
82 #define BIT23 0x00800000
83 #define BIT24 0x01000000
84 #define BIT25 0x02000000
85 #define BIT26 0x04000000
86 #define BIT27 0x08000000
87 #define BIT28 0x10000000
88 #define BIT29 0x20000000
89 #define BIT30 0x40000000
90 #define BIT31 0x80000000
93 #define Rx_Smooth_Factor 20
94 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
95 #define DMESG(x,a...) printk(KERN_INFO RTL819xU_MODULE_NAME ": " x "\n", ## a)
96 #define DMESGW(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": WW:" x "\n", ## a)
97 #define DMESGE(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": EE:" x "\n", ## a)
100 #define DMESGW(x,a...)
101 #define DMESGE(x,a...)
102 extern u32 rt_global_debug_component;
103 #define RT_TRACE(component, x, args...) \
104 do { if(rt_global_debug_component & component) \
105 printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
108 //----------------------------------------------------------------------
109 //// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15.
110 ////----------------------------------------------------------------------
111 #define RX_DESC_SIZE 24
112 #define RX_DRV_INFO_SIZE_UNIT 8
114 #define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
115 (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
117 #define COMP_TRACE BIT0 // For function call tracing.
118 #define COMP_DBG BIT1 // Only for temporary debug message.
119 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
122 #define COMP_RECV BIT3 // Reveive part data path.
123 #define COMP_SEND BIT4 // Send part path.
124 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
125 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
126 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
127 #define COMP_SWBW BIT8 // For bandwidth switch.
128 #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
129 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
130 #define COMP_QOS BIT11 // For QoS.
131 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
132 #define COMP_LPS BIT13 // For Radio Measurement.
133 #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
134 #define COMP_PHY BIT15
135 #define COMP_CH BIT16 //channel setting debug
136 #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
137 #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
138 #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
139 #define COMP_SEC BIT20 // Event handling
140 #define COMP_LED BIT21 // For LED.
141 #define COMP_RF BIT22 // For RF.
142 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
143 #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
144 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
145 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
147 #define COMP_FIRMWARE BIT24 //for firmware downloading
148 #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
149 #define COMP_AMSDU BIT26 // For A-MSDU Debugging
151 #define COMP_SCAN BIT27
152 #define COMP_CMD BIT28
153 #define COMP_DOWN BIT29 //for rm driver module
154 #define COMP_RESET BIT30 //for silent reset
155 #define COMP_ERR BIT31 //for error out, always on
158 #define RTL819x_DEBUG
160 #define assert(expr) \
162 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
163 #expr,__FILE__,__FUNCTION__,__LINE__); \
165 //wb added to debug out data buf
166 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
167 #define RT_DEBUG_DATA(level, data, datalen) \
168 do{ if ((rt_global_debug_component & (level)) == (level)) \
171 u8* pdata = (u8*) data; \
172 printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
173 for(i=0; i<(int)(datalen); i++) \
175 printk("%2x ", pdata[i]); \
176 if ((i+1)%16 == 0) printk("\n"); \
182 #define assert(expr) do {} while (0)
183 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
184 #endif /* RTL8169_DEBUG */
187 //2TODO: We should define 8192S firmware related macro settings here!!
188 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
189 #define RTL819X_TOTAL_RF_PATH 2
191 //#define Rtl819XFwBootArray Rtl8192UsbFwBootArray
192 //#define Rtl819XFwMainArray Rtl8192UsbFwMainArray
193 //#define Rtl819XFwDataArray Rtl8192UsbFwDataArray
195 #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
196 #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
197 #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray
198 #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
199 //#define Rtl819XRadioA_Array Rtl8192UsbRadioA_Array
200 //#define Rtl819XRadioB_Array Rtl8192UsbRadioB_Array
201 #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array
202 #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array
205 #define Rtl819XFwImageArray Rtl8192SUFwImgArray
206 #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array
207 #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array
208 #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray
209 #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray
210 #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray
211 #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray
212 #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG
213 #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array
214 #define Rtl819XRadioB_Array Rtl8192SURadioB_Array
215 #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array
216 #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array
217 #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array
221 // Queue Select Value in TxDesc
227 #define QSLT_BEACON 0x10
228 #define QSLT_HIGH 0x11
229 #define QSLT_MGNT 0x12
230 #define QSLT_CMD 0x13
232 #define DESC90_RATE1M 0x00
233 #define DESC90_RATE2M 0x01
234 #define DESC90_RATE5_5M 0x02
235 #define DESC90_RATE11M 0x03
236 #define DESC90_RATE6M 0x04
237 #define DESC90_RATE9M 0x05
238 #define DESC90_RATE12M 0x06
239 #define DESC90_RATE18M 0x07
240 #define DESC90_RATE24M 0x08
241 #define DESC90_RATE36M 0x09
242 #define DESC90_RATE48M 0x0a
243 #define DESC90_RATE54M 0x0b
244 #define DESC90_RATEMCS0 0x00
245 #define DESC90_RATEMCS1 0x01
246 #define DESC90_RATEMCS2 0x02
247 #define DESC90_RATEMCS3 0x03
248 #define DESC90_RATEMCS4 0x04
249 #define DESC90_RATEMCS5 0x05
250 #define DESC90_RATEMCS6 0x06
251 #define DESC90_RATEMCS7 0x07
252 #define DESC90_RATEMCS8 0x08
253 #define DESC90_RATEMCS9 0x09
254 #define DESC90_RATEMCS10 0x0a
255 #define DESC90_RATEMCS11 0x0b
256 #define DESC90_RATEMCS12 0x0c
257 #define DESC90_RATEMCS13 0x0d
258 #define DESC90_RATEMCS14 0x0e
259 #define DESC90_RATEMCS15 0x0f
260 #define DESC90_RATEMCS32 0x20
263 // CCK Rates, TxHT = 0
264 #define DESC92S_RATE1M 0x00
265 #define DESC92S_RATE2M 0x01
266 #define DESC92S_RATE5_5M 0x02
267 #define DESC92S_RATE11M 0x03
269 // OFDM Rates, TxHT = 0
270 #define DESC92S_RATE6M 0x04
271 #define DESC92S_RATE9M 0x05
272 #define DESC92S_RATE12M 0x06
273 #define DESC92S_RATE18M 0x07
274 #define DESC92S_RATE24M 0x08
275 #define DESC92S_RATE36M 0x09
276 #define DESC92S_RATE48M 0x0a
277 #define DESC92S_RATE54M 0x0b
279 // MCS Rates, TxHT = 1
280 #define DESC92S_RATEMCS0 0x0c
281 #define DESC92S_RATEMCS1 0x0d
282 #define DESC92S_RATEMCS2 0x0e
283 #define DESC92S_RATEMCS3 0x0f
284 #define DESC92S_RATEMCS4 0x10
285 #define DESC92S_RATEMCS5 0x11
286 #define DESC92S_RATEMCS6 0x12
287 #define DESC92S_RATEMCS7 0x13
288 #define DESC92S_RATEMCS8 0x14
289 #define DESC92S_RATEMCS9 0x15
290 #define DESC92S_RATEMCS10 0x16
291 #define DESC92S_RATEMCS11 0x17
292 #define DESC92S_RATEMCS12 0x18
293 #define DESC92S_RATEMCS13 0x19
294 #define DESC92S_RATEMCS14 0x1a
295 #define DESC92S_RATEMCS15 0x1b
296 #define DESC92S_RATEMCS15_SG 0x1c
297 #define DESC92S_RATEMCS32 0x20
300 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
302 #define IEEE80211_WATCH_DOG_TIME 2000
303 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
304 //for txpowertracking by amy
305 #define OFDM_Table_Length 19
306 #define CCK_Table_length 12
310 //Tx Descriptor for RLT8192SU(Normal mode)
312 typedef struct _tx_desc_819x_usb {
316 u8 Type:2; // Reserved for MAC header Frame Type subfield.
340 u8 PktOffset:5; //padding_len (hw)
347 u32 RTSRC:6; // Reserved for HW RTS Retry Count.
348 u32 DATARC:6; // Reserved for HW DATA Retry Count.
350 u32 AllowAggregation:1;
351 u32 BK:1; //Aggregation break.
355 u8 NextHeadPage;//:8;
366 u32 RaBRSRID:3; //Rate adaptive BRSR ID.
368 u32 TxShort:1;//for data
391 //u16 TxBuffSize;//:16;//pcie
396 }tx_desc_819x_usb, *ptx_desc_819x_usb;
397 typedef struct _tx_status_desc_8192s_usb{
425 }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
428 typedef struct _tx_desc_819x_usb {
457 u8 ResvForPaddingLen:7;
465 }tx_desc_819x_usb, *ptx_desc_819x_usb;
468 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
469 typedef struct _tx_desc_819x_usb_aggr_subframe {
490 }tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
496 //Tx Descriptor for RLT8192SU(Load FW mode)
498 typedef struct _tx_desc_cmd_819x_usb{
507 // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
516 u16 TxBuffSize;//pcie
518 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
520 //H2C Command for RLT8192SU(Host TxCmd)
522 typedef struct _tx_h2c_desc_cmd_8192s_usb{
547 }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
550 typedef struct _tx_h2c_cmd_hdr_8192s_usb{
558 }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
560 typedef struct _tx_desc_cmd_819x_usb {
584 //u32 NextDescAddress;
588 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
592 typedef struct _tx_fwinfo_819x_usb{
599 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
600 u8 TxBandwidth:1; // This is used for HT MCS rate only.
601 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
603 u8 AllowAggregation:1;
604 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
605 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
606 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
607 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
609 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
615 u32 TxAGCOffSet:4;//TxAGCOffset:4;
619 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
621 typedef struct _tx_fwinfo_819x_usb {
628 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
629 u8 TxBandwidth:1; // This is used for HT MCS rate only.
630 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
632 u8 AllowAggregation:1;
633 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
634 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
635 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
636 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
638 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
643 u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
650 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
653 typedef struct rtl8192_rx_info {
655 struct net_device *dev;
660 //typedef struct _RX_DESC_STATUS_8192SU{
661 typedef struct rx_desc_819x_usb{
696 #ifdef USB_RX_AGGREGATION_SUPPORT
697 u8 UsbAggPktNum;//:8;
724 //}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
725 }rx_desc_819x_usb, *prx_desc_819x_usb;
727 typedef struct rx_desc_819x_usb{
751 }rx_desc_819x_usb, *prx_desc_819x_usb;
754 #ifdef USB_RX_AGGREGATION_SUPPORT
755 typedef struct _rx_desc_819x_usb_aggr_subframe{
772 //u4Byte BufferAddress;
773 }rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
778 // Driver info are written to the begining of the RxBuffer
780 //typedef struct _RX_DRIVER_INFO_8192S{
781 typedef struct rx_drvinfo_819x_usb{
783 // Driver info contain PHY status and other variabel size info
784 // PHY Status content as below
810 u4Byte cfotail_2:8;*/
814 /*u4Byte cfotail_3:8;
830 u4Byte csi_current_0:8;
831 u4Byte csi_current_1:8;
832 u4Byte csi_target_0:8;*/
837 /*u4Byte csi_target_1:8;
840 u4Byte ex_intf_flag:1;
851 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
853 typedef struct rx_drvinfo_819x_usb{
874 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
877 #define HWSET_MAX_SIZE_92S 128
879 #define MAX_802_11_HEADER_LENGTH 40
880 #define MAX_PKT_AGG_NUM 256
881 #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
883 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
884 #define MAX_PKT_AGG_NUM 64
885 #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
888 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
889 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
890 //#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
891 #define ENCRYPTION_MAX_OVERHEAD 128
892 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
893 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
894 #define MAX_FRAGMENT_COUNT 8
896 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
897 #define MAX_TRANSMIT_BUFFER_SIZE 32000
899 #define MAX_TRANSMIT_BUFFER_SIZE 8000
902 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
904 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
905 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
907 #define scrclng 4 // octets for crc32 (FCS, ICV)
909 typedef enum rf_optype
911 RF_OP_By_SW_3wire = 0,
915 /* 8190 Loopback Mode definition */
916 typedef enum _rtl819xUsb_loopback{
917 RTL819xU_NO_LOOPBACK = 0,
918 RTL819xU_MAC_LOOPBACK = 1,
919 RTL819xU_DMA_LOOPBACK = 2,
920 RTL819xU_CCK_LOOPBACK = 3,
921 }rtl819xUsb_loopback_e;
924 typedef enum _RT_STATUS{
925 RT_STATUS_SUCCESS = 0,
926 RT_STATUS_FAILURE = 1,
927 RT_STATUS_PENDING = 2,
928 RT_STATUS_RESOURCE = 3
929 }RT_STATUS,*PRT_STATUS;
932 typedef enum _RTL8192SUSB_LOOPBACK{
933 RTL8192SU_NO_LOOPBACK = 0,
934 RTL8192SU_MAC_LOOPBACK = 1,
935 RTL8192SU_DMA_LOOPBACK = 2,
936 RTL8192SU_CCK_LOOPBACK = 3,
937 }RTL8192SUSB_LOOPBACK_E;
942 /* due to rtl8192 firmware */
943 typedef enum _desc_packet_type_e{
944 DESC_PACKET_TYPE_INIT = 0,
945 DESC_PACKET_TYPE_NORMAL = 1,
948 typedef enum _firmware_source{
949 FW_SOURCE_IMG_FILE = 0,
950 FW_SOURCE_HEADER_FILE = 1, //from header file
951 }firmware_source_e, *pfirmware_source_e;
953 typedef enum _firmware_status{
954 FW_STATUS_0_INIT = 0,
955 FW_STATUS_1_MOVE_BOOT_CODE = 1,
956 FW_STATUS_2_MOVE_MAIN_CODE = 2,
957 FW_STATUS_3_TURNON_CPU = 3,
958 FW_STATUS_4_MOVE_DATA_CODE = 4,
959 FW_STATUS_5_READY = 5,
962 typedef struct _rt_firmare_seg_container {
965 }fw_seg_container, *pfw_seg_container;
968 //--------------------------------------------------------------------------------
969 // 8192S Firmware related
970 //--------------------------------------------------------------------------------
971 typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
973 //--- LONG WORD 0 ----
977 //--- LONG WORD 1 ----
981 //--- LONG WORD 2 ----
985 //--- LONG WORD 3 ----
987 u8 Qos_En; // QoS enable
988 u8 En40MHz; // 40MHz BW enable
989 u8 AMSDU2AMPDU_En; //14181 convert AMSDU to AMPDU, 0: disable
990 u8 AMPDU_En; //111n AMPDU/AMSDU enable
992 //--- LONG WORD 4 ----
993 u8 rate_control_offload;//FW offloads, 0: driver handles
994 u8 aggregation_offload; // FW offloads, 0: driver handles
995 u8 beacon_offload; //FW offloads, 0: driver handles
996 u8 MLME_offload; // FW offloads, 0: driver handles
997 u8 hwpc_offload; // FW offloads, 0: driver handles
998 u8 tcp_checksum_offload; //FW offloads, 0: driver handles
999 u8 tcp_offload; //FW offloads, 0: driver handles
1000 u8 ps_control_offload; //FW offloads, 0: driver handles
1002 //--- LONG WORD 5 ----
1003 u8 WWLAN_Offload; // FW offloads, 0: driver handles
1004 u8 MPMode; // normal mode, 0: MP mode;
1005 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
1006 u16 Signature; //0x12: 8712, 0x92: 8192S
1010 // u32 wireless_band; //no A-band exists in 8712
1011 }RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
1013 typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
1015 //--- LONG WORD 0 ----
1017 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
1018 u32 DMEMSize; //define the size of boot loader
1021 //--- LONG WORD 1 ----
1022 u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
1023 u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
1025 //--- LONG WORD 2 ----
1026 u32 FW_PRIV_SIZE; //define the size of DMEM variable
1029 //--- LONG WORD 3 ----
1033 RT_8192S_FIRMWARE_PRIV FWPriv;
1035 }RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
1037 #define RT_8192S_FIRMWARE_HDR_SIZE 80
1039 typedef enum _FIRMWARE_8192S_STATUS{
1041 FW_STATUS_LOAD_IMEM = 1,
1042 FW_STATUS_LOAD_EMEM = 2,
1043 FW_STATUS_LOAD_DMEM = 3,
1044 FW_STATUS_READY = 4,
1045 }FIRMWARE_8192S_STATUS;
1047 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
1049 typedef struct _rt_firmware{
1050 firmware_source_e eFWSource;
1051 PRT_8192S_FIRMWARE_HDR pFwHeader;
1052 FIRMWARE_8192S_STATUS FWStatus;
1057 u8 szFwTmpBuffer[164000];
1058 u16 CmdPacketFragThresold;
1059 //firmware_status_e firmware_status;//in 92u temp FIXLZM
1060 //u16 cmdpacket_frag_thresold;//in 92u temp FIXLZM
1061 //u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];//in 92u temp FIXLZM
1062 //u16 firmware_buf_size;//in 92u temp FIXLZM
1064 }rt_firmware, *prt_firmware;
1066 typedef struct _rt_firmware{
1067 firmware_status_e firmware_status;
1068 u16 cmdpacket_frag_thresold;
1069 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
1070 #define MAX_FW_INIT_STEP 3
1071 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
1072 u16 firmware_buf_size[MAX_FW_INIT_STEP];
1073 }rt_firmware, *prt_firmware;
1075 typedef struct _rt_firmware_info_819xUsb{
1077 }rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
1081 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
1084 /* Firmware Queue Layout */
1085 #define NUM_OF_FIRMWARE_QUEUE 10
1086 #define NUM_OF_PAGES_IN_FW 0x100
1089 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
1090 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
1091 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
1092 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
1093 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
1094 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
1095 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
1096 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
1097 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
1098 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
1101 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
1102 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
1103 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
1104 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
1105 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
1106 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
1107 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
1108 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
1109 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
1110 //=================================================================
1111 //=================================================================
1113 #define EPROM_93c46 0
1114 #define EPROM_93c56 1
1116 #define DEFAULT_FRAG_THRESHOLD 2342U
1117 #define MIN_FRAG_THRESHOLD 256U
1118 #define DEFAULT_BEACONINTERVAL 0x64U
1119 #define DEFAULT_BEACON_ESSID "Rtl819xU"
1121 #define DEFAULT_SSID ""
1122 #define DEFAULT_RETRY_RTS 7
1123 #define DEFAULT_RETRY_DATA 7
1124 #define PRISM_HDR_SIZE 64
1126 #define PHY_RSSI_SLID_WIN_MAX 100
1129 typedef enum _WIRELESS_MODE {
1130 WIRELESS_MODE_UNKNOWN = 0x00,
1131 WIRELESS_MODE_A = 0x01,
1132 WIRELESS_MODE_B = 0x02,
1133 WIRELESS_MODE_G = 0x04,
1134 WIRELESS_MODE_AUTO = 0x08,
1135 WIRELESS_MODE_N_24G = 0x10,
1136 WIRELESS_MODE_N_5G = 0x20
1140 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
1142 typedef struct buffer
1144 struct buffer *next;
1149 typedef struct rtl_reg_debug{
1155 unsigned char length;
1157 unsigned char buf[0xff];
1166 typedef struct tx_pendingbuf
1168 struct ieee80211_txb *txb;
1175 typedef struct _rt_9x_tx_rate_history {
1178 // HT_MCS[0][]: BW=0 SG=0
1179 // HT_MCS[1][]: BW=1 SG=0
1180 // HT_MCS[2][]: BW=0 SG=1
1181 // HT_MCS[3][]: BW=1 SG=1
1183 }rt_tx_rahis_t, *prt_tx_rahis_t;
1184 typedef struct _RT_SMOOTH_DATA_4RF {
1185 char elements[4][100];//array to store values
1186 u32 index; //index to current array to store
1187 u32 TotalNum; //num of valid elements
1188 u32 TotalVal[4]; //sum of valid elements
1189 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
1191 #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
1192 //stats seems messed up, clean it ASAP
1193 typedef struct Stats
1195 unsigned long txrdu;
1196 // unsigned long rxrdu;
1197 //unsigned long rxnolast;
1198 //unsigned long rxnodata;
1199 // unsigned long rxreset;
1200 // unsigned long rxnopointer;
1202 unsigned long rxframgment;
1203 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
1204 unsigned long rxurberr;
1205 unsigned long rxstaterr;
1206 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
1207 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
1208 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
1209 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
1210 unsigned long numpacket_matchbssid; // debug use only.
1211 unsigned long numpacket_toself; // debug use only.
1212 unsigned long num_process_phyinfo; // debug use only.
1213 unsigned long numqry_phystatus;
1214 unsigned long numqry_phystatusCCK;
1215 unsigned long numqry_phystatusHT;
1216 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
1217 unsigned long txnperr;
1218 unsigned long txnpdrop;
1219 unsigned long txresumed;
1220 // unsigned long rxerr;
1221 // unsigned long rxoverflow;
1222 // unsigned long rxint;
1223 unsigned long txnpokint;
1224 // unsigned long txhpokint;
1225 // unsigned long txhperr;
1226 // unsigned long ints;
1227 // unsigned long shints;
1228 unsigned long txoverflow;
1229 // unsigned long rxdmafail;
1230 // unsigned long txbeacon;
1231 // unsigned long txbeaconerr;
1232 unsigned long txlpokint;
1233 unsigned long txlpdrop;
1234 unsigned long txlperr;
1235 unsigned long txbeokint;
1236 unsigned long txbedrop;
1237 unsigned long txbeerr;
1238 unsigned long txbkokint;
1239 unsigned long txbkdrop;
1240 unsigned long txbkerr;
1241 unsigned long txviokint;
1242 unsigned long txvidrop;
1243 unsigned long txvierr;
1244 unsigned long txvookint;
1245 unsigned long txvodrop;
1246 unsigned long txvoerr;
1247 unsigned long txbeaconokint;
1248 unsigned long txbeacondrop;
1249 unsigned long txbeaconerr;
1250 unsigned long txmanageokint;
1251 unsigned long txmanagedrop;
1252 unsigned long txmanageerr;
1253 unsigned long txdatapkt;
1254 unsigned long txfeedback;
1255 unsigned long txfeedbackok;
1257 unsigned long txoktotal;
1258 unsigned long txokbytestotal;
1259 unsigned long txokinperiod;
1260 unsigned long txmulticast;
1261 unsigned long txbytesmulticast;
1262 unsigned long txbroadcast;
1263 unsigned long txbytesbroadcast;
1264 unsigned long txunicast;
1265 unsigned long txbytesunicast;
1267 unsigned long rxoktotal;
1268 unsigned long rxbytesunicast;
1269 unsigned long txfeedbackfail;
1270 unsigned long txerrtotal;
1271 unsigned long txerrbytestotal;
1272 unsigned long txerrmulticast;
1273 unsigned long txerrbroadcast;
1274 unsigned long txerrunicast;
1275 unsigned long txretrycount;
1276 unsigned long txfeedbackretry;
1277 u8 last_packet_rate;
1278 unsigned long slide_signal_strength[100];
1279 unsigned long slide_evm[100];
1280 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
1281 unsigned long slide_evm_total; // For recording sliding window's EVM value
1282 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
1283 long signal_quality;
1284 long last_signal_strength_inpercent;
1285 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
1286 u8 rx_rssi_percentage[4];
1287 u8 rx_evm_percentage[2];
1289 rt_tx_rahis_t txrate;
1290 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
1291 u32 Slide_Beacon_Total; //cosa add for beacon rssi
1292 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
1294 u32 CurrentShowTxate;
1299 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
1300 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
1301 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
1305 typedef struct ChnlAccessSetting {
1312 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
1314 typedef struct _BB_REGISTER_DEFINITION{
1315 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
1316 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
1317 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
1318 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
1319 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
1320 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
1321 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
1322 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
1323 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
1324 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
1325 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
1326 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
1327 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
1328 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
1329 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
1330 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
1331 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
1332 u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
1333 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
1335 typedef enum _RT_RF_TYPE_819xU{
1340 RF_6052=4, // 4 11b/g/n RF
1342 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
1345 typedef enum _RF_POWER_STATE{
1350 }RF_POWER_STATE, *PRF_POWER_STATE;
1353 typedef struct _rate_adaptive
1355 u8 rate_adaptive_disabled;
1359 u32 high_rssi_thresh_for_ra;
1360 u32 high2low_rssi_thresh_for_ra;
1361 u8 low2high_rssi_thresh_for_ra40M;
1362 u32 low_rssi_thresh_for_ra40M;
1363 u8 low2high_rssi_thresh_for_ra20M;
1364 u32 low_rssi_thresh_for_ra20M;
1365 u32 upper_rssi_threshold_ratr;
1366 u32 middle_rssi_threshold_ratr;
1367 u32 low_rssi_threshold_ratr;
1368 u32 low_rssi_threshold_ratr_40M;
1369 u32 low_rssi_threshold_ratr_20M;
1370 u8 ping_rssi_enable; //cosa add for test
1371 u32 ping_rssi_ratr; //cosa add for test
1372 u32 ping_rssi_thresh_for_ra;//cosa add for test
1375 } rate_adaptive, *prate_adaptive;
1377 #define TxBBGainTableLength 37
1378 #define CCKTxBBGainTableLength 23
1380 typedef struct _txbbgain_struct
1382 long txbb_iq_amplifygain;
1384 } txbbgain_struct, *ptxbbgain_struct;
1386 typedef struct _ccktxbbgain_struct
1388 //The Value is from a22 to a29 one Byte one time is much Safer
1389 u8 ccktxbb_valuearray[8];
1390 } ccktxbbgain_struct,*pccktxbbgain_struct;
1393 typedef struct _init_gain
1401 } init_gain, *pinit_gain;
1404 typedef struct _phy_ofdm_rx_status_report_819xusb
1413 u8 csi_current_X[2];
1418 u8 rxsc_sgien_exflg;
1419 }phy_sts_ofdm_819xusb_t;
1421 typedef struct _phy_cck_rx_status_report_819xusb
1423 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
1424 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
1428 }phy_sts_cck_819xusb_t;
1431 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
1436 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
1438 typedef enum _RT_CUSTOMER_ID
1441 RT_CID_8187_ALPHA0 = 1,
1442 RT_CID_8187_SERCOMM_PS = 2,
1443 RT_CID_8187_HW_LED = 3,
1444 RT_CID_8187_NETGEAR = 4,
1446 RT_CID_819x_CAMEO = 6,
1447 RT_CID_819x_RUNTOP = 7,
1448 RT_CID_819x_Senao = 8,
1449 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
1450 RT_CID_819x_Netcore = 10,
1451 RT_CID_Nettronix = 11,
1454 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
1456 //================================================================================
1457 // LED customization.
1458 //================================================================================
1460 typedef enum _LED_STRATEGY_8190{
1461 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
1462 SW_LED_MODE1, // SW control for PCI Express
1463 SW_LED_MODE2, // SW control for Cameo.
1464 SW_LED_MODE3, // SW contorl for RunTop.
1465 SW_LED_MODE4, // SW control for Netcore
1466 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
1467 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
1469 typedef enum _RESET_TYPE {
1470 RESET_TYPE_NORESET = 0x00,
1471 RESET_TYPE_NORMAL = 0x01,
1472 RESET_TYPE_SILENT = 0x02
1475 /* The simple tx command OP code. */
1476 typedef enum _tag_TxCmd_Config_Index{
1477 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
1478 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
1479 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
1480 TXCMD_SET_TX_DURATION = 0xFF900003,
1481 TXCMD_SET_RX_RSSI = 0xFF900004,
1482 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
1494 //definded by WB. Ready to fill handlers for different NIC types.
1495 //add handle here when necessary.
1498 void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1499 short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1500 short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1501 void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1502 void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1503 bool (* rtl819x_adapter_start)(struct net_device *dev);
1504 void (* rtl819x_link_change)(struct net_device *dev);
1505 void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1506 void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1509 typedef struct r8192_priv
1511 struct rtl819x_ops* ops;
1512 struct usb_device *udev;
1513 //added for maintain info from eeprom
1517 u8 eeprom_CustomerID;
1518 u8 eeprom_SubCustomerID;
1519 u8 eeprom_ChannelPlan;
1520 RT_CUSTOMER_ID CustomerID;
1521 LED_STRATEGY_8190 LedStrategy;
1522 u8 txqueue_to_outpipemap[9];
1529 struct ieee80211_device *ieee80211;
1531 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1532 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1533 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1535 enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1537 short plcp_preamble_mode;
1539 spinlock_t irq_lock;
1540 // spinlock_t irq_th_lock;
1544 spinlock_t rf_lock; //used to lock rf write operation added by wb
1547 // short irq_enabled;
1548 // struct net_device *dev; //comment this out.
1554 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1555 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1556 // u8 cck_txpwr_base;
1557 // u8 ofdm_txpwr_base;
1558 // u8 challow[15]; //channels from 1 to 14, 0 not used
1560 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1563 // struct timer_list scan_timer;
1564 /*short scanpending;
1566 // spinlock_t scan_lock;
1568 //u8 active_scan_num;
1569 struct semaphore wx_sem;
1570 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1577 // short rcr_csense;
1578 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1579 RT_RF_TYPE_819xU rf_chip;
1582 short (*rf_set_sens)(struct net_device *dev,short sens);
1583 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1584 void (*rf_close)(struct net_device *dev);
1585 void (*rf_init)(struct net_device *dev);
1590 struct iw_statistics wstats;
1591 struct proc_dir_entry *dir_dev;
1596 // dma_addr_t rxringdma;
1597 struct urb **rx_urb;
1598 struct urb **rx_cmd_urb;
1600 /* modified by davad for Rx process */
1601 struct sk_buff_head rx_queue;
1602 struct sk_buff_head skb_queue;
1604 struct work_struct qos_activate;
1607 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1610 struct tasklet_struct irq_rx_tasklet;
1611 struct urb *rxurb_task;
1613 //2 Tx Related variables
1614 u16 ShortRetryLimit;
1617 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1619 u32 LastRxDescTSFHigh;
1620 u32 LastRxDescTSFLow;
1623 //2 Rx Related variables
1624 u16 EarlyRxThreshold;
1634 struct ChnlAccessSetting ChannelAccessSetting;
1636 struct work_struct reset_wq;
1638 /**********************************************************/
1644 bool bCurrentRxAggrEnable;
1645 u8 Rf_Mode; //add for Firmware RF -R/W switch
1646 prt_firmware pFirmware;
1647 rtl819xUsb_loopback_e LoopbackMode;
1648 firmware_source_e firmware_source;
1651 u16 EEPROMTxPowerDiff;
1652 u8 EEPROMThermalMeter;
1654 u8 EEPROMCrystalCap;
1656 u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1657 u8 EEPROMTxPowerLevelCCK_V1[3];
1658 u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1659 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1662 bool bDmDisableProtect;
1663 bool bIgnoreDiffRateTxPowerOffset;
1665 #ifdef EEPROM_OLD_FORMAT_SUPPORT
1666 u8 EEPROMTxPowerLevelCCK24G[14]; // CCK 2.4G channel 1~14
1667 //u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1668 //u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1670 // For EEPROM TX Power Index like 8190 series
1671 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1672 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1673 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1674 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1676 // F92S new definition
1677 //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1678 u8 RfCckChnlAreaTxPwr[2][3];
1679 u8 RfOfdmChnlAreaTxPwr1T[2][3];
1680 u8 RfOfdmChnlAreaTxPwr2T[2][3];
1683 // Add For EEPROM Efuse switch and Efuse Shadow map Setting
1685 bool bBootFromEfuse; // system boot form EFUSE
1686 u8 EfuseMap[2][HWSET_MAX_SIZE_92S];
1689 u8 EEPROMUsbPhyParam[5];
1692 bool bBootFromEEPROM; // system boot from EEPROM
1695 u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B.
1696 u8 EEPROMTxPwrTkMode;
1698 u8 bTXPowerDataReadFromEEPORM;
1701 u8 EEPROMUsbEndPointNumber;
1703 bool AutoloadFailFlag;
1704 u8 RfTxPwrLevelCck[2][14];
1705 u8 RfTxPwrLevelOfdm1T[2][14];
1706 u8 RfTxPwrLevelOfdm2T[2][14];
1707 // 2009/01/20 MH Add for new EEPROM format.
1708 u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff
1709 u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff
1710 u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel
1711 u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel
1712 u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel
1713 u8 TxPwrbandEdgeFlag; // Band edge enable flag
1715 // L1 and L2 high power threshold.
1716 u8 MidHighPwrTHR_L1;
1717 u8 MidHighPwrTHR_L2;
1718 u8 TxPwrSafetyFlag; // for Tx power safety spec
1722 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1723 // Read/write are allow for following hardware information variables
1725 u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1727 u32 MCSTxPowerLevelOriginalOffset[6];
1729 u32 CCKTxPowerLevelOriginalOffset;
1730 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1731 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1732 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1735 u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1736 u8 CrystalCap; // CrystalCap.
1737 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1740 // Use to calculate PWBD.
1742 long undecorated_smoothed_pwdb;
1745 u8 SwChnlInProgress;
1748 u8 SetBWModeInProgress;
1749 HT_CHANNEL_WIDTH CurrentChannelBW;
1754 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1755 // Joseph test for shorten RF configuration time.
1756 // We save RF reg0 in this variable to reduce RF reading.
1760 bool brfpath_rxenable[4];
1762 bool SetRFPowerStateInProgress;
1764 struct timer_list watch_dog_timer;
1766 //+by amy 080515 for dynamic mechenism
1767 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1768 bool bdynamic_txpower; //bDynamicTxPower
1769 bool bDynamicTxHighPower; // Tx high power state
1770 bool bDynamicTxLowPower; // Tx low power state
1771 bool bLastDTPFlag_High;
1772 bool bLastDTPFlag_Low;
1774 bool bstore_last_dtpflag;
1775 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1776 //Add by amy for Rate Adaptive
1777 rate_adaptive rate_adaptive;
1778 //Add by amy for TX power tracking
1779 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1780 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1781 u8 EEPROMTxPowerTrackEnable;
1782 u8 txpower_count;//For 6 sec do tracking again
1783 bool btxpower_trackingInit;
1786 //2007/09/10 Mars Add CCK TX Power Tracking
1787 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1788 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1789 u8 rfa_txpowertrackingindex;
1790 u8 rfa_txpowertrackingindex_real;
1791 u8 rfa_txpowertracking_default;
1792 u8 rfc_txpowertrackingindex;
1793 u8 rfc_txpowertrackingindex_real;
1795 s8 cck_present_attentuation;
1796 u8 cck_present_attentuation_20Mdefault;
1797 u8 cck_present_attentuation_40Mdefault;
1798 char cck_present_attentuation_difference;
1799 bool btxpower_tracking;
1801 bool btxpowerdata_readfromEEPORM;
1803 //For Backup Initial Gain
1804 init_gain initgain_backup;
1805 u8 DefaultInitialGain[4];
1806 // For EDCA Turbo mode, Added by amy 080515.
1807 bool bis_any_nonbepkts;
1808 bool bcurrent_turbo_EDCA;
1809 bool bis_cur_rdlstate;
1810 struct timer_list fsync_timer;
1811 bool bfsync_processing; // 500ms Fsync timer is active or not
1813 u32 rateCountDiffRecord;
1814 u32 ContiuneDiffCount;
1819 u8 framesyncMonitor;
1820 //Added by amy 080516 for RX related
1822 u8 nrxAMPDU_aggr_num;
1827 //by amy for reset_count
1831 u32 txpower_checkcnt;
1832 u32 txpower_tracking_callback_cnt;
1833 u8 thermal_read_val[40];
1834 u8 thermal_readback_index;
1835 u32 ccktxpower_adjustcnt_not_ch14;
1836 u32 ccktxpower_adjustcnt_ch14;
1837 u8 tx_fwinfo_force_subcarriermode;
1838 u8 tx_fwinfo_force_subcarrierval;
1839 //by amy for silent reset
1840 RESET_TYPE ResetProgress;
1841 bool bForcedSilentReset;
1842 bool bDisableNormalResetCheck;
1845 int IrpPendingCount;
1846 bool bResetInProgress;
1848 u8 InitialGainOperateType;
1852 //define work item by amy 080526
1853 struct delayed_work update_beacon_wq;
1854 struct delayed_work watch_dog_wq;
1855 struct delayed_work txpower_tracking_wq;
1856 struct delayed_work rfpath_check_wq;
1857 struct delayed_work gpio_change_rf_wq;
1858 struct delayed_work initialgain_operate_wq;
1860 struct workqueue_struct *priv_wq;
1864 // RF and BB access related synchronization flags.
1865 bool bChangeBBInProgress; // BaseBand RW is still in progress.
1866 bool bChangeRFInProgress; // RF RW is still in progress.
1868 u32 CCKTxPowerAdjustCntCh14; //debug only
1869 u32 CCKTxPowerAdjustCntNotCh14; //debug only
1870 u32 TXPowerTrackingCallbackCnt; //debug only
1871 u32 TxPowerCheckCnt; //debug only
1872 u32 RFWritePageCnt[3]; //debug only
1873 u32 RFReadPageCnt[3]; //debug only
1874 u8 ThermalReadBackIndex; //debug only
1875 u8 ThermalReadVal[40]; //debug only
1877 // For HCT test, 2005.07.15, by rcnjko.
1878 // not realize true, just define it, set it 0 default, because some func use it
1881 // The current Tx Power Level
1882 u8 CurrentCckTxPwrIdx;
1883 u8 CurrentOfdm24GTxPwrIdx;
1885 // For pass 92S common phycfg.c compiler
1886 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1887 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1888 u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14
1889 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1890 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1891 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1893 bool bRFSiOrPi;//0=si, 1=pi.
1896 bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1905 #ifdef USB_RX_AGGREGATION_SUPPORT
1906 bool bCurrentRxAggrEnable;
1907 bool bForcedUsbRxAggr;
1908 u32 ForcedUsbRxAggrInfo;
1909 u32 LastUsbRxAggrInfoSetting;
1910 u32 RegUsbRxAggrInfo;
1918 // now mirging to rtl8187B
1921 LOW_PRIORITY = 0x02,
1927 BULK_PRIORITY = 0x01,
1938 BEACON_PRIORITY, //0x0A
1943 UART_PRIORITY //0x0F
1956 #if 0 //defined in Qos.h
1957 //typedef u32 AC_CODING;
1958 #define AC0_BE 0 // ACI: 0x00 // Best Effort
1959 #define AC1_BK 1 // ACI: 0x01 // Background
1960 #define AC2_VI 2 // ACI: 0x10 // Video
1961 #define AC3_VO 3 // ACI: 0x11 // Voice
1962 #define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
1965 // ECWmin/ECWmax field.
1966 // Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
1979 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1981 typedef union _ACI_AIFSN{
1991 }ACI_AIFSN, *PACI_AIFSN;
1994 // AC Parameters Record Format.
1995 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1997 typedef union _AC_PARAM{
2007 }AC_PARAM, *PAC_PARAM;
2011 struct ssid_thread {
2012 struct net_device *dev;
2013 u8 name[IW_ESSID_MAX_SIZE + 1];
2018 short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
2019 short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
2020 bool FirmwareDownload92S(struct net_device *dev);
2022 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
2023 bool init_firmware(struct net_device *dev);
2026 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
2027 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
2029 u32 read_cam(struct net_device *dev, u8 addr);
2030 void write_cam(struct net_device *dev, u8 addr, u32 data);
2032 u8 read_nic_byte(struct net_device *dev, int x);
2033 u8 read_nic_byte_E(struct net_device *dev, int x);
2034 u32 read_nic_dword(struct net_device *dev, int x);
2035 u16 read_nic_word(struct net_device *dev, int x) ;
2036 void write_nic_byte(struct net_device *dev, int x,u8 y);
2037 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
2038 void write_nic_word(struct net_device *dev, int x,u16 y);
2039 void write_nic_dword(struct net_device *dev, int x,u32 y);
2040 void force_pci_posting(struct net_device *dev);
2042 void rtl8192_rtx_disable(struct net_device *);
2043 void rtl8192_rx_enable(struct net_device *);
2044 void rtl8192_tx_enable(struct net_device *);
2046 void rtl8192_disassociate(struct net_device *dev);
2047 //void fix_rx_fifo(struct net_device *dev);
2048 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
2050 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
2051 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
2052 void rtl8192_update_msr(struct net_device *dev);
2053 int rtl8192_down(struct net_device *dev);
2054 int rtl8192_up(struct net_device *dev);
2055 void rtl8192_commit(struct net_device *dev);
2056 void rtl8192_set_chan(struct net_device *dev,short ch);
2057 void write_phy(struct net_device *dev, u8 adr, u8 data);
2058 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
2059 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
2060 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
2061 void rtl8192_set_rxconf(struct net_device *dev);
2062 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
2063 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate);
2064 void CamResetAllEntry(struct net_device* dev);
2065 void EnableHWSecurityConfig8192(struct net_device *dev);
2066 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
2067 short rtl8192_is_tx_queue_empty(struct net_device *dev);