drivers/staging/rtl8192su/r8192U.h

   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to tanks the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 //#include <linux/config.h>
  24 #include <linux/init.h>
  25 #include <linux/ioport.h>
  26 #include <linux/sched.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/netdevice.h>
  30 //#include <linux/pci.h>
  31 #include <linux/usb.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/delay.h>
  34 #include <linux/rtnetlink.h>    //for rtnl_lock()
  35 #include <linux/wireless.h>
  36 #include <linux/timer.h>
  37 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  38 #include <linux/if_arp.h>
  39 #include <linux/random.h>
  40 #include <linux/version.h>
  41 #include <asm/io.h>
  42 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27))
  43 #include <asm/semaphore.h>
  44 #endif
  45 #include "ieee80211.h"
  46
  47 #ifdef RTL8192SU
  48 #include "r8192S_firmware.h"
  49 #else
  50 #include "r819xU_firmware.h"
  51 #endif
  52
  53 //#define RTL8192U
  54 #define RTL819xU_MODULE_NAME "rtl819xU"
  55 //added for HW security, john.0629
  56 #define FALSE 0
  57 #define TRUE 1
  58 #define MAX_KEY_LEN     61
  59 #define KEY_BUF_SIZE    5
  60
  61 #define BIT0            0x00000001
  62 #define BIT1            0x00000002
  63 #define BIT2            0x00000004
  64 #define BIT3            0x00000008
  65 #define BIT4            0x00000010
  66 #define BIT5            0x00000020
  67 #define BIT6            0x00000040
  68 #define BIT7            0x00000080
  69 #define BIT8            0x00000100
  70 #define BIT9            0x00000200
  71 #define BIT10           0x00000400
  72 #define BIT11           0x00000800
  73 #define BIT12           0x00001000
  74 #define BIT13           0x00002000
  75 #define BIT14           0x00004000
  76 #define BIT15           0x00008000
  77 #define BIT16           0x00010000
  78 #define BIT17           0x00020000
  79 #define BIT18           0x00040000
  80 #define BIT19           0x00080000
  81 #define BIT20           0x00100000
  82 #define BIT21           0x00200000
  83 #define BIT22           0x00400000
  84 #define BIT23           0x00800000
  85 #define BIT24           0x01000000
  86 #define BIT25           0x02000000
  87 #define BIT26           0x04000000
  88 #define BIT27           0x08000000
  89 #define BIT28           0x10000000
  90 #define BIT29           0x20000000
  91 #define BIT30           0x40000000
  92 #define BIT31           0x80000000
  93
  94 // Rx smooth factor
  95 #define Rx_Smooth_Factor                20
  96 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
  97 #define DMESG(x,a...) printk(KERN_INFO RTL819xU_MODULE_NAME ": " x "\n", ## a)
  98 #define DMESGW(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": WW:" x "\n", ## a)
  99 #define DMESGE(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": EE:" x "\n", ## a)
 100 #else
 101 #define DMESG(x,a...)
 102 #define DMESGW(x,a...)
 103 #define DMESGE(x,a...)
 104 extern u32 rt_global_debug_component;
 105 #define RT_TRACE(component, x, args...) \
 106 do { if(rt_global_debug_component & component) \
 107         printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
 108                ##args);\
 109 }while(0);
 110 //----------------------------------------------------------------------
 111 //// Get 8192SU  Rx descriptor. Added by Roger, 2008.04.15.
 112 ////----------------------------------------------------------------------
 113 #define RX_DESC_SIZE 24
 114 #define RX_DRV_INFO_SIZE_UNIT   8
 115
 116 #define IS_UNDER_11N_AES_MODE(_ieee)  ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
 117                                                                         (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
 118
 119 #define COMP_TRACE                              BIT0            // For function call tracing.
 120 #define COMP_DBG                                BIT1            // Only for temporary debug message.
 121 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
 122
 123
 124 #define COMP_RECV                               BIT3            // Reveive part data path.
 125 #define COMP_SEND                               BIT4            // Send part path.
 126 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 127 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 128 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 129 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 130 #define COMP_POWER_TRACKING                     BIT9    //FOR 8190 TX POWER TRACKING
 131 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 132 #define COMP_QOS                                BIT11   // For QoS.
 133 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
 134 #define COMP_LPS                                        BIT13   // For Radio Measurement.
 135 #define COMP_DIG                                BIT14   // For DIG, 2006.09.25, by rcnjko.
 136 #define COMP_PHY                                BIT15
 137 #define COMP_CH                                 BIT16   //channel setting debug
 138 #define COMP_TXAGC                              BIT17   // For Tx power, 060928, by rcnjko.
 139 #define COMP_HIPWR                              BIT18   // For High Power Mechanism, 060928, by rcnjko.
 140 #define COMP_HALDM                              BIT19   // For HW Dynamic Mechanism, 061010, by rcnjko.
 141 #define COMP_SEC                                BIT20   // Event handling
 142 #define COMP_LED                                BIT21   // For LED.
 143 #define COMP_RF                                 BIT22   // For RF.
 144 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 145 #define COMP_RXDESC                             BIT23   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 146 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
 147 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 148
 149 #define COMP_FIRMWARE                           BIT24   //for firmware downloading
 150 #define COMP_HT                                 BIT25   // For 802.11n HT related information. by Emily 2006-8-11
 151 #define COMP_AMSDU                              BIT26   // For A-MSDU Debugging
 152
 153 #define COMP_SCAN                               BIT27
 154 #define COMP_CMD                                BIT28
 155 #define COMP_DOWN                               BIT29  //for rm driver module
 156 #define COMP_RESET                              BIT30  //for silent reset
 157 #define COMP_ERR                                BIT31 //for error out, always on
 158 #endif
 159
 160 #define RTL819x_DEBUG
 161 #ifdef RTL819x_DEBUG
 162 #define assert(expr) \
 163         if (!(expr)) {                                  \
 164                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
 165                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
 166         }
 167 //wb added to debug out data buf
 168 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
 169 #define RT_DEBUG_DATA(level, data, datalen)      \
 170         do{ if ((rt_global_debug_component & (level)) == (level))   \
 171                 {       \
 172                         int i;                                  \
 173                         u8* pdata = (u8*) data;                 \
 174                         printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__);   \
 175                         for(i=0; i<(int)(datalen); i++)                 \
 176                         {                                               \
 177                                 printk("%2x ", pdata[i]);               \
 178                                 if ((i+1)%16 == 0) printk("\n");        \
 179                         }                               \
 180                         printk("\n");                   \
 181                 }                                       \
 182         } while (0)
 183 #else
 184 #define assert(expr) do {} while (0)
 185 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
 186 #endif /* RTL8169_DEBUG */
 187
 188 //#ifdef RTL8192SU
 189         //2TODO: We should define 8192S firmware related macro settings here!!
 190         #define RTL819X_DEFAULT_RF_TYPE                         RF_1T2R
 191         #define RTL819X_TOTAL_RF_PATH                           2
 192
 193         //#define Rtl819XFwBootArray                                    Rtl8192UsbFwBootArray
 194         //#define Rtl819XFwMainArray                                    Rtl8192UsbFwMainArray
 195         //#define Rtl819XFwDataArray                                    Rtl8192UsbFwDataArray
 196
 197         #define Rtl819XMACPHY_Array_PG                          Rtl8192UsbMACPHY_Array_PG
 198         #define Rtl819XMACPHY_Array                                     Rtl8192UsbMACPHY_Array
 199         #define Rtl819XPHY_REGArray                                     Rtl8192UsbPHY_REGArray
 200         #define Rtl819XPHY_REG_1T2RArray                                Rtl8192UsbPHY_REG_1T2RArray
 201         //#define Rtl819XRadioA_Array                                   Rtl8192UsbRadioA_Array
 202         //#define Rtl819XRadioB_Array                                   Rtl8192UsbRadioB_Array
 203         #define Rtl819XRadioC_Array                                     Rtl8192UsbRadioC_Array
 204         #define Rtl819XRadioD_Array                                     Rtl8192UsbRadioD_Array
 205
 206         //2008.11.06 Add.
 207         #define Rtl819XFwImageArray                                     Rtl8192SUFwImgArray
 208         #define Rtl819XMAC_Array                                                Rtl8192SUMAC_2T_Array
 209         #define Rtl819XAGCTAB_Array                                     Rtl8192SUAGCTAB_Array
 210         #define Rtl819XPHY_REG_Array                                    Rtl8192SUPHY_REG_2T2RArray
 211         #define Rtl819XPHY_REG_to1T1R_Array                     Rtl8192SUPHY_ChangeTo_1T1RArray
 212         #define Rtl819XPHY_REG_to1T2R_Array                     Rtl8192SUPHY_ChangeTo_1T2RArray
 213         #define Rtl819XPHY_REG_to2T2R_Array                     Rtl8192SUPHY_ChangeTo_2T2RArray
 214         #define Rtl819XPHY_REG_Array_PG                         Rtl8192SUPHY_REG_Array_PG
 215         #define Rtl819XRadioA_Array                                     Rtl8192SURadioA_1T_Array
 216         #define Rtl819XRadioB_Array                                     Rtl8192SURadioB_Array
 217         #define Rtl819XRadioB_GM_Array                          Rtl8192SURadioB_GM_Array
 218         #define Rtl819XRadioA_to1T_Array                                Rtl8192SURadioA_to1T_Array
 219         #define Rtl819XRadioA_to2T_Array                                Rtl8192SURadioA_to2T_Array
 220 //#endif
 221
 222 //
 223 // Queue Select Value in TxDesc
 224 //
 225 #define QSLT_BK                                 0x1
 226 #define QSLT_BE                                 0x0
 227 #define QSLT_VI                                 0x4
 228 #define QSLT_VO                                 0x6
 229 #define QSLT_BEACON                             0x10
 230 #define QSLT_HIGH                               0x11
 231 #define QSLT_MGNT                               0x12
 232 #define QSLT_CMD                                0x13
 233
 234 #define DESC90_RATE1M                           0x00
 235 #define DESC90_RATE2M                           0x01
 236 #define DESC90_RATE5_5M                         0x02
 237 #define DESC90_RATE11M                          0x03
 238 #define DESC90_RATE6M                           0x04
 239 #define DESC90_RATE9M                           0x05
 240 #define DESC90_RATE12M                          0x06
 241 #define DESC90_RATE18M                          0x07
 242 #define DESC90_RATE24M                          0x08
 243 #define DESC90_RATE36M                          0x09
 244 #define DESC90_RATE48M                          0x0a
 245 #define DESC90_RATE54M                          0x0b
 246 #define DESC90_RATEMCS0                         0x00
 247 #define DESC90_RATEMCS1                         0x01
 248 #define DESC90_RATEMCS2                         0x02
 249 #define DESC90_RATEMCS3                         0x03
 250 #define DESC90_RATEMCS4                         0x04
 251 #define DESC90_RATEMCS5                         0x05
 252 #define DESC90_RATEMCS6                         0x06
 253 #define DESC90_RATEMCS7                         0x07
 254 #define DESC90_RATEMCS8                         0x08
 255 #define DESC90_RATEMCS9                         0x09
 256 #define DESC90_RATEMCS10                        0x0a
 257 #define DESC90_RATEMCS11                        0x0b
 258 #define DESC90_RATEMCS12                        0x0c
 259 #define DESC90_RATEMCS13                        0x0d
 260 #define DESC90_RATEMCS14                        0x0e
 261 #define DESC90_RATEMCS15                        0x0f
 262 #define DESC90_RATEMCS32                        0x20
 263
 264 //#ifdef RTL8192SU
 265 // CCK Rates, TxHT = 0
 266 #define DESC92S_RATE1M                                  0x00
 267 #define DESC92S_RATE2M                                  0x01
 268 #define DESC92S_RATE5_5M                                0x02
 269 #define DESC92S_RATE11M                                 0x03
 270
 271 // OFDM Rates, TxHT = 0
 272 #define DESC92S_RATE6M                                  0x04
 273 #define DESC92S_RATE9M                                  0x05
 274 #define DESC92S_RATE12M                                 0x06
 275 #define DESC92S_RATE18M                                 0x07
 276 #define DESC92S_RATE24M                                 0x08
 277 #define DESC92S_RATE36M                                 0x09
 278 #define DESC92S_RATE48M                                 0x0a
 279 #define DESC92S_RATE54M                                 0x0b
 280
 281 // MCS Rates, TxHT = 1
 282 #define DESC92S_RATEMCS0                                0x0c
 283 #define DESC92S_RATEMCS1                                0x0d
 284 #define DESC92S_RATEMCS2                                0x0e
 285 #define DESC92S_RATEMCS3                                0x0f
 286 #define DESC92S_RATEMCS4                                0x10
 287 #define DESC92S_RATEMCS5                                0x11
 288 #define DESC92S_RATEMCS6                                0x12
 289 #define DESC92S_RATEMCS7                                0x13
 290 #define DESC92S_RATEMCS8                                0x14
 291 #define DESC92S_RATEMCS9                                0x15
 292 #define DESC92S_RATEMCS10                               0x16
 293 #define DESC92S_RATEMCS11                               0x17
 294 #define DESC92S_RATEMCS12                               0x18
 295 #define DESC92S_RATEMCS13                               0x19
 296 #define DESC92S_RATEMCS14                               0x1a
 297 #define DESC92S_RATEMCS15                               0x1b
 298 #define DESC92S_RATEMCS15_SG                    0x1c
 299 #define DESC92S_RATEMCS32                               0x20
 300 //#endif
 301
 302 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 303
 304 #define IEEE80211_WATCH_DOG_TIME    2000
 305 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 306 //for txpowertracking by amy
 307 #define         OFDM_Table_Length       19
 308 #define CCK_Table_length        12
 309
 310 #ifdef RTL8192SU
 311 //
 312 //Tx Descriptor for RLT8192SU(Normal mode)
 313 //
 314 typedef struct _tx_desc_819x_usb {
 315         // DWORD 0
 316         u16             PktSize;//:16;
 317         u8              Offset;//:8;
 318         u8              Type:2; // Reserved for MAC header Frame Type subfield.
 319         u8              LastSeg:1;
 320         u8              FirstSeg:1;
 321         u8              LINIP:1;
 322         u8              AMSDU:1;
 323         u8              GF:1;
 324         u8              OWN:1;
 325
 326         // DWORD 1
 327         u8              MacID:5;
 328         u8              MoreData:1;
 329         u8              MOREFRAG:1;
 330         u8              PIFS:1;
 331         u8              QueueSelect:5;
 332         u8              AckPolicy:2;
 333         u8              NoACM:1;
 334         u8              NonQos:1;
 335         u8              KeyID:2;
 336         u8              OUI:1;
 337         u8              PktType:1;
 338         u8              EnDescID:1;
 339         u8              SecType:2;
 340         u8              HTC:1;  //padding0
 341         u8              WDS:1;  //padding1
 342         u8              PktOffset:5;    //padding_len (hw)
 343         u8              HWPC:1;
 344
 345         // DWORD 2
 346         u32             DataRetryLmt:6;
 347         u32             RetryLmtEn:1;
 348         u32             TSFL:5;
 349         u32             RTSRC:6;        // Reserved for HW RTS Retry Count.
 350         u32             DATARC:6;       // Reserved for HW DATA Retry Count.
 351         u32             Rsvd1:5;
 352         u32             AllowAggregation:1;
 353         u32             BK:1;   //Aggregation break.
 354         u32             OwnMAC:1;
 355
 356         // DWORD 3
 357         u8              NextHeadPage;//:8;
 358         u8              TailPage;//:8;
 359         u16             Seq:12;
 360         u16             Frag:4;
 361
 362         // DWORD 4
 363         u32             RTSRate:6;
 364         u32             DisRTSFB:1;
 365         u32             RTSRateFBLmt:4;
 366         u32             CTS2Self:1;
 367         u32             RTSEn:1;
 368         u32             RaBRSRID:3;     //Rate adaptive BRSR ID.
 369         u32             TxHT:1;
 370         u32             TxShort:1;//for data
 371         u32             TxBandwidth:1;
 372         u32             TxSubCarrier:2;
 373         u32             STBC:2;
 374         u32             RD:1;
 375         u32             RTSHT:1;
 376         u32             RTSShort:1;
 377         u32             RTSBW:1;
 378         u32             RTSSubcarrier:2;
 379         u32             RTSSTBC:2;
 380         u32             USERATE:1;
 381         // DWORD 5
 382         u32             PktID:9;
 383         u32             TxRate:6;
 384         u32             DISFB:1;
 385         u32             DataRateFBLmt:5;
 386         u32             TxAGC:11;
 387
 388         // DWORD 6
 389         u16             IPChkSum;//:16;
 390         u16             TCPChkSum;//:16;
 391
 392         // DWORD 7
 393         //u16           TxBuffSize;//:16;//pcie
 394         u16             TxBufferSize;
 395         u16             IPHdrOffset:8;
 396         u16             Rsvd2:7;
 397         u16             TCPEn:1;
 398 }tx_desc_819x_usb, *ptx_desc_819x_usb;
 399 typedef struct _tx_status_desc_8192s_usb{
 400
 401         //DWORD 0
 402         u8              TxRate:6;
 403         u8              Rsvd1:1;
 404         u8              BandWidth:1;
 405         u8              RTSRate:6;
 406         u8              AGGLS:1;
 407         u8              AGG:1;
 408         u8              RTSRC:6;
 409         u8              DataRC:6;
 410         u8              FailCause:2;
 411         u8              TxOK:1;
 412         u8              Own:1;
 413
 414         //DWORD 1
 415         u16             Seq:12;
 416         u8              QueueSel:5;
 417         u8              MACID:5;
 418         u8              PwrMgt:1;
 419         u8              MoreData:1;
 420         u8              Rsvd2;
 421
 422         //DWORD 2
 423         u8              RxAGC1;
 424         u8              RxAGC2;
 425         u8              RxAGC3;
 426         u8              RxAGC4;
 427 }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
 428 #else
 429 /* for rtl819x */
 430 typedef struct _tx_desc_819x_usb {
 431         //DWORD 0
 432         u16     PktSize;
 433         u8      Offset;
 434         u8      Reserved0:3;
 435         u8      CmdInit:1;
 436         u8      LastSeg:1;
 437         u8      FirstSeg:1;
 438         u8      LINIP:1;
 439         u8      OWN:1;
 440
 441         //DWORD 1
 442         u8      TxFWInfoSize;
 443         u8      RATid:3;
 444         u8      DISFB:1;
 445         u8      USERATE:1;
 446         u8      MOREFRAG:1;
 447         u8      NoEnc:1;
 448         u8      PIFS:1;
 449         u8      QueueSelect:5;
 450         u8      NoACM:1;
 451         u8      Reserved1:2;
 452         u8      SecCAMID:5;
 453         u8      SecDescAssign:1;
 454         u8      SecType:2;
 455
 456         //DWORD 2
 457         u16     TxBufferSize;
 458         //u16 Reserved2;
 459         u8      ResvForPaddingLen:7;
 460         u8      Reserved3:1;
 461         u8      Reserved4;
 462
 463         //DWORD 3, 4, 5
 464         u32     Reserved5;
 465         u32     Reserved6;
 466         u32     Reserved7;
 467 }tx_desc_819x_usb, *ptx_desc_819x_usb;
 468 #endif
 469
 470 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 471 typedef struct _tx_desc_819x_usb_aggr_subframe {
 472         //DWORD 0
 473         u16     PktSize;
 474         u8      Offset;
 475         u8      TxFWInfoSize;
 476
 477         //DWORD 1
 478         u8      RATid:3;
 479         u8      DISFB:1;
 480         u8      USERATE:1;
 481         u8      MOREFRAG:1;
 482         u8      NoEnc:1;
 483         u8      PIFS:1;
 484         u8      QueueSelect:5;
 485         u8      NoACM:1;
 486         u8      Reserved1:2;
 487         u8      SecCAMID:5;
 488         u8      SecDescAssign:1;
 489         u8      SecType:2;
 490         u8      PacketID:7;
 491         u8      OWN:1;
 492 }tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 493 #endif
 494
 495
 496 #ifdef RTL8192SU
 497 //
 498 //Tx Descriptor for RLT8192SU(Load FW mode)
 499 //
 500 typedef struct _tx_desc_cmd_819x_usb{
 501        // DWORD 0
 502         u16             PktSize;
 503         u8              Offset;
 504         u8              Rsvd0:4;
 505         u8              LINIP:1;
 506         u8              Rsvd1:2;
 507         u8              OWN:1;
 508
 509         // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
 510         u32             Rsvd2;
 511         u32             Rsvd3;
 512         u32             Rsvd4;
 513         u32             Rsvd5;
 514         u32             Rsvd6;
 515         u32             Rsvd7;
 516
 517         // DWORD 7
 518         u16             TxBuffSize;//pcie
 519         u16             Rsvd8;
 520 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 521 //
 522 //H2C Command for RLT8192SU(Host TxCmd)
 523 //
 524 typedef struct _tx_h2c_desc_cmd_8192s_usb{
 525        // DWORD 0
 526         u32             PktSize:16;
 527         u32             Offset:8;
 528         u32             Rsvd0:7;
 529         u32             OWN:1;
 530
 531         // DWORD 1
 532         u32             Rsvd1:8;
 533         u32             QSEL:5;
 534         u32             Rsvd2:19;
 535
 536         // DWORD 2
 537         u32             Rsvd3;
 538
 539         // DWORD 3
 540         u32             NextHeadPage:8;
 541         u32             TailPage:8;
 542         u32             Rsvd4:16;
 543
 544         // DWORD 4, 5, 6, 7
 545         u32             Rsvd5;
 546         u32             Rsvd6;
 547         u32             Rsvd7;
 548         u32             Rsvd8;
 549 }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
 550
 551
 552 typedef struct _tx_h2c_cmd_hdr_8192s_usb{
 553        // DWORD 0
 554         u32             CmdLen:16;
 555         u32             ElementID:8;
 556         u32             CmdSeq:8;
 557
 558         // DWORD 1
 559         u32             Rsvd0;
 560 }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
 561 #else
 562 typedef struct _tx_desc_cmd_819x_usb {
 563         //DWORD 0
 564         u16     Reserved0;
 565         u8      Reserved1;
 566         u8      Reserved2:3;
 567         u8      CmdInit:1;
 568         u8      LastSeg:1;
 569         u8      FirstSeg:1;
 570         u8      LINIP:1;
 571         u8      OWN:1;
 572
 573         //DOWRD 1
 574         //u32   Reserved3;
 575         u8      TxFWInfoSize;
 576         u8      Reserved3;
 577         u8      QueueSelect;
 578         u8      Reserved4;
 579
 580         //DOWRD 2
 581         u16     TxBufferSize;
 582         u16     Reserved5;
 583
 584        //DWORD 3,4,5
 585         //u32   TxBufferAddr;
 586         //u32   NextDescAddress;
 587         u32     Reserved6;
 588         u32     Reserved7;
 589         u32     Reserved8;
 590 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 591 #endif
 592
 593 #ifdef RTL8192SU
 594 typedef struct _tx_fwinfo_819x_usb{
 595         //DWORD 0
 596         u8                      TxRate:7;
 597         u8                      CtsEnable:1;
 598         u8                      RtsRate:7;
 599         u8                      RtsEnable:1;
 600         u8                      TxHT:1;
 601         u8                      Short:1;                                                //Short PLCP for CCK, or short GI for 11n MCS
 602         u8                      TxBandwidth:1;                          // This is used for HT MCS rate only.
 603         u8                      TxSubCarrier:2;                         // This is used for legacy OFDM rate only.
 604         u8                      STBC:2;
 605         u8                      AllowAggregation:1;
 606         u8                      RtsHT:1;                                                //Interpre RtsRate field as high throughput data rate
 607         u8                      RtsShort:1;                                     //Short PLCP for CCK, or short GI for 11n MCS
 608         u8                      RtsBandwidth:1;                         // This is used for HT MCS rate only.
 609         u8                      RtsSubcarrier:2;                                // This is used for legacy OFDM rate only.
 610         u8                      RtsSTBC:2;
 611         u8                      EnableCPUDur:1;                         //Enable firmware to recalculate and assign packet duration
 612
 613         //DWORD 1
 614         u32                     RxMF:2;
 615         u32                     RxAMD:3;
 616         u32                     Reserved1:3;
 617         u32                     TxAGCOffSet:4;//TxAGCOffset:4;
 618         u32                     TxAGCSign:1;
 619         u32                     Tx_INFO_RSVD:6;
 620         u32                     PacketID:13;
 621 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 622 #else
 623 typedef struct _tx_fwinfo_819x_usb {
 624         //DOWRD 0
 625         u8              TxRate:7;
 626         u8              CtsEnable:1;
 627         u8              RtsRate:7;
 628         u8              RtsEnable:1;
 629         u8              TxHT:1;
 630         u8              Short:1;                //Short PLCP for CCK, or short GI for 11n MCS
 631         u8              TxBandwidth:1;          // This is used for HT MCS rate only.
 632         u8              TxSubCarrier:2;         // This is used for legacy OFDM rate only.
 633         u8              STBC:2;
 634         u8              AllowAggregation:1;
 635         u8              RtsHT:1;                //Interpre RtsRate field as high throughput data rate
 636         u8              RtsShort:1;             //Short PLCP for CCK, or short GI for 11n MCS
 637         u8              RtsBandwidth:1;         // This is used for HT MCS rate only.
 638         u8              RtsSubcarrier:2;        // This is used for legacy OFDM rate only.
 639         u8              RtsSTBC:2;
 640         u8              EnableCPUDur:1;         //Enable firmware to recalculate and assign packet duration
 641
 642         //DWORD 1
 643         u32             RxMF:2;
 644         u32             RxAMD:3;
 645         u32             TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
 646         u32             Reserved1:2;
 647         u32             TxAGCOffSet:4;
 648         u32             TxAGCSign:1;
 649         u32             Tx_INFO_RSVD:6;
 650         u32             PacketID:13;
 651         //u32                Reserved;
 652 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 653 #endif
 654
 655 typedef struct rtl8192_rx_info {
 656         struct urb *urb;
 657         struct net_device *dev;
 658         u8 out_pipe;
 659 }rtl8192_rx_info ;
 660
 661 #ifdef RTL8192SU
 662 //typedef struct _RX_DESC_STATUS_8192SU{
 663 typedef struct rx_desc_819x_usb{
 664         //DWORD 0
 665         u16             Length:14;
 666         u16             CRC32:1;
 667         u16             ICV:1;
 668         u8              RxDrvInfoSize:4;
 669         u8              Security:3;
 670         u8              Qos:1;
 671         u8              Shift:2;
 672         u8              PHYStatus:1;
 673         u8              SWDec:1;
 674         u8              LastSeg:1;
 675         u8              FirstSeg:1;
 676         u8              EOR:1;
 677         u8              Own:1;
 678
 679         //DWORD 1
 680         u16             MACID:5;
 681         u16             TID:4;
 682         u16             HwRsvd:5;
 683         u16             PAGGR:1;
 684         u16             FAGGR:1;
 685         u8              A1_FIT:4;
 686         u8              A2_FIT:4;
 687         u8              PAM:1;
 688         u8              PWR:1;
 689         u8              MoreData:1;
 690         u8              MoreFrag:1;
 691         u8              Type:2;
 692         u8              MC:1;
 693         u8              BC:1;
 694
 695         //DWORD 2
 696         u16             Seq:12;
 697         u16             Frag:4;
 698 #ifdef USB_RX_AGGREGATION_SUPPORT
 699         u8              UsbAggPktNum;//:8;
 700 #else
 701         u8              NextPktLen;//:8;
 702 #endif
 703         u8              Rsvd0:6;
 704         u8              NextIND:1;
 705         u8              Rsvd1:1;
 706
 707         //DWORD 3
 708         u8              RxMCS:6;
 709         u8              RxHT:1;
 710         u8              AMSDU:1;
 711         u8              SPLCP:1;
 712         u8              BW:1;
 713         u8              HTC:1;
 714         u8              TCPChkRpt:1;
 715         u8              IPChkRpt:1;
 716         u8              TCPChkValID:1;
 717         u8              HwPCErr:1;
 718         u8              HwPCInd:1;
 719         u16             IV0;//:16;
 720
 721         //DWORD 4
 722         u32             IV1;
 723
 724         //DWORD 5
 725         u32             TSFL;
 726 //}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
 727 }rx_desc_819x_usb, *prx_desc_819x_usb;
 728 #else
 729 typedef struct rx_desc_819x_usb{
 730         //DOWRD 0
 731         u16                 Length:14;
 732         u16                 CRC32:1;
 733         u16                 ICV:1;
 734         u8                  RxDrvInfoSize;
 735         u8                  Shift:2;
 736         u8                  PHYStatus:1;
 737         u8                  SWDec:1;
 738         //u8                LastSeg:1;
 739         //u8                FirstSeg:1;
 740         //u8                EOR:1;
 741         //u8                OWN:1;
 742         u8                  Reserved1:4;
 743
 744         //DWORD 1
 745         u32                 Reserved2;
 746
 747         //DWORD 2
 748         //u32               Reserved3;
 749
 750         //DWORD 3
 751         //u32                BufferAddress;
 752
 753 }rx_desc_819x_usb, *prx_desc_819x_usb;
 754 #endif
 755
 756 #ifdef USB_RX_AGGREGATION_SUPPORT
 757 typedef struct _rx_desc_819x_usb_aggr_subframe{
 758         //DOWRD 0
 759         u16                     Length:14;
 760         u16                     CRC32:1;
 761         u16                     ICV:1;
 762         u8                      Offset;
 763         u8                      RxDrvInfoSize;
 764         //DOWRD 1
 765         u8                      Shift:2;
 766         u8                      PHYStatus:1;
 767         u8                      SWDec:1;
 768         u8                      Reserved1:4;
 769         u8                      Reserved2;
 770         u16                     Reserved3;
 771         //DWORD 2
 772         //u4Byte                Reserved3;
 773         //DWORD 3
 774         //u4Byte                BufferAddress;
 775 }rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 776 #endif
 777
 778 #ifdef RTL8192SU
 779 //
 780 // Driver info are written to the begining of the RxBuffer
 781 //
 782 //typedef struct _RX_DRIVER_INFO_8192S{
 783 typedef struct rx_drvinfo_819x_usb{
 784         //
 785         // Driver info contain PHY status and other variabel size info
 786         // PHY Status content as below
 787         //
 788
 789         //DWORD 0
 790         /*u4Byte                        gain_0:7;
 791         u4Byte                  trsw_0:1;
 792         u4Byte                  gain_1:7;
 793         u4Byte                  trsw_1:1;
 794         u4Byte                  gain_2:7;
 795         u4Byte                  trsw_2:1;
 796         u4Byte                  gain_3:7;
 797         u4Byte                  trsw_3:1;       */
 798         u8                      gain_trsw[4];
 799
 800         //DWORD 1
 801         /*u4Byte                        pwdb_all:8;
 802         u4Byte                  cfosho_0:8;
 803         u4Byte                  cfosho_1:8;
 804         u4Byte                  cfosho_2:8;*/
 805         u8                      pwdb_all;
 806         u8                      cfosho[4];
 807
 808         //DWORD 2
 809         /*u4Byte                        cfosho_3:8;
 810         u4Byte                  cfotail_0:8;
 811         u4Byte                  cfotail_1:8;
 812         u4Byte                  cfotail_2:8;*/
 813         u8                      cfotail[4];
 814
 815         //DWORD 3
 816         /*u4Byte                        cfotail_3:8;
 817         u4Byte                  rxevm_0:8;
 818         u4Byte                  rxevm_1:8;
 819         u4Byte                  rxsnr_0:8;*/
 820         char                            rxevm[2];
 821         char                            rxsnr[4];
 822
 823         //DWORD 4
 824         /*u4Byte                        rxsnr_1:8;
 825         u4Byte                  rxsnr_2:8;
 826         u4Byte                  rxsnr_3:8;
 827         u4Byte                  pdsnr_0:8;*/
 828         u8                      pdsnr[2];
 829
 830         //DWORD 5
 831         /*u4Byte                        pdsnr_1:8;
 832         u4Byte                  csi_current_0:8;
 833         u4Byte                  csi_current_1:8;
 834         u4Byte                  csi_target_0:8;*/
 835         u8                      csi_current[2];
 836         u8                      csi_target[2];
 837
 838         //DWORD 6
 839         /*u4Byte                        csi_target_1:8;
 840         u4Byte                  sigevm:8;
 841         u4Byte                  max_ex_pwr:8;
 842         u4Byte                  ex_intf_flag:1;
 843         u4Byte                  sgi_en:1;
 844         u4Byte                  rxsc:2;
 845         u4Byte                  reserve:4;*/
 846         u8                      sigevm;
 847         u8                      max_ex_pwr;
 848         u8                      ex_intf_flag:1;
 849         u8                      sgi_en:1;
 850         u8                      rxsc:2;
 851         u8                      reserve:4;
 852
 853 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 854 #else
 855 typedef struct rx_drvinfo_819x_usb{
 856         //DWORD 0
 857         u16                 Reserved1:12;
 858         u16                 PartAggr:1;
 859         u16                 FirstAGGR:1;
 860         u16                 Reserved2:2;
 861
 862         u8                  RxRate:7;
 863         u8                  RxHT:1;
 864
 865         u8                  BW:1;
 866         u8                  SPLCP:1;
 867         u8                  Reserved3:2;
 868         u8                  PAM:1;
 869         u8                  Mcast:1;
 870         u8                  Bcast:1;
 871         u8                  Reserved4:1;
 872
 873         //DWORD 1
 874         u32                  TSFL;
 875
 876 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 877 #endif
 878
 879         #define HWSET_MAX_SIZE_92S      128
 880 #ifdef RTL8192SU
 881         #define MAX_802_11_HEADER_LENGTH 40
 882         #define MAX_PKT_AGG_NUM         256
 883         #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
 884 #else
 885         #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 886         #define MAX_PKT_AGG_NUM         64
 887         #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 888 #endif
 889
 890 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 891 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 892 //#define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 893 #define ENCRYPTION_MAX_OVERHEAD         128
 894 #define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 895 //#define TX_PACKET_SHIFT_BYTES                 (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 896 #define MAX_FRAGMENT_COUNT              8
 897 #ifdef RTL8192U
 898 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 899 #define MAX_TRANSMIT_BUFFER_SIZE                        32000
 900 #else
 901 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 902 #endif
 903 #else
 904 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 905 #endif
 906 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 907 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 908 #endif
 909 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 910
 911 typedef enum rf_optype
 912 {
 913         RF_OP_By_SW_3wire = 0,
 914         RF_OP_By_FW,
 915         RF_OP_MAX
 916 }rf_op_type;
 917 /* 8190 Loopback Mode definition */
 918 typedef enum _rtl819xUsb_loopback{
 919         RTL819xU_NO_LOOPBACK = 0,
 920         RTL819xU_MAC_LOOPBACK = 1,
 921         RTL819xU_DMA_LOOPBACK = 2,
 922         RTL819xU_CCK_LOOPBACK = 3,
 923 }rtl819xUsb_loopback_e;
 924
 925 /* for rtl819x */
 926 typedef enum _RT_STATUS{
 927         RT_STATUS_SUCCESS = 0,
 928         RT_STATUS_FAILURE = 1,
 929         RT_STATUS_PENDING = 2,
 930         RT_STATUS_RESOURCE = 3
 931 }RT_STATUS,*PRT_STATUS;
 932
 933 //#ifdef RTL8192SU
 934 typedef enum _RTL8192SUSB_LOOPBACK{
 935         RTL8192SU_NO_LOOPBACK = 0,
 936         RTL8192SU_MAC_LOOPBACK = 1,
 937         RTL8192SU_DMA_LOOPBACK = 2,
 938         RTL8192SU_CCK_LOOPBACK = 3,
 939 }RTL8192SUSB_LOOPBACK_E;
 940 //#endif
 941
 942
 943 #if 0
 944 /* due to rtl8192 firmware */
 945 typedef enum _desc_packet_type_e{
 946         DESC_PACKET_TYPE_INIT = 0,
 947         DESC_PACKET_TYPE_NORMAL = 1,
 948 }desc_packet_type_e;
 949
 950 typedef enum _firmware_source{
 951         FW_SOURCE_IMG_FILE = 0,
 952         FW_SOURCE_HEADER_FILE = 1,              //from header file
 953 }firmware_source_e, *pfirmware_source_e;
 954
 955 typedef enum _firmware_status{
 956         FW_STATUS_0_INIT = 0,
 957         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 958         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 959         FW_STATUS_3_TURNON_CPU = 3,
 960         FW_STATUS_4_MOVE_DATA_CODE = 4,
 961         FW_STATUS_5_READY = 5,
 962 }firmware_status_e;
 963
 964 typedef struct _rt_firmare_seg_container {
 965         u16     seg_size;
 966         u8      *seg_ptr;
 967 }fw_seg_container, *pfw_seg_container;
 968
 969 #ifdef RTL8192SU
 970 //--------------------------------------------------------------------------------
 971 // 8192S Firmware related
 972 //--------------------------------------------------------------------------------
 973 typedef  struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
 974
 975         //--- LONG WORD 0 ----
 976         u32             RegulatoryClass;
 977         u32             Rfintfs;
 978
 979         //--- LONG WORD 1 ----
 980         u32             ChipVer;
 981         u32             HCISel;
 982
 983         //--- LONG WORD 2 ----
 984         u32             IBKMode;
 985         u32             Rsvd00;
 986
 987         //--- LONG WORD 3 ----
 988         u32             Rsvd01;
 989         u8              Qos_En;                 // QoS enable
 990         u8              En40MHz;                // 40MHz BW enable
 991         u8              AMSDU2AMPDU_En; //14181 convert AMSDU to AMPDU, 0: disable
 992         u8              AMPDU_En;               //111n AMPDU/AMSDU enable
 993
 994         //--- LONG WORD 4 ----
 995         u8              rate_control_offload;//FW offloads, 0: driver handles
 996         u8              aggregation_offload;    // FW offloads, 0: driver handles
 997         u8              beacon_offload; //FW offloads, 0: driver handles
 998         u8              MLME_offload;   // FW offloads, 0: driver handles
 999         u8              hwpc_offload;   // FW offloads, 0: driver handles
1000         u8              tcp_checksum_offload;   //FW offloads, 0: driver handles
1001         u8              tcp_offload;                    //FW offloads, 0: driver handles
1002         u8              ps_control_offload;     //FW offloads, 0: driver handles
1003
1004         //--- LONG WORD 5 ----
1005         u8              WWLAN_Offload;  // FW offloads, 0: driver handles
1006         u8              MPMode; // normal mode, 0: MP mode;
1007         u16             Version;                //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
1008         u16             Signature;      //0x12: 8712, 0x92: 8192S
1009         u16             Rsvd11;
1010
1011 //      u32             rsvd1;
1012 //      u32             wireless_band;  //no A-band exists in 8712
1013 }RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
1014
1015 typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
1016
1017         //--- LONG WORD 0 ----
1018         u16             Signature;
1019         u16             Version;                  //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
1020         u32             DMEMSize;    //define the size of boot loader
1021
1022
1023         //--- LONG WORD 1 ----
1024         u32             IMG_IMEM_SIZE;    //define the size of FW in IMEM
1025         u32             IMG_SRAM_SIZE;    //define the size of FW in SRAM
1026
1027         //--- LONG WORD 2 ----
1028         u32             FW_PRIV_SIZE;       //define the size of DMEM variable
1029         u32             Rsvd0;
1030
1031         //--- LONG WORD 3 ----
1032         u32             Rsvd1;
1033         u32             Rsvd2;
1034
1035         RT_8192S_FIRMWARE_PRIV  FWPriv;
1036
1037 }RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
1038
1039 #define RT_8192S_FIRMWARE_HDR_SIZE      80
1040
1041 typedef enum _FIRMWARE_8192S_STATUS{
1042         FW_STATUS_INIT = 0,
1043         FW_STATUS_LOAD_IMEM = 1,
1044         FW_STATUS_LOAD_EMEM = 2,
1045         FW_STATUS_LOAD_DMEM = 3,
1046         FW_STATUS_READY = 4,
1047 }FIRMWARE_8192S_STATUS;
1048
1049 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
1050
1051 typedef struct _rt_firmware{
1052         firmware_source_e       eFWSource;
1053         PRT_8192S_FIRMWARE_HDR          pFwHeader;
1054         FIRMWARE_8192S_STATUS   FWStatus;
1055         u8              FwIMEM[64000];
1056         u8              FwEMEM[64000];
1057         u32             FwIMEMLen;
1058         u32             FwEMEMLen;
1059         u8              szFwTmpBuffer[164000];
1060         u16             CmdPacketFragThresold;
1061         //firmware_status_e       firmware_status;//in 92u temp FIXLZM
1062         //u16               cmdpacket_frag_thresold;//in 92u temp FIXLZM
1063         //u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];//in 92u temp FIXLZM
1064         //u16               firmware_buf_size;//in 92u temp FIXLZM
1065
1066 }rt_firmware, *prt_firmware;
1067 #else
1068 typedef struct _rt_firmware{
1069         firmware_status_e firmware_status;
1070         u16               cmdpacket_frag_thresold;
1071 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
1072 #define MAX_FW_INIT_STEP                3
1073         u8                firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
1074         u16               firmware_buf_size[MAX_FW_INIT_STEP];
1075 }rt_firmware, *prt_firmware;
1076 #endif
1077 typedef struct _rt_firmware_info_819xUsb{
1078         u8              sz_info[16];
1079 }rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
1080 #endif
1081
1082 //+by amy 080507
1083 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
1084
1085
1086 /* Firmware Queue Layout */
1087 #define NUM_OF_FIRMWARE_QUEUE           10
1088 #define NUM_OF_PAGES_IN_FW              0x100
1089
1090 #ifdef USE_ONE_PIPE
1091 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
1092 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
1093 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
1094 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
1095 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
1096 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
1097 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
1098 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
1099 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
1100 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
1101 #else
1102
1103 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
1104 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
1105 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
1106 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
1107 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
1108 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
1109 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
1110 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
1111 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
1112 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
1113
1114 #endif
1115
1116 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
1117 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
1118 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
1119 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
1120 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
1121 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
1122 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
1123 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
1124 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
1125 //=================================================================
1126 //=================================================================
1127
1128 #define EPROM_93c46 0
1129 #define EPROM_93c56 1
1130
1131 #define DEFAULT_FRAG_THRESHOLD 2342U
1132 #define MIN_FRAG_THRESHOLD     256U
1133 #define DEFAULT_BEACONINTERVAL 0x64U
1134 #define DEFAULT_BEACON_ESSID "Rtl819xU"
1135
1136 #define DEFAULT_SSID ""
1137 #define DEFAULT_RETRY_RTS 7
1138 #define DEFAULT_RETRY_DATA 7
1139 #define PRISM_HDR_SIZE 64
1140
1141 #define         PHY_RSSI_SLID_WIN_MAX                           100
1142
1143
1144 typedef enum _WIRELESS_MODE {
1145         WIRELESS_MODE_UNKNOWN = 0x00,
1146         WIRELESS_MODE_A = 0x01,
1147         WIRELESS_MODE_B = 0x02,
1148         WIRELESS_MODE_G = 0x04,
1149         WIRELESS_MODE_AUTO = 0x08,
1150         WIRELESS_MODE_N_24G = 0x10,
1151         WIRELESS_MODE_N_5G = 0x20
1152 } WIRELESS_MODE;
1153
1154
1155 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
1156
1157 typedef struct buffer
1158 {
1159         struct buffer *next;
1160         u32 *buf;
1161
1162 } buffer;
1163
1164 typedef struct rtl_reg_debug{
1165         unsigned int  cmd;
1166         struct {
1167                 unsigned char type;
1168                 unsigned char addr;
1169                 unsigned char page;
1170                 unsigned char length;
1171         } head;
1172         unsigned char buf[0xff];
1173 }rtl_reg_debug;
1174
1175
1176
1177
1178
1179 #if 0
1180
1181 typedef struct tx_pendingbuf
1182 {
1183         struct ieee80211_txb *txb;
1184         short ispending;
1185         short descfrag;
1186 } tx_pendigbuf;
1187
1188 #endif
1189
1190 typedef struct _rt_9x_tx_rate_history {
1191         u32             cck[4];
1192         u32             ofdm[8];
1193         // HT_MCS[0][]: BW=0 SG=0
1194         // HT_MCS[1][]: BW=1 SG=0
1195         // HT_MCS[2][]: BW=0 SG=1
1196         // HT_MCS[3][]: BW=1 SG=1
1197         u32             ht_mcs[4][16];
1198 }rt_tx_rahis_t, *prt_tx_rahis_t;
1199 typedef struct _RT_SMOOTH_DATA_4RF {
1200         char    elements[4][100];//array to store values
1201         u32     index;                  //index to current array to store
1202         u32     TotalNum;               //num of valid elements
1203         u32     TotalVal[4];            //sum of valid elements
1204 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
1205
1206 #define MAX_8192U_RX_SIZE                       8192    // This maybe changed for D-cut larger aggregation size
1207 //stats seems messed up, clean it ASAP
1208 typedef struct Stats
1209 {
1210         unsigned long txrdu;
1211 //      unsigned long rxrdu;
1212         //unsigned long rxnolast;
1213         //unsigned long rxnodata;
1214 //      unsigned long rxreset;
1215 //      unsigned long rxnopointer;
1216         unsigned long rxok;
1217         unsigned long rxframgment;
1218         unsigned long rxcmdpkt[4];              //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
1219         unsigned long rxurberr;
1220         unsigned long rxstaterr;
1221         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
1222         unsigned long received_preamble_GI[2][32];              //0: Long preamble/GI, 1:Short preamble/GI
1223         unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
1224         unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
1225         unsigned long numpacket_matchbssid;     // debug use only.
1226         unsigned long numpacket_toself;         // debug use only.
1227         unsigned long num_process_phyinfo;              // debug use only.
1228         unsigned long numqry_phystatus;
1229         unsigned long numqry_phystatusCCK;
1230         unsigned long numqry_phystatusHT;
1231         unsigned long received_bwtype[5];              //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
1232         unsigned long txnperr;
1233         unsigned long txnpdrop;
1234         unsigned long txresumed;
1235 //      unsigned long rxerr;
1236 //      unsigned long rxoverflow;
1237 //      unsigned long rxint;
1238         unsigned long txnpokint;
1239 //      unsigned long txhpokint;
1240 //      unsigned long txhperr;
1241 //      unsigned long ints;
1242 //      unsigned long shints;
1243         unsigned long txoverflow;
1244 //      unsigned long rxdmafail;
1245 //      unsigned long txbeacon;
1246 //      unsigned long txbeaconerr;
1247         unsigned long txlpokint;
1248         unsigned long txlpdrop;
1249         unsigned long txlperr;
1250         unsigned long txbeokint;
1251         unsigned long txbedrop;
1252         unsigned long txbeerr;
1253         unsigned long txbkokint;
1254         unsigned long txbkdrop;
1255         unsigned long txbkerr;
1256         unsigned long txviokint;
1257         unsigned long txvidrop;
1258         unsigned long txvierr;
1259         unsigned long txvookint;
1260         unsigned long txvodrop;
1261         unsigned long txvoerr;
1262         unsigned long txbeaconokint;
1263         unsigned long txbeacondrop;
1264         unsigned long txbeaconerr;
1265         unsigned long txmanageokint;
1266         unsigned long txmanagedrop;
1267         unsigned long txmanageerr;
1268         unsigned long txdatapkt;
1269         unsigned long txfeedback;
1270         unsigned long txfeedbackok;
1271
1272         unsigned long txoktotal;
1273         unsigned long txokbytestotal;
1274         unsigned long txokinperiod;
1275         unsigned long txmulticast;
1276         unsigned long txbytesmulticast;
1277         unsigned long txbroadcast;
1278         unsigned long txbytesbroadcast;
1279         unsigned long txunicast;
1280         unsigned long txbytesunicast;
1281
1282         unsigned long rxoktotal;
1283         unsigned long rxbytesunicast;
1284         unsigned long txfeedbackfail;
1285         unsigned long txerrtotal;
1286         unsigned long txerrbytestotal;
1287         unsigned long txerrmulticast;
1288         unsigned long txerrbroadcast;
1289         unsigned long txerrunicast;
1290         unsigned long txretrycount;
1291         unsigned long txfeedbackretry;
1292         u8            last_packet_rate;
1293         unsigned long slide_signal_strength[100];
1294         unsigned long slide_evm[100];
1295         unsigned long slide_rssi_total; // For recording sliding window's RSSI value
1296         unsigned long slide_evm_total;  // For recording sliding window's EVM value
1297         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
1298         long signal_quality;
1299         long last_signal_strength_inpercent;
1300         long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
1301         u8 rx_rssi_percentage[4];
1302         u8 rx_evm_percentage[2];
1303         long rxSNRdB[4];
1304         rt_tx_rahis_t txrate;
1305         u32 Slide_Beacon_pwdb[100];     //cosa add for beacon rssi
1306         u32 Slide_Beacon_Total;         //cosa add for beacon rssi
1307         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
1308
1309         u32     CurrentShowTxate;
1310 } Stats;
1311
1312
1313 // Bandwidth Offset
1314 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
1315 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
1316 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
1317
1318 //+by amy 080507
1319
1320 typedef struct  ChnlAccessSetting {
1321         u16 SIFS_Timer;
1322         u16 DIFS_Timer;
1323         u16 SlotTimeTimer;
1324         u16 EIFS_Timer;
1325         u16 CWminIndex;
1326         u16 CWmaxIndex;
1327 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
1328
1329 typedef struct _BB_REGISTER_DEFINITION{
1330         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
1331         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
1332         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
1333         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
1334         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
1335         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
1336         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
1337         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
1338         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
1339         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
1340         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
1341         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
1342         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
1343         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
1344         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
1345         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
1346         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
1347         u32 rfLSSIReadBackPi;   //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
1348 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
1349
1350 typedef enum _RT_RF_TYPE_819xU{
1351         RF_TYPE_MIN = 0,
1352         RF_8225,
1353         RF_8256,
1354         RF_8258,
1355         RF_6052=4,              // 4 11b/g/n RF
1356         RF_PSEUDO_11N = 5,
1357 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
1358
1359 //#ifdef RTL8192SU
1360 typedef enum _RF_POWER_STATE{
1361         RF_ON,
1362         RF_SLEEP,
1363         RF_OFF,
1364         RF_SHUT_DOWN,
1365 }RF_POWER_STATE, *PRF_POWER_STATE;
1366 //#endif
1367
1368 typedef struct _rate_adaptive
1369 {
1370         u8                              rate_adaptive_disabled;
1371         u8                              ratr_state;
1372         u16                             reserve;
1373
1374         u32                             high_rssi_thresh_for_ra;
1375         u32                             high2low_rssi_thresh_for_ra;
1376         u8                              low2high_rssi_thresh_for_ra40M;
1377         u32                             low_rssi_thresh_for_ra40M;
1378         u8                              low2high_rssi_thresh_for_ra20M;
1379         u32                             low_rssi_thresh_for_ra20M;
1380         u32                             upper_rssi_threshold_ratr;
1381         u32                             middle_rssi_threshold_ratr;
1382         u32                             low_rssi_threshold_ratr;
1383         u32                             low_rssi_threshold_ratr_40M;
1384         u32                             low_rssi_threshold_ratr_20M;
1385         u8                              ping_rssi_enable;       //cosa add for test
1386         u32                             ping_rssi_ratr; //cosa add for test
1387         u32                             ping_rssi_thresh_for_ra;//cosa add for test
1388         u32                             last_ratr;
1389
1390 } rate_adaptive, *prate_adaptive;
1391
1392 #define TxBBGainTableLength 37
1393 #define CCKTxBBGainTableLength 23
1394
1395 typedef struct _txbbgain_struct
1396 {
1397         long    txbb_iq_amplifygain;
1398         u32     txbbgain_value;
1399 } txbbgain_struct, *ptxbbgain_struct;
1400
1401 typedef struct _ccktxbbgain_struct
1402 {
1403         //The Value is from a22 to a29 one Byte one time is much Safer
1404         u8      ccktxbb_valuearray[8];
1405 } ccktxbbgain_struct,*pccktxbbgain_struct;
1406
1407
1408 typedef struct _init_gain
1409 {
1410         u8                              xaagccore1;
1411         u8                              xbagccore1;
1412         u8                              xcagccore1;
1413         u8                              xdagccore1;
1414         u8                              cca;
1415
1416 } init_gain, *pinit_gain;
1417 //by amy 0606
1418
1419 typedef struct _phy_ofdm_rx_status_report_819xusb
1420 {
1421         u8      trsw_gain_X[4];
1422         u8      pwdb_all;
1423         u8      cfosho_X[4];
1424         u8      cfotail_X[4];
1425         u8      rxevm_X[2];
1426         u8      rxsnr_X[4];
1427         u8      pdsnr_X[2];
1428         u8      csi_current_X[2];
1429         u8      csi_target_X[2];
1430         u8      sigevm;
1431         u8      max_ex_pwr;
1432         u8      sgi_en;
1433         u8  rxsc_sgien_exflg;
1434 }phy_sts_ofdm_819xusb_t;
1435
1436 typedef struct _phy_cck_rx_status_report_819xusb
1437 {
1438         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
1439            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
1440         u8      adc_pwdb_X[4];
1441         u8      sq_rpt;
1442         u8      cck_agc_rpt;
1443 }phy_sts_cck_819xusb_t;
1444
1445
1446 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
1447         u8                      reserved:4;
1448         u8                      rxsc:2;
1449         u8                      sgi_en:1;
1450         u8                      ex_intf_flag:1;
1451 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
1452
1453 typedef enum _RT_CUSTOMER_ID
1454 {
1455         RT_CID_DEFAULT = 0,
1456         RT_CID_8187_ALPHA0 = 1,
1457         RT_CID_8187_SERCOMM_PS = 2,
1458         RT_CID_8187_HW_LED = 3,
1459         RT_CID_8187_NETGEAR = 4,
1460         RT_CID_WHQL = 5,
1461         RT_CID_819x_CAMEO  = 6,
1462         RT_CID_819x_RUNTOP = 7,
1463         RT_CID_819x_Senao = 8,
1464         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
1465         RT_CID_819x_Netcore = 10,
1466         RT_CID_Nettronix = 11,
1467         RT_CID_DLINK = 12,
1468         RT_CID_PRONET = 13,
1469 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
1470
1471 //================================================================================
1472 // LED customization.
1473 //================================================================================
1474
1475 typedef enum _LED_STRATEGY_8190{
1476         SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
1477         SW_LED_MODE1, // SW control for PCI Express
1478         SW_LED_MODE2, // SW control for Cameo.
1479         SW_LED_MODE3, // SW contorl for RunTop.
1480         SW_LED_MODE4, // SW control for Netcore
1481         HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
1482 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
1483
1484 typedef enum _RESET_TYPE {
1485         RESET_TYPE_NORESET = 0x00,
1486         RESET_TYPE_NORMAL = 0x01,
1487         RESET_TYPE_SILENT = 0x02
1488 } RESET_TYPE;
1489
1490 /* The simple tx command OP code. */
1491 typedef enum _tag_TxCmd_Config_Index{
1492         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
1493         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
1494         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
1495         TXCMD_SET_TX_DURATION                           = 0xFF900003,
1496         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
1497         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
1498         TXCMD_XXXX_CTRL,
1499 }DCMD_TXCMD_OP;
1500
1501 typedef enum{
1502         NIC_8192U = 1,
1503         NIC_8190P = 2,
1504         NIC_8192E = 3,
1505         NIC_8192SE = 4,
1506         NIC_8192SU = 5,
1507         } nic_t;
1508
1509 //definded by WB. Ready to fill handlers for different NIC types.
1510 //add handle here when necessary.
1511 struct rtl819x_ops{
1512         nic_t nic_type;
1513         void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1514         short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1515         short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1516         void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1517         void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1518         bool (* rtl819x_adapter_start)(struct net_device *dev);
1519         void (* rtl819x_link_change)(struct net_device *dev);
1520         void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1521         void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1522 };
1523
1524 typedef struct r8192_priv
1525 {
1526         struct rtl819x_ops* ops;
1527         struct usb_device *udev;
1528         //added for maintain info from eeprom
1529         short epromtype;
1530         u16 eeprom_vid;
1531         u16 eeprom_pid;
1532         u8  eeprom_CustomerID;
1533         u8  eeprom_SubCustomerID;
1534         u8  eeprom_ChannelPlan;
1535         RT_CUSTOMER_ID CustomerID;
1536         LED_STRATEGY_8190       LedStrategy;
1537         u8  txqueue_to_outpipemap[9];
1538         u8  RtOutPipes[16];
1539         u8  RtInPipes[16];
1540         u8  ep_in_num;
1541         u8  ep_out_num;
1542         u8  ep_num;
1543         int irq;
1544         struct ieee80211_device *ieee80211;
1545
1546         short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1547         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1548 //      short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1549         short enable_gpio0;
1550         enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1551         short hw_plcp_len;
1552         short plcp_preamble_mode;
1553
1554         spinlock_t irq_lock;
1555 //      spinlock_t irq_th_lock;
1556         spinlock_t tx_lock;
1557         spinlock_t ps_lock;
1558 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
1559         struct semaphore mutex;
1560 #else
1561         struct mutex mutex;
1562 #endif
1563         spinlock_t rf_lock; //used to lock rf write operation added by wb
1564
1565         u16 irq_mask;
1566 //      short irq_enabled;
1567 //      struct net_device *dev; //comment this out.
1568         short chan;
1569         short sens;
1570         short max_sens;
1571
1572
1573         //      u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1574 //      u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1575 //      u8 cck_txpwr_base;
1576 //      u8 ofdm_txpwr_base;
1577 //      u8 challow[15]; //channels from 1 to 14, 0 not used
1578         short up;
1579         short crcmon; //if 1 allow bad crc frame reception in monitor mode
1580 //      short prism_hdr;
1581
1582 //      struct timer_list scan_timer;
1583         /*short scanpending;
1584         short stopscan;*/
1585 //      spinlock_t scan_lock;
1586 //      u8 active_probe;
1587         //u8 active_scan_num;
1588         struct semaphore wx_sem;
1589         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1590 //      short hw_wep;
1591
1592 //      short digphy;
1593 //      short antb;
1594 //      short diversity;
1595 //      u8 cs_treshold;
1596 //      short rcr_csense;
1597         u8 rf_type; //0 means 1T2R, 1 means 2T4R
1598         RT_RF_TYPE_819xU rf_chip;
1599
1600 //      u32 key0[4];
1601         short (*rf_set_sens)(struct net_device *dev,short sens);
1602         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1603         void (*rf_close)(struct net_device *dev);
1604         void (*rf_init)(struct net_device *dev);
1605         //short rate;
1606         short promisc;
1607         /*stats*/
1608         struct Stats stats;
1609         struct iw_statistics wstats;
1610         struct proc_dir_entry *dir_dev;
1611
1612         /*RX stuff*/
1613 //      u32 *rxring;
1614 //      u32 *rxringtail;
1615 //      dma_addr_t rxringdma;
1616         struct urb **rx_urb;
1617         struct urb **rx_cmd_urb;
1618
1619 /* modified by davad for Rx process */
1620        struct sk_buff_head rx_queue;
1621        struct sk_buff_head skb_queue;
1622 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
1623         struct tq_struct qos_activate;
1624 #else
1625        struct work_struct qos_activate;
1626 #endif
1627         short  tx_urb_index;
1628         atomic_t tx_pending[0x10];//UART_PRIORITY+1
1629
1630
1631         struct tasklet_struct irq_rx_tasklet;
1632         struct urb *rxurb_task;
1633
1634         //2 Tx Related variables
1635         u16     ShortRetryLimit;
1636         u16     LongRetryLimit;
1637         u32     TransmitConfig;
1638         u8      RegCWinMin;             // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1639
1640         u32     LastRxDescTSFHigh;
1641         u32     LastRxDescTSFLow;
1642
1643
1644         //2 Rx Related variables
1645         u16     EarlyRxThreshold;
1646         u32     ReceiveConfig;
1647         u8      AcmControl;
1648
1649         u8      RFProgType;
1650
1651         u8 retry_data;
1652         u8 retry_rts;
1653         u16 rts;
1654
1655         struct  ChnlAccessSetting  ChannelAccessSetting;
1656 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1657         struct work_struct reset_wq;
1658 #else
1659         struct tq_struct reset_wq;
1660 #endif
1661
1662 /**********************************************************/
1663         //for rtl819xUsb
1664         u16     basic_rate;
1665         u8      short_preamble;
1666         u8      slot_time;
1667         bool    bDcut;
1668         bool bCurrentRxAggrEnable;
1669         u8 Rf_Mode; //add for Firmware RF -R/W switch
1670         prt_firmware            pFirmware;
1671         rtl819xUsb_loopback_e   LoopbackMode;
1672         firmware_source_e       firmware_source;
1673         bool usb_error;
1674
1675         u16 EEPROMTxPowerDiff;
1676         u8 EEPROMThermalMeter;
1677         u8 EEPROMPwDiff;
1678         u8 EEPROMCrystalCap;
1679         u8 EEPROM_Def_Ver;
1680         u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1681         u8 EEPROMTxPowerLevelCCK_V1[3];
1682         u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1683         u8 EEPROMTxPowerLevelOFDM5G[24];        // OFDM 5G
1684
1685 //RTL8192SU
1686         bool    bDmDisableProtect;
1687         bool    bIgnoreDiffRateTxPowerOffset;
1688
1689 #ifdef EEPROM_OLD_FORMAT_SUPPORT
1690         u8  EEPROMTxPowerLevelCCK24G[14];               // CCK 2.4G channel 1~14
1691         //u8  EEPROMTxPowerLevelOFDM24G[14];    // OFDM 2.4G channel 1~14
1692         //u8  EEPROMTxPowerLevelOFDM5G[24];     // OFDM 5G
1693 #else
1694         // For EEPROM TX Power Index like 8190 series
1695         u8  EEPROMRfACCKChnl1TxPwLevel[3];      //RF-A CCK Tx Power Level at channel 7
1696         u8  EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1697         u8  EEPROMRfCCCKChnl1TxPwLevel[3];      //RF-C CCK Tx Power Level at channel 7
1698         u8  EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1699
1700         // F92S new definition
1701         //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1702         u8  RfCckChnlAreaTxPwr[2][3];
1703         u8  RfOfdmChnlAreaTxPwr1T[2][3];
1704         u8  RfOfdmChnlAreaTxPwr2T[2][3];
1705 #endif
1706
1707         // Add For EEPROM Efuse switch and  Efuse Shadow map Setting
1708         bool            EepromOrEfuse;
1709         bool            bBootFromEfuse; // system boot form EFUSE
1710         u8              EfuseMap[2][HWSET_MAX_SIZE_92S];
1711
1712         u8              EEPROMUsbOption;
1713         u8              EEPROMUsbPhyParam[5];
1714         u8              EEPROMTxPwrBase;
1715         u8              EEPROMBoardType;
1716         bool            bBootFromEEPROM;   // system boot from EEPROM
1717         u8              EEPROMTSSI_A;
1718         u8              EEPROMTSSI_B;
1719         u8              EEPROMHT2T_TxPwr[6];                    // For channel 1, 7 and 13 on path A/B.
1720         u8              EEPROMTxPwrTkMode;
1721
1722         u8              bTXPowerDataReadFromEEPORM;
1723
1724         u8              EEPROMVersion;
1725         u8              EEPROMUsbEndPointNumber;
1726
1727         bool            AutoloadFailFlag;
1728         u8      RfTxPwrLevelCck[2][14];
1729         u8      RfTxPwrLevelOfdm1T[2][14];
1730         u8      RfTxPwrLevelOfdm2T[2][14];
1731         // 2009/01/20 MH Add for new EEPROM format.
1732         u8                                      TxPwrHt20Diff[2][14];                           // HT 20<->40 Pwr diff
1733         u8                                      TxPwrLegacyHtDiff[2][14];               // For HT<->legacy pwr diff
1734         u8                                      TxPwrbandEdgeHt40[2][2];                // Band edge for HY 40MHZlow/up channel
1735         u8                                      TxPwrbandEdgeHt20[2][2];                // Band edge for HY 40MHZ low/up channel
1736         u8                                      TxPwrbandEdgeLegacyOfdm[2][2];  // Band edge for legacy ofdm low/up channel
1737         u8                                      TxPwrbandEdgeFlag;                              // Band edge enable flag
1738
1739         // L1 and L2 high power threshold.
1740         u8                              MidHighPwrTHR_L1;
1741         u8                              MidHighPwrTHR_L2;
1742         u8                              TxPwrSafetyFlag;                                // for Tx power safety spec
1743 //RTL8192SU
1744
1745 /*PHY related*/
1746         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
1747         // Read/write are allow for following hardware information variables
1748 #ifdef RTL8192SU
1749         u32     MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1750 #else
1751         u32     MCSTxPowerLevelOriginalOffset[6];
1752 #endif
1753         u32     CCKTxPowerLevelOriginalOffset;
1754         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
1755         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
1756         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
1757         u32     Pwr_Track;
1758         u8      TxPowerDiff;
1759         u8      AntennaTxPwDiff[2];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1760         u8      CrystalCap;                                             // CrystalCap.
1761         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1762
1763         u8      CckPwEnl;
1764         // Use to calculate PWBD.
1765         u8      bCckHighPower;
1766         long    undecorated_smoothed_pwdb;
1767
1768         //for set channel
1769         u8      SwChnlInProgress;
1770         u8      SwChnlStage;
1771         u8      SwChnlStep;
1772         u8      SetBWModeInProgress;
1773         HT_CHANNEL_WIDTH                CurrentChannelBW;
1774         u8      ChannelPlan;
1775         u8      pwrGroupCnt;
1776         // 8190 40MHz mode
1777         //
1778         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
1779         // Joseph test for shorten RF configuration time.
1780         // We save RF reg0 in this variable to reduce RF reading.
1781         //
1782         u32                                     RfReg0Value[4];
1783         u8                                      NumTotalRFPath;
1784         bool                            brfpath_rxenable[4];
1785         //RF set related
1786         bool                            SetRFPowerStateInProgress;
1787 //+by amy 080507
1788         struct timer_list watch_dog_timer;
1789
1790 //+by amy 080515 for dynamic mechenism
1791         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1792         bool    bdynamic_txpower;  //bDynamicTxPower
1793         bool    bDynamicTxHighPower;  // Tx high power state
1794         bool    bDynamicTxLowPower;  // Tx low power state
1795         bool    bLastDTPFlag_High;
1796         bool    bLastDTPFlag_Low;
1797
1798         bool    bstore_last_dtpflag;
1799         bool    bstart_txctrl_bydtp;   //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1800         //Add by amy for Rate Adaptive
1801         rate_adaptive rate_adaptive;
1802         //Add by amy for TX power tracking
1803         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
1804        txbbgain_struct txbbgain_table[TxBBGainTableLength];
1805        u8       EEPROMTxPowerTrackEnable;
1806         u8                         txpower_count;//For 6 sec do tracking again
1807         bool                       btxpower_trackingInit;
1808         u8                         OFDM_index;
1809         u8                         CCK_index;
1810         //2007/09/10 Mars Add CCK TX Power Tracking
1811         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1812         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1813         u8 rfa_txpowertrackingindex;
1814         u8 rfa_txpowertrackingindex_real;
1815         u8 rfa_txpowertracking_default;
1816         u8 rfc_txpowertrackingindex;
1817         u8 rfc_txpowertrackingindex_real;
1818
1819         s8 cck_present_attentuation;
1820         u8 cck_present_attentuation_20Mdefault;
1821         u8 cck_present_attentuation_40Mdefault;
1822         char cck_present_attentuation_difference;
1823         bool btxpower_tracking;
1824         bool bcck_in_ch14;
1825         bool btxpowerdata_readfromEEPORM;
1826         u16     TSSI_13dBm;
1827         //For Backup Initial Gain
1828         init_gain initgain_backup;
1829         u8 DefaultInitialGain[4];
1830         // For EDCA Turbo mode, Added by amy 080515.
1831         bool            bis_any_nonbepkts;
1832         bool            bcurrent_turbo_EDCA;
1833         bool            bis_cur_rdlstate;
1834         struct timer_list fsync_timer;
1835         bool bfsync_processing; // 500ms Fsync timer is active or not
1836         u32     rate_record;
1837         u32     rateCountDiffRecord;
1838         u32     ContiuneDiffCount;
1839         bool bswitch_fsync;
1840
1841         u8      framesync;
1842         u32     framesyncC34;
1843         u8      framesyncMonitor;
1844                 //Added by amy 080516  for RX related
1845         u16     nrxAMPDU_size;
1846         u8      nrxAMPDU_aggr_num;
1847
1848         //by amy for gpio
1849          bool bHwRadioOff;
1850
1851         //by amy for reset_count
1852         u32 reset_count;
1853         bool bpbc_pressed;
1854         //by amy for debug
1855         u32 txpower_checkcnt;
1856         u32 txpower_tracking_callback_cnt;
1857         u8 thermal_read_val[40];
1858         u8 thermal_readback_index;
1859         u32 ccktxpower_adjustcnt_not_ch14;
1860         u32 ccktxpower_adjustcnt_ch14;
1861         u8 tx_fwinfo_force_subcarriermode;
1862         u8 tx_fwinfo_force_subcarrierval;
1863         //by amy for silent reset
1864         RESET_TYPE      ResetProgress;
1865         bool            bForcedSilentReset;
1866         bool            bDisableNormalResetCheck;
1867         u16             TxCounter;
1868         u16             RxCounter;
1869         int             IrpPendingCount;
1870         bool            bResetInProgress;
1871         bool            force_reset;
1872         u8              InitialGainOperateType;
1873
1874         u16             SifsTime;
1875
1876         //define work item by amy 080526
1877 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1878
1879 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1880         struct delayed_work update_beacon_wq;
1881         struct delayed_work watch_dog_wq;
1882         struct delayed_work txpower_tracking_wq;
1883         struct delayed_work rfpath_check_wq;
1884         struct delayed_work gpio_change_rf_wq;
1885         struct delayed_work initialgain_operate_wq;
1886 #else
1887         struct work_struct update_beacon_wq;
1888         struct work_struct watch_dog_wq;
1889         struct work_struct txpower_tracking_wq;
1890         struct work_struct rfpath_check_wq;
1891         struct work_struct gpio_change_rf_wq;
1892         struct work_struct initialgain_operate_wq;
1893 #endif
1894         struct workqueue_struct *priv_wq;
1895 #else
1896         /* used for periodly scan */
1897         struct tq_struct update_beacon_wq;
1898         struct tq_struct txpower_tracking_wq;
1899         struct tq_struct rfpath_check_wq;
1900         struct tq_struct watch_dog_wq;
1901         struct tq_struct gpio_change_rf_wq;
1902         struct tq_struct initialgain_operate_wq;
1903 #endif
1904 //#ifdef RTL8192SU
1905         //lzm add for 8192S
1906          u32                    IntrMask;
1907         // RF and BB access related synchronization flags.
1908         bool                            bChangeBBInProgress; // BaseBand RW is still in progress.
1909         bool                            bChangeRFInProgress; // RF RW is still in progress.
1910
1911         u32                             CCKTxPowerAdjustCntCh14;                //debug only
1912         u32                             CCKTxPowerAdjustCntNotCh14;     //debug only
1913         u32                             TXPowerTrackingCallbackCnt;             //debug only
1914         u32                             TxPowerCheckCnt;                                //debug only
1915         u32                             RFWritePageCnt[3];                              //debug only
1916         u32                             RFReadPageCnt[3];                               //debug only
1917         u8                              ThermalReadBackIndex;                   //debug only
1918         u8                              ThermalReadVal[40];                             //debug only
1919
1920         // For HCT test, 2005.07.15, by rcnjko.
1921         // not realize true, just define it, set it 0 default, because some func use it
1922         bool                            bInHctTest;
1923
1924         // The current Tx Power Level
1925         u8                              CurrentCckTxPwrIdx;
1926         u8                              CurrentOfdm24GTxPwrIdx;
1927
1928         // For pass 92S common phycfg.c compiler
1929         u8                                      TxPowerLevelCCK_A[14];                  // RF-A, CCK channel 1~14
1930         u8                                      TxPowerLevelOFDM24G_A[14];      // RF-A, OFDM 2.4G channel 1~14
1931         u8                                      TxPowerLevelCCK_C[14];                  // RF-C, CCK channel 1~14
1932         u8                                      TxPowerLevelOFDM24G_C[14];      // RF-C, OFDM 2.4G channel 1~14
1933         u8                                      LegacyHTTxPowerDiff;                    // Legacy to HT rate power diff
1934         char                                    RF_C_TxPwDiff;                                  // Antenna gain offset, rf-c to rf-a
1935
1936         bool    bRFSiOrPi;//0=si, 1=pi.
1937         //lzm add for 8192S
1938
1939         bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1940         u8 CurrentFwCmdIO;
1941
1942         u8 MinSpaceCfg;
1943
1944         u16 rf_pathmap;
1945 //#endif
1946
1947
1948 #ifdef USB_RX_AGGREGATION_SUPPORT
1949         bool            bCurrentRxAggrEnable;
1950         bool            bForcedUsbRxAggr;
1951         u32             ForcedUsbRxAggrInfo;
1952         u32             LastUsbRxAggrInfoSetting;
1953         u32             RegUsbRxAggrInfo;
1954 #endif
1955
1956
1957
1958 }r8192_priv;
1959
1960 // for rtl8187
1961 // now mirging to rtl8187B
1962 /*
1963 typedef enum{
1964         LOW_PRIORITY = 0x02,
1965         NORM_PRIORITY
1966         } priority_t;
1967 */
1968 //for rtl8187B
1969 typedef enum{
1970         BULK_PRIORITY = 0x01,
1971         //RSVD0,
1972         //RSVD1,
1973         LOW_PRIORITY,
1974         NORM_PRIORITY,
1975         VO_PRIORITY,
1976         VI_PRIORITY, //0x05
1977         BE_PRIORITY,
1978         BK_PRIORITY,
1979         RSVD2,
1980         RSVD3,
1981         BEACON_PRIORITY, //0x0A
1982         HIGH_PRIORITY,
1983         MANAGE_PRIORITY,
1984         RSVD4,
1985         RSVD5,
1986         UART_PRIORITY //0x0F
1987 } priority_t;
1988
1989 #if 0
1990 typedef enum{
1991         NIC_8192U = 1,
1992         NIC_8190P = 2,
1993         NIC_8192E = 3,
1994         NIC_8192SE = 4,
1995         NIC_8192SU = 5,
1996         } nic_t;
1997 #endif
1998
1999 #if 0 //defined in Qos.h
2000 //typedef u32 AC_CODING;
2001 #define AC0_BE  0               // ACI: 0x00    // Best Effort
2002 #define AC1_BK  1               // ACI: 0x01    // Background
2003 #define AC2_VI  2               // ACI: 0x10    // Video
2004 #define AC3_VO  3               // ACI: 0x11    // Voice
2005 #define AC_MAX  4               // Max: define total number; Should not to be used as a real enum.
2006
2007 //
2008 // ECWmin/ECWmax field.
2009 // Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
2010 //
2011 typedef union _ECW{
2012         u8      charData;
2013         struct
2014         {
2015                 u8      ECWmin:4;
2016                 u8      ECWmax:4;
2017         }f;     // Field
2018 }ECW, *PECW;
2019
2020 //
2021 // ACI/AIFSN Field.
2022 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
2023 //
2024 typedef union _ACI_AIFSN{
2025         u8      charData;
2026
2027         struct
2028         {
2029                 u8      AIFSN:4;
2030                 u8      ACM:1;
2031                 u8      ACI:2;
2032                 u8      Reserved:1;
2033         }f;     // Field
2034 }ACI_AIFSN, *PACI_AIFSN;
2035
2036 //
2037 // AC Parameters Record Format.
2038 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
2039 //
2040 typedef union _AC_PARAM{
2041         u32     longData;
2042         u8      charData[4];
2043
2044         struct
2045         {
2046                 ACI_AIFSN       AciAifsn;
2047                 ECW             Ecw;
2048                 u16             TXOPLimit;
2049         }f;     // Field
2050 }AC_PARAM, *PAC_PARAM;
2051
2052 #endif
2053 #ifdef JOHN_HWSEC
2054 struct ssid_thread {
2055         struct net_device *dev;
2056         u8 name[IW_ESSID_MAX_SIZE + 1];
2057 };
2058 #endif
2059
2060 #ifdef RTL8192SU
2061 short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
2062 short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
2063 bool FirmwareDownload92S(struct net_device *dev);
2064 #else
2065 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
2066 bool init_firmware(struct net_device *dev);
2067 #endif
2068
2069 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
2070 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
2071
2072 u32 read_cam(struct net_device *dev, u8 addr);
2073 void write_cam(struct net_device *dev, u8 addr, u32 data);
2074
2075 u8 read_nic_byte(struct net_device *dev, int x);
2076 u8 read_nic_byte_E(struct net_device *dev, int x);
2077 u32 read_nic_dword(struct net_device *dev, int x);
2078 u16 read_nic_word(struct net_device *dev, int x) ;
2079 void write_nic_byte(struct net_device *dev, int x,u8 y);
2080 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
2081 void write_nic_word(struct net_device *dev, int x,u16 y);
2082 void write_nic_dword(struct net_device *dev, int x,u32 y);
2083 void force_pci_posting(struct net_device *dev);
2084
2085 void rtl8192_rtx_disable(struct net_device *);
2086 void rtl8192_rx_enable(struct net_device *);
2087 void rtl8192_tx_enable(struct net_device *);
2088
2089 void rtl8192_disassociate(struct net_device *dev);
2090 //void fix_rx_fifo(struct net_device *dev);
2091 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
2092
2093 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
2094 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
2095 void rtl8192_update_msr(struct net_device *dev);
2096 int rtl8192_down(struct net_device *dev);
2097 int rtl8192_up(struct net_device *dev);
2098 void rtl8192_commit(struct net_device *dev);
2099 void rtl8192_set_chan(struct net_device *dev,short ch);
2100 void write_phy(struct net_device *dev, u8 adr, u8 data);
2101 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
2102 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
2103 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
2104 void rtl8192_set_rxconf(struct net_device *dev);
2105 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
2106 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16  tx_rate);
2107 void CamResetAllEntry(struct net_device* dev);
2108 void EnableHWSecurityConfig8192(struct net_device *dev);
2109 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
2110 short rtl8192_is_tx_queue_empty(struct net_device *dev);
2111
2112 #endif