drivers/staging/rtl8192u/r8192U.h

   1 /*
   2  * This is part of rtl8187 OpenSource driver.
   3  * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
   4  * Released under the terms of GPL (General Public Licence)
   5  *
   6  * Parts of this driver are based on the GPL part of the
   7  * official realtek driver
   8  *
   9  * Parts of this driver are based on the rtl8192 driver skeleton
  10  * from Patric Schenke & Andres Salomon
  11  *
  12  * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13  *
  14  * We want to thank the Authors of those projects and the Ndiswrapper
  15  * project Authors.
  16  */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/usb.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/wireless.h>
  34 #include <linux/timer.h>
  35 #include <linux/proc_fs.h>
  36 #include <linux/if_arp.h>
  37 #include <linux/random.h>
  38 #include <asm/io.h>
  39 #include "ieee80211/ieee80211.h"
  40
  41 #define RTL8192U
  42 #define RTL819xU_MODULE_NAME "rtl819xU"
  43 /* HW security */
  44 #define FALSE 0
  45 #define TRUE 1
  46 #define MAX_KEY_LEN     61
  47 #define KEY_BUF_SIZE    5
  48
  49 #define BIT0            0x00000001
  50 #define BIT1            0x00000002
  51 #define BIT2            0x00000004
  52 #define BIT3            0x00000008
  53 #define BIT4            0x00000010
  54 #define BIT5            0x00000020
  55 #define BIT6            0x00000040
  56 #define BIT7            0x00000080
  57 #define BIT8            0x00000100
  58 #define BIT9            0x00000200
  59 #define BIT10           0x00000400
  60 #define BIT11           0x00000800
  61 #define BIT12           0x00001000
  62 #define BIT13           0x00002000
  63 #define BIT14           0x00004000
  64 #define BIT15           0x00008000
  65 #define BIT16           0x00010000
  66 #define BIT17           0x00020000
  67 #define BIT18           0x00040000
  68 #define BIT19           0x00080000
  69 #define BIT20           0x00100000
  70 #define BIT21           0x00200000
  71 #define BIT22           0x00400000
  72 #define BIT23           0x00800000
  73 #define BIT24           0x01000000
  74 #define BIT25           0x02000000
  75 #define BIT26           0x04000000
  76 #define BIT27           0x08000000
  77 #define BIT28           0x10000000
  78 #define BIT29           0x20000000
  79 #define BIT30           0x40000000
  80 #define BIT31           0x80000000
  81
  82 #define Rx_Smooth_Factor                20
  83 #define DMESG(x, a...)
  84 #define DMESGW(x, a...)
  85 #define DMESGE(x, a...)
  86 extern u32 rt_global_debug_component;
  87 #define RT_TRACE(component, x, args...) \
  88         do {                                                    \
  89                 if (rt_global_debug_component & component)      \
  90                         pr_debug("RTL8192U: " x "\n", ##args);  \
  91         } while (0)
  92
  93 #define COMP_TRACE              BIT0  /* Function call tracing. */
  94 #define COMP_DBG                BIT1
  95 #define COMP_INIT               BIT2  /* Driver initialization/halt/reset. */
  96
  97
  98 #define COMP_RECV               BIT3  /* Receive data path. */
  99 #define COMP_SEND               BIT4  /* Send data path. */
 100 #define COMP_IO                 BIT5
 101 /* 802.11 Power Save mode or System/Device Power state. */
 102 #define COMP_POWER              BIT6
 103 /* 802.11 link related: join/start BSS, leave BSS. */
 104 #define COMP_EPROM              BIT7
 105 #define COMP_SWBW               BIT8  /* Bandwidth switch. */
 106 #define COMP_POWER_TRACKING     BIT9  /* 8190 TX Power Tracking */
 107 #define COMP_TURBO              BIT10 /* Turbo Mode */
 108 #define COMP_QOS                BIT11
 109 #define COMP_RATE               BIT12 /* Rate Adaptive mechanism */
 110 #define COMP_RM                 BIT13 /* Radio Measurement */
 111 #define COMP_DIG                BIT14
 112 #define COMP_PHY                BIT15
 113 #define COMP_CH                 BIT16 /* Channel setting debug */
 114 #define COMP_TXAGC              BIT17 /* Tx power */
 115 #define COMP_HIPWR              BIT18 /* High Power Mechanism */
 116 #define COMP_HALDM              BIT19 /* HW Dynamic Mechanism */
 117 #define COMP_SEC                BIT20 /* Event handling */
 118 #define COMP_LED                BIT21
 119 #define COMP_RF                 BIT22
 120 #define COMP_RXDESC             BIT23 /* Rx desc information for SD3 debug */
 121
 122 /* 11n or 8190 specific code */
 123
 124 #define COMP_FIRMWARE           BIT24 /* Firmware downloading */
 125 #define COMP_HT                 BIT25 /* 802.11n HT related information */
 126 #define COMP_AMSDU              BIT26 /* A-MSDU Debugging */
 127 #define COMP_SCAN               BIT27
 128 #define COMP_DOWN               BIT29 /* rm driver module */
 129 #define COMP_RESET              BIT30 /* Silent reset */
 130 #define COMP_ERR                BIT31 /* Error out, always on */
 131
 132 #define RTL819x_DEBUG
 133 #ifdef RTL819x_DEBUG
 134 #define RTL8192U_ASSERT(expr) \
 135         do {                                                            \
 136                 if (!(expr)) {                                          \
 137                         pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
 138                                  #expr, __FILE__, __func__, __LINE__);  \
 139                 }                                                       \
 140         } while (0)
 141 /*
 142  * Debug out data buf.
 143  * If you want to print DATA buffer related BA,
 144  * please set ieee80211_debug_level to DATA|BA
 145  */
 146 #define RT_DEBUG_DATA(level, data, datalen) \
 147         do {                                                            \
 148                 if ((rt_global_debug_component & (level)) == (level)) { \
 149                         int i;                                          \
 150                         u8 *pdata = (u8 *) data;                        \
 151                         pr_debug("RTL8192U: %s()\n", __func__);         \
 152                         for (i = 0; i < (int)(datalen); i++) {          \
 153                                 printk("%2x ", pdata[i]);               \
 154                                 if ((i+1)%16 == 0)                      \
 155                                         printk("\n");                   \
 156                         }                                               \
 157                         printk("\n");                                   \
 158                 }                                                       \
 159         } while (0)
 160 #else
 161 #define RTL8192U_ASSERT(expr) do {} while (0)
 162 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
 163 #endif /* RTL8169_DEBUG */
 164
 165
 166 /* Queue Select Value in TxDesc */
 167 #define QSLT_BK                                 0x1
 168 #define QSLT_BE                                 0x0
 169 #define QSLT_VI                                 0x4
 170 #define QSLT_VO                                 0x6
 171 #define QSLT_BEACON                             0x10
 172 #define QSLT_HIGH                               0x11
 173 #define QSLT_MGNT                               0x12
 174 #define QSLT_CMD                                0x13
 175
 176 #define DESC90_RATE1M                           0x00
 177 #define DESC90_RATE2M                           0x01
 178 #define DESC90_RATE5_5M                         0x02
 179 #define DESC90_RATE11M                          0x03
 180 #define DESC90_RATE6M                           0x04
 181 #define DESC90_RATE9M                           0x05
 182 #define DESC90_RATE12M                          0x06
 183 #define DESC90_RATE18M                          0x07
 184 #define DESC90_RATE24M                          0x08
 185 #define DESC90_RATE36M                          0x09
 186 #define DESC90_RATE48M                          0x0a
 187 #define DESC90_RATE54M                          0x0b
 188 #define DESC90_RATEMCS0                         0x00
 189 #define DESC90_RATEMCS1                         0x01
 190 #define DESC90_RATEMCS2                         0x02
 191 #define DESC90_RATEMCS3                         0x03
 192 #define DESC90_RATEMCS4                         0x04
 193 #define DESC90_RATEMCS5                         0x05
 194 #define DESC90_RATEMCS6                         0x06
 195 #define DESC90_RATEMCS7                         0x07
 196 #define DESC90_RATEMCS8                         0x08
 197 #define DESC90_RATEMCS9                         0x09
 198 #define DESC90_RATEMCS10                        0x0a
 199 #define DESC90_RATEMCS11                        0x0b
 200 #define DESC90_RATEMCS12                        0x0c
 201 #define DESC90_RATEMCS13                        0x0d
 202 #define DESC90_RATEMCS14                        0x0e
 203 #define DESC90_RATEMCS15                        0x0f
 204 #define DESC90_RATEMCS32                        0x20
 205
 206 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 207
 208 #define IEEE80211_WATCH_DOG_TIME    2000
 209 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 210 /* For Tx Power Tracking */
 211 #define         OFDM_Table_Length       19
 212 #define CCK_Table_length        12
 213
 214 /* For rtl819x */
 215 typedef struct _tx_desc_819x_usb {
 216         /* DWORD 0 */
 217         u16     PktSize;
 218         u8      Offset;
 219         u8      Reserved0:3;
 220         u8      CmdInit:1;
 221         u8      LastSeg:1;
 222         u8      FirstSeg:1;
 223         u8      LINIP:1;
 224         u8      OWN:1;
 225
 226         /* DWORD 1 */
 227         u8      TxFWInfoSize;
 228         u8      RATid:3;
 229         u8      DISFB:1;
 230         u8      USERATE:1;
 231         u8      MOREFRAG:1;
 232         u8      NoEnc:1;
 233         u8      PIFS:1;
 234         u8      QueueSelect:5;
 235         u8      NoACM:1;
 236         u8      Reserved1:2;
 237         u8      SecCAMID:5;
 238         u8      SecDescAssign:1;
 239         u8      SecType:2;
 240
 241         /* DWORD 2 */
 242         u16     TxBufferSize;
 243         u8      ResvForPaddingLen:7;
 244         u8      Reserved3:1;
 245         u8      Reserved4;
 246
 247         /* DWORD 3, 4, 5 */
 248         u32     Reserved5;
 249         u32     Reserved6;
 250         u32     Reserved7;
 251 } tx_desc_819x_usb, *ptx_desc_819x_usb;
 252
 253 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 254 typedef struct _tx_desc_819x_usb_aggr_subframe {
 255         /* DWORD 0 */
 256         u16     PktSize;
 257         u8      Offset;
 258         u8      TxFWInfoSize;
 259
 260         /* DWORD 1 */
 261         u8      RATid:3;
 262         u8      DISFB:1;
 263         u8      USERATE:1;
 264         u8      MOREFRAG:1;
 265         u8      NoEnc:1;
 266         u8      PIFS:1;
 267         u8      QueueSelect:5;
 268         u8      NoACM:1;
 269         u8      Reserved1:2;
 270         u8      SecCAMID:5;
 271         u8      SecDescAssign:1;
 272         u8      SecType:2;
 273         u8      PacketID:7;
 274         u8      OWN:1;
 275 } tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 276 #endif
 277
 278
 279
 280 typedef struct _tx_desc_cmd_819x_usb {
 281         /* DWORD 0 */
 282         u16     Reserved0;
 283         u8      Reserved1;
 284         u8      Reserved2:3;
 285         u8      CmdInit:1;
 286         u8      LastSeg:1;
 287         u8      FirstSeg:1;
 288         u8      LINIP:1;
 289         u8      OWN:1;
 290
 291         /* DOWRD 1 */
 292         u8      TxFWInfoSize;
 293         u8      Reserved3;
 294         u8      QueueSelect;
 295         u8      Reserved4;
 296
 297         /* DOWRD 2 */
 298         u16     TxBufferSize;
 299         u16     Reserved5;
 300
 301         /* DWORD 3, 4, 5 */
 302         u32     Reserved6;
 303         u32     Reserved7;
 304         u32     Reserved8;
 305 } tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 306
 307
 308 typedef struct _tx_fwinfo_819x_usb {
 309         /* DOWRD 0 */
 310         u8      TxRate:7;
 311         u8      CtsEnable:1;
 312         u8      RtsRate:7;
 313         u8      RtsEnable:1;
 314         u8      TxHT:1;
 315         u8      Short:1;        /* Error out, always on */
 316         u8      TxBandwidth:1;  /* Used for HT MCS rate only */
 317         u8      TxSubCarrier:2; /* Used for legacy OFDM rate only */
 318         u8      STBC:2;
 319         u8      AllowAggregation:1;
 320         /* Interpret RtsRate field as high throughput data rate */
 321         u8      RtsHT:1;
 322         u8      RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
 323         u8      RtsBandwidth:1; /* Used for HT MCS rate only */
 324         u8      RtsSubcarrier:2;/* Used for legacy OFDM rate only */
 325         u8      RtsSTBC:2;
 326         /* Enable firmware to recalculate and assign packet duration */
 327         u8      EnableCPUDur:1;
 328
 329         /* DWORD 1 */
 330         u32     RxMF:2;
 331         u32     RxAMD:3;
 332         /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
 333         u32     TxPerPktInfoFeedback:1;
 334         u32     Reserved1:2;
 335         u32     TxAGCOffSet:4;
 336         u32     TxAGCSign:1;
 337         u32     Tx_INFO_RSVD:6;
 338         u32     PacketID:13;
 339 } tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 340
 341 typedef struct rtl8192_rx_info {
 342         struct urb *urb;
 343         struct net_device *dev;
 344         u8 out_pipe;
 345 } rtl8192_rx_info ;
 346
 347 typedef struct rx_desc_819x_usb {
 348         /* DOWRD 0 */
 349         u16                 Length:14;
 350         u16                 CRC32:1;
 351         u16                 ICV:1;
 352         u8                  RxDrvInfoSize;
 353         u8                  Shift:2;
 354         u8                  PHYStatus:1;
 355         u8                  SWDec:1;
 356         u8                  Reserved1:4;
 357
 358         /* DWORD 1 */
 359         u32                 Reserved2;
 360 } rx_desc_819x_usb, *prx_desc_819x_usb;
 361
 362 #ifdef USB_RX_AGGREGATION_SUPPORT
 363 typedef struct _rx_desc_819x_usb_aggr_subframe {
 364         /* DOWRD 0 */
 365         u16                     Length:14;
 366         u16                     CRC32:1;
 367         u16                     ICV:1;
 368         u8                      Offset;
 369         u8                      RxDrvInfoSize;
 370         /* DOWRD 1 */
 371         u8                      Shift:2;
 372         u8                      PHYStatus:1;
 373         u8                      SWDec:1;
 374         u8                      Reserved1:4;
 375         u8                      Reserved2;
 376         u16                     Reserved3;
 377 } rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 378 #endif
 379
 380 typedef struct rx_drvinfo_819x_usb {
 381         /* DWORD 0 */
 382         u16                 Reserved1:12;
 383         u16                 PartAggr:1;
 384         u16                 FirstAGGR:1;
 385         u16                 Reserved2:2;
 386
 387         u8                  RxRate:7;
 388         u8                  RxHT:1;
 389
 390         u8                  BW:1;
 391         u8                  SPLCP:1;
 392         u8                  Reserved3:2;
 393         u8                  PAM:1;
 394         u8                  Mcast:1;
 395         u8                  Bcast:1;
 396         u8                  Reserved4:1;
 397
 398         /* DWORD 1 */
 399         u32                  TSFL;
 400
 401 } rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 402
 403 /* Support till 64 bit bus width OS */
 404 #define MAX_DEV_ADDR_SIZE               8
 405 /* For RTL8190 */
 406 #define MAX_FIRMWARE_INFORMATION_SIZE   32
 407 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 408 #define ENCRYPTION_MAX_OVERHEAD         128
 409 #define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 410 #define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 411 #define MAX_FRAGMENT_COUNT              8
 412 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 413 #define MAX_TRANSMIT_BUFFER_SIZE                        32000
 414 #else
 415 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 416 #endif
 417 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 418 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 419 #endif
 420 /* Octets for crc32 (FCS, ICV) */
 421 #define scrclng                                 4
 422
 423 typedef enum rf_optype {
 424         RF_OP_By_SW_3wire = 0,
 425         RF_OP_By_FW,
 426         RF_OP_MAX
 427 } rf_op_type;
 428 /* 8190 Loopback Mode definition */
 429 typedef enum _rtl819xUsb_loopback {
 430         RTL819xU_NO_LOOPBACK = 0,
 431         RTL819xU_MAC_LOOPBACK = 1,
 432         RTL819xU_DMA_LOOPBACK = 2,
 433         RTL819xU_CCK_LOOPBACK = 3,
 434 } rtl819xUsb_loopback_e;
 435
 436 /* due to rtl8192 firmware */
 437 typedef enum _desc_packet_type_e {
 438         DESC_PACKET_TYPE_INIT = 0,
 439         DESC_PACKET_TYPE_NORMAL = 1,
 440 } desc_packet_type_e;
 441
 442 typedef enum _firmware_status {
 443         FW_STATUS_0_INIT = 0,
 444         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 445         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 446         FW_STATUS_3_TURNON_CPU = 3,
 447         FW_STATUS_4_MOVE_DATA_CODE = 4,
 448         FW_STATUS_5_READY = 5,
 449 } firmware_status_e;
 450
 451 typedef struct _rt_firmare_seg_container {
 452         u16     seg_size;
 453         u8      *seg_ptr;
 454 } fw_seg_container, *pfw_seg_container;
 455 typedef struct _rt_firmware {
 456         firmware_status_e firmware_status;
 457         u16               cmdpacket_frag_thresold;
 458 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
 459         u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 460         u16               firmware_buf_size;
 461 } rt_firmware, *prt_firmware;
 462
 463 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
 464 #define MAX_RECEIVE_BUFFER_SIZE 9100
 465
 466 typedef struct _rt_firmware_info_819xUsb {
 467         u8              sz_info[16];
 468 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 469
 470 /* Firmware Queue Layout */
 471 #define NUM_OF_FIRMWARE_QUEUE           10
 472 #define NUM_OF_PAGES_IN_FW              0x100
 473
 474 #ifdef USE_ONE_PIPE
 475 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 476 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 477 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 478 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 479 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 480 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 481 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 482 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 483 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 484 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 485 #else
 486
 487 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 488 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 489 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 490 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 491 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 492 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 493 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 494 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 495 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 496 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 497
 498 #endif
 499
 500 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 501 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 502 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 503 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 504 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 505 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 506 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 507 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 508 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 509
 510 /*
 511  * =================================================================
 512  * =================================================================
 513  */
 514
 515 #define EPROM_93c46 0
 516 #define EPROM_93c56 1
 517
 518 #define DEFAULT_FRAG_THRESHOLD 2342U
 519 #define MIN_FRAG_THRESHOLD     256U
 520 #define DEFAULT_BEACONINTERVAL 0x64U
 521 #define DEFAULT_BEACON_ESSID "Rtl819xU"
 522
 523 #define DEFAULT_SSID ""
 524 #define DEFAULT_RETRY_RTS 7
 525 #define DEFAULT_RETRY_DATA 7
 526 #define PRISM_HDR_SIZE 64
 527
 528 #define         PHY_RSSI_SLID_WIN_MAX                           100
 529
 530
 531 typedef enum _WIRELESS_MODE {
 532         WIRELESS_MODE_UNKNOWN = 0x00,
 533         WIRELESS_MODE_A = 0x01,
 534         WIRELESS_MODE_B = 0x02,
 535         WIRELESS_MODE_G = 0x04,
 536         WIRELESS_MODE_AUTO = 0x08,
 537         WIRELESS_MODE_N_24G = 0x10,
 538         WIRELESS_MODE_N_5G = 0x20
 539 } WIRELESS_MODE;
 540
 541
 542 #define RTL_IOCTL_WPA_SUPPLICANT                (SIOCIWFIRSTPRIV + 30)
 543
 544 typedef struct buffer {
 545         struct buffer *next;
 546         u32 *buf;
 547
 548 } buffer;
 549
 550 typedef struct rtl_reg_debug {
 551         unsigned int  cmd;
 552         struct {
 553                 unsigned char type;
 554                 unsigned char addr;
 555                 unsigned char page;
 556                 unsigned char length;
 557         } head;
 558         unsigned char buf[0xff];
 559 } rtl_reg_debug;
 560
 561
 562
 563
 564
 565
 566 typedef struct _rt_9x_tx_rate_history {
 567         u32             cck[4];
 568         u32             ofdm[8];
 569         u32             ht_mcs[4][16];
 570 } rt_tx_rahis_t, *prt_tx_rahis_t;
 571 typedef struct _RT_SMOOTH_DATA_4RF {
 572         char    elements[4][100]; /* array to store values */
 573         u32     index;            /* index to current array to store */
 574         u32     TotalNum;         /* num of valid elements */
 575         u32     TotalVal[4];      /* sum of valid elements */
 576 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 577
 578 /* This maybe changed for D-cut larger aggregation size */
 579 #define MAX_8192U_RX_SIZE                       8192
 580 /* Stats seems messed up, clean it ASAP */
 581 typedef struct Stats {
 582         unsigned long txrdu;
 583         unsigned long rxok;
 584         unsigned long rxframgment;
 585         unsigned long rxurberr;
 586         unsigned long rxstaterr;
 587         /* 0: Total, 1: OK, 2: CRC, 3: ICV */
 588         unsigned long received_rate_histogram[4][32];
 589         /* 0: Long preamble/GI, 1: Short preamble/GI */
 590         unsigned long received_preamble_GI[2][32];
 591         /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
 592         unsigned long rx_AMPDUsize_histogram[5];
 593         /* level: (<5), (5~10), (10~20), (20~40), (>40) */
 594         unsigned long rx_AMPDUnum_histogram[5];
 595         unsigned long numpacket_matchbssid;
 596         unsigned long numpacket_toself;
 597         unsigned long num_process_phyinfo;
 598         unsigned long numqry_phystatus;
 599         unsigned long numqry_phystatusCCK;
 600         unsigned long numqry_phystatusHT;
 601         /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
 602         unsigned long received_bwtype[5];
 603         unsigned long txnperr;
 604         unsigned long txnpdrop;
 605         unsigned long txresumed;
 606         unsigned long txnpokint;
 607         unsigned long txoverflow;
 608         unsigned long txlpokint;
 609         unsigned long txlpdrop;
 610         unsigned long txlperr;
 611         unsigned long txbeokint;
 612         unsigned long txbedrop;
 613         unsigned long txbeerr;
 614         unsigned long txbkokint;
 615         unsigned long txbkdrop;
 616         unsigned long txbkerr;
 617         unsigned long txviokint;
 618         unsigned long txvidrop;
 619         unsigned long txvierr;
 620         unsigned long txvookint;
 621         unsigned long txvodrop;
 622         unsigned long txvoerr;
 623         unsigned long txbeaconokint;
 624         unsigned long txbeacondrop;
 625         unsigned long txbeaconerr;
 626         unsigned long txmanageokint;
 627         unsigned long txmanagedrop;
 628         unsigned long txmanageerr;
 629         unsigned long txdatapkt;
 630         unsigned long txfeedback;
 631         unsigned long txfeedbackok;
 632
 633         unsigned long txoktotal;
 634         unsigned long txokbytestotal;
 635         unsigned long txokinperiod;
 636         unsigned long txmulticast;
 637         unsigned long txbytesmulticast;
 638         unsigned long txbroadcast;
 639         unsigned long txbytesbroadcast;
 640         unsigned long txunicast;
 641         unsigned long txbytesunicast;
 642
 643         unsigned long rxoktotal;
 644         unsigned long rxbytesunicast;
 645         unsigned long txfeedbackfail;
 646         unsigned long txerrtotal;
 647         unsigned long txerrbytestotal;
 648         unsigned long txerrmulticast;
 649         unsigned long txerrbroadcast;
 650         unsigned long txerrunicast;
 651         unsigned long txretrycount;
 652         unsigned long txfeedbackretry;
 653         u8            last_packet_rate;
 654         unsigned long slide_signal_strength[100];
 655         unsigned long slide_evm[100];
 656         /* For recording sliding window's RSSI value */
 657         unsigned long slide_rssi_total;
 658         /* For recording sliding window's EVM value */
 659         unsigned long slide_evm_total;
 660         /* Transformed in dbm. Beautified signal strength for UI, not correct */
 661         long signal_strength;
 662         long signal_quality;
 663         long last_signal_strength_inpercent;
 664         /* Correct smoothed ss in dbm, only used in driver
 665          * to report real power now */
 666         long recv_signal_power;
 667         u8 rx_rssi_percentage[4];
 668         u8 rx_evm_percentage[2];
 669         long rxSNRdB[4];
 670         rt_tx_rahis_t txrate;
 671         /* For beacon RSSI */
 672         u32 Slide_Beacon_pwdb[100];
 673         u32 Slide_Beacon_Total;
 674         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 675
 676         u32     CurrentShowTxate;
 677 } Stats;
 678
 679
 680 /* Bandwidth Offset */
 681 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 682 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 683 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 684
 685
 686 typedef struct  ChnlAccessSetting {
 687         u16 SIFS_Timer;
 688         u16 DIFS_Timer;
 689         u16 SlotTimeTimer;
 690         u16 EIFS_Timer;
 691         u16 CWminIndex;
 692         u16 CWmaxIndex;
 693 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
 694
 695 typedef struct _BB_REGISTER_DEFINITION {
 696         /* set software control:        0x870~0x877 [8 bytes]  */
 697         u32 rfintfs;
 698         /* readback data:               0x8e0~0x8e7 [8 bytes]  */
 699         u32 rfintfi;
 700         /* output data:                 0x860~0x86f [16 bytes] */
 701         u32 rfintfo;
 702         /* output enable:               0x860~0x86f [16 bytes] */
 703         u32 rfintfe;
 704         /* LSSI data:                   0x840~0x84f [16 bytes] */
 705         u32 rf3wireOffset;
 706         /* BB Band Select:              0x878~0x87f [8 bytes]  */
 707         u32 rfLSSI_Select;
 708         /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
 709         u32 rfTxGainStage;
 710         /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
 711          *                              0x830~0x833, 0x838~0x83b [16 bytes] */
 712         u32 rfHSSIPara1;
 713         /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
 714          *                              0x834~0x837, 0x83c~0x83f [16 bytes] */
 715         u32 rfHSSIPara2;
 716         /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
 717         u32 rfSwitchControl;
 718         /* AGC parameter control1:      0xc50~0xc53, 0xc58~0xc5b,
 719          *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
 720         u32 rfAGCControl1;
 721         /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
 722          *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
 723         u32 rfAGCControl2;
 724         /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
 725          *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
 726         u32 rfRxIQImbalance;
 727         /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
 728          *                              0xc10~0xc13, 0xc18~0xc1b,
 729          *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
 730         u32 rfRxAFE;
 731         /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
 732          *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
 733         u32 rfTxIQImbalance;
 734         /* Tx IQ DC Offset and Tx DFIR type:
 735          *                              0xc84~0xc87, 0xc8c~0xc8f,
 736          *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
 737         u32 rfTxAFE;
 738         /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
 739         u32 rfLSSIReadBack;
 740 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 741
 742 typedef enum _RT_RF_TYPE_819xU {
 743         RF_TYPE_MIN = 0,
 744         RF_8225,
 745         RF_8256,
 746         RF_8258,
 747         RF_PSEUDO_11N = 4,
 748 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 749
 750 typedef struct _rate_adaptive {
 751         u8                              rate_adaptive_disabled;
 752         u8                              ratr_state;
 753         u16                             reserve;
 754
 755         u32                             high_rssi_thresh_for_ra;
 756         u32                             high2low_rssi_thresh_for_ra;
 757         u8                              low2high_rssi_thresh_for_ra40M;
 758         u32                             low_rssi_thresh_for_ra40M;
 759         u8                              low2high_rssi_thresh_for_ra20M;
 760         u32                             low_rssi_thresh_for_ra20M;
 761         u32                             upper_rssi_threshold_ratr;
 762         u32                             middle_rssi_threshold_ratr;
 763         u32                             low_rssi_threshold_ratr;
 764         u32                             low_rssi_threshold_ratr_40M;
 765         u32                             low_rssi_threshold_ratr_20M;
 766         u8                              ping_rssi_enable;
 767         u32                             ping_rssi_ratr;
 768         u32                             ping_rssi_thresh_for_ra;
 769         u32                             last_ratr;
 770
 771 } rate_adaptive, *prate_adaptive;
 772
 773 #define TxBBGainTableLength 37
 774 #define CCKTxBBGainTableLength 23
 775
 776 typedef struct _txbbgain_struct {
 777         long    txbb_iq_amplifygain;
 778         u32     txbbgain_value;
 779 } txbbgain_struct, *ptxbbgain_struct;
 780
 781 typedef struct _ccktxbbgain_struct {
 782         /* The value is from a22 to a29, one byte one time is much safer */
 783         u8      ccktxbb_valuearray[8];
 784 } ccktxbbgain_struct, *pccktxbbgain_struct;
 785
 786
 787 typedef struct _init_gain {
 788         u8                              xaagccore1;
 789         u8                              xbagccore1;
 790         u8                              xcagccore1;
 791         u8                              xdagccore1;
 792         u8                              cca;
 793
 794 } init_gain, *pinit_gain;
 795
 796 typedef struct _phy_ofdm_rx_status_report_819xusb {
 797         u8      trsw_gain_X[4];
 798         u8      pwdb_all;
 799         u8      cfosho_X[4];
 800         u8      cfotail_X[4];
 801         u8      rxevm_X[2];
 802         u8      rxsnr_X[4];
 803         u8      pdsnr_X[2];
 804         u8      csi_current_X[2];
 805         u8      csi_target_X[2];
 806         u8      sigevm;
 807         u8      max_ex_pwr;
 808         u8      sgi_en;
 809         u8  rxsc_sgien_exflg;
 810 } phy_sts_ofdm_819xusb_t;
 811
 812 typedef struct _phy_cck_rx_status_report_819xusb {
 813         /* For CCK rate descriptor. This is an unsigned 8:1 variable.
 814          * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
 815          * Range from -64~+63.5. */
 816         u8      adc_pwdb_X[4];
 817         u8      sq_rpt;
 818         u8      cck_agc_rpt;
 819 } phy_sts_cck_819xusb_t;
 820
 821
 822 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 823         u8                      reserved:4;
 824         u8                      rxsc:2;
 825         u8                      sgi_en:1;
 826         u8                      ex_intf_flag:1;
 827 } phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 828
 829 typedef enum _RT_CUSTOMER_ID {
 830         RT_CID_DEFAULT = 0,
 831         RT_CID_8187_ALPHA0 = 1,
 832         RT_CID_8187_SERCOMM_PS = 2,
 833         RT_CID_8187_HW_LED = 3,
 834         RT_CID_8187_NETGEAR = 4,
 835         RT_CID_WHQL = 5,
 836         RT_CID_819x_CAMEO  = 6,
 837         RT_CID_819x_RUNTOP = 7,
 838         RT_CID_819x_Senao = 8,
 839         RT_CID_TOSHIBA = 9,
 840         RT_CID_819x_Netcore = 10,
 841         RT_CID_Nettronix = 11,
 842         RT_CID_DLINK = 12,
 843         RT_CID_PRONET = 13,
 844 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 845
 846 /*
 847  * ==========================================================================
 848  * LED customization.
 849  * ==========================================================================
 850  */
 851
 852 typedef enum _LED_STRATEGY_8190 {
 853         SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
 854         SW_LED_MODE1, /* SW control for PCI Express */
 855         SW_LED_MODE2, /* SW control for Cameo. */
 856         SW_LED_MODE3, /* SW control for RunTop. */
 857         SW_LED_MODE4, /* SW control for Netcore. */
 858         /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
 859         HW_LED,
 860 } LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 861
 862 typedef enum _RESET_TYPE {
 863         RESET_TYPE_NORESET = 0x00,
 864         RESET_TYPE_NORMAL = 0x01,
 865         RESET_TYPE_SILENT = 0x02
 866 } RESET_TYPE;
 867
 868 /* The simple tx command OP code. */
 869 typedef enum _tag_TxCmd_Config_Index {
 870         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 871         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 872         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 873         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 874         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 875         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 876         TXCMD_XXXX_CTRL,
 877 } DCMD_TXCMD_OP;
 878
 879 typedef struct r8192_priv {
 880         struct usb_device *udev;
 881         /* For maintain info from eeprom */
 882         short epromtype;
 883         u16 eeprom_vid;
 884         u16 eeprom_pid;
 885         u8  eeprom_CustomerID;
 886         u8  eeprom_ChannelPlan;
 887         RT_CUSTOMER_ID CustomerID;
 888         LED_STRATEGY_8190       LedStrategy;
 889         u8  txqueue_to_outpipemap[9];
 890         int irq;
 891         struct ieee80211_device *ieee80211;
 892
 893         /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
 894         short card_8192;
 895         /* If TCR reports card V B/C, this discriminates */
 896         u8 card_8192_version;
 897         short enable_gpio0;
 898         enum card_type {
 899                 PCI, MINIPCI, CARDBUS, USB
 900         } card_type;
 901         short hw_plcp_len;
 902         short plcp_preamble_mode;
 903
 904         spinlock_t irq_lock;
 905         spinlock_t tx_lock;
 906         struct mutex mutex;
 907
 908         u16 irq_mask;
 909         short chan;
 910         short sens;
 911         short max_sens;
 912
 913
 914         short up;
 915         /* If 1, allow bad crc frame, reception in monitor mode */
 916         short crcmon;
 917
 918         struct semaphore wx_sem;
 919         struct semaphore rf_sem;        /* Used to lock rf write operation */
 920
 921         u8 rf_type;                     /* 0: 1T2R, 1: 2T4R */
 922         RT_RF_TYPE_819xU rf_chip;
 923
 924         short (*rf_set_sens)(struct net_device *dev, short sens);
 925         u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
 926         void (*rf_close)(struct net_device *dev);
 927         void (*rf_init)(struct net_device *dev);
 928         short promisc;
 929         /* Stats */
 930         struct Stats stats;
 931         struct iw_statistics wstats;
 932
 933         /* RX stuff */
 934         struct urb **rx_urb;
 935         struct urb **rx_cmd_urb;
 936 #ifdef THOMAS_BEACON
 937         u32 *oldaddr;
 938 #endif
 939 #ifdef THOMAS_TASKLET
 940         atomic_t irt_counter; /* count for irq_rx_tasklet */
 941 #endif
 942 #ifdef JACKSON_NEW_RX
 943         struct sk_buff **pp_rxskb;
 944         int     rx_inx;
 945 #endif
 946
 947        struct sk_buff_head rx_queue;
 948        struct sk_buff_head skb_queue;
 949        struct work_struct qos_activate;
 950         short  tx_urb_index;
 951         atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
 952
 953
 954         struct tasklet_struct irq_rx_tasklet;
 955         struct urb *rxurb_task;
 956
 957         /* Tx Related variables */
 958         u16     ShortRetryLimit;
 959         u16     LongRetryLimit;
 960         u32     TransmitConfig;
 961         u8      RegCWinMin;     /* For turbo mode CW adaptive */
 962
 963         u32     LastRxDescTSFHigh;
 964         u32     LastRxDescTSFLow;
 965
 966
 967         /* Rx Related variables */
 968         u16     EarlyRxThreshold;
 969         u32     ReceiveConfig;
 970         u8      AcmControl;
 971
 972         u8      RFProgType;
 973
 974         u8 retry_data;
 975         u8 retry_rts;
 976         u16 rts;
 977
 978         struct  ChnlAccessSetting  ChannelAccessSetting;
 979         struct work_struct reset_wq;
 980
 981 /**********************************************************/
 982         /* For rtl819xUsb */
 983         u16     basic_rate;
 984         u8      short_preamble;
 985         u8      slot_time;
 986         bool    bDcut;
 987         bool bCurrentRxAggrEnable;
 988         u8 Rf_Mode;     /* For Firmware RF -R/W switch */
 989         prt_firmware            pFirmware;
 990         rtl819xUsb_loopback_e   LoopbackMode;
 991         u16 EEPROMTxPowerDiff;
 992         u8 EEPROMThermalMeter;
 993         u8 EEPROMPwDiff;
 994         u8 EEPROMCrystalCap;
 995         u8 EEPROM_Def_Ver;
 996         u8 EEPROMTxPowerLevelCCK;               /* CCK channel 1~14 */
 997         u8 EEPROMTxPowerLevelCCK_V1[3];
 998         u8 EEPROMTxPowerLevelOFDM24G[3];        /* OFDM 2.4G channel 1~14 */
 999         u8 EEPROMTxPowerLevelOFDM5G[24];        /* OFDM 5G */
1000
1001         /* PHY related */
1002         BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
1003         /* Read/write are allow for following hardware information variables */
1004         u32     MCSTxPowerLevelOriginalOffset[6];
1005         u32     CCKTxPowerLevelOriginalOffset;
1006         u8      TxPowerLevelCCK[14];            /* CCK channel 1~14 */
1007         u8      TxPowerLevelOFDM24G[14];        /* OFDM 2.4G channel 1~14 */
1008         u8      TxPowerLevelOFDM5G[14];         /* OFDM 5G */
1009         u32     Pwr_Track;
1010         u8      TxPowerDiff;
1011         u8      AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
1012         u8      CrystalCap;
1013         u8      ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
1014
1015         u8      CckPwEnl;
1016         /* Use to calculate PWBD */
1017         u8      bCckHighPower;
1018         long    undecorated_smoothed_pwdb;
1019
1020         /* For set channel */
1021         u8      SwChnlInProgress;
1022         u8      SwChnlStage;
1023         u8      SwChnlStep;
1024         u8      SetBWModeInProgress;
1025         HT_CHANNEL_WIDTH                CurrentChannelBW;
1026         u8      ChannelPlan;
1027         /* 8190 40MHz mode */
1028         /* Control channel sub-carrier */
1029         u8      nCur40MhzPrimeSC;
1030         /* Test for shorten RF configuration time.
1031          * We save RF reg0 in this variable to reduce RF reading. */
1032         u32                                     RfReg0Value[4];
1033         u8                                      NumTotalRFPath;
1034         bool                            brfpath_rxenable[4];
1035         /* RF set related */
1036         bool                            SetRFPowerStateInProgress;
1037         struct timer_list watch_dog_timer;
1038
1039         /* For dynamic mechanism */
1040         /* Tx Power Control for Near/Far Range */
1041         bool    bdynamic_txpower;
1042         bool    bDynamicTxHighPower;
1043         bool    bDynamicTxLowPower;
1044         bool    bLastDTPFlag_High;
1045         bool    bLastDTPFlag_Low;
1046
1047         bool    bstore_last_dtpflag;
1048         /* Define to discriminate on High power State or
1049          * on sitesurvey to change Tx gain index */
1050         bool    bstart_txctrl_bydtp;
1051         rate_adaptive rate_adaptive;
1052         /* TX power tracking
1053          * OPEN/CLOSE TX POWER TRACKING */
1054         txbbgain_struct txbbgain_table[TxBBGainTableLength];
1055         u8              txpower_count; /* For 6 sec do tracking again */
1056         bool            btxpower_trackingInit;
1057         u8              OFDM_index;
1058         u8              CCK_index;
1059         /* CCK TX Power Tracking */
1060         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1061         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1062         u8 rfa_txpowertrackingindex;
1063         u8 rfa_txpowertrackingindex_real;
1064         u8 rfa_txpowertracking_default;
1065         u8 rfc_txpowertrackingindex;
1066         u8 rfc_txpowertrackingindex_real;
1067
1068         s8 cck_present_attentuation;
1069         u8 cck_present_attentuation_20Mdefault;
1070         u8 cck_present_attentuation_40Mdefault;
1071         char cck_present_attentuation_difference;
1072         bool btxpower_tracking;
1073         bool bcck_in_ch14;
1074         bool btxpowerdata_readfromEEPORM;
1075         u16     TSSI_13dBm;
1076         init_gain initgain_backup;
1077         u8 DefaultInitialGain[4];
1078         /* For EDCA Turbo mode */
1079         bool            bis_any_nonbepkts;
1080         bool            bcurrent_turbo_EDCA;
1081         bool            bis_cur_rdlstate;
1082         struct timer_list fsync_timer;
1083         bool bfsync_processing; /* 500ms Fsync timer is active or not */
1084         u32     rate_record;
1085         u32     rateCountDiffRecord;
1086         u32     ContinueDiffCount;
1087         bool bswitch_fsync;
1088
1089         u8      framesync;
1090         u32     framesyncC34;
1091         u8      framesyncMonitor;
1092         u16     nrxAMPDU_size;
1093         u8      nrxAMPDU_aggr_num;
1094
1095         /* For gpio */
1096          bool bHwRadioOff;
1097
1098         u32 reset_count;
1099         bool bpbc_pressed;
1100         u32 txpower_checkcnt;
1101         u32 txpower_tracking_callback_cnt;
1102         u8 thermal_read_val[40];
1103         u8 thermal_readback_index;
1104         u32 ccktxpower_adjustcnt_not_ch14;
1105         u32 ccktxpower_adjustcnt_ch14;
1106         u8 tx_fwinfo_force_subcarriermode;
1107         u8 tx_fwinfo_force_subcarrierval;
1108         /* For silent reset */
1109         RESET_TYPE      ResetProgress;
1110         bool            bForcedSilentReset;
1111         bool            bDisableNormalResetCheck;
1112         u16             TxCounter;
1113         u16             RxCounter;
1114         int             IrpPendingCount;
1115         bool            bResetInProgress;
1116         bool            force_reset;
1117         u8              InitialGainOperateType;
1118
1119         u16             SifsTime;
1120
1121         /* Define work item */
1122
1123         struct delayed_work update_beacon_wq;
1124         struct delayed_work watch_dog_wq;
1125         struct delayed_work txpower_tracking_wq;
1126         struct delayed_work rfpath_check_wq;
1127         struct delayed_work gpio_change_rf_wq;
1128         struct delayed_work initialgain_operate_wq;
1129         struct workqueue_struct *priv_wq;
1130 } r8192_priv;
1131
1132 /* For rtl8187B */
1133 typedef enum{
1134         BULK_PRIORITY = 0x01,
1135         LOW_PRIORITY,
1136         NORM_PRIORITY,
1137         VO_PRIORITY,
1138         VI_PRIORITY,
1139         BE_PRIORITY,
1140         BK_PRIORITY,
1141         RSVD2,
1142         RSVD3,
1143         BEACON_PRIORITY,
1144         HIGH_PRIORITY,
1145         MANAGE_PRIORITY,
1146         RSVD4,
1147         RSVD5,
1148         UART_PRIORITY
1149 } priority_t;
1150
1151 typedef enum {
1152         NIC_8192U = 1,
1153         NIC_8190P = 2,
1154         NIC_8192E = 3,
1155 } nic_t;
1156
1157 bool init_firmware(struct net_device *dev);
1158 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1159 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1160
1161 u32 read_cam(struct net_device *dev, u8 addr);
1162 void write_cam(struct net_device *dev, u8 addr, u32 data);
1163
1164 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1165 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1166 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1167 int read_nic_word(struct net_device *dev, int x, u16 *data);
1168 void write_nic_byte(struct net_device *dev, int x, u8 y);
1169 void write_nic_byte_E(struct net_device *dev, int x, u8 y);
1170 void write_nic_word(struct net_device *dev, int x, u16 y);
1171 void write_nic_dword(struct net_device *dev, int x, u32 y);
1172 void force_pci_posting(struct net_device *dev);
1173
1174 void rtl8192_rtx_disable(struct net_device *);
1175 void rtl8192_rx_enable(struct net_device *);
1176 void rtl8192_tx_enable(struct net_device *);
1177
1178 void rtl8192_disassociate(struct net_device *dev);
1179 void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a);
1180
1181 void rtl8192_set_anaparam(struct net_device *dev, u32 a);
1182 void rtl8185_set_anaparam2(struct net_device *dev, u32 a);
1183 void rtl8192_update_msr(struct net_device *dev);
1184 int rtl8192_down(struct net_device *dev);
1185 int rtl8192_up(struct net_device *dev);
1186 void rtl8192_commit(struct net_device *dev);
1187 void rtl8192_set_chan(struct net_device *dev, short ch);
1188 void write_phy(struct net_device *dev, u8 adr, u8 data);
1189 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1190 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1191 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1192 void rtl8192_set_rxconf(struct net_device *dev);
1193 extern void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1194
1195 void EnableHWSecurityConfig8192(struct net_device *dev);
1196 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1197
1198
1199 #endif