drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 #include <linux/bitops.h>
  11
  12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  13         0,
  14         0x085c, //2412 1
  15         0x08dc, //2417 2
  16         0x095c, //2422 3
  17         0x09dc, //2427 4
  18         0x0a5c, //2432 5
  19         0x0adc, //2437 6
  20         0x0b5c, //2442 7
  21         0x0bdc, //2447 8
  22         0x0c5c, //2452 9
  23         0x0cdc, //2457 10
  24         0x0d5c, //2462 11
  25         0x0ddc, //2467 12
  26         0x0e5c, //2472 13
  27         0x0f72, //2484
  28 };
  29
  30
  31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  34 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  39
  40 /******************************************************************************
  41  *function:  This function read BB parameters from Header file we gen,
  42  *           and do register read/write
  43  *   input:  u32        dwBitMask  //taget bit pos in the addr to be modified
  44  *  output:  none
  45  *  return:  u32        return the shift bit position of the mask
  46  * ****************************************************************************/
  47 u32 rtl8192_CalculateBitShift(u32 dwBitMask)
  48 {
  49         u32 i;
  50         i = ffs(dwBitMask) - 1;
  51         return i;
  52 }
  53 /******************************************************************************
  54  *function:  This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
  55  *   input:  none
  56  *  output:  none
  57  *  return:  0(illegal, false), 1(legal,true)
  58  * ***************************************************************************/
  59 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  60 {
  61         u8 ret = 1;
  62         struct r8192_priv *priv = ieee80211_priv(dev);
  63         if (priv->rf_type == RF_2T4R) {
  64                 ret = 0;
  65         } else if (priv->rf_type == RF_1T2R) {
  66                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  67                         ret = 1;
  68                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  69                         ret = 0;
  70         }
  71         return ret;
  72 }
  73 /******************************************************************************
  74  *function:  This function set specific bits to BB register
  75  *   input:  net_device dev
  76  *           u32        dwRegAddr  //target addr to be modified
  77  *           u32        dwBitMask  //taget bit pos in the addr to be modified
  78  *           u32        dwData     //value to be write
  79  *  output:  none
  80  *  return:  none
  81  *  notice:
  82  * ****************************************************************************/
  83 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
  84 {
  85
  86         u32 OriginalValue, BitShift, NewValue;
  87
  88         if (dwBitMask!= bMaskDWord) { //if not "double word" write
  89                 read_nic_dword(dev, dwRegAddr, &OriginalValue);
  90                 BitShift = rtl8192_CalculateBitShift(dwBitMask);
  91                 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
  92                 write_nic_dword(dev, dwRegAddr, NewValue);
  93         } else {
  94                 write_nic_dword(dev, dwRegAddr, dwData);
  95         }
  96         return;
  97 }
  98 /******************************************************************************
  99  *function:  This function reads specific bits from BB register
 100  *   input:  net_device dev
 101  *           u32        dwRegAddr  //target addr to be readback
 102  *           u32        dwBitMask  //taget bit pos in the addr to be readback
 103  *  output:  none
 104  *  return:  u32        Data    //the readback register value
 105  *  notice:
 106  * ****************************************************************************/
 107 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
 108 {
 109         u32 Ret = 0, OriginalValue, BitShift;
 110
 111         read_nic_dword(dev, dwRegAddr, &OriginalValue);
 112         BitShift = rtl8192_CalculateBitShift(dwBitMask);
 113         Ret =(OriginalValue & dwBitMask) >> BitShift;
 114
 115         return Ret;
 116 }
 117 static  u32 phy_FwRFSerialRead( struct net_device *dev, RF90_RADIO_PATH_E       eRFPath, u32 Offset  );
 118
 119 static void phy_FwRFSerialWrite( struct net_device *dev, RF90_RADIO_PATH_E       eRFPath, u32  Offset, u32  Data);
 120
 121 /******************************************************************************
 122  *function:  This function read register from RF chip
 123  *   input:  net_device dev
 124  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 125  *           u32        Offset     //target address to be read
 126  *  output:  none
 127  *  return:  u32        readback value
 128  *  notice:  There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
 129  * ****************************************************************************/
 130 u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
 131 {
 132         struct r8192_priv *priv = ieee80211_priv(dev);
 133         u32 ret = 0;
 134         u32 NewOffset = 0;
 135         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 136         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 137         //make sure RF register offset is correct
 138         Offset &= 0x3f;
 139
 140         //switch page for 8256 RF IC
 141         if (priv->rf_chip == RF_8256) {
 142                 if (Offset >= 31) {
 143                         priv->RfReg0Value[eRFPath] |= 0x140;
 144                         //Switch to Reg_Mode2 for Reg 31-45
 145                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 146                         //modify offset
 147                         NewOffset = Offset -30;
 148                 } else if (Offset >= 16) {
 149                         priv->RfReg0Value[eRFPath] |= 0x100;
 150                         priv->RfReg0Value[eRFPath] &= (~0x40);
 151                         //Switch to Reg_Mode 1 for Reg16-30
 152                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 153
 154                         NewOffset = Offset - 15;
 155                 } else {
 156                         NewOffset = Offset;
 157                 }
 158         } else {
 159                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
 160                 NewOffset = Offset;
 161         }
 162         //put desired read addr to LSSI control Register
 163         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 164         //Issue a posedge trigger
 165         //
 166         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 167         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 168
 169
 170         // TODO: we should not delay such a long time. Ask for help from SD3
 171         msleep(1);
 172
 173         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 174
 175
 176         // Switch back to Reg_Mode0;
 177         if (priv->rf_chip == RF_8256) {
 178                 priv->RfReg0Value[eRFPath] &= 0xebf;
 179
 180                 rtl8192_setBBreg(
 181                         dev,
 182                         pPhyReg->rf3wireOffset,
 183                         bMaskDWord,
 184                         (priv->RfReg0Value[eRFPath] << 16));
 185         }
 186
 187         return ret;
 188
 189 }
 190
 191 /******************************************************************************
 192  *function:  This function write data to RF register
 193  *   input:  net_device dev
 194  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 195  *           u32        Offset     //target address to be written
 196  *           u32        Data    //The new register data to be written
 197  *  output:  none
 198  *  return:  none
 199  *  notice:  For RF8256 only.
 200   ===========================================================
 201  *Reg Mode      RegCTL[1]       RegCTL[0]               Note
 202  *              (Reg00[12])     (Reg00[10])
 203  *===========================================================
 204  *Reg_Mode0     0               x                       Reg 0 ~15(0x0 ~ 0xf)
 205  *------------------------------------------------------------------
 206  *Reg_Mode1     1               0                       Reg 16 ~30(0x1 ~ 0xf)
 207  *------------------------------------------------------------------
 208  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 209  *------------------------------------------------------------------
 210  * ****************************************************************************/
 211 void rtl8192_phy_RFSerialWrite(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
 212 {
 213         struct r8192_priv *priv = ieee80211_priv(dev);
 214         u32 DataAndAddr = 0, NewOffset = 0;
 215         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 216
 217         Offset &= 0x3f;
 218         if (priv->rf_chip == RF_8256) {
 219
 220                 if (Offset >= 31) {
 221                         priv->RfReg0Value[eRFPath] |= 0x140;
 222                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
 223                         NewOffset = Offset - 30;
 224                 } else if (Offset >= 16) {
 225                         priv->RfReg0Value[eRFPath] |= 0x100;
 226                         priv->RfReg0Value[eRFPath] &= (~0x40);
 227                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
 228                         NewOffset = Offset - 15;
 229                 } else {
 230                         NewOffset = Offset;
 231                 }
 232         } else {
 233                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
 234                 NewOffset = Offset;
 235         }
 236
 237         // Put write addr in [5:0] and write data in [31:16]
 238         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 239
 240         // Write Operation
 241         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 242
 243
 244         if (Offset==0x0)
 245                 priv->RfReg0Value[eRFPath] = Data;
 246
 247         // Switch back to Reg_Mode0;
 248         if (priv->rf_chip == RF_8256) {
 249                 if (Offset != 0) {
 250                         priv->RfReg0Value[eRFPath] &= 0xebf;
 251                         rtl8192_setBBreg(
 252                                 dev,
 253                                 pPhyReg->rf3wireOffset,
 254                                 bMaskDWord,
 255                                 (priv->RfReg0Value[eRFPath] << 16));
 256                 }
 257         }
 258         return;
 259 }
 260
 261 /******************************************************************************
 262  *function:  This function set specific bits to RF register
 263  *   input:  net_device dev
 264  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 265  *           u32        RegAddr  //target addr to be modified
 266  *           u32        BitMask  //taget bit pos in the addr to be modified
 267  *           u32        Data     //value to be write
 268  *  output:  none
 269  *  return:  none
 270  *  notice:
 271  * ****************************************************************************/
 272 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 273 {
 274         struct r8192_priv *priv = ieee80211_priv(dev);
 275         u32 Original_Value, BitShift, New_Value;
 276
 277         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 278                 return;
 279
 280         if (priv->Rf_Mode == RF_OP_By_FW) {
 281                 if (BitMask != bMask12Bits) { // RF data is 12 bits only
 282                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 283                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 284                         New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift);
 285
 286                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 287                 } else {
 288                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 289                 }
 290
 291                 udelay(200);
 292
 293         } else {
 294                 if (BitMask != bMask12Bits) { // RF data is 12 bits only
 295                         Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
 296                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 297                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 298
 299                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 300                 } else {
 301                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 302                 }
 303         }
 304         return;
 305 }
 306
 307 /******************************************************************************
 308  *function:  This function reads specific bits from RF register
 309  *   input:  net_device dev
 310  *           u32        RegAddr  //target addr to be readback
 311  *           u32        BitMask  //taget bit pos in the addr to be readback
 312  *  output:  none
 313  *  return:  u32        Data    //the readback register value
 314  *  notice:
 315  * ****************************************************************************/
 316 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 317 {
 318         u32 Original_Value, Readback_Value, BitShift;
 319         struct r8192_priv *priv = ieee80211_priv(dev);
 320
 321
 322         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 323                 return 0;
 324         if (priv->Rf_Mode == RF_OP_By_FW) {
 325                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 326                 BitShift =  rtl8192_CalculateBitShift(BitMask);
 327                 Readback_Value = (Original_Value & BitMask) >> BitShift;
 328                 udelay(200);
 329                 return Readback_Value;
 330         } else {
 331                 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
 332                 BitShift =  rtl8192_CalculateBitShift(BitMask);
 333                 Readback_Value = (Original_Value & BitMask) >> BitShift;
 334                 return Readback_Value;
 335         }
 336 }
 337 /******************************************************************************
 338  *function:  We support firmware to execute RF-R/W.
 339  *   input:  dev
 340  *  output:  none
 341  *  return:  none
 342  *  notice:
 343  * ***************************************************************************/
 344 static  u32
 345 phy_FwRFSerialRead(
 346         struct net_device *dev,
 347         RF90_RADIO_PATH_E       eRFPath,
 348         u32                             Offset  )
 349 {
 350         u32             retValue = 0;
 351         u32             Data = 0;
 352         u8              time = 0;
 353         u32             tmp;
 354         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 355            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 356            much time. This is only for site survey. */
 357         // 1. Read operation need not insert data. bit 0-11
 358         // 2. Write RF register address. Bit 12-19
 359         Data |= ((Offset&0xFF)<<12);
 360         // 3. Write RF path.  bit 20-21
 361         Data |= ((eRFPath&0x3)<<20);
 362         // 4. Set RF read indicator. bit 22=0
 363         // 5. Trigger Fw to operate the command. bit 31
 364         Data |= 0x80000000;
 365         // 6. We can not execute read operation if bit 31 is 1.
 366         read_nic_dword(dev, QPNR, &tmp);
 367         while (tmp & 0x80000000) {
 368                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 369                 if (time++ < 100) {
 370                         udelay(10);
 371                         read_nic_dword(dev, QPNR, &tmp);
 372                 } else {
 373                         break;
 374                 }
 375         }
 376         // 7. Execute read operation.
 377         write_nic_dword(dev, QPNR, Data);
 378         // 8. Check if firmawre send back RF content.
 379         read_nic_dword(dev, QPNR, &tmp);
 380         while (tmp & 0x80000000) {
 381                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 382                 if (time++ < 100) {
 383                         udelay(10);
 384                         read_nic_dword(dev, QPNR, &tmp);
 385                 } else {
 386                         return 0;
 387                 }
 388         }
 389         read_nic_dword(dev, RF_DATA, &retValue);
 390
 391         return retValue;
 392
 393 }       /* phy_FwRFSerialRead */
 394
 395 /******************************************************************************
 396  *function:  We support firmware to execute RF-R/W.
 397  *   input:  dev
 398  *  output:  none
 399  *  return:  none
 400  *  notice:
 401  * ***************************************************************************/
 402 static void
 403 phy_FwRFSerialWrite(
 404                 struct net_device *dev,
 405                 RF90_RADIO_PATH_E       eRFPath,
 406                 u32                             Offset,
 407                 u32                             Data    )
 408 {
 409         u8      time = 0;
 410         u32     tmp;
 411
 412         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 413            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 414            much time. This is only for site survey. */
 415
 416         // 1. Set driver write bit and 12 bit data. bit 0-11
 417         // 2. Write RF register address. bit 12-19
 418         Data |= ((Offset&0xFF)<<12);
 419         // 3. Write RF path.  bit 20-21
 420         Data |= ((eRFPath&0x3)<<20);
 421         // 4. Set RF write indicator. bit 22=1
 422         Data |= 0x400000;
 423         // 5. Trigger Fw to operate the command. bit 31=1
 424         Data |= 0x80000000;
 425
 426         // 6. Write operation. We can not write if bit 31 is 1.
 427         read_nic_dword(dev, QPNR, &tmp);
 428         while (tmp & 0x80000000) {
 429                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 430                 if (time++ < 100) {
 431                         udelay(10);
 432                         read_nic_dword(dev, QPNR, &tmp);
 433                 } else {
 434                         break;
 435                 }
 436         }
 437         // 7. No matter check bit. We always force the write. Because FW will
 438         //    not accept the command.
 439         write_nic_dword(dev, QPNR, Data);
 440         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
 441            to finish RF write operation. */
 442         /* 2008/01/17 MH We support delay in firmware side now. */
 443
 444 }       /* phy_FwRFSerialWrite */
 445
 446
 447 /******************************************************************************
 448  *function:  This function read BB parameters from Header file we gen,
 449  *           and do register read/write
 450  *   input:  dev
 451  *  output:  none
 452  *  return:  none
 453  *  notice:  BB parameters may change all the time, so please make
 454  *           sure it has been synced with the newest.
 455  * ***************************************************************************/
 456 void rtl8192_phy_configmac(struct net_device *dev)
 457 {
 458         u32 dwArrayLen = 0, i;
 459         u32 *pdwArray = NULL;
 460         struct r8192_priv *priv = ieee80211_priv(dev);
 461
 462         if (priv->btxpowerdata_readfromEEPORM) {
 463                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 464                 dwArrayLen = MACPHY_Array_PGLength;
 465                 pdwArray = rtl819XMACPHY_Array_PG;
 466
 467         } else {
 468                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 469                 dwArrayLen = MACPHY_ArrayLength;
 470                 pdwArray = rtl819XMACPHY_Array;
 471         }
 472         for (i = 0; i<dwArrayLen; i=i+3) {
 473                 if (pdwArray[i] == 0x318) {
 474                         pdwArray[i+2] = 0x00000800;
 475                 }
 476
 477                 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
 478                                 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 479                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 480         }
 481         return;
 482
 483 }
 484
 485 /******************************************************************************
 486  *function:  This function does dirty work
 487  *   input:  dev
 488  *  output:  none
 489  *  return:  none
 490  *  notice:  BB parameters may change all the time, so please make
 491  *           sure it has been synced with the newest.
 492  * ***************************************************************************/
 493
 494 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 495 {
 496         u32 i;
 497
 498 #ifdef TO_DO_LIST
 499         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 500         if (Adapter->bInHctTest) {
 501                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 502                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 503                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 504                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 505         }
 506 #endif
 507         if (ConfigType == BaseBand_Config_PHY_REG) {
 508                 for (i=0; i<PHY_REG_1T2RArrayLength; i+=2) {
 509                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]);
 510                         RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]);
 511                 }
 512         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 513                 for (i=0; i<AGCTAB_ArrayLength; i+=2) {
 514                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 515                         RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]);
 516                 }
 517         }
 518         return;
 519
 520
 521 }
 522 /******************************************************************************
 523  *function:  This function initialize Register definition offset for Radio Path
 524  *           A/B/C/D
 525  *   input:  net_device dev
 526  *  output:  none
 527  *  return:  none
 528  *  notice:  Initialization value here is constant and it should never be changed
 529  * ***************************************************************************/
 530 void rtl8192_InitBBRFRegDef(struct net_device *dev)
 531 {
 532         struct r8192_priv *priv = ieee80211_priv(dev);
 533 // RF Interface Software Control
 534         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
 535         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
 536         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
 537         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
 538
 539         // RF Interface Readback Value
 540         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
 541         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
 542         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
 543         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
 544
 545         // RF Interface Output (and Enable)
 546         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
 547         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
 548         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
 549         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
 550
 551         // RF Interface (Output and)  Enable
 552         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
 553         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
 554         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
 555         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
 556
 557         //Addr of LSSI. Write RF register by driver
 558         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
 559         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 560         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 561         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 562
 563         // RF parameter
 564         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
 565         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 566         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 567         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 568
 569         // Tx AGC Gain Stage (same for all path. Should we remove this?)
 570         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 571         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 572         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 573         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 574
 575         // Tranceiver A~D HSSI Parameter-1
 576         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
 577         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
 578         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
 579         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
 580
 581         // Tranceiver A~D HSSI Parameter-2
 582         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
 583         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
 584         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
 585         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
 586
 587         // RF switch Control
 588         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
 589         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 590         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 591         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 592
 593         // AGC control 1
 594         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 595         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 596         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 597         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 598
 599         // AGC control 2
 600         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 601         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 602         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 603         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 604
 605         // RX AFE control 1
 606         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 607         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 608         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 609         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 610
 611         // RX AFE control 1
 612         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 613         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 614         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 615         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 616
 617         // Tx AFE control 1
 618         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 619         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 620         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 621         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 622
 623         // Tx AFE control 2
 624         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 625         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 626         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 627         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 628
 629         // Tranceiver LSSI Readback
 630         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 631         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 632         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 633         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 634
 635 }
 636 /******************************************************************************
 637  *function:  This function is to write register and then readback to make sure whether BB and RF is OK
 638  *   input:  net_device dev
 639  *           HW90_BLOCK_E CheckBlock
 640  *           RF90_RADIO_PATH_E eRFPath  //only used when checkblock is HW90_BLOCK_RF
 641  *  output:  none
 642  *  return:  return whether BB and RF is ok(0:OK; 1:Fail)
 643  *  notice:  This function may be removed in the ASIC
 644  * ***************************************************************************/
 645 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
 646 {
 647         u8 ret = 0;
 648         u32 i, CheckTimes = 4, dwRegRead = 0;
 649         u32 WriteAddr[4];
 650         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 651         // Initialize register address offset to be checked
 652         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 653         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 654         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 655         WriteAddr[HW90_BLOCK_RF] = 0x3;
 656         RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
 657         for (i=0 ; i < CheckTimes ; i++) {
 658
 659                 //
 660                 // Write Data to register and readback
 661                 //
 662                 switch (CheckBlock) {
 663                 case HW90_BLOCK_MAC:
 664                         RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
 665                         break;
 666
 667                 case HW90_BLOCK_PHY0:
 668                 case HW90_BLOCK_PHY1:
 669                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
 670                         read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
 671                         break;
 672
 673                 case HW90_BLOCK_RF:
 674                         WriteData[i] &= 0xfff;
 675                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
 676                         // TODO: we should not delay for such a long time. Ask SD3
 677                         msleep(1);
 678                         dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits);
 679                         msleep(1);
 680                         break;
 681
 682                 default:
 683                         ret = 1;
 684                         break;
 685                 }
 686
 687
 688                 //
 689                 // Check whether readback data is correct
 690                 //
 691                 if (dwRegRead != WriteData[i]) {
 692                         RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
 693                         ret = 1;
 694                         break;
 695                 }
 696         }
 697
 698         return ret;
 699 }
 700
 701
 702 /******************************************************************************
 703  *function:  This function initialize BB&RF
 704  *   input:  net_device dev
 705  *  output:  none
 706  *  return:  none
 707  *  notice:  Initialization value may change all the time, so please make
 708  *           sure it has been synced with the newest.
 709  * ***************************************************************************/
 710 void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 711 {
 712         struct r8192_priv *priv = ieee80211_priv(dev);
 713         u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0;
 714         u32 dwRegValue = 0;
 715         /**************************************
 716         //<1>Initialize BaseBand
 717         **************************************/
 718
 719         /*--set BB Global Reset--*/
 720         read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue);
 721         write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
 722         mdelay(50);
 723         /*---set BB reset Active---*/
 724         read_nic_dword(dev, CPU_GEN, &dwRegValue);
 725         write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
 726
 727         /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
 728         // TODO: this function should be removed on ASIC , Emily 2007.2.2
 729         for (eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) {
 730                 rtStatus  = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
 731                 if (rtStatus != 0) {
 732                         RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
 733                         return ;
 734                 }
 735         }
 736         /*---- Set CCK and OFDM Block "OFF"----*/
 737         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 738         /*----BB Register Initilazation----*/
 739         //==m==>Set PHY REG From Header<==m==
 740         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 741
 742         /*----Set BB reset de-Active----*/
 743         read_nic_dword(dev, CPU_GEN, &dwRegValue);
 744         write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
 745
 746         /*----BB AGC table Initialization----*/
 747         //==m==>Set PHY REG From Header<==m==
 748         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 749
 750         /*----Enable XSTAL ----*/
 751         write_nic_byte_E(dev, 0x5e, 0x00);
 752         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 753                 //Antenna gain offset from B/C/D to A
 754                 dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
 755                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);
 756
 757                 //XSTALLCap
 758                 dwRegValue = priv->CrystalCap & 0xf;
 759                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);
 760         }
 761
 762         // Check if the CCK HighPower is turned ON.
 763         // This is used to calculate PWDB.
 764         priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
 765         return;
 766 }
 767 /******************************************************************************
 768  *function:  This function initialize BB&RF
 769  *   input:  net_device dev
 770  *  output:  none
 771  *  return:  none
 772  *  notice:  Initialization value may change all the time, so please make
 773  *           sure it has been synced with the newest.
 774  * ***************************************************************************/
 775 void rtl8192_BBConfig(struct net_device *dev)
 776 {
 777         rtl8192_InitBBRFRegDef(dev);
 778         //config BB&RF. As hardCode based initialization has not been well
 779         //implemented, so use file first.FIXME:should implement it for hardcode?
 780         rtl8192_BB_Config_ParaFile(dev);
 781         return;
 782 }
 783
 784 /******************************************************************************
 785  *function:  This function obtains the initialization value of Tx power Level offset
 786  *   input:  net_device dev
 787  *  output:  none
 788  *  return:  none
 789  * ***************************************************************************/
 790 void rtl8192_phy_getTxPower(struct net_device *dev)
 791 {
 792         struct r8192_priv *priv = ieee80211_priv(dev);
 793         u8 tmp;
 794         read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]);
 795         read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]);
 796         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]);
 797         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]);
 798         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
 799         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
 800
 801         // read rx initial gain
 802         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 803         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 804         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 805         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 806         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
 807                 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 808                 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 809
 810         // read framesync
 811         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 812         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 813         priv->framesyncC34 = tmp;
 814         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 815                 rOFDM0_RxDetector3, priv->framesync);
 816
 817         // read SIFS (save the value read fome MACPHY_REG.txt)
 818         read_nic_word(dev, SIFS, &priv->SifsTime);
 819
 820         return;
 821 }
 822
 823 /******************************************************************************
 824  *function:  This function obtains the initialization value of Tx power Level offset
 825  *   input:  net_device dev
 826  *  output:  none
 827  *  return:  none
 828  * ***************************************************************************/
 829 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 830 {
 831         struct r8192_priv *priv = ieee80211_priv(dev);
 832         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 833         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 834
 835         switch (priv->rf_chip) {
 836         case RF_8256:
 837                 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
 838                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 839                 break;
 840         default:
 841                 RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__);
 842                 break;
 843         }
 844         return;
 845 }
 846
 847 /******************************************************************************
 848  *function:  This function check Rf chip to do RF config
 849  *   input:  net_device dev
 850  *  output:  none
 851  *  return:  only 8256 is supported
 852  * ***************************************************************************/
 853 void rtl8192_phy_RFConfig(struct net_device *dev)
 854 {
 855         struct r8192_priv *priv = ieee80211_priv(dev);
 856
 857         switch (priv->rf_chip) {
 858                 case RF_8256:
 859                         PHY_RF8256_Config(dev);
 860                         break;
 861                 default:
 862                         RT_TRACE(COMP_ERR, "error chip id\n");
 863                         break;
 864         }
 865         return;
 866 }
 867
 868 /******************************************************************************
 869  *function:  This function update Initial gain
 870  *   input:  net_device dev
 871  *  output:  none
 872  *  return:  As Windows has not implemented this, wait for complement
 873  * ***************************************************************************/
 874 void rtl8192_phy_updateInitGain(struct net_device *dev)
 875 {
 876         return;
 877 }
 878
 879 /******************************************************************************
 880  *function:  This function read RF parameters from general head file, and do RF 3-wire
 881  *   input:  net_device dev
 882  *  output:  none
 883  *  return:  return code show if RF configuration is successful(0:pass, 1:fail)
 884  *    Note:  Delay may be required for RF configuration
 885  * ***************************************************************************/
 886 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E eRFPath)
 887 {
 888
 889         int i;
 890         u8 ret = 0;
 891
 892         switch (eRFPath) {
 893         case RF90_PATH_A:
 894                 for (i = 0;i<RadioA_ArrayLength; i=i+2) {
 895
 896                         if (rtl819XRadioA_Array[i] == 0xfe) {
 897                                         mdelay(100);
 898                                         continue;
 899                         }
 900                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]);
 901                         mdelay(1);
 902
 903                 }
 904                 break;
 905         case RF90_PATH_B:
 906                 for (i = 0;i<RadioB_ArrayLength; i=i+2) {
 907
 908                         if (rtl819XRadioB_Array[i] == 0xfe) {
 909                                         mdelay(100);
 910                                         continue;
 911                         }
 912                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]);
 913                         mdelay(1);
 914
 915                 }
 916                 break;
 917         case RF90_PATH_C:
 918                 for (i = 0;i<RadioC_ArrayLength; i=i+2) {
 919
 920                         if (rtl819XRadioC_Array[i] == 0xfe) {
 921                                         mdelay(100);
 922                                         continue;
 923                         }
 924                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]);
 925                         mdelay(1);
 926
 927                 }
 928                 break;
 929         case RF90_PATH_D:
 930                 for (i = 0;i<RadioD_ArrayLength; i=i+2) {
 931
 932                         if (rtl819XRadioD_Array[i] == 0xfe) {
 933                                         mdelay(100);
 934                                         continue;
 935                         }
 936                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]);
 937                         mdelay(1);
 938
 939                 }
 940                 break;
 941         default:
 942                 break;
 943         }
 944
 945         return ret;
 946
 947 }
 948 /******************************************************************************
 949  *function:  This function set Tx Power of the channel
 950  *   input:  struct net_device *dev
 951  *           u8                 channel
 952  *  output:  none
 953  *  return:  none
 954  *    Note:
 955  * ***************************************************************************/
 956 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
 957 {
 958         struct r8192_priv *priv = ieee80211_priv(dev);
 959         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 960         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 961
 962         switch (priv->rf_chip) {
 963         case RF_8225:
 964 #ifdef TO_DO_LIST
 965                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
 966                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
 967 #endif
 968                 break;
 969
 970         case RF_8256:
 971                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 972                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 973                 break;
 974
 975         case RF_8258:
 976                 break;
 977         default:
 978                 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
 979                 break;
 980         }
 981         return;
 982 }
 983
 984 /******************************************************************************
 985  *function:  This function set RF state on or off
 986  *   input:  struct net_device *dev
 987  *           RT_RF_POWER_STATE eRFPowerState  //Power State to set
 988  *  output:  none
 989  *  return:  none
 990  *    Note:
 991  * ***************************************************************************/
 992 bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
 993 {
 994         bool                            bResult = true;
 995         struct r8192_priv *priv = ieee80211_priv(dev);
 996
 997         if (eRFPowerState == priv->ieee80211->eRFPowerState)
 998                 return false;
 999
1000         if (priv->SetRFPowerStateInProgress == true)
1001                 return false;
1002
1003         priv->SetRFPowerStateInProgress = true;
1004
1005         switch (priv->rf_chip) {
1006                 case RF_8256:
1007                 switch ( eRFPowerState ) {
1008                         case eRfOn:
1009         //RF-A, RF-B
1010                                         //enable RF-Chip A/B
1011                                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);      // 0x860[4]
1012                                         //analog to digital on
1013                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1014                                         //digital to analog on
1015                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
1016                                         //rx antenna on
1017                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
1018                                         //rx antenna on
1019                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
1020                                         //analog to digital part2 on
1021                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
1022
1023                                 break;
1024
1025                         case eRfSleep:
1026
1027                                 break;
1028
1029                         case eRfOff:
1030                                         //RF-A, RF-B
1031                                         //disable RF-Chip A/B
1032                                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);      // 0x860[4]
1033                                         //analog to digital off, for power save
1034                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1035                                         //digital to analog off, for power save
1036                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3]
1037                                         //rx antenna off
1038                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0]
1039                                         //rx antenna off
1040                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0]
1041                                         //analog to digital part2 off, for power save
1042                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
1043
1044                                 break;
1045
1046                         default:
1047                                 bResult = false;
1048                                 RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1049                                 break;
1050                 }
1051                         break;
1052                 default:
1053                         RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1054                         break;
1055         }
1056 #ifdef TO_DO_LIST
1057         if (bResult) {
1058                 // Update current RF state variable.
1059                 pHalData->eRFPowerState = eRFPowerState;
1060                 switch (pHalData->RFChipID ) {
1061                         case RF_8256:
1062                 switch (pHalData->eRFPowerState) {
1063                                 case eRfOff:
1064                                         //
1065                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1066                                         //
1067                                         if (pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1068                                                 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
1069                                         else
1070                                                 // Turn off LED if RF is not ON.
1071                                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1072                                         break;
1073
1074                                 case eRfOn:
1075                                         // Turn on RF we are still linked, which might happen when
1076                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1077                                         if ( pMgntInfo->bMediaConnect == TRUE )
1078                                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1079                                         else
1080                                                 // Turn off LED if RF is not ON.
1081                                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1082                                         break;
1083
1084                                 default:
1085                                         // do nothing.
1086                                         break;
1087                                 }// Switch RF state
1088                                 break;
1089
1090                                 default:
1091                                         RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n"));
1092                                         break;
1093                         }
1094
1095         }
1096 #endif
1097         priv->SetRFPowerStateInProgress = false;
1098
1099         return bResult;
1100 }
1101
1102 /****************************************************************************************
1103  *function:  This function set command table variable(struct SwChnlCmd).
1104  *   input:  SwChnlCmd*         CmdTable        //table to be set.
1105  *           u32                CmdTableIdx     //variable index in table to be set
1106  *           u32                CmdTableSz      //table size.
1107  *           SwChnlCmdID        CmdID           //command ID to set.
1108  *           u32                Para1
1109  *           u32                Para2
1110  *           u32                msDelay
1111  *  output:
1112  *  return:  true if finished, false otherwise
1113  *    Note:
1114  * ************************************************************************************/
1115 u8 rtl8192_phy_SetSwChnlCmdArray(
1116         SwChnlCmd               *CmdTable,
1117         u32                     CmdTableIdx,
1118         u32                     CmdTableSz,
1119         SwChnlCmdID             CmdID,
1120         u32                     Para1,
1121         u32                     Para2,
1122         u32                     msDelay
1123         )
1124 {
1125         SwChnlCmd *pCmd;
1126
1127         if (CmdTable == NULL) {
1128                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1129                 return false;
1130         }
1131         if (CmdTableIdx >= CmdTableSz) {
1132                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1133                                 CmdTableIdx, CmdTableSz);
1134                 return false;
1135         }
1136
1137         pCmd = CmdTable + CmdTableIdx;
1138         pCmd->CmdID = CmdID;
1139         pCmd->Para1 = Para1;
1140         pCmd->Para2 = Para2;
1141         pCmd->msDelay = msDelay;
1142
1143         return true;
1144 }
1145 /******************************************************************************
1146  *function:  This function set channel step by step
1147  *   input:  struct net_device *dev
1148  *           u8                 channel
1149  *           u8*                stage //3 stages
1150  *           u8*                step  //
1151  *           u32*               delay //whether need to delay
1152  *  output:  store new stage, step and delay for next step(combine with function above)
1153  *  return:  true if finished, false otherwise
1154  *    Note:  Wait for simpler function to replace it //wb
1155  * ***************************************************************************/
1156 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u8 *step, u32 *delay)
1157 {
1158         struct r8192_priv *priv = ieee80211_priv(dev);
1159         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
1160         u32                                     PreCommonCmdCnt;
1161         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
1162         u32                                     PostCommonCmdCnt;
1163         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
1164         u32                                     RfDependCmdCnt;
1165         SwChnlCmd                               *CurrentCmd = NULL;
1166         u8              eRFPath;
1167
1168         RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1169         if (!IsLegalChannel(priv->ieee80211, channel)) {
1170                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1171                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1172         }
1173 //FIXME:need to check whether channel is legal or not here.WB
1174
1175
1176                 // <1> Fill up pre common command.
1177                 PreCommonCmdCnt = 0;
1178                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1179                                         CmdID_SetTxPowerLevel, 0, 0, 0);
1180                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1181                                         CmdID_End, 0, 0, 0);
1182
1183                 // <2> Fill up post common command.
1184                 PostCommonCmdCnt = 0;
1185
1186                 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1187                                         CmdID_End, 0, 0, 0);
1188
1189                 // <3> Fill up RF dependent command.
1190                 RfDependCmdCnt = 0;
1191                 switch ( priv->rf_chip ) {
1192                 case RF_8225:
1193                         if (!(channel >= 1 && channel <= 14)) {
1194                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
1195                                 return true;
1196                         }
1197                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1198                                 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
1199                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1200                                 CmdID_End, 0, 0, 0);
1201                         break;
1202
1203                 case RF_8256:
1204                         // TEST!! This is not the table for 8256!!
1205                         if (!(channel >= 1 && channel <= 14)) {
1206                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1207                                 return true;
1208                         }
1209                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1210                                 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1211                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1212                         CmdID_End, 0, 0, 0);
1213                         break;
1214
1215                 case RF_8258:
1216                         break;
1217
1218                 default:
1219                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1220                         return true;
1221                         break;
1222                 }
1223
1224
1225                 do {
1226                         switch (*stage) {
1227                         case 0:
1228                                 CurrentCmd=&PreCommonCmd[*step];
1229                                 break;
1230                         case 1:
1231                                 CurrentCmd=&RfDependCmd[*step];
1232                                 break;
1233                         case 2:
1234                                 CurrentCmd=&PostCommonCmd[*step];
1235                                 break;
1236                         }
1237
1238                         if (CurrentCmd->CmdID==CmdID_End) {
1239                                 if ((*stage)==2) {
1240                                         (*delay)=CurrentCmd->msDelay;
1241                                         return true;
1242                                 } else {
1243                                         (*stage)++;
1244                                         (*step)=0;
1245                                         continue;
1246                                 }
1247                         }
1248
1249                         switch (CurrentCmd->CmdID) {
1250                         case CmdID_SetTxPowerLevel:
1251                                 if (priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
1252                                         rtl8192_SetTxPowerLevel(dev,channel);
1253                                 break;
1254                         case CmdID_WritePortUlong:
1255                                 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
1256                                 break;
1257                         case CmdID_WritePortUshort:
1258                                 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1259                                 break;
1260                         case CmdID_WritePortUchar:
1261                                 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1262                                 break;
1263                         case CmdID_RF_WriteReg:
1264                                 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1265                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2);
1266                                 }
1267                                 break;
1268                         default:
1269                                 break;
1270                         }
1271
1272                         break;
1273                 } while (true);
1274
1275         (*delay)=CurrentCmd->msDelay;
1276         (*step)++;
1277         return false;
1278 }
1279
1280 /******************************************************************************
1281  *function:  This function does actually set channel work
1282  *   input:  struct net_device *dev
1283  *           u8                 channel
1284  *  output:  none
1285  *  return:  noin
1286  *    Note:  We should not call this function directly
1287  * ***************************************************************************/
1288 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1289 {
1290         struct r8192_priv *priv = ieee80211_priv(dev);
1291         u32     delay = 0;
1292
1293         while (!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) {
1294                 if (!priv->up)
1295                         break;
1296         }
1297 }
1298 /******************************************************************************
1299  *function:  Callback routine of the work item for switch channel.
1300  *   input:
1301  *
1302  *  output:  none
1303  *  return:  noin
1304  * ***************************************************************************/
1305 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1306 {
1307
1308         struct r8192_priv *priv = ieee80211_priv(dev);
1309
1310         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan);
1311
1312
1313         rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1314
1315         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1316 }
1317
1318 /******************************************************************************
1319  *function:  This function scheduled actual work item to set channel
1320  *   input:  net_device dev
1321  *           u8         channel //channel to set
1322  *  output:  none
1323  *  return:  return code show if workitem is scheduled(1:pass, 0:fail)
1324  *    Note:  Delay may be required for RF configuration
1325  * ***************************************************************************/
1326 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1327 {
1328         struct r8192_priv *priv = ieee80211_priv(dev);
1329         RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress);
1330         if (!priv->up)
1331                 return false;
1332         if (priv->SwChnlInProgress)
1333                 return false;
1334
1335         //--------------------------------------------
1336         switch (priv->ieee80211->mode) {
1337         case WIRELESS_MODE_A:
1338         case WIRELESS_MODE_N_5G:
1339                 if (channel<=14) {
1340                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1341                         return false;
1342                 }
1343                 break;
1344         case WIRELESS_MODE_B:
1345                 if (channel>14) {
1346                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1347                         return false;
1348                 }
1349                 break;
1350         case WIRELESS_MODE_G:
1351         case WIRELESS_MODE_N_24G:
1352                 if (channel>14) {
1353                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1354                         return false;
1355                 }
1356                 break;
1357         }
1358         //--------------------------------------------
1359
1360         priv->SwChnlInProgress = true;
1361         if (channel == 0)
1362                 channel = 1;
1363
1364         priv->chan=channel;
1365
1366         priv->SwChnlStage=0;
1367         priv->SwChnlStep=0;
1368         if (priv->up)
1369         rtl8192_SwChnl_WorkItem(dev);
1370
1371         priv->SwChnlInProgress = false;
1372         return true;
1373 }
1374
1375
1376 //
1377 /******************************************************************************
1378  *function:  Callback routine of the work item for set bandwidth mode.
1379  *   input:  struct net_device *dev
1380  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
1381  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
1382  *  output:  none
1383  *  return:  none
1384  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
1385  *           test whether current work in the queue or not.//do I?
1386  * ***************************************************************************/
1387 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1388 {
1389
1390         struct r8192_priv *priv = ieee80211_priv(dev);
1391         u8 regBwOpMode;
1392
1393         RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem()  Switch to %s bandwidth\n", \
1394                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1395
1396
1397         if (priv->rf_chip == RF_PSEUDO_11N) {
1398                 priv->SetBWModeInProgress= false;
1399                 return;
1400         }
1401
1402         //<1>Set MAC register
1403         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1404
1405         switch (priv->CurrentChannelBW) {
1406                 case HT_CHANNEL_WIDTH_20:
1407                         regBwOpMode |= BW_OPMODE_20MHZ;
1408                        // 2007/02/07 Mark by Emily because we have not verify whether this register works
1409                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1410                         break;
1411
1412                 case HT_CHANNEL_WIDTH_20_40:
1413                         regBwOpMode &= ~BW_OPMODE_20MHZ;
1414                         // 2007/02/07 Mark by Emily because we have not verify whether this register works
1415                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1416                         break;
1417
1418                 default:
1419                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
1420                         break;
1421         }
1422
1423         //<2>Set PHY related register
1424         switch (priv->CurrentChannelBW) {
1425                 case HT_CHANNEL_WIDTH_20:
1426                         // Add by Vivi 20071119
1427                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1428                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1429                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1430
1431                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
1432                         priv->cck_present_attentuation =
1433                                 priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
1434
1435                         if (priv->cck_present_attentuation > 22)
1436                                 priv->cck_present_attentuation= 22;
1437                         if (priv->cck_present_attentuation< 0)
1438                                 priv->cck_present_attentuation = 0;
1439                         RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1440
1441                         if (priv->chan == 14 && !priv->bcck_in_ch14) {
1442                                 priv->bcck_in_ch14 = TRUE;
1443                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1444                         } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1445                                 priv->bcck_in_ch14 = FALSE;
1446                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1447                         } else {
1448                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1449                         }
1450
1451                         break;
1452                 case HT_CHANNEL_WIDTH_20_40:
1453                         // Add by Vivi 20071119
1454                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1455                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1456                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
1457                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1458                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
1459                         priv->cck_present_attentuation =
1460                                 priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
1461
1462                         if (priv->cck_present_attentuation > 22)
1463                                 priv->cck_present_attentuation = 22;
1464                         if (priv->cck_present_attentuation < 0)
1465                                 priv->cck_present_attentuation = 0;
1466
1467                         RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1468                         if (priv->chan == 14 && !priv->bcck_in_ch14) {
1469                                 priv->bcck_in_ch14 = true;
1470                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1471                         } else if (priv->chan!= 14 && priv->bcck_in_ch14) {
1472                                 priv->bcck_in_ch14 = false;
1473                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1474                         } else {
1475                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1476                         }
1477
1478                         break;
1479                 default:
1480                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
1481                         break;
1482
1483         }
1484         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
1485
1486         //<3>Set RF related register
1487         switch ( priv->rf_chip ) {
1488                 case RF_8225:
1489 #ifdef TO_DO_LIST
1490                         PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1491 #endif
1492                         break;
1493
1494                 case RF_8256:
1495                         PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1496                         break;
1497
1498                 case RF_8258:
1499                         // PHY_SetRF8258Bandwidth();
1500                         break;
1501
1502                 case RF_PSEUDO_11N:
1503                         // Do Nothing
1504                         break;
1505
1506                 default:
1507                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1508                         break;
1509         }
1510         priv->SetBWModeInProgress= false;
1511
1512         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) );
1513 }
1514
1515 /******************************************************************************
1516  *function:  This function schedules bandwidth switch work.
1517  *   input:  struct net_device *dev
1518  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
1519  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
1520  *  output:  none
1521  *  return:  none
1522  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
1523  *           test whether current work in the queue or not.//do I?
1524  * ***************************************************************************/
1525 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
1526 {
1527         struct r8192_priv *priv = ieee80211_priv(dev);
1528
1529         if (priv->SetBWModeInProgress)
1530                 return;
1531         priv->SetBWModeInProgress= true;
1532
1533         priv->CurrentChannelBW = Bandwidth;
1534
1535         if (Offset==HT_EXTCHNL_OFFSET_LOWER)
1536                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1537         else if (Offset==HT_EXTCHNL_OFFSET_UPPER)
1538                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1539         else
1540                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1541
1542         rtl8192_SetBWModeWorkItem(dev);
1543
1544 }
1545
1546 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1547 {
1548         struct r8192_priv *priv = ieee80211_priv(dev);
1549
1550         priv->InitialGainOperateType = Operation;
1551
1552         if (priv->up)
1553                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
1554 }
1555
1556 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1557 {
1558         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1559        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
1560        struct net_device *dev = priv->ieee80211->dev;
1561 #define SCAN_RX_INITIAL_GAIN    0x17
1562 #define POWER_DETECTION_TH      0x08
1563         u32     BitMask;
1564         u8      initial_gain;
1565         u8      Operation;
1566
1567         Operation = priv->InitialGainOperateType;
1568
1569         switch (Operation) {
1570                 case IG_Backup:
1571                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1572                         initial_gain = SCAN_RX_INITIAL_GAIN;
1573                         BitMask = bMaskByte0;
1574                         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1575                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
1576                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
1577                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1578                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
1579                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1580                         BitMask  = bMaskByte2;
1581                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
1582
1583                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1584                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1585                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1586                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1587                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1588
1589                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
1590                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1591                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1592                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1593                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1594                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
1595                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1596                         break;
1597                 case IG_Restore:
1598                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1599                         BitMask = 0x7f; //Bit0~ Bit6
1600                         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1601                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
1602
1603                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
1604                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
1605                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
1606                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
1607                         BitMask  = bMaskByte2;
1608                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
1609
1610                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1611                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1612                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1613                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1614                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1615
1616 #ifdef RTL8190P
1617                         SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1618 #endif
1619 #ifdef RTL8192E
1620                         SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1621 #endif
1622                         rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
1623
1624                         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1625                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
1626                         break;
1627                 default:
1628                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1629                         break;
1630         }
1631 }