drivers/staging/rtl8723au/include/odm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16
  17 #ifndef __HALDMOUTSRC_H__
  18 #define __HALDMOUTSRC_H__
  19
  20 /*  */
  21 /*  Definition */
  22 /*  */
  23 /*  */
  24 /*  2011/09/22 MH Define all team supprt ability. */
  25 /*  */
  26
  27 /*  */
  28 /*  2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */
  29 /*  */
  30 /* define               DM_ODM_SUPPORT_AP                       0 */
  31 /* define               DM_ODM_SUPPORT_ADSL                     0 */
  32 /* define               DM_ODM_SUPPORT_CE                       0 */
  33 /* define               DM_ODM_SUPPORT_MP                       1 */
  34
  35 #define TP_MODE         0
  36 #define RSSI_MODE               1
  37 #define TRAFFIC_LOW     0
  38 #define TRAFFIC_HIGH    1
  39
  40
  41 /*  */
  42 /* 3 Tx Power Tracking */
  43 /* 3============================================================ */
  44 #define         DPK_DELTA_MAPPING_NUM   13
  45 #define         index_mapping_HP_NUM    15
  46
  47
  48 /*  */
  49 /* 3 PSD Handler */
  50 /* 3============================================================ */
  51
  52 #define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  53 #define MODE_40M                0       /* 0:20M, 1:40M */
  54 #define PSD_TH2         3
  55 #define PSD_CHMIN               20   /*  Minimum channel number for BT AFH */
  56 #define SIR_STEP_SIZE   3
  57 #define   Smooth_Size_1         5
  58 #define Smooth_TH_1     3
  59 #define   Smooth_Size_2         10
  60 #define Smooth_TH_2     4
  61 #define   Smooth_Size_3         20
  62 #define Smooth_TH_3     4
  63 #define   Smooth_Step_Size 5
  64 #define Adaptive_SIR    1
  65 #define PSD_RESCAN              4
  66 #define PSD_SCAN_INTERVAL       700 /* ms */
  67
  68 /* 8723A High Power IGI Setting */
  69 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  70 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  71 #define DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  72
  73 /*  LPS define */
  74 #define DM_DIG_FA_TH0_LPS                               4 /*  4 in lps */
  75 #define DM_DIG_FA_TH1_LPS                               15 /*  15 lps */
  76 #define DM_DIG_FA_TH2_LPS                               30 /*  30 lps */
  77 #define RSSI_OFFSET_DIG                                 0x05;
  78
  79 /* ANT Test */
  80 #define                 ANTTESTALL              0x00            /* Ant A or B will be Testing */
  81 #define         ANTTESTA                0x01            /* Ant A will be Testing */
  82 #define         ANTTESTB                0x02            /* Ant B will be testing */
  83
  84
  85 /*  */
  86 /*  structure and define */
  87 /*  */
  88
  89 struct  dig_t {
  90         u8              Dig_Enable_Flag;
  91         u8              Dig_Ext_Port_Stage;
  92
  93         int             RssiLowThresh;
  94         int             RssiHighThresh;
  95
  96         u32             FALowThresh;
  97         u32             FAHighThresh;
  98
  99         u8              CurSTAConnectState;
 100         u8              PreSTAConnectState;
 101         u8              CurMultiSTAConnectState;
 102
 103         u8              PreIGValue;
 104         u8              CurIGValue;
 105         u8              BackupIGValue;
 106
 107         s8              BackoffVal;
 108         s8              BackoffVal_range_max;
 109         s8              BackoffVal_range_min;
 110         u8              rx_gain_range_max;
 111         u8              rx_gain_range_min;
 112         u8              Rssi_val_min;
 113
 114         u8              PreCCK_CCAThres;
 115         u8              CurCCK_CCAThres;
 116         u8              PreCCKPDState;
 117         u8              CurCCKPDState;
 118
 119         u8              LargeFAHit;
 120         u8              ForbiddenIGI;
 121         u32             Recover_cnt;
 122
 123         u8              DIG_Dynamic_MIN_0;
 124         u8              DIG_Dynamic_MIN_1;
 125         bool            bMediaConnect_0;
 126         bool            bMediaConnect_1;
 127
 128         u32             AntDiv_RSSI_max;
 129         u32             RSSI_max;
 130 };
 131
 132 struct dynamic_pwr_sav {
 133         u8              PreCCAState;
 134         u8              CurCCAState;
 135
 136         u8              PreRFState;
 137         u8              CurRFState;
 138
 139         int                 Rssi_val_min;
 140
 141         u8              initialize;
 142         u32             Reg874,RegC70,Reg85C,RegA74;
 143 };
 144
 145 struct false_alarm_stats {
 146         u32     Cnt_Parity_Fail;
 147         u32     Cnt_Rate_Illegal;
 148         u32     Cnt_Crc8_fail;
 149         u32     Cnt_Mcs_fail;
 150         u32     Cnt_Ofdm_fail;
 151         u32     Cnt_Cck_fail;
 152         u32     Cnt_all;
 153         u32     Cnt_Fast_Fsync;
 154         u32     Cnt_SB_Search_fail;
 155         u32     Cnt_OFDM_CCA;
 156         u32     Cnt_CCK_CCA;
 157         u32     Cnt_CCA_all;
 158         u32     Cnt_BW_USC;     /* Gary */
 159         u32     Cnt_BW_LSC;     /* Gary */
 160 };
 161
 162 struct pri_cca {
 163         u8              PriCCA_flag;
 164         u8              intf_flag;
 165         u8              intf_type;
 166         u8              DupRTS_flag;
 167         u8              Monitor_flag;
 168 };
 169
 170 struct rx_hp {
 171         u8              RXHP_flag;
 172         u8              PSD_func_trigger;
 173         u8              PSD_bitmap_RXHP[80];
 174         u8              Pre_IGI;
 175         u8              Cur_IGI;
 176         u8              Pre_pw_th;
 177         u8              Cur_pw_th;
 178         bool            First_time_enter;
 179         bool            RXHP_enable;
 180         u8              TP_Mode;
 181 };
 182
 183 #define ASSOCIATE_ENTRY_NUM                                     32 /*  Max size of AsocEntry[]. */
 184 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM
 185
 186 /*  This indicates two different the steps. */
 187 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
 188 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
 189 /*  with original RSSI to determine if it is necessary to switch antenna. */
 190 #define SWAW_STEP_PEAK          0
 191 #define SWAW_STEP_DETERMINE     1
 192
 193 #define TP_MODE         0
 194 #define RSSI_MODE               1
 195 #define TRAFFIC_LOW     0
 196 #define TRAFFIC_HIGH    1
 197
 198 struct sw_ant_sw {
 199         u8              try_flag;
 200         s32             PreRSSI;
 201         u8              CurAntenna;
 202         u8              PreAntenna;
 203         u8              RSSI_Trying;
 204         u8              TestMode;
 205         u8              bTriggerAntennaSwitch;
 206         u8              SelectAntennaMap;
 207         u8              RSSI_target;
 208
 209         /*  Before link Antenna Switch check */
 210         u8              SWAS_NoLink_State;
 211         u32             SWAS_NoLink_BK_Reg860;
 212         bool            ANTA_ON;        /* To indicate Ant A is or not */
 213         bool            ANTB_ON;        /* To indicate Ant B is on or not */
 214
 215         s32             RSSI_sum_A;
 216         s32             RSSI_sum_B;
 217         s32             RSSI_cnt_A;
 218         s32             RSSI_cnt_B;
 219
 220         u64             lastTxOkCnt;
 221         u64             lastRxOkCnt;
 222         u64             TXByteCnt_A;
 223         u64             TXByteCnt_B;
 224         u64             RXByteCnt_A;
 225         u64             RXByteCnt_B;
 226         u8              TrafficLoad;
 227 };
 228
 229 struct edca_turbo {
 230         bool bCurrentTurboEDCA;
 231         bool bIsCurRDLState;
 232         u32     prv_traffic_idx; /*  edca turbo */
 233 };
 234
 235 struct odm_rate_adapt {
 236         u8      Type;           /*  DM_Type_ByFW/DM_Type_ByDriver */
 237         u8      HighRSSIThresh; /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 238         u8      LowRSSIThresh;  /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 239         u8      RATRState;      /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 240         u32     LastRATR;       /*  RATR Register Content */
 241 };
 242
 243 #define IQK_MAC_REG_NUM         4
 244 #define IQK_ADDA_REG_NUM                16
 245 #define IQK_BB_REG_NUM_MAX      10
 246 #define IQK_BB_REG_NUM          9
 247 #define HP_THERMAL_NUM          8
 248
 249 #define AVG_THERMAL_NUM         8
 250 #define IQK_Matrix_REG_NUM      8
 251 #define IQK_Matrix_Settings_NUM 1+24+21
 252
 253 #define         DM_Type_ByFW                    0
 254 #define         DM_Type_ByDriver                1
 255
 256 /*  Declare for common info */
 257
 258 struct odm_phy_dbg_info {
 259         /* ODM Write,debug info */
 260         s8              RxSNRdB[RF_PATH_MAX];
 261         u64             NumQryPhyStatus;
 262         u64             NumQryPhyStatusCCK;
 263         u64             NumQryPhyStatusOFDM;
 264         /* Others */
 265         s32             RxEVM[RF_PATH_MAX];
 266
 267 };
 268
 269 struct odm_packet_info {
 270         u8              Rate;
 271         u8              StationID;
 272         bool            bPacketMatchBSSID;
 273         bool            bPacketToSelf;
 274         bool            bPacketBeacon;
 275 };
 276
 277
 278 enum {
 279         /*  BB Team */
 280         ODM_DIG                 = 0x00000001,
 281         ODM_HIGH_POWER          = 0x00000002,
 282         ODM_CCK_CCA_TH          = 0x00000004,
 283         ODM_FA_STATISTICS       = 0x00000008,
 284         ODM_RAMASK              = 0x00000010,
 285         ODM_RSSI_MONITOR        = 0x00000020,
 286         ODM_SW_ANTDIV           = 0x00000040,
 287         ODM_HW_ANTDIV           = 0x00000080,
 288         ODM_BB_PWRSV            = 0x00000100,
 289         ODM_2TPATHDIV           = 0x00000200,
 290         ODM_1TPATHDIV           = 0x00000400,
 291         ODM_PSD2AFH             = 0x00000800
 292 };
 293
 294 /*  */
 295 /*  2011/10/20 MH Define Common info enum for all team. */
 296 /*  */
 297
 298 enum odm_cmninfo {
 299         /*  Fixed value: */
 300         /*  */
 301
 302         ODM_CMNINFO_PLATFORM = 0,
 303         ODM_CMNINFO_ABILITY,                                    /*  enum odm_ability */
 304         ODM_CMNINFO_INTERFACE,                          /*  enum odm_interface_def */
 305         ODM_CMNINFO_MP_TEST_CHIP,
 306         ODM_CMNINFO_IC_TYPE,                                    /*  enum odm_ic_type_def */
 307         ODM_CMNINFO_CUT_VER,                                    /*  enum odm_cut_version */
 308         ODM_CMNINFO_FAB_VER,                                    /*  enum odm_fab_version */
 309         ODM_CMNINFO_RF_TYPE,                                    /*  enum rf_path_def or enum odm_rf_type? */
 310         ODM_CMNINFO_BOARD_TYPE,                         /*  enum odm_board_type */
 311         ODM_CMNINFO_EXT_LNA,                                    /*  true */
 312         ODM_CMNINFO_EXT_PA,
 313         ODM_CMNINFO_EXT_TRSW,
 314         ODM_CMNINFO_PATCH_ID,                           /* CUSTOMER ID */
 315         ODM_CMNINFO_BINHCT_TEST,
 316         ODM_CMNINFO_BWIFI_TEST,
 317         ODM_CMNINFO_SMART_CONCURRENT,
 318
 319
 320         /*  */
 321         /*  Dynamic value: */
 322         /*  */
 323         ODM_CMNINFO_MAC_PHY_MODE,                       /*  enum odm_mac_phy_mode */
 324         ODM_CMNINFO_TX_UNI,
 325         ODM_CMNINFO_RX_UNI,
 326         ODM_CMNINFO_WM_MODE,                            /*  enum odm_wireless_mode */
 327         ODM_CMNINFO_BAND,                                       /*  enum odm_band_type */
 328         ODM_CMNINFO_SEC_CHNL_OFFSET,            /*  enum odm_sec_chnl_offset */
 329         ODM_CMNINFO_SEC_MODE,                           /*  enum odm_security */
 330         ODM_CMNINFO_BW,                                         /*  enum odm_band_width */
 331         ODM_CMNINFO_CHNL,
 332
 333         ODM_CMNINFO_DMSP_GET_VALUE,
 334         ODM_CMNINFO_BUDDY_ADAPTOR,
 335         ODM_CMNINFO_DMSP_IS_MASTER,
 336         ODM_CMNINFO_SCAN,
 337         ODM_CMNINFO_POWER_SAVING,
 338         ODM_CMNINFO_ONE_PATH_CCA,                       /*  enum odm_cca_path */
 339         ODM_CMNINFO_DRV_STOP,
 340         ODM_CMNINFO_PNP_IN,
 341         ODM_CMNINFO_INIT_ON,
 342         ODM_CMNINFO_ANT_TEST,
 343         ODM_CMNINFO_NET_CLOSED,
 344         ODM_CMNINFO_MP_MODE,
 345
 346         ODM_CMNINFO_WIFI_DIRECT,
 347         ODM_CMNINFO_WIFI_DISPLAY,
 348         ODM_CMNINFO_LINK,
 349         ODM_CMNINFO_RSSI_MIN,
 350         ODM_CMNINFO_DBG_COMP,                           /*  u64 */
 351         ODM_CMNINFO_DBG_LEVEL,                          /*  u32 */
 352         ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 353         ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 354         ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 355         ODM_CMNINFO_BT_DISABLED,
 356         ODM_CMNINFO_BT_OPERATION,
 357         ODM_CMNINFO_BT_DIG,
 358         ODM_CMNINFO_BT_BUSY,                                    /* Check Bt is using or not */
 359         ODM_CMNINFO_BT_DISABLE_EDCA,
 360
 361         /*  */
 362         /*  Dynamic ptr array hook itms. */
 363         /*  */
 364         ODM_CMNINFO_STA_STATUS,
 365         ODM_CMNINFO_PHY_STATUS,
 366         ODM_CMNINFO_MAC_STATUS,
 367
 368         ODM_CMNINFO_MAX,
 369 };
 370
 371 /*  Define ODM support ability.  ODM_CMNINFO_ABILITY */
 372 enum {
 373         /*  BB ODM section BIT 0-15 */
 374         ODM_BB_DIG                              = BIT0,
 375         ODM_BB_RA_MASK                          = BIT1,
 376         ODM_BB_DYNAMIC_TXPWR                    = BIT2,
 377         ODM_BB_FA_CNT                           = BIT3,
 378         ODM_BB_RSSI_MONITOR                     = BIT4,
 379         ODM_BB_CCK_PD                           = BIT5,
 380         ODM_BB_ANT_DIV                          = BIT6,
 381         ODM_BB_PWR_SAVE                         = BIT7,
 382         ODM_BB_PWR_TRAIN                        = BIT8,
 383         ODM_BB_RATE_ADAPTIVE                    = BIT9,
 384         ODM_BB_PATH_DIV                         = BIT10,
 385         ODM_BB_PSD                              = BIT11,
 386         ODM_BB_RXHP                             = BIT12,
 387
 388         /*  MAC DM section BIT 16-23 */
 389         ODM_MAC_EDCA_TURBO                      = BIT16,
 390         ODM_MAC_EARLY_MODE                      = BIT17,
 391
 392         /*  RF ODM section BIT 24-31 */
 393         ODM_RF_TX_PWR_TRACK                     = BIT24,
 394         ODM_RF_RX_GAIN_TRACK                    = BIT25,
 395         ODM_RF_CALIBRATION                      = BIT26,
 396
 397 };
 398
 399 /*      ODM_CMNINFO_INTERFACE */
 400 enum odm_interface_def {
 401         ODM_ITRF_PCIE   =       0x1,
 402         ODM_ITRF_USB    =       0x2,
 403         ODM_ITRF_SDIO   =       0x4,
 404         ODM_ITRF_ALL    =       0x7,
 405 };
 406
 407 /*  ODM_CMNINFO_IC_TYPE */
 408 enum odm_ic_type_def {
 409         ODM_RTL8192S    =       BIT0,
 410         ODM_RTL8192C    =       BIT1,
 411         ODM_RTL8192D    =       BIT2,
 412         ODM_RTL8723A    =       BIT3,
 413         ODM_RTL8188E    =       BIT4,
 414         ODM_RTL8812     =       BIT5,
 415         ODM_RTL8821     =       BIT6,
 416 };
 417
 418 #define ODM_IC_11N_SERIES                       \
 419         (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E)
 420 #define ODM_IC_11AC_SERIES              (ODM_RTL8812)
 421
 422 /* ODM_CMNINFO_CUT_VER */
 423 enum odm_cut_version {
 424         ODM_CUT_A               =       1,
 425         ODM_CUT_B               =       2,
 426         ODM_CUT_C               =       3,
 427         ODM_CUT_D               =       4,
 428         ODM_CUT_E               =       5,
 429         ODM_CUT_F               =       6,
 430         ODM_CUT_TEST            =       7,
 431 };
 432
 433 /*  ODM_CMNINFO_FAB_VER */
 434 enum odm_fab_version {
 435         ODM_TSMC        =       0,
 436         ODM_UMC         =       1,
 437 };
 438
 439 /*  ODM_CMNINFO_RF_TYPE */
 440 /*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
 441 enum rf_path_def {
 442         ODM_RF_TX_A     =       BIT0,
 443         ODM_RF_TX_B     =       BIT1,
 444         ODM_RF_TX_C     =       BIT2,
 445         ODM_RF_TX_D     =       BIT3,
 446         ODM_RF_RX_A     =       BIT4,
 447         ODM_RF_RX_B     =       BIT5,
 448         ODM_RF_RX_C     =       BIT6,
 449         ODM_RF_RX_D     =       BIT7,
 450 };
 451
 452
 453 enum odm_rf_type {
 454         ODM_1T1R        =       0,
 455         ODM_1T2R        =       1,
 456         ODM_2T2R        =       2,
 457         ODM_2T3R        =       3,
 458         ODM_2T4R        =       4,
 459         ODM_3T3R        =       5,
 460         ODM_3T4R        =       6,
 461         ODM_4T4R        =       7,
 462 };
 463
 464 /*  ODM Dynamic common info value definition */
 465
 466 enum odm_mac_phy_mode {
 467         ODM_SMSP        = 0,
 468         ODM_DMSP        = 1,
 469         ODM_DMDP        = 2,
 470 };
 471
 472
 473 enum odm_bt_coexist {
 474         ODM_BT_BUSY             = 1,
 475         ODM_BT_ON               = 2,
 476         ODM_BT_OFF              = 3,
 477         ODM_BT_NONE             = 4,
 478 };
 479
 480 /*  ODM_CMNINFO_OP_MODE */
 481 enum odm_operation_mode {
 482         ODM_NO_LINK             = BIT0,
 483         ODM_LINK                = BIT1,
 484         ODM_SCAN                = BIT2,
 485         ODM_POWERSAVE           = BIT3,
 486         ODM_AP_MODE             = BIT4,
 487         ODM_CLIENT_MODE         = BIT5,
 488         ODM_AD_HOC              = BIT6,
 489         ODM_WIFI_DIRECT         = BIT7,
 490         ODM_WIFI_DISPLAY        = BIT8,
 491 };
 492
 493 /*  ODM_CMNINFO_WM_MODE */
 494 enum odm_wireless_mode {
 495         ODM_WM_UNKNOW           = 0x0,
 496         ODM_WM_B                = BIT0,
 497         ODM_WM_G                = BIT1,
 498         ODM_WM_A                = BIT2,
 499         ODM_WM_N24G             = BIT3,
 500         ODM_WM_N5G              = BIT4,
 501         ODM_WM_AUTO             = BIT5,
 502         ODM_WM_AC               = BIT6,
 503 };
 504
 505 /*  ODM_CMNINFO_BAND */
 506 enum odm_band_type {
 507         ODM_BAND_2_4G           = BIT0,
 508         ODM_BAND_5G             = BIT1,
 509
 510 };
 511
 512 /*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 513 enum odm_sec_chnl_offset {
 514         ODM_DONT_CARE           = 0,
 515         ODM_BELOW               = 1,
 516         ODM_ABOVE               = 2
 517 };
 518
 519 /*  ODM_CMNINFO_SEC_MODE */
 520 enum odm_security {
 521         ODM_SEC_OPEN            = 0,
 522         ODM_SEC_WEP40           = 1,
 523         ODM_SEC_TKIP            = 2,
 524         ODM_SEC_RESERVE         = 3,
 525         ODM_SEC_AESCCMP         = 4,
 526         ODM_SEC_WEP104          = 5,
 527         ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 528         ODM_SEC_SMS4            = 7,
 529 };
 530
 531 /*  ODM_CMNINFO_BW */
 532 enum odm_band_width {
 533         ODM_BW20M               = 0,
 534         ODM_BW40M               = 1,
 535         ODM_BW80M               = 2,
 536         ODM_BW160M              = 3,
 537         ODM_BW10M               = 4,
 538 };
 539
 540 /*  ODM_CMNINFO_CHNL */
 541
 542 /*  ODM_CMNINFO_BOARD_TYPE */
 543 enum odm_board_type {
 544         ODM_BOARD_NORMAL        = 0,
 545         ODM_BOARD_HIGHPWR       = 1,
 546         ODM_BOARD_MINICARD      = 2,
 547         ODM_BOARD_SLIM          = 3,
 548         ODM_BOARD_COMBO         = 4,
 549
 550 };
 551
 552 /*  ODM_CMNINFO_ONE_PATH_CCA */
 553 enum odm_cca_path {
 554         ODM_CCA_2R                      = 0,
 555         ODM_CCA_1R_A                    = 1,
 556         ODM_CCA_1R_B                    = 2,
 557 };
 558
 559 struct iqk_matrix_regs_set {
 560         bool    bIQKDone;
 561         s32     Value[1][IQK_Matrix_REG_NUM];
 562 };
 563
 564 struct odm_rf_cal_t {
 565         /* for tx power tracking */
 566
 567         u32     RegA24; /*  for TempCCK */
 568         s32     RegE94;
 569         s32     RegE9C;
 570         s32     RegEB4;
 571         s32     RegEBC;
 572
 573         /* u8 bTXPowerTracking; */
 574         u8              TXPowercount;
 575         bool bTXPowerTrackingInit;
 576         bool bTXPowerTracking;
 577         u8              TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
 578         u8              TM_Trigger;
 579         u8              InternalPA5G[2];        /* pathA / pathB */
 580
 581         u8              ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
 582         u8              ThermalValue;
 583         u8              ThermalValue_LCK;
 584         u8              ThermalValue_IQK;
 585         u8      ThermalValue_DPK;
 586         u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 587         u8      ThermalValue_AVG_index;
 588         u8      ThermalValue_RxGain;
 589         u8      ThermalValue_Crystal;
 590         u8      ThermalValue_DPKstore;
 591         u8      ThermalValue_DPKtrack;
 592         bool    TxPowerTrackingInProgress;
 593         bool    bDPKenable;
 594
 595         bool    bReloadtxpowerindex;
 596         u8      bRfPiEnable;
 597         u32     TXPowerTrackingCallbackCnt; /* cosa add for debug */
 598
 599         u8      bCCKinCH14;
 600         u8      CCK_index;
 601         u8      OFDM_index[2];
 602         bool bDoneTxpower;
 603
 604         u8      ThermalValue_HP[HP_THERMAL_NUM];
 605         u8      ThermalValue_HP_index;
 606         struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 607
 608         u8      Delta_IQK;
 609         u8      Delta_LCK;
 610
 611         /* for IQK */
 612         u32     RegC04;
 613         u32     Reg874;
 614         u32     RegC08;
 615         u32     RegB68;
 616         u32     RegB6C;
 617         u32     Reg870;
 618         u32     Reg860;
 619         u32     Reg864;
 620
 621         bool    bIQKInitialized;
 622         bool bLCKInProgress;
 623         bool    bAntennaDetected;
 624         u32     ADDA_backup[IQK_ADDA_REG_NUM];
 625         u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 626         u32     IQK_BB_backup_recover[9];
 627         u32     IQK_BB_backup[IQK_BB_REG_NUM];
 628
 629         /* for APK */
 630         u32     APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 631         u8      bAPKdone;
 632         u8      bAPKThermalMeterIgnore;
 633         u8      bDPdone;
 634         u8      bDPPathAOK;
 635         u8      bDPPathBOK;
 636 };
 637
 638 /*  ODM Dynamic common info value definition */
 639 struct odm_fat_t {
 640         u8      Bssid[6];
 641         u8      antsel_rx_keep_0;
 642         u8      antsel_rx_keep_1;
 643         u8      antsel_rx_keep_2;
 644         u32     antSumRSSI[7];
 645         u32     antRSSIcnt[7];
 646         u32     antAveRSSI[7];
 647         u8      FAT_State;
 648         u32     TrainIdx;
 649         u8      antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 650         u8      antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 651         u8      antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 652         u32     MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 653         u32     AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 654         u32     MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 655         u32     AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 656         u8      RxIdleAnt;
 657         bool    bBecomeLinked;
 658 };
 659
 660 enum fat_state {
 661         FAT_NORMAL_STATE                = 0,
 662         FAT_TRAINING_STATE              = 1,
 663 };
 664
 665 enum ant_dif_type {
 666         NO_ANTDIV                       = 0xFF,
 667         CG_TRX_HW_ANTDIV                = 0x01,
 668         CGCS_RX_HW_ANTDIV               = 0x02,
 669         FIXED_HW_ANTDIV                 = 0x03,
 670         CG_TRX_SMART_ANTDIV             = 0x04,
 671         CGCS_RX_SW_ANTDIV               = 0x05,
 672 };
 673
 674 /*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
 675 struct dm_odm_t {
 676         /*  */
 677         /*      Add for different team use temporarily */
 678         /*  */
 679         struct rtw_adapter      *Adapter;               /*  For CE/NIC team */
 680
 681         u64                     DebugComponents;
 682         u32                     DebugLevel;
 683
 684 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 685         bool                    bCckHighPower;
 686         u8                      RFPathRxEnable;         /*  ODM_CMNINFO_RFPATH_ENABLE */
 687         u8                      ControlChannel;
 688 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 689
 690 /* 1  COMMON INFORMATION */
 691
 692         /*  Init Value */
 693 /* HOOK BEFORE REG INIT----------- */
 694         /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
 695         u32                     SupportAbility;
 696         /*  ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
 697         u8                      SupportInterface;
 698         /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
 699         u32                     SupportICType;
 700         /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 701         u8                      CutVersion;
 702         /*  Fab Version TSMC/UMC = 0/1 */
 703         u8                      FabVersion;
 704         /*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
 705         u8                      RFType;
 706         /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
 707         u8                      BoardType;
 708         /*  with external LNA  NO/Yes = 0/1 */
 709         u8                      ExtLNA;
 710         /*  with external PA  NO/Yes = 0/1 */
 711         u8                      ExtPA;
 712         /*  with external TRSW  NO/Yes = 0/1 */
 713         u8                      ExtTRSW;
 714         u8                      PatchID; /* Customer ID */
 715         bool                    bInHctTest;
 716         bool                    bWIFITest;
 717
 718         bool                    bDualMacSmartConcurrent;
 719         u32                     BK_SupportAbility;
 720         u8                      AntDivType;
 721 /* HOOK BEFORE REG INIT----------- */
 722
 723         /*  */
 724         /*  Dynamic Value */
 725         /*  */
 726 /*  POINTER REFERENCE----------- */
 727
 728         u8                      u8_temp;
 729         bool                    bool_temp;
 730         struct rtw_adapter      *PADAPTER_temp;
 731
 732         /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 733         u8                      *pMacPhyMode;
 734         /* TX Unicast byte count */
 735         u64                     *pNumTxBytesUnicast;
 736         /* RX Unicast byte count */
 737         u64                     *pNumRxBytesUnicast;
 738         /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
 739         u8                      *pWirelessMode; /* enum odm_wireless_mode */
 740         /*  Frequence band 2.4G/5G = 0/1 */
 741         u8                      *pBandType;
 742         /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 743         u8                      *pSecChOffset;
 744         /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 745         u8                      *pSecurity;
 746         /*  BW info 20M/40M/80M = 0/1/2 */
 747         u8                      *pBandWidth;
 748         /*  Central channel location Ch1/Ch2/.... */
 749         u8                      *pChannel;      /* central channel number */
 750         /*  Common info for 92D DMSP */
 751
 752         bool                    *pbGetValueFromOtherMac;
 753         struct rtw_adapter      **pBuddyAdapter;
 754         bool                    *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 755         /*  Common info for Status */
 756         bool                    *pbScanInProcess;
 757         bool                    *pbPowerSaving;
 758         /*  CCA Path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path. */
 759         u8                      *pOnePathCCA;
 760         /* pMgntInfo->AntennaTest */
 761         u8                      *pAntennaTest;
 762         bool                    *pbNet_closed;
 763 /*  POINTER REFERENCE----------- */
 764         /*  */
 765 /* CALL BY VALUE------------- */
 766         bool                    bWIFI_Direct;
 767         bool                    bWIFI_Display;
 768         bool                    bLinked;
 769         u8                      RSSI_Min;
 770         u8                      InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
 771         bool            bIsMPChip;
 772         bool                    bOneEntryOnly;
 773         /*  Common info for BTDM */
 774         bool                    bBtDisabled;                    /*  BT is disabled */
 775         bool                    bBtHsOperation;         /*  BT HS mode is under progress */
 776         u8                      btHsDigVal;                     /*  use BT rssi to decide the DIG value */
 777         bool                    bBtDisableEdcaTurbo;    /*  Under some condition, don't enable the EDCA Turbo */
 778         bool                    bBtBusy;                        /*  BT is busy. */
 779 /* CALL BY VALUE------------- */
 780
 781         /* 2 Define STA info. */
 782         /*  _ODM_STA_INFO */
 783         /*  2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
 784         struct sta_info *               pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
 785
 786         /*  */
 787         /*  2012/02/14 MH Add to share 88E ra with other SW team. */
 788         /*  We need to colelct all support abilit to a proper area. */
 789         /*  */
 790         bool                            RaSupport88E;
 791
 792         /*  Define ........... */
 793
 794         /*  Latest packet phy info (ODM write) */
 795         struct odm_phy_dbg_info  PhyDbgInfo;
 796         /* PHY_INFO_88E         PhyInfo; */
 797
 798         /*  Latest packet phy info (ODM write) */
 799         /* MAC_INFO_88E         MacInfo; */
 800
 801         /*  Different Team independt structure?? */
 802
 803         /*  */
 804         /* TX_RTP_CMN           TX_retrpo; */
 805         /* TX_RTP_88E           TX_retrpo; */
 806         /* TX_RTP_8195          TX_retrpo; */
 807
 808         /*  */
 809         /* ODM Structure */
 810         /*  */
 811         struct odm_fat_t                DM_FatTable;
 812         struct dig_t    DM_DigTable;
 813         struct dynamic_pwr_sav          DM_PSTable;
 814         struct pri_cca  DM_PriCCA;
 815         struct rx_hp            DM_RXHP_Table;
 816         struct false_alarm_stats        FalseAlmCnt;
 817         struct false_alarm_stats        FlaseAlmCntBuddyAdapter;
 818         struct sw_ant_sw                DM_SWAT_Table;
 819         bool            RSSI_test;
 820
 821         struct edca_turbo               DM_EDCA_Table;
 822         u32             WMMEDCA_BE;
 823         /*  Copy from SD4 structure */
 824         /*  */
 825         /*  ================================================== */
 826         /*  */
 827
 828         /* common */
 829         bool                    *pbDriverStopped;
 830         bool                    *pbDriverIsGoingToPnpSetPowerSleep;
 831         bool                    *pinit_adpt_in_progress;
 832
 833         /* PSD */
 834         bool                    bUserAssignLevel;
 835         u8                      RSSI_BT;                        /* come from BT */
 836         bool                    bPSDinProcess;
 837         bool                    bDMInitialGainEnable;
 838
 839         /* for rate adaptive, in fact,  88c/92c fw will handle this */
 840         u8                      bUseRAMask;
 841
 842         struct odm_rate_adapt   RateAdaptive;
 843
 844
 845         struct odm_rf_cal_t     RFCalibrateInfo;
 846
 847         /*  */
 848         /*  TX power tracking */
 849         /*  */
 850         u8                      BbSwingIdxOfdm;
 851         u8                      BbSwingIdxOfdmCurrent;
 852         u8                      BbSwingIdxOfdmBase;
 853         bool                    BbSwingFlagOfdm;
 854         u8                      BbSwingIdxCck;
 855         u8                      BbSwingIdxCckCurrent;
 856         u8                      BbSwingIdxCckBase;
 857         bool                    BbSwingFlagCck;
 858         /*  */
 859         /*  ODM system resource. */
 860         /*  */
 861 };      /*  DM_Dynamic_Mechanism_Structure */
 862
 863 enum odm_rf_content {
 864         odm_radioa_txt = 0x1000,
 865         odm_radiob_txt = 0x1001,
 866         odm_radioc_txt = 0x1002,
 867         odm_radiod_txt = 0x1003
 868 };
 869
 870 enum odm_bb_config_type {
 871     CONFIG_BB_PHY_REG,
 872     CONFIG_BB_AGC_TAB,
 873     CONFIG_BB_AGC_TAB_2G,
 874     CONFIG_BB_AGC_TAB_5G,
 875     CONFIG_BB_PHY_REG_PG,
 876 };
 877
 878 /*  Status code */
 879 enum rt_status {
 880         RT_STATUS_SUCCESS,
 881         RT_STATUS_FAILURE,
 882         RT_STATUS_PENDING,
 883         RT_STATUS_RESOURCE,
 884         RT_STATUS_INVALID_CONTEXT,
 885         RT_STATUS_INVALID_PARAMETER,
 886         RT_STATUS_NOT_SUPPORT,
 887         RT_STATUS_OS_API_FAILED,
 888 };
 889
 890 /* include "odm_function.h" */
 891
 892 /* 3=========================================================== */
 893 /* 3 DIG */
 894 /* 3=========================================================== */
 895
 896 enum dm_dig_op {
 897         DIG_TYPE_THRESH_HIGH    = 0,
 898         DIG_TYPE_THRESH_LOW     = 1,
 899         DIG_TYPE_BACKOFF                = 2,
 900         DIG_TYPE_RX_GAIN_MIN    = 3,
 901         DIG_TYPE_RX_GAIN_MAX    = 4,
 902         DIG_TYPE_ENABLE                 = 5,
 903         DIG_TYPE_DISABLE                = 6,
 904         DIG_OP_TYPE_MAX
 905 };
 906
 907 #define         DM_DIG_THRESH_HIGH                      40
 908 #define         DM_DIG_THRESH_LOW                       35
 909
 910 #define         DM_SCAN_RSSI_TH                         0x14 /* scan return issue for LC */
 911
 912
 913 #define         DM_FALSEALARM_THRESH_LOW        400
 914 #define         DM_FALSEALARM_THRESH_HIGH       1000
 915
 916 #define         DM_DIG_MAX_NIC                          0x4e
 917 #define         DM_DIG_MIN_NIC                          0x1e
 918
 919 #define         DM_DIG_MAX_AP                           0x32
 920 #define         DM_DIG_MIN_AP                           0x20
 921
 922 #define         DM_DIG_MAX_NIC_HP                       0x46
 923 #define         DM_DIG_MIN_NIC_HP                       0x2e
 924
 925 #define         DM_DIG_MAX_AP_HP                                0x42
 926 #define         DM_DIG_MIN_AP_HP                                0x30
 927
 928 /* vivi 92c&92d has different definition, 20110504 */
 929 /* this is for 92c */
 930 #define         DM_DIG_FA_TH0                           0x200
 931 #define         DM_DIG_FA_TH1                           0x300
 932 #define         DM_DIG_FA_TH2                           0x400
 933 /* this is for 92d */
 934 #define         DM_DIG_FA_TH0_92D                       0x100
 935 #define         DM_DIG_FA_TH1_92D                       0x400
 936 #define         DM_DIG_FA_TH2_92D                       0x600
 937
 938 #define         DM_DIG_BACKOFF_MAX                      12
 939 #define         DM_DIG_BACKOFF_MIN                      -4
 940 #define         DM_DIG_BACKOFF_DEFAULT          10
 941
 942 /* 3=========================================================== */
 943 /* 3 AGC RX High Power Mode */
 944 /* 3=========================================================== */
 945 #define          LNA_Low_Gain_1                      0x64
 946 #define          LNA_Low_Gain_2                      0x5A
 947 #define          LNA_Low_Gain_3                      0x58
 948
 949 #define          FA_RXHP_TH1                           5000
 950 #define          FA_RXHP_TH2                           1500
 951 #define          FA_RXHP_TH3                             800
 952 #define          FA_RXHP_TH4                             600
 953 #define          FA_RXHP_TH5                             500
 954
 955 /* 3=========================================================== */
 956 /* 3 EDCA */
 957 /* 3=========================================================== */
 958
 959 /* 3=========================================================== */
 960 /* 3 Dynamic Tx Power */
 961 /* 3=========================================================== */
 962 /* Dynamic Tx Power Control Threshold */
 963 #define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
 964 #define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
 965 #define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F
 966
 967 #define         TxHighPwrLevel_Normal           0
 968 #define         TxHighPwrLevel_Level1           1
 969 #define         TxHighPwrLevel_Level2           2
 970 #define         TxHighPwrLevel_BT1                      3
 971 #define         TxHighPwrLevel_BT2                      4
 972 #define         TxHighPwrLevel_15                       5
 973 #define         TxHighPwrLevel_35                       6
 974 #define         TxHighPwrLevel_50                       7
 975 #define         TxHighPwrLevel_70                       8
 976 #define         TxHighPwrLevel_100                      9
 977
 978 /* 3=========================================================== */
 979 /* 3 Rate Adaptive */
 980 /* 3=========================================================== */
 981 #define         DM_RATR_STA_INIT                        0
 982 #define         DM_RATR_STA_HIGH                        1
 983 #define                 DM_RATR_STA_MIDDLE              2
 984 #define                 DM_RATR_STA_LOW                 3
 985
 986 /* 3=========================================================== */
 987 /* 3 BB Power Save */
 988 /* 3=========================================================== */
 989
 990
 991 enum dm_1r_cca {
 992         CCA_1R =0,
 993         CCA_2R = 1,
 994         CCA_MAX = 2,
 995 };
 996
 997 enum dm_rf_def {
 998         RF_Save =0,
 999         RF_Normal = 1,
1000         RF_MAX = 2,
1001 };
1002
1003 /* 3=========================================================== */
1004 /* 3 Antenna Diversity */
1005 /* 3=========================================================== */
1006 enum dm_swas {
1007         Antenna_A = 1,
1008         Antenna_B = 2,
1009         Antenna_MAX = 3,
1010 };
1011
1012 /*  Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1013 #define MAX_ANTENNA_DETECTION_CNT       10
1014
1015 /*  */
1016 /*  Extern Global Variables. */
1017 /*  */
1018 #define OFDM_TABLE_SIZE_92C     37
1019 #define OFDM_TABLE_SIZE_92D     43
1020 #define CCK_TABLE_SIZE          33
1021
1022 extern  u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D];
1023 extern  u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8];
1024 extern  u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8];
1025
1026
1027
1028 /*  */
1029 /*  check Sta pointer valid or not */
1030 /*  */
1031 #define IS_STA_VALID(pSta)              (pSta)
1032 /*  20100514 Joseph: Add definition for antenna switching test after link. */
1033 /*  This indicates two different the steps. */
1034 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1035 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1036 /*  with original RSSI to determine if it is necessary to switch antenna. */
1037 #define SWAW_STEP_PEAK          0
1038 #define SWAW_STEP_DETERMINE     1
1039
1040 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8      CurrentIGI);
1041 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8    CurCCK_CCAThres);
1042
1043 void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna);
1044
1045
1046 #define dm_RF_Saving    ODM_RF_Saving23a
1047 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal);
1048
1049 #define SwAntDivRestAfterLink   ODM_SwAntDivRestAfterLink
1050 void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm);
1051
1052 #define dm_CheckTXPowerTracking         ODM_TXPowerTrackingCheck23a
1053 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
1054
1055 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1056                       u8 *pRATRState);
1057
1058
1059 #define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi
1060 void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID,
1061                                struct phy_info *pPhyInfo);
1062
1063 u32 ConvertTo_dB23a(u32 Value);
1064
1065 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd);
1066
1067 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm);
1068
1069 u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level);
1070
1071
1072 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm);
1073
1074 void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm); /*  For common use in the future */
1075
1076 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo      CmnInfo, u32 Value);
1077
1078 void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo      CmnInfo, void *pValue);
1079
1080 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo      CmnInfo, u16 Index, void *pValue);
1081
1082 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value);
1083
1084 void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm);
1085
1086 void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate);
1087
1088 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm);
1089
1090 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode);
1091
1092 void odm_dtc(struct dm_odm_t *pDM_Odm);
1093
1094 #endif