drivers/staging/rtl8723au/include/rtl8723a_hal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #ifndef __RTL8723A_HAL_H__
  16 #define __RTL8723A_HAL_H__
  17
  18 #include "rtl8723a_spec.h"
  19 #include "rtl8723a_pg.h"
  20 #include "Hal8723APhyReg.h"
  21 #include "Hal8723APhyCfg.h"
  22 #include "rtl8723a_rf.h"
  23 #ifdef CONFIG_8723AU_BT_COEXIST
  24 #include "rtl8723a_bt-coexist.h"
  25 #endif
  26 #include "rtl8723a_dm.h"
  27 #include "rtl8723a_recv.h"
  28 #include "rtl8723a_xmit.h"
  29 #include "rtl8723a_cmd.h"
  30 #include "rtl8723a_sreset.h"
  31 #include "rtw_efuse.h"
  32
  33 #include "odm_precomp.h"
  34
  35
  36 /* 2TODO: We should define 8192S firmware related macro settings here!! */
  37 #define RTL819X_DEFAULT_RF_TYPE                 RF_1T2R
  38 #define RTL819X_TOTAL_RF_PATH                           2
  39
  40 /* TODO:  The following need to check!! */
  41 #define RTL8723_FW_UMC_IMG                              "rtl8192CU\\rtl8723fw.bin"
  42 #define RTL8723_FW_UMC_B_IMG                    "rtl8192CU\\rtl8723fw_B.bin"
  43 #define RTL8723_PHY_REG                                 "rtl8723S\\PHY_REG_1T.txt"
  44 #define RTL8723_PHY_RADIO_A                             "rtl8723S\\radio_a_1T.txt"
  45 #define RTL8723_PHY_RADIO_B                             "rtl8723S\\radio_b_1T.txt"
  46 #define RTL8723_AGC_TAB                                 "rtl8723S\\AGC_TAB_1T.txt"
  47 #define RTL8723_PHY_MACREG                              "rtl8723S\\MAC_REG.txt"
  48 #define RTL8723_PHY_REG_PG                              "rtl8723S\\PHY_REG_PG.txt"
  49 #define RTL8723_PHY_REG_MP                              "rtl8723S\\PHY_REG_MP.txt"
  50
  51 /*  */
  52 /*              RTL8723S From header */
  53 /*  */
  54
  55 /*  Fw Array */
  56 #define Rtl8723_FwImageArray                            Rtl8723UFwImgArray
  57 #define Rtl8723_FwUMCBCutImageArrayWithBT               Rtl8723UFwUMCBCutImgArrayWithBT
  58 #define Rtl8723_FwUMCBCutImageArrayWithoutBT    Rtl8723UFwUMCBCutImgArrayWithoutBT
  59
  60 #define Rtl8723_ImgArrayLength                          Rtl8723UImgArrayLength
  61 #define Rtl8723_UMCBCutImgArrayWithBTLength             Rtl8723UUMCBCutImgArrayWithBTLength
  62 #define Rtl8723_UMCBCutImgArrayWithoutBTLength  Rtl8723UUMCBCutImgArrayWithoutBTLength
  63
  64 #define Rtl8723_PHY_REG_Array_PG                        Rtl8723UPHY_REG_Array_PG
  65 #define Rtl8723_PHY_REG_Array_PGLength          Rtl8723UPHY_REG_Array_PGLength
  66
  67 #define Rtl8723_FwUMCBCutMPImageArray           Rtl8723SFwUMCBCutMPImgAr
  68 #define Rtl8723_UMCBCutMPImgArrayLength         Rtl8723SUMCBCutMPImgArrayLength
  69
  70 #define DRVINFO_SZ                              4 /*  unit is 8bytes */
  71 #define PageNum_128(_Len)               (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
  72
  73 #define FW_8723A_SIZE                   0x8000
  74 #define FW_8723A_START_ADDRESS  0x1000
  75 #define FW_8723A_END_ADDRESS            0x1FFF /* 0x5FFF */
  76
  77 #define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  78
  79 #define IS_FW_HEADER_EXIST(_pFwHdr)     ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
  80                                                                         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
  81                                                                         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
  82
  83 /*  */
  84 /*  This structure must be cared byte-ordering */
  85 /*  */
  86 /*  Added by tynli. 2009.12.04. */
  87 struct rt_8723a_firmware_hdr {
  88         /*  8-byte alinment required */
  89
  90         /*  LONG WORD 0 ---- */
  91         u16             Signature;      /*  92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
  92         u8              Category;       /*  AP/NIC and USB/PCI */
  93         u8              Function;       /*  Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
  94         u16             Version;                /*  FW Version */
  95         u8              Subversion;     /*  FW Subversion, default 0x00 */
  96         u16             Rsvd1;
  97
  98
  99         /*  LONG WORD 1 ---- */
 100         u8              Month;  /*  Release time Month field */
 101         u8              Date;   /*  Release time Date field */
 102         u8              Hour;   /*  Release time Hour field */
 103         u8              Minute; /*  Release time Minute field */
 104         u16             RamCodeSize;    /*  The size of RAM code */
 105         u16             Rsvd2;
 106
 107         /*  LONG WORD 2 ---- */
 108         u32             SvnIdx; /*  The SVN entry index */
 109         u32             Rsvd3;
 110
 111         /*  LONG WORD 3 ---- */
 112         u32             Rsvd4;
 113         u32             Rsvd5;
 114 };
 115
 116 #define DRIVER_EARLY_INT_TIME           0x05
 117 #define BCN_DMA_ATIME_INT_TIME          0x02
 118
 119
 120 /*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
 121 #define MAX_TX_QUEUE            9
 122
 123 #define TX_SELE_HQ                      BIT(0)          /*  High Queue */
 124 #define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
 125 #define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 126
 127 /*  Note: We will divide number of page equally for each queue other than public queue! */
 128 #define TX_TOTAL_PAGE_NUMBER    0xF8
 129 #define TX_PAGE_BOUNDARY                (TX_TOTAL_PAGE_NUMBER + 1)
 130
 131 /*  For Normal Chip Setting */
 132 /*  (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
 133 #define NORMAL_PAGE_NUM_PUBQ    0xE7
 134 #define NORMAL_PAGE_NUM_HPQ             0x0C
 135 #define NORMAL_PAGE_NUM_LPQ             0x02
 136 #define NORMAL_PAGE_NUM_NPQ             0x02
 137
 138 /*  For Test Chip Setting */
 139 /*  (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
 140 #define TEST_PAGE_NUM_PUBQ              0x7E
 141
 142 /*  For Test Chip Setting */
 143 #define WMM_TEST_TX_TOTAL_PAGE_NUMBER   0xF5
 144 #define WMM_TEST_TX_PAGE_BOUNDARY               (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
 145
 146 #define WMM_TEST_PAGE_NUM_PUBQ          0xA3
 147 #define WMM_TEST_PAGE_NUM_HPQ           0x29
 148 #define WMM_TEST_PAGE_NUM_LPQ           0x29
 149
 150 /*  Note: For Normal Chip Setting, modify later */
 151 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
 152 #define WMM_NORMAL_TX_PAGE_BOUNDARY             (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
 153
 154 #define WMM_NORMAL_PAGE_NUM_PUBQ        0xB0
 155 #define WMM_NORMAL_PAGE_NUM_HPQ         0x29
 156 #define WMM_NORMAL_PAGE_NUM_LPQ         0x1C
 157 #define WMM_NORMAL_PAGE_NUM_NPQ         0x1C
 158
 159
 160 /*  */
 161 /*      Chip specific */
 162 /*  */
 163 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 164 #define CHIP_BONDING_92C_1T2R                   0x1
 165 #define CHIP_BONDING_88C_USB_MCARD              0x2
 166 #define CHIP_BONDING_88C_USB_HP                 0x1
 167
 168 #include "HalVerDef.h"
 169 #include "hal_com.h"
 170
 171 /*  */
 172 /*      Channel Plan */
 173 /*  */
 174 enum ChannelPlan
 175 {
 176         CHPL_FCC        = 0,
 177         CHPL_IC         = 1,
 178         CHPL_ETSI       = 2,
 179         CHPL_SPAIN      = 3,
 180         CHPL_FRANCE     = 4,
 181         CHPL_MKK        = 5,
 182         CHPL_MKK1       = 6,
 183         CHPL_ISRAEL     = 7,
 184         CHPL_TELEC      = 8,
 185         CHPL_GLOBAL     = 9,
 186         CHPL_WORLD      = 10,
 187 };
 188
 189 #define EFUSE_REAL_CONTENT_LEN          512
 190 #define EFUSE_MAP_LEN                           128
 191 #define EFUSE_MAX_SECTION                       16
 192 #define EFUSE_IC_ID_OFFSET                      506     /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
 193 #define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 194 /*  */
 195 /*  <Roger_Notes> */
 196 /*  To prevent out of boundary programming case, */
 197 /*  leave 1byte and program full section */
 198 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 199 /*  For worst case: */
 200 /*  | 1byte|----8bytes----|1byte|--5bytes--| */
 201 /*  |         |            Reserved(14bytes)          | */
 202 /*  */
 203
 204 /*  PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
 205 #define EFUSE_OOB_PROTECT_BYTES                 15
 206
 207 #define EFUSE_REAL_CONTENT_LEN_8723A    512
 208 #define EFUSE_MAP_LEN_8723A                             256
 209 #define EFUSE_MAX_SECTION_8723A                 32
 210
 211 /*  */
 212 /*                      EFUSE for BT definition */
 213 /*  */
 214 #define EFUSE_BT_REAL_BANK_CONTENT_LEN  512
 215 #define EFUSE_BT_REAL_CONTENT_LEN               1536    /*  512*3 */
 216 #define EFUSE_BT_MAP_LEN                                1024    /*  1k bytes */
 217 #define EFUSE_BT_MAX_SECTION                    128             /*  1024/8 */
 218
 219 #define EFUSE_PROTECT_BYTES_BANK                16
 220
 221 /*  */
 222 /*  <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
 223 /*  */
 224 enum RT_MULTI_FUNC {
 225         RT_MULTI_FUNC_NONE = 0x00,
 226         RT_MULTI_FUNC_WIFI = 0x01,
 227         RT_MULTI_FUNC_BT = 0x02,
 228         RT_MULTI_FUNC_GPS = 0x04,
 229 };
 230
 231 /*  */
 232 /*  <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
 233 /*  */
 234 enum RT_POLARITY_CTL {
 235         RT_POLARITY_LOW_ACT = 0,
 236         RT_POLARITY_HIGH_ACT = 1,
 237 };
 238
 239 /*  For RTL8723 regulator mode. by tynli. 2011.01.14. */
 240 enum RT_REGULATOR_MODE {
 241         RT_SWITCHING_REGULATOR = 0,
 242         RT_LDO_REGULATOR = 1,
 243 };
 244
 245 /*  Description: Determine the types of C2H events that are the same in driver and Fw. */
 246 /*  Fisrt constructed by tynli. 2009.10.09. */
 247 enum {
 248         C2H_DBG = 0,
 249         C2H_TSF = 1,
 250         C2H_AP_RPT_RSP = 2,
 251         C2H_CCX_TX_RPT = 3,     /*  The FW notify the report of the specific tx packet. */
 252         C2H_BT_RSSI = 4,
 253         C2H_BT_OP_MODE = 5,
 254         C2H_EXT_RA_RPT = 6,
 255         C2H_HW_INFO_EXCH = 10,
 256         C2H_C2H_H2C_TEST = 11,
 257         C2H_BT_INFO = 12,
 258         C2H_BT_MP_INFO = 15,
 259         MAX_C2HEVENT
 260 };
 261
 262 struct hal_data_8723a {
 263         struct hal_version              VersionID;
 264         enum rt_customer_id CustomerID;
 265
 266         u16     FirmwareVersion;
 267         u16     FirmwareVersionRev;
 268         u16     FirmwareSubVersion;
 269         u16     FirmwareSignature;
 270
 271         /* current WIFI_PHY values */
 272         u32     ReceiveConfig;
 273         enum WIRELESS_MODE              CurrentWirelessMode;
 274         enum ht_channel_width   CurrentChannelBW;
 275         u8      CurrentChannel;
 276         u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 277
 278         u16     BasicRateSet;
 279
 280         /* rf_ctrl */
 281         u8      rf_chip;
 282         u8      rf_type;
 283         u8      NumTotalRFPath;
 284
 285         u8      BoardType;
 286         u8      CrystalCap;
 287         /*  */
 288         /*  EEPROM setting. */
 289         /*  */
 290         u8      EEPROMVersion;
 291         u16     EEPROMVID;
 292         u16     EEPROMPID;
 293         u16     EEPROMSVID;
 294         u16     EEPROMSDID;
 295         u8      EEPROMCustomerID;
 296         u8      EEPROMSubCustomerID;
 297         u8      EEPROMRegulatory;
 298         u8      EEPROMThermalMeter;
 299         u8      EEPROMBluetoothCoexist;
 300         u8      EEPROMBluetoothType;
 301         u8      EEPROMBluetoothAntNum;
 302         u8      EEPROMBluetoothAntIsolation;
 303         u8      EEPROMBluetoothRadioShared;
 304
 305         u8      bTXPowerDataReadFromEEPORM;
 306         u8      bAPKThermalMeterIgnore;
 307
 308         u8      bIQKInitialized;
 309         u8      bAntennaDetected;
 310
 311         u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 312         u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     /*  For HT 40MHZ pwr */
 313         u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     /*  For HT 40MHZ pwr */
 314         u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/*  HT 20<->40 Pwr diff */
 315         u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/*  For HT<->legacy pwr diff */
 316         /*  For power group */
 317         u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 318         u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 319
 320         u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 321
 322         /*  Read/write are allow for following hardware information variables */
 323         u8      framesync;
 324         u32     framesyncC34;
 325         u8      framesyncMonitor;
 326         u8      DefaultInitialGain[4];
 327         u8      pwrGroupCnt;
 328         u32     MCSTxPowerLevelOriginalOffset[7][16];
 329         u32     CCKTxPowerLevelOriginalOffset;
 330
 331         u32     AntennaTxPath;                                  /*  Antenna path Tx */
 332         u32     AntennaRxPath;                                  /*  Antenna path Rx */
 333         u8      ExternalPA;
 334
 335         u8      bLedOpenDrain; /*  Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
 336
 337         u8      b1x1RecvCombine;        /*  for 1T1R receive combining */
 338
 339         /*  For EDCA Turbo mode */
 340
 341         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 342
 343         /* vivi, for tx power tracking, 20080407 */
 344         /* u16  TSSI_13dBm; */
 345         /* u32  Pwr_Track; */
 346         /*  The current Tx Power Level */
 347         u8      CurrentCckTxPwrIdx;
 348         u8      CurrentOfdm24GTxPwrIdx;
 349
 350         struct bb_reg_define    PHYRegDef[4];   /* Radio A/B/C/D */
 351
 352         bool            bRFPathRxEnable[4];     /*  We support 4 RF path now. */
 353
 354         u32     RfRegChnlVal[2];
 355
 356         u8      bCckHighPower;
 357
 358         /* RDG enable */
 359         bool     bRDGEnable;
 360
 361         /* for host message to fw */
 362         u8      LastHMEBoxNum;
 363
 364         u8      fw_ractrl;
 365         u8      RegTxPause;
 366         /*  Beacon function related global variable. */
 367         u32     RegBcnCtrlVal;
 368         u8      RegFwHwTxQCtrl;
 369         u8      RegReg542;
 370
 371         struct dm_priv  dmpriv;
 372         struct dm_odm_t         odmpriv;
 373         struct sreset_priv srestpriv;
 374
 375 #ifdef CONFIG_8723AU_BT_COEXIST
 376         u8                              bBTMode;
 377         /*  BT only. */
 378         struct bt_30info                BtInfo;
 379         /*  For bluetooth co-existance */
 380         struct bt_coexist_str   bt_coexist;
 381 #endif
 382
 383         u8      bDumpRxPkt;/* for debug */
 384         u8      FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
 385
 386         /*  2010/08/09 MH Add CU power down mode. */
 387         u8      pwrdown;
 388
 389         /*  Add for dual MAC  0--Mac0 1--Mac1 */
 390         u32     interfaceIndex;
 391
 392         u8      OutEpQueueSel;
 393         u8      OutEpNumber;
 394
 395         /*  2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
 396         bool            UsbRxHighSpeedMode;
 397
 398         /*  2010/11/22 MH Add for slim combo debug mode selective. */
 399         /*  This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */
 400         bool            SlimComboDbg;
 401
 402         /*  */
 403         /*  Add For EEPROM Efuse switch and  Efuse Shadow map Setting */
 404         /*  */
 405         u8                      EepromOrEfuse;
 406         u16                     EfuseUsedBytes;
 407         u16                     BTEfuseUsedBytes;
 408
 409         /*  Interrupt relatd register information. */
 410         u32                     SysIntrStatus;
 411         u32                     SysIntrMask;
 412
 413         /*  */
 414         /*  2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
 415         /*  independent file in the future. */
 416         /*  */
 417         /* 8723-----------------------------------------*/
 418         enum RT_MULTI_FUNC      MultiFunc; /*  For multi-function consideration. */
 419         enum RT_POLARITY_CTL    PolarityCtl; /*  For Wifi PDn Polarity control. */
 420         enum RT_REGULATOR_MODE  RegulatorMode; /*  switching regulator or LDO */
 421         /* 8723-----------------------------------------
 422          *  2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
 423         /*  independent file in the future. */
 424
 425         bool                            bMACFuncEnable;
 426
 427 #ifdef CONFIG_8723AU_P2P
 428         struct P2P_PS_Offload_t p2p_ps_offload;
 429 #endif
 430
 431
 432         /*  */
 433         /*  For USB Interface HAL related */
 434         /*  */
 435         u32     UsbBulkOutSize;
 436
 437         /*  Interrupt related register information. */
 438         u32     IntArray[2];
 439         u32     IntrMask[2];
 440
 441         /*  */
 442         /*  For SDIO Interface HAL related */
 443         /*  */
 444
 445         /*  Auto FSM to Turn On, include clock, isolation, power control for MAC only */
 446         u8                      bMacPwrCtrlOn;
 447
 448 };
 449
 450 #define GET_HAL_DATA(__pAdapter)        ((struct hal_data_8723a *)((__pAdapter)->HalData))
 451 #define GET_RF_TYPE(priv)                       (GET_HAL_DATA(priv)->rf_type)
 452
 453 #define INCLUDE_MULTI_FUNC_BT(_Adapter)         (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 454 #define INCLUDE_MULTI_FUNC_GPS(_Adapter)        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 455
 456 struct rxreport_8723a {
 457         u32 pktlen:14;
 458         u32 crc32:1;
 459         u32 icverr:1;
 460         u32 drvinfosize:4;
 461         u32 security:3;
 462         u32 qos:1;
 463         u32 shift:2;
 464         u32 physt:1;
 465         u32 swdec:1;
 466         u32 ls:1;
 467         u32 fs:1;
 468         u32 eor:1;
 469         u32 own:1;
 470
 471         u32 macid:5;
 472         u32 tid:4;
 473         u32 hwrsvd:4;
 474         u32 amsdu:1;
 475         u32 paggr:1;
 476         u32 faggr:1;
 477         u32 a1fit:4;
 478         u32 a2fit:4;
 479         u32 pam:1;
 480         u32 pwr:1;
 481         u32 md:1;
 482         u32 mf:1;
 483         u32 type:2;
 484         u32 mc:1;
 485         u32 bc:1;
 486
 487         u32 seq:12;
 488         u32 frag:4;
 489         u32 nextpktlen:14;
 490         u32 nextind:1;
 491         u32 rsvd0831:1;
 492
 493         u32 rxmcs:6;
 494         u32 rxht:1;
 495         u32 gf:1;
 496         u32 splcp:1;
 497         u32 bw:1;
 498         u32 htc:1;
 499         u32 eosp:1;
 500         u32 bssidfit:2;
 501         u32 rsvd1214:16;
 502         u32 unicastwake:1;
 503         u32 magicwake:1;
 504
 505         u32 pattern0match:1;
 506         u32 pattern1match:1;
 507         u32 pattern2match:1;
 508         u32 pattern3match:1;
 509         u32 pattern4match:1;
 510         u32 pattern5match:1;
 511         u32 pattern6match:1;
 512         u32 pattern7match:1;
 513         u32 pattern8match:1;
 514         u32 pattern9match:1;
 515         u32 patternamatch:1;
 516         u32 patternbmatch:1;
 517         u32 patterncmatch:1;
 518         u32 rsvd1613:19;
 519
 520         u32 tsfl;
 521
 522         u32 bassn:12;
 523         u32 bavld:1;
 524         u32 rsvd2413:19;
 525 };
 526
 527 /*  rtl8723a_hal_init.c */
 528 s32 rtl8723a_FirmwareDownload(struct rtw_adapter *padapter);
 529 void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter);
 530 void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter);
 531
 532 void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter);
 533 void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter);
 534 void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter);
 535 void rtl8723a_init_default_value(struct rtw_adapter *padapter);
 536
 537 s32 InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary);
 538
 539 s32 CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU);
 540 s32 CardDisableWithoutHWSM(struct rtw_adapter *padapter);
 541
 542 /*  EFuse */
 543 u8 GetEEPROMSize8723A(struct rtw_adapter *padapter);
 544 void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent);
 545 void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo);
 546 void Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter, u8 *PROMContent, bool AutoLoadFail);
 547 void Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 548 void Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 549 void rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 550 void Hal_EfuseParseCustomerID(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 551 void Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 552 void Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 553 void Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter, u8 *hwinfo, u8 AutoLoadFail);
 554 void Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter, u8 *hwinfo, u8 AutoLoadFail);
 555
 556 void Hal_InitChannelPlan23a(struct rtw_adapter *padapter);
 557
 558 void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc);
 559 void SetHwReg8723A(struct rtw_adapter *padapter, u8 variable, u8 *val);
 560 void GetHwReg8723A(struct rtw_adapter *padapter, u8 variable, u8 *val);
 561 #ifdef CONFIG_8723AU_BT_COEXIST
 562 void rtl8723a_SingleDualAntennaDetection(struct rtw_adapter *padapter);
 563 #endif
 564
 565 /*  register */
 566 void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits);
 567 void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter);
 568
 569 void rtl8723a_clone_haldata(struct rtw_adapter *dst_adapter, struct rtw_adapter *src_adapter);
 570 void rtl8723a_start_thread(struct rtw_adapter *padapter);
 571 void rtl8723a_stop_thread(struct rtw_adapter *padapter);
 572
 573 s32 c2h_id_filter_ccx_8723a(u8 id);
 574
 575 #endif