drivers/staging/rtl8821ae/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44 #include "pwrseqcmd.h"
  45 #include "pwrseq.h"
  46 #include "btc.h"
  47 #include "../btcoexist/rtl_btc.h"
  48
  49 #define LLT_CONFIG      5
  50
  51 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  52 {
  53         struct rtl_priv *rtlpriv = rtl_priv(hw);
  54         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  55         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  56
  57         while (skb_queue_len(&ring->queue)) {
  58                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  59                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  60
  61                 pci_unmap_single(rtlpci->pdev,
  62                                  le32_to_cpu(rtlpriv->cfg->ops->get_desc(
  63                                  (u8 *) entry, true, HW_DESC_TXBUFF_ADDR)),
  64                                  skb->len, PCI_DMA_TODEVICE);
  65                 kfree_skb(skb);
  66                 ring->idx = (ring->idx + 1) % ring->entries;
  67         }
  68
  69 }
  70
  71 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  72                                       u8 set_bits, u8 clear_bits)
  73 {
  74         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76
  77         rtlpci->reg_bcn_ctrl_val |= set_bits;
  78         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  79
  80         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  81 }
  82
  83 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  84 {
  85         struct rtl_priv *rtlpriv = rtl_priv(hw);
  86         u8 tmp1byte;
  87
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  89         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  91         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  92         tmp1byte &= ~(BIT(0));
  93         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  94 }
  95
  96 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  97 {
  98         struct rtl_priv *rtlpriv = rtl_priv(hw);
  99         u8 tmp1byte;
 100
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 102         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 104         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 105         tmp1byte |= BIT(0);
 106         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 107 }
 108
 109 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 110 {
 111         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 112 }
 113
 114 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 115 {
 116         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 117 }
 118
 119 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 120         u8 rpwm_val, bool b_need_turn_off_ckk)
 121 {
 122         struct rtl_priv *rtlpriv = rtl_priv(hw);
 123         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 124         bool b_support_remote_wake_up;
 125         u32 count = 0,isr_regaddr,content;
 126         bool b_schedule_timer = b_need_turn_off_ckk;
 127         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 128                                         (u8 *) (&b_support_remote_wake_up));
 129
 130         if (!rtlhal->bfw_ready)
 131                 return;
 132         if (!rtlpriv->psc.b_fw_current_inpsmode)
 133                 return;
 134
 135         while (1) {
 136                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 137                 if (rtlhal->bfw_clk_change_in_progress) {
 138                         while (rtlhal->bfw_clk_change_in_progress) {
 139                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 140                                 count++;
 141                                 udelay(100);
 142                                 if (count > 1000)
 143                                         return;
 144                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         }
 146                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 147                 } else {
 148                         rtlhal->bfw_clk_change_in_progress = false;
 149                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 150                         break;
 151                 }
 152         }
 153
 154         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 155                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 156                                         (u8 *) (&rpwm_val));
 157                 if (FW_PS_IS_ACK(rpwm_val)) {
 158                         isr_regaddr = REG_HISR;
 159                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 160                         while (!(content & IMR_CPWM) && (count < 500)) {
 161                                 udelay(50);
 162                                 count++;
 163                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 164                         }
 165
 166                         if (content & IMR_CPWM) {
 167                         rtl_write_word(rtlpriv,isr_regaddr, 0x0100);
 168                         rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 169                         RT_TRACE(COMP_POWER, DBG_LOUD, ("Receive CPWM INT!!! Set pHalData->FwPSState = %X\n", rtlhal->fw_ps_state));
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->bfw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer) {
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179                 }
 180
 181         } else  {
 182                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 183                 rtlhal->bfw_clk_change_in_progress = false;
 184                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 185         }
 186
 187
 188 }
 189
 190 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 191         u8 rpwm_val)
 192 {
 193         struct rtl_priv *rtlpriv = rtl_priv(hw);
 194         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 195         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 196         struct rtl8192_tx_ring *ring;
 197         enum rf_pwrstate rtstate;
 198         bool b_schedule_timer = false;
 199         u8 queue;
 200
 201         if (!rtlhal->bfw_ready)
 202                 return;
 203         if (!rtlpriv->psc.b_fw_current_inpsmode)
 204                 return;
 205         if (!rtlhal->ballow_sw_to_change_hwclc)
 206                 return;
 207         rtlpriv->cfg->ops->get_hw_reg(hw,HW_VAR_RF_STATE,(u8 *)(&rtstate));
 208         if (rtstate == ERFOFF ||rtlpriv->psc.inactive_pwrstate ==ERFOFF)
 209                 return;
 210
 211         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 212                 ring = &rtlpci->tx_ring[queue];
 213                 if (skb_queue_len(&ring->queue)) {
 214                         b_schedule_timer = true;
 215                         break;
 216                 }
 217         }
 218
 219         if (b_schedule_timer) {
 220                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 221                                           jiffies + MSECS(10));
 222                 return;
 223         }
 224
 225         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 226                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 227                 if (!rtlhal->bfw_clk_change_in_progress) {
 228                         rtlhal->bfw_clk_change_in_progress = true;
 229                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 230                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 231                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 232                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 233                                 (u8 *) (&rpwm_val));
 234                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 235                         rtlhal->bfw_clk_change_in_progress = false;
 236                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 237                 } else {
 238                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 239                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 240                                           jiffies + MSECS(10));
 241                 }
 242         }
 243
 244 }
 245
 246 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 247 {
 248         u8 rpwm_val = 0;
 249         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 250         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 251 }
 252
 253 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 254 {
 255         struct rtl_priv *rtlpriv = rtl_priv(hw);
 256         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 257         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 258         bool b_fw_current_inps = false;
 259         u8 rpwm_val = 0,fw_pwrmode = FW_PS_ACTIVE_MODE;
 260
 261         if (ppsc->b_low_power_enable){
 262                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 263                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 264                 rtlhal->ballow_sw_to_change_hwclc = false;
 265                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 266                                 (u8 *) (&fw_pwrmode));
 267                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 268                                 (u8 *) (&b_fw_current_inps));
 269         } else {
 270                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 271                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 272                                 (u8 *) (&rpwm_val));
 273                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 274                                 (u8 *) (&fw_pwrmode));
 275                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 276                                 (u8 *) (&b_fw_current_inps));
 277         }
 278
 279 }
 280
 281 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 282 {
 283         struct rtl_priv *rtlpriv = rtl_priv(hw);
 284         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 285         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 286         bool b_fw_current_inps = true;
 287         u8 rpwm_val;
 288
 289         if (ppsc->b_low_power_enable){
 290                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 291                 rtlpriv->cfg->ops->set_hw_reg(hw,
 292                                 HW_VAR_FW_PSMODE_STATUS,
 293                                 (u8 *) (&b_fw_current_inps));
 294                 rtlpriv->cfg->ops->set_hw_reg(hw,
 295                                 HW_VAR_H2C_FW_PWRMODE,
 296                                 (u8 *) (&ppsc->fwctrl_psmode));
 297                 rtlhal->ballow_sw_to_change_hwclc = true;
 298                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 299
 300
 301         } else {
 302                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 303                 rtlpriv->cfg->ops->set_hw_reg(hw,
 304                                 HW_VAR_FW_PSMODE_STATUS,
 305                                 (u8 *) (&b_fw_current_inps));
 306                 rtlpriv->cfg->ops->set_hw_reg(hw,
 307                                 HW_VAR_H2C_FW_PWRMODE,
 308                                 (u8 *) (&ppsc->fwctrl_psmode));
 309                 rtlpriv->cfg->ops->set_hw_reg(hw,
 310                                 HW_VAR_SET_RPWM,
 311                                 (u8 *) (&rpwm_val));
 312         }
 313
 314 }
 315
 316 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 317 {
 318         struct rtl_priv *rtlpriv = rtl_priv(hw);
 319         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 320         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 321         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 322
 323         switch (variable) {
 324         case HW_VAR_ETHER_ADDR:
 325                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 326                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 327                 break;
 328         case HW_VAR_BSSID:
 329                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 330                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 331                 break;
 332         case HW_VAR_MEDIA_STATUS:
 333                 val[0] = rtl_read_byte(rtlpriv, REG_CR+2) & 0x3;
 334                 break;
 335         case HW_VAR_SLOT_TIME:
 336                 *((u8 *)(val)) = mac->slot_time;
 337                 break;
 338         case HW_VAR_BEACON_INTERVAL:
 339                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 340                 break;
 341         case HW_VAR_ATIM_WINDOW:
 342                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 343                 break;
 344         case HW_VAR_RCR:
 345                 *((u32 *) (val)) = rtlpci->receive_config;
 346                 break;
 347         case HW_VAR_RF_STATE:
 348                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 349                 break;
 350         case HW_VAR_FWLPS_RF_ON:{
 351                         enum rf_pwrstate rfState;
 352                         u32 val_rcr;
 353
 354                         rtlpriv->cfg->ops->get_hw_reg(hw,
 355                                                       HW_VAR_RF_STATE,
 356                                                       (u8 *) (&rfState));
 357                         if (rfState == ERFOFF) {
 358                                 *((bool *) (val)) = true;
 359                         } else {
 360                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 361                                 val_rcr &= 0x00070000;
 362                                 if (val_rcr)
 363                                         *((bool *) (val)) = false;
 364                                 else
 365                                         *((bool *) (val)) = true;
 366                         }
 367                         break;
 368                 }
 369         case HW_VAR_FW_PSMODE_STATUS:
 370                 *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
 371                 break;
 372         case HW_VAR_CORRECT_TSF:{
 373                         u64 tsf;
 374                         u32 *ptsf_low = (u32 *) & tsf;
 375                         u32 *ptsf_high = ((u32 *) & tsf) + 1;
 376
 377                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 378                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 379
 380                         *((u64 *) (val)) = tsf;
 381
 382                         break;
 383                 }
 384         default:
 385                 RT_TRACE(COMP_ERR, DBG_EMERG,
 386                          ("switch case not process %x\n",variable));
 387                 break;
 388         }
 389 }
 390
 391
 392 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 393 {
 394         struct rtl_priv *rtlpriv = rtl_priv(hw);
 395         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 396         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 397         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 398         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 399         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 400         u8 idx;
 401
 402         switch (variable) {
 403         case HW_VAR_ETHER_ADDR:{
 404                         for (idx = 0; idx < ETH_ALEN; idx++) {
 405                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 406                                                val[idx]);
 407                         }
 408                         break;
 409                 }
 410         case HW_VAR_BASIC_RATE:{
 411                         u16 b_rate_cfg = ((u16 *) val)[0];
 412                         u8 rate_index = 0;
 413                         b_rate_cfg = b_rate_cfg & 0x15f;
 414                         b_rate_cfg |= 0x01;
 415                         rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 416                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 417                                        (b_rate_cfg >> 8) & 0xff);
 418                         while (b_rate_cfg > 0x1) {
 419                                 b_rate_cfg = (b_rate_cfg >> 1);
 420                                 rate_index++;
 421                         }
 422                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 423                                        rate_index);
 424                         break;
 425                 }
 426         case HW_VAR_BSSID:{
 427                         for (idx = 0; idx < ETH_ALEN; idx++) {
 428                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 429                                                val[idx]);
 430                         }
 431                         break;
 432                 }
 433         case HW_VAR_SIFS:{
 434                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 435                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 436
 437                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 438                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 439
 440                         if (!mac->ht_enable)
 441                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 442                                                0x0e0e);
 443                         else
 444                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 445                                                *((u16 *) val));
 446                         break;
 447                 }
 448         case HW_VAR_SLOT_TIME:{
 449                         u8 e_aci;
 450
 451                         RT_TRACE(COMP_MLME, DBG_LOUD,
 452                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 453
 454                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 455
 456                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 457                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 458                                                               HW_VAR_AC_PARAM,
 459                                                               (u8 *) (&e_aci));
 460                         }
 461                         break;
 462                 }
 463         case HW_VAR_ACK_PREAMBLE:{
 464                         u8 reg_tmp;
 465                         u8 short_preamble = (bool) (*(u8 *) val);
 466                         reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 467                         if (short_preamble){
 468                                 reg_tmp |= BIT(1);
 469                                 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 470                         } else {
 471                                 reg_tmp &= (~BIT(1));
 472                                 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 473                         }
 474                         break;
 475                 }
 476         case HW_VAR_WPA_CONFIG:
 477                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 478                 break;
 479         case HW_VAR_AMPDU_MIN_SPACE:{
 480                         u8 min_spacing_to_set;
 481                         u8 sec_min_space;
 482
 483                         min_spacing_to_set = *((u8 *) val);
 484                         if (min_spacing_to_set <= 7) {
 485                                 sec_min_space = 0;
 486
 487                                 if (min_spacing_to_set < sec_min_space)
 488                                         min_spacing_to_set = sec_min_space;
 489
 490                                 mac->min_space_cfg = ((mac->min_space_cfg &
 491                                                        0xf8) |
 492                                                       min_spacing_to_set);
 493
 494                                 *val = min_spacing_to_set;
 495
 496                                 RT_TRACE(COMP_MLME, DBG_LOUD,
 497                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 498                                           mac->min_space_cfg));
 499
 500                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 501                                                mac->min_space_cfg);
 502                         }
 503                         break;
 504                 }
 505         case HW_VAR_SHORTGI_DENSITY:{
 506                         u8 density_to_set;
 507
 508                         density_to_set = *((u8 *) val);
 509                         mac->min_space_cfg |= (density_to_set << 3);
 510
 511                         RT_TRACE(COMP_MLME, DBG_LOUD,
 512                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 513                                   mac->min_space_cfg));
 514
 515                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 516                                        mac->min_space_cfg);
 517
 518                         break;
 519                 }
 520         case HW_VAR_AMPDU_FACTOR:{
 521                         u32     ampdu_len =  (*((u8 *)val));
 522                         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 523                                 if(ampdu_len < VHT_AGG_SIZE_128K)
 524                                         ampdu_len = (0x2000 << (*((u8 *)val))) -1;
 525                                 else
 526                                         ampdu_len = 0x1ffff;
 527                         } else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 528                                 if(ampdu_len < HT_AGG_SIZE_64K)
 529                                         ampdu_len = (0x2000 << (*((u8 *)val))) -1;
 530                                 else
 531                                         ampdu_len = 0xffff;
 532                         }
 533                         ampdu_len |= BIT(31);
 534
 535                         rtl_write_dword(rtlpriv,
 536                                 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 537                         break;
 538                 }
 539         case HW_VAR_AC_PARAM:{
 540                         u8 e_aci = *((u8 *) val);
 541                         rtl8821ae_dm_init_edca_turbo(hw);
 542
 543                         if (rtlpci->acm_method != eAcmWay2_SW)
 544                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 545                                                               HW_VAR_ACM_CTRL,
 546                                                               (u8 *) (&e_aci));
 547                         break;
 548                 }
 549         case HW_VAR_ACM_CTRL:{
 550                         u8 e_aci = *((u8 *) val);
 551                         union aci_aifsn *p_aci_aifsn =
 552                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 553                         u8 acm = p_aci_aifsn->f.acm;
 554                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 555
 556                         acm_ctrl =
 557                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 558
 559                         if (acm) {
 560                                 switch (e_aci) {
 561                                 case AC0_BE:
 562                                         acm_ctrl |= AcmHw_BeqEn;
 563                                         break;
 564                                 case AC2_VI:
 565                                         acm_ctrl |= AcmHw_ViqEn;
 566                                         break;
 567                                 case AC3_VO:
 568                                         acm_ctrl |= AcmHw_VoqEn;
 569                                         break;
 570                                 default:
 571                                         RT_TRACE(COMP_ERR, DBG_WARNING,
 572                                                  ("HW_VAR_ACM_CTRL acm set "
 573                                                   "failed: eACI is %d\n", acm));
 574                                         break;
 575                                 }
 576                         } else {
 577                                 switch (e_aci) {
 578                                 case AC0_BE:
 579                                         acm_ctrl &= (~AcmHw_BeqEn);
 580                                         break;
 581                                 case AC2_VI:
 582                                         acm_ctrl &= (~AcmHw_ViqEn);
 583                                         break;
 584                                 case AC3_VO:
 585                                         acm_ctrl &= (~AcmHw_BeqEn);
 586                                         break;
 587                                 default:
 588                                         RT_TRACE(COMP_ERR, DBG_EMERG,
 589                                                  ("switch case not process \n"));
 590                                         break;
 591                                 }
 592                         }
 593
 594                         RT_TRACE(COMP_QOS, DBG_TRACE,
 595                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 596                                   "Write 0x%X\n", acm_ctrl));
 597                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 598                         break;
 599                 }
 600         case HW_VAR_RCR:{
 601                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 602                         rtlpci->receive_config = ((u32 *) (val))[0];
 603                         break;
 604                 }
 605         case HW_VAR_RETRY_LIMIT:{
 606                         u8 retry_limit = ((u8 *) (val))[0];
 607
 608                         rtl_write_word(rtlpriv, REG_RL,
 609                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 610                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 611                         break;
 612                 }
 613         case HW_VAR_DUAL_TSF_RST:
 614                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 615                 break;
 616         case HW_VAR_EFUSE_BYTES:
 617                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 618                 break;
 619         case HW_VAR_EFUSE_USAGE:
 620                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 621                 break;
 622         case HW_VAR_IO_CMD:
 623                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 624                 break;
 625         case HW_VAR_SET_RPWM:{
 626                         u8 rpwm_val;
 627
 628                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 629                         udelay(1);
 630
 631                         if (rpwm_val & BIT(7)) {
 632                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 633                                                (*(u8 *) val));
 634                         } else {
 635                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 636                                                ((*(u8 *) val) | BIT(7)));
 637                         }
 638
 639                         break;
 640                 }
 641         case HW_VAR_H2C_FW_PWRMODE:{
 642                         rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 643                         break;
 644                 }
 645         case HW_VAR_FW_PSMODE_STATUS:
 646                 ppsc->b_fw_current_inpsmode = *((bool *) val);
 647                 break;
 648
 649         case HW_VAR_RESUME_CLK_ON:
 650                 _rtl8821ae_set_fw_ps_rf_on(hw);
 651                 break;
 652
 653         case HW_VAR_FW_LPS_ACTION:{
 654                 bool b_enter_fwlps = *((bool *) val);
 655
 656                 if (b_enter_fwlps)
 657                         _rtl8821ae_fwlps_enter(hw);
 658                  else
 659                         _rtl8821ae_fwlps_leave(hw);
 660
 661                  break;
 662                 }
 663
 664         case HW_VAR_H2C_FW_JOINBSSRPT:{
 665                         u8 mstatus = (*(u8 *) val);
 666                         u8 tmp_regcr, tmp_reg422,bcnvalid_reg;
 667                         u8 count = 0, dlbcn_count = 0;
 668                         bool b_recover = false;
 669
 670                         if (mstatus == RT_MEDIA_CONNECT) {
 671                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 672                                                               NULL);
 673
 674                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 675                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 676                                                (tmp_regcr | BIT(0)));
 677
 678                                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 679                                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 680
 681                                 tmp_reg422 =
 682                                     rtl_read_byte(rtlpriv,
 683                                                   REG_FWHW_TXQ_CTRL + 2);
 684                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 685                                                tmp_reg422 & (~BIT(6)));
 686                                 if (tmp_reg422 & BIT(6))
 687                                         b_recover = true;
 688
 689                                 do {
 690                                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 691                                         rtl_write_byte(rtlpriv, REG_TDECTRL+2,(bcnvalid_reg | BIT(0)));
 692                                         _rtl8821ae_return_beacon_queue_skb(hw);
 693
 694                                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 695                                                 rtl8812ae_set_fw_rsvdpagepkt(hw, 0);
 696                                         else
 697                                                 rtl8821ae_set_fw_rsvdpagepkt(hw, 0);
 698                                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 699                                         count = 0;
 700                                         while (!(bcnvalid_reg & BIT(0)) && count <20){
 701                                                 count++;
 702                                                 udelay(10);
 703                                                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 704                                         }
 705                                         dlbcn_count++;
 706                                 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count <5);
 707
 708                                 if (bcnvalid_reg & BIT(0))
 709                                         rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 710
 711                                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 712                                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 713
 714                                 if (b_recover) {
 715                                         rtl_write_byte(rtlpriv,
 716                                                        REG_FWHW_TXQ_CTRL + 2,
 717                                                        tmp_reg422);
 718                                 }
 719
 720                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 721                                                (tmp_regcr & ~(BIT(0))));
 722                         }
 723                         rtl8821ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 724
 725                         break;
 726                 }
 727         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
 728                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *) val));
 729                 break;
 730         }
 731
 732         case HW_VAR_AID:{
 733                         u16 u2btmp;
 734                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 735                         u2btmp &= 0xC000;
 736                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 737                                                 mac->assoc_id));
 738
 739                         break;
 740                 }
 741         case HW_VAR_CORRECT_TSF:{
 742                         u8 btype_ibss = ((u8 *) (val))[0];
 743
 744                         if (btype_ibss == true)
 745                                 _rtl8821ae_stop_tx_beacon(hw);
 746
 747                         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 748
 749                         rtl_write_dword(rtlpriv, REG_TSFTR,
 750                                         (u32) (mac->tsf & 0xffffffff));
 751                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 752                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 753
 754                         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 755
 756                         if (btype_ibss == true)
 757                                 _rtl8821ae_resume_tx_beacon(hw);
 758
 759                         break;
 760
 761                 }
 762         case HW_VAR_NAV_UPPER: {
 763                         u32     us_nav_upper = ((u32)*val);
 764
 765                         if(us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF)
 766                         {
 767                                 RT_TRACE(COMP_INIT , DBG_WARNING,
 768                                         ("The setting value (0x%08X us) of NAV_UPPER"
 769                                          " is larger than (%d * 0xFF)!!!\n",
 770                                          us_nav_upper, HAL_92C_NAV_UPPER_UNIT));
 771                                 break;
 772                         }
 773                         rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 774                                 ((u8)((us_nav_upper + HAL_92C_NAV_UPPER_UNIT - 1) / HAL_92C_NAV_UPPER_UNIT)));
 775                         break;
 776                 }
 777         case HW_VAR_KEEP_ALIVE: {
 778                         u8 array[2];
 779                         array[0] = 0xff;
 780                         array[1] = *((u8 *)val);
 781                         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, array);
 782                 }
 783         default:
 784                 RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case "
 785                                                         "not process %x\n",variable));
 786                 break;
 787         }
 788 }
 789
 790 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 791 {
 792         struct rtl_priv *rtlpriv = rtl_priv(hw);
 793         bool status = true;
 794         long count = 0;
 795         u32 value = _LLT_INIT_ADDR(address) |
 796             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 797
 798         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 799
 800         do {
 801                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 802                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 803                         break;
 804
 805                 if (count > POLLING_LLT_THRESHOLD) {
 806                         RT_TRACE(COMP_ERR, DBG_EMERG,
 807                                  ("Failed to polling write LLT done at "
 808                                   "address %d!\n", address));
 809                         status = false;
 810                         break;
 811                 }
 812         } while (++count);
 813
 814         return status;
 815 }
 816
 817 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 818 {
 819         struct rtl_priv *rtlpriv = rtl_priv(hw);
 820         unsigned short i;
 821         u8 txpktbuf_bndy;
 822         u8 maxPage;
 823         bool status;
 824
 825         maxPage = 255;
 826         txpktbuf_bndy = 0xF8;
 827
 828
 829         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 830         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 831
 832         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 833
 834         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 835         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 836
 837         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 838         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 839
 840         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 841                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 842                 if (true != status)
 843                         return status;
 844         }
 845
 846         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 847         if (true != status)
 848                 return status;
 849
 850         for (i = txpktbuf_bndy; i < maxPage; i++) {
 851                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 852                 if (true != status)
 853                         return status;
 854         }
 855
 856         status = _rtl8821ae_llt_write(hw, maxPage, txpktbuf_bndy);
 857         if (true != status)
 858                 return status;
 859
 860         rtl_write_dword(rtlpriv, REG_RQPN, 0x80e70808);
 861         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 862
 863         return true;
 864 }
 865
 866 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 867 {
 868         struct rtl_priv *rtlpriv = rtl_priv(hw);
 869         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 870         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 871         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 872         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 873
 874         if (rtlpriv->rtlhal.up_first_time)
 875                 return;
 876
 877         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 878                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 879                         rtl8812ae_sw_led_on(hw, pLed0);
 880                 else
 881                         rtl8821ae_sw_led_on(hw, pLed0);
 882         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 883                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 884                         rtl8812ae_sw_led_on(hw, pLed0);
 885                 else
 886                         rtl8821ae_sw_led_on(hw, pLed0);
 887         else
 888                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 889                         rtl8812ae_sw_led_off(hw, pLed0);
 890                 else
 891                         rtl8821ae_sw_led_off(hw, pLed0);
 892 }
 893
 894 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 895 {
 896         struct rtl_priv *rtlpriv = rtl_priv(hw);
 897         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 898         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 899
 900         u8 bytetmp = 0;
 901         u16 wordtmp = 0;
 902         bool b_mac_func_enable = rtlhal->b_mac_func_enable;
 903
 904         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 905
 906         /*Auto Power Down to CHIP-off State*/
 907         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 908         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 909
 910         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 911                 /* HW Power on sequence*/
 912                 if(!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 913                         PWR_INTF_PCI_MSK, RTL8812_NIC_ENABLE_FLOW)) {
 914                                 RT_TRACE(COMP_INIT,DBG_LOUD,("init 8812 MAC Fail as power on failure\n"));
 915                                 return false;
 916                 }
 917         } else {
 918                 /* HW Power on sequence */
 919                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, PWR_FAB_ALL_MSK,
 920                         PWR_INTF_PCI_MSK, RTL8821A_NIC_ENABLE_FLOW)){
 921                         RT_TRACE(COMP_INIT,DBG_LOUD,("init 8821 MAC Fail as power on failure\n"));
 922                         return false;
 923                 }
 924         }
 925
 926         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 927         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 928
 929         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 930         bytetmp = 0xff;
 931         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 932         mdelay(2);
 933
 934         bytetmp |= 0x7f;
 935         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 936         mdelay(2);
 937
 938         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 939                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 940                 if (bytetmp & BIT(0)) {
 941                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 942                         bytetmp |= BIT(6);
 943                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 944                 }
 945         }
 946
 947         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 948         bytetmp &= ~BIT(4);
 949         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 950
 951         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 952
 953         if (!b_mac_func_enable) {
 954                 if (!_rtl8821ae_llt_table_init(hw))
 955                         return false;
 956         }
 957
 958         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 959         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 960
 961         /* Enable FW Beamformer Interrupt */
 962         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 963         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 964
 965         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 966         wordtmp &= 0xf;
 967         wordtmp |= 0xF5B1;
 968         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 969
 970         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 971         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 972         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 973         /*low address*/
 974         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 975                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
 976         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 977                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
 978         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 979                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 980         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 981                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 982         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 983                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 984         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 985                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 986         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 987                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
 988         rtl_write_dword(rtlpriv, REG_RX_DESA,
 989                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
 990
 991         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 992
 993         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 994
 995         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
 996         _rtl8821ae_gen_refresh_led_state(hw);
 997
 998         return true;
 999 }
1000
1001 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1002 {
1003         struct rtl_priv *rtlpriv = rtl_priv(hw);
1004         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1005         u32 reg_rrsr;
1006
1007         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1008
1009         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1010         /* ARFB table 9 for 11ac 5G 2SS */
1011         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1012         /* ARFB table 10 for 11ac 5G 1SS */
1013         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1014         /* ARFB table 11 for 11ac 24G 1SS */
1015         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1016         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1017         /* ARFB table 12 for 11ac 24G 1SS */
1018         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1019         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1020         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not signal MPDU. */
1021         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1022         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1023
1024         /*Set retry limit*/
1025         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1026
1027
1028         /* Set Data / Response auto rate fallack retry count*/
1029         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1030         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1031         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1032         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1033
1034         rtlpci->reg_bcn_ctrl_val = 0x1d;
1035         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1036
1037         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1038         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1,0xff); // 8 ms
1039
1040         /* AGGR_BK_TIME Reg51A 0x16 */
1041         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1042
1043         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1044         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1045
1046         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1047         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1048         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1049 }
1050
1051 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1052 {
1053         u16 ret = 0;
1054         u8 tmp = 0, count = 0;
1055
1056         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1057         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6) ;
1058         count = 0;
1059         while (tmp && count < 20) {
1060                 udelay(10);
1061                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1062                 count++;
1063         }
1064         if (0 == tmp)
1065                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1066
1067         return ret;
1068 }
1069
1070 void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1071 {
1072         u8 tmp = 0, count = 0;
1073
1074         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1075         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1076         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5) ;
1077         count = 0;
1078         while (tmp && count < 20) {
1079                 udelay(10);
1080                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1081                 count++;
1082         }
1083 }
1084
1085 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1086 {
1087         u16 read_addr = addr & 0xfffc;
1088         u8 tmp = 0, count = 0, ret = 0;
1089
1090         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1091         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1092         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1093         count = 0;
1094         while (tmp && count < 20) {
1095                 udelay(10);
1096                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1097                 count++;
1098         }
1099         if (0 == tmp) {
1100                 read_addr = REG_DBI_RDATA + addr % 4;
1101                 ret = rtl_read_word(rtlpriv, read_addr);
1102         }
1103         return ret;
1104 }
1105
1106 void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1107 {
1108         u8 tmp = 0, count = 0;
1109         u16 wrtie_addr, remainder = addr % 4;
1110
1111         wrtie_addr = REG_DBI_WDATA + remainder;
1112         rtl_write_byte(rtlpriv, wrtie_addr, data);
1113
1114         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1115         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1116
1117         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1118
1119         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1120         count = 0;
1121         while (tmp && count < 20) {
1122                 udelay(10);
1123                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1124                 count++;
1125         }
1126
1127 }
1128
1129 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1130 {
1131         struct rtl_priv *rtlpriv = rtl_priv(hw);
1132         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1133         u8 tmp;
1134
1135         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1136                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1137                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1138
1139                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1140                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1141         }
1142
1143         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1144         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1145
1146         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1147         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1148
1149         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1150         {
1151                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1152                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1153         }
1154 }
1155
1156 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1157 {
1158         struct rtl_priv *rtlpriv = rtl_priv(hw);
1159         u8 sec_reg_value;
1160         u8 tmp;
1161
1162         RT_TRACE(COMP_INIT, DBG_DMESG,
1163                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1164                   rtlpriv->sec.pairwise_enc_algorithm,
1165                   rtlpriv->sec.group_enc_algorithm));
1166
1167         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1168                 RT_TRACE(COMP_SEC, DBG_DMESG, ("not open hw encryption\n"));
1169                 return;
1170         }
1171
1172         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1173
1174         if (rtlpriv->sec.use_defaultkey) {
1175                 sec_reg_value |= SCR_TxUseDK;
1176                 sec_reg_value |= SCR_RxUseDK;
1177         }
1178
1179         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1180
1181         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1182         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1183
1184         RT_TRACE(COMP_SEC, DBG_DMESG,
1185                  ("The SECR-value %x \n", sec_reg_value));
1186
1187         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1188
1189 }
1190
1191 #if 0
1192 bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1193 {
1194         struct rtl_priv *rtlpriv = rtl_priv(hw);
1195         u8 tmp;
1196         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL+3);
1197         if (!(tmp&BIT(2))) {
1198                 rtl_write_byte(rtlpriv, REG_DBI_CTRL+3, tmp|BIT(2));
1199                 mdelay(100);
1200         }
1201
1202         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL+3);
1203         if (tmp&BIT(0) || tmp&BIT(1)) {
1204                 RT_TRACE(COMP_INIT, DBG_LOUD,
1205                         ("rtl8821ae_check_pcie_dma_hang(): TRUE! Reset PCIE DMA!\n"));
1206                 return true;
1207         } else {
1208                 return false;
1209         }
1210 }
1211
1212 void _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1213                                                                                                         bool mac_power_on, bool watch_dog)
1214 {
1215         struct rtl_priv *rtlpriv = rtl_priv(hw);
1216         u8 tmp;
1217         bool release_mac_rx_pause;
1218         u8 backup_pcie_dma_pause;
1219
1220         RT_TRACE(COMP_INIT, DBG_LOUD, ("_rtl8821ae_reset_pcie_interface_dma()\n"));
1221
1222         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1223         tmp &= ~BIT(1);
1224         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1225         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1226         tmp |= BIT2;
1227         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1228
1229         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1230         if (tmp & BIT(2)) {
1231                 release_mac_rx_pause = false;
1232         } else {
1233                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp | BIT(2));
1234                 release_mac_rx_pause = true;
1235         }
1236         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+1);
1237         if (backup_pcie_dma_pause != 0xFF)
1238                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1239
1240         if (mac_power_on)
1241                 rtl_write_byte(rtlpriv, REG_CR, 0);
1242
1243         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1244         tmp &= ~BIT(0);
1245         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, tmp);
1246
1247         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1248         tmp |= ~BIT(0);
1249         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, tmp);
1250
1251         if (mac_power_on)
1252                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1253
1254         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL+2);
1255         tmp |= BIT1;
1256         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL+2, tmp);
1257
1258         if (watch_dog) {
1259                 u32 rqpn = 0;
1260                 u32 rqpn_npq = 0;
1261                 u8 tx_page_boundary = _RQPN_Init_8812E(Adapter, &rqpn_npq, &rqpn);
1262
1263                 if(LLT_table_init_8812(Adapter, TX_PAGE_BOUNDARY, RQPN, RQPN_NPQ) == RT_STATUS_FAILURE)
1264                         return false;
1265
1266                         PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
1267                         PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
1268
1269                         // <1> Reset Tx descriptor
1270                         Adapter->HalFunc.ResetTxDescHandler(Adapter,Adapter->NumTxDesc);
1271
1272                         // <2> Reset Rx descriptor
1273                         Adapter->HalFunc.ResetRxDescHandler(Adapter,Adapter->NumRxDesc);
1274
1275                         // <3> Reset RFDs
1276                         FreeRFDs( Adapter, TRUE);
1277
1278                         // <4> Reset TCBs
1279                         FreeTCBs( Adapter, TRUE);
1280
1281                         // We should set all Rx desc own bit to 1 to prevent from RDU after enable Rx DMA. 2013.02.18, by tynli.
1282                         PrepareAllRxDescBuffer(Adapter);
1283
1284                         PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
1285                         PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
1286
1287                         //
1288                         // Initialize TRx DMA address.
1289                         //
1290                         // Because set 0x100 to 0x0 will cause the Rx descriptor address 0x340 be cleared to zero on 88EE,
1291                         // we should re-initialize Rx desc. address before enable DMA. 2012.11.07. by tynli.
1292                         InitTRxDescHwAddress8812AE(Adapter);
1293                 }
1294
1295                 // In MAC power on state, BB and RF maybe in ON state, if we release TRx DMA here
1296                 // it will cause packets to be started to Tx/Rx, so we release Tx/Rx DMA later.
1297                 if(!bInMACPowerOn || bInWatchDog)
1298                 {
1299                         // 8. release TRX DMA
1300                         //write 0x284 bit[18] = 1'b0
1301                         //write 0x301 = 0x00
1302                         if(bReleaseMACRxPause)
1303                         {
1304                                 u1Tmp = PlatformEFIORead1Byte(Adapter, REG_RXDMA_CONTROL);
1305                                 PlatformEFIOWrite1Byte(Adapter, REG_RXDMA_CONTROL, (u1Tmp&~BIT2));
1306                         }
1307                         PlatformEFIOWrite1Byte(Adapter,         REG_PCIE_CTRL_REG+1, BackUpPcieDMAPause);
1308                 }
1309
1310                 if(IS_HARDWARE_TYPE_8821E(Adapter))
1311                 {
1312                         //9. lock system register
1313                         //       write 0xCC bit[2] = 1'b0
1314                         u1Tmp = PlatformEFIORead1Byte(Adapter, REG_PMC_DBG_CTRL2_8723B);
1315                         u1Tmp &= ~(BIT2);
1316                         PlatformEFIOWrite1Byte(Adapter, REG_PMC_DBG_CTRL2_8723B, u1Tmp);
1317                 }
1318
1319                 return RT_STATUS_SUCCESS;
1320 }
1321 #endif
1322
1323 // Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ----------
1324 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1325 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1326 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1327 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1328 // -----------------------------------------------------------
1329
1330 void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1331 {
1332         struct rtl_priv *rtlpriv = rtl_priv(hw);
1333         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1, \
1334                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, \
1335                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1336
1337         rtlpriv->cfg->ops->set_hw_reg(hw, \
1338                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1339
1340         RT_TRACE(COMP_INIT,DBG_LOUD, \
1341                 ("Initialize MacId media status: from %d to %d\n", \
1342                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, \
1343                 MAC_ID_STATIC_FOR_BT_CLIENT_END));
1344 }
1345
1346 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1347 {
1348         struct rtl_priv *rtlpriv = rtl_priv(hw);
1349         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1350         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1351         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1352         bool rtstatus = true;
1353         int err;
1354         u8 tmp_u1b;
1355         u32 nav_upper = WIFI_NAV_UPPER_US;
1356
1357         rtlpriv->rtlhal.being_init_adapter = true;
1358         rtlpriv->intf_ops->disable_aspm(hw);
1359
1360         /*YP wowlan not considered*/
1361
1362         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1363         if (tmp_u1b!=0 && tmp_u1b != 0xEA) {
1364                 rtlhal->b_mac_func_enable = true;
1365                 RT_TRACE(COMP_INIT,DBG_LOUD,(" MAC has already power on.\n"));
1366         } else {
1367                 rtlhal->b_mac_func_enable = false;
1368                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1369         }
1370
1371 /*      if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1372                 _rtl8821ae_reset_pcie_interface_dma(hw,rtlhal->b_mac_func_enable,false);
1373                 rtlhal->b_mac_func_enable = false;
1374         } */
1375
1376         rtstatus = _rtl8821ae_init_mac(hw);
1377         if (rtstatus != true) {
1378                 RT_TRACE(COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
1379                 err = 1;
1380                 return err;
1381         }
1382
1383         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1384         tmp_u1b &= 0x7F;
1385         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1386
1387         err = rtl8821ae_download_fw(hw, false);
1388         if (err) {
1389                 RT_TRACE(COMP_ERR, DBG_WARNING,
1390                          ("Failed to download FW. Init HW "
1391                           "without FW now..\n"));
1392                 err = 1;
1393                 rtlhal->bfw_ready = false;
1394                 return err;
1395         } else {
1396                 rtlhal->bfw_ready = true;
1397         }
1398         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1399         rtlhal->bfw_clk_change_in_progress = false;
1400         rtlhal->ballow_sw_to_change_hwclc = false;
1401         rtlhal->last_hmeboxnum = 0;
1402
1403         /*SIC_Init(Adapter);
1404         if(pHalData->AMPDUBurstMode)
1405                 PlatformEFIOWrite1Byte(Adapter,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1406
1407         rtl8821ae_phy_mac_config(hw);
1408         /* because last function modify RCR, so we update
1409          * rcr var here, or TP will unstable for receive_config
1410          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1411          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1412         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1413         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1414         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1415         rtl8821ae_phy_bb_config(hw);
1416
1417         rtl8821ae_phy_rf_config(hw);
1418
1419         _rtl8821ae_hw_configure(hw);
1420
1421         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1422
1423         /*set wireless mode*/
1424
1425         rtlhal->b_mac_func_enable = true;
1426
1427         rtl_cam_reset_all_entry(hw);
1428
1429         rtl8821ae_enable_hw_security_config(hw);
1430
1431         ppsc->rfpwr_state = ERFON;
1432
1433         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1434         _rtl8821ae_enable_aspm_back_door(hw);
1435         rtlpriv->intf_ops->enable_aspm(hw);
1436
1437         //rtl8821ae_bt_hw_init(hw);
1438         rtlpriv->rtlhal.being_init_adapter = false;
1439
1440         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1441
1442         //rtl8821ae_dm_check_txpower_tracking(hw);
1443         //rtl8821ae_phy_lc_calibrate(hw);
1444
1445         /* Release Rx DMA*/
1446         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1447         if (tmp_u1b & BIT(2)) {
1448                 /* Release Rx DMA if needed*/
1449                 tmp_u1b &= ~BIT(2);
1450                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1451         }
1452
1453         /* Release Tx/Rx PCIE DMA if*/
1454         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1455
1456         rtl8821ae_dm_init(hw);
1457         rtl8821ae_macid_initialize_mediastatus(hw);
1458
1459         RT_TRACE(COMP_INIT, DBG_LOUD, ("rtl8821ae_hw_init() <====\n"));
1460         return err;
1461 }
1462
1463 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
1464 {
1465         struct rtl_priv *rtlpriv = rtl_priv(hw);
1466         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1467         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1468         enum version_8821ae version = VERSION_UNKNOWN;
1469         u32 value32;
1470
1471         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1472         RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadChipVersion8812A 0xF0 = 0x%x \n", value32));
1473
1474
1475
1476         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1477                 rtlphy->rf_type = RF_2T2R;
1478         else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1479                 rtlphy->rf_type = RF_1T1R;
1480
1481         RT_TRACE(COMP_INIT, DBG_LOUD, ("RF_Type is %x!!\n", rtlphy->rf_type));
1482
1483
1484         if (value32 & TRP_VAUX_EN)
1485         {
1486                 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1487                 {
1488                         if(rtlphy->rf_type == RF_2T2R)
1489                                 version = VERSION_TEST_CHIP_2T2R_8812;
1490                         else
1491                                 version = VERSION_TEST_CHIP_1T1R_8812;
1492                 }
1493                 else
1494                         version = VERSION_TEST_CHIP_8821;
1495         } else {
1496                 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1497                 {
1498                         u32     rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) +1 ;
1499
1500                         if(rtlphy->rf_type == RF_2T2R)
1501                                 version = (enum version_8821ae)(CHIP_8812 | NORMAL_CHIP | RF_TYPE_2T2R);
1502                         else
1503                                 version = (enum version_8821ae)(CHIP_8812 | NORMAL_CHIP);
1504
1505                         version = (enum version_8821ae)(version| (rtl_id << 12));
1506                 }
1507                 else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1508                 {
1509                         u32     rtl_id = value32 & CHIP_VER_RTL_MASK;
1510
1511                         version = (enum version_8821ae)(CHIP_8821 | NORMAL_CHIP | rtl_id);
1512                 }
1513         }
1514
1515         RT_TRACE(COMP_INIT, DBG_LOUD,
1516                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1517                   "RF_2T2R" : "RF_1T1R"));
1518
1519         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1520         {
1521                 /*WL_HWROF_EN.*/
1522                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1523                 rtlphy->hw_rof_enable= ((value32 & WL_HWROF_EN) ? 1 : 0);
1524         }
1525
1526         switch(version)
1527         {
1528                 case VERSION_TEST_CHIP_1T1R_8812:
1529                         RT_TRACE(COMP_INIT, DBG_LOUD,
1530                                 ("Chip Version ID: VERSION_TEST_CHIP_1T1R_8812.\n"));
1531                         break;
1532                 case VERSION_TEST_CHIP_2T2R_8812:
1533                         RT_TRACE(COMP_INIT, DBG_LOUD,
1534                                 ("Chip Version ID: VERSION_TEST_CHIP_2T2R_8812.\n"));
1535                         break;
1536                 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
1537                         RT_TRACE(COMP_INIT, DBG_LOUD,
1538                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812.\n"));
1539                         break;
1540                 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
1541                         RT_TRACE(COMP_INIT, DBG_LOUD,
1542                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812.\n"));
1543                         break;
1544                 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
1545                         RT_TRACE(COMP_INIT, DBG_LOUD,
1546                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT.\n"));
1547                         break;
1548                 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
1549                         RT_TRACE(COMP_INIT, DBG_LOUD,
1550                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT.\n"));
1551                         break;
1552                 case VERSION_TEST_CHIP_8821:
1553                         RT_TRACE(COMP_INIT, DBG_LOUD,
1554                                 ("Chip Version ID: VERSION_TEST_CHIP_8821.\n"));
1555                         break;
1556                 case VERSION_NORMAL_TSMC_CHIP_8821:
1557                         RT_TRACE(COMP_INIT, DBG_LOUD,
1558                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT.\n"));
1559                         break;
1560                 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
1561                         RT_TRACE(COMP_INIT, DBG_LOUD,
1562                                 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT.\n"));
1563                         break;
1564                 default:
1565                         RT_TRACE(COMP_INIT, DBG_LOUD,
1566                                 ("Chip Version ID: Unknown (0x%X).\n", version));
1567                         break;
1568         }
1569
1570         return version;
1571 }
1572
1573 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
1574                                      enum nl80211_iftype type)
1575 {
1576         struct rtl_priv *rtlpriv = rtl_priv(hw);
1577         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1578         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1579         bt_msr &= 0xfc;
1580
1581         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1582         RT_TRACE(COMP_BEACON, DBG_LOUD,
1583                 ("clear 0x550 when set HW_VAR_MEDIA_STATUS\n"));
1584
1585         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1586             type == NL80211_IFTYPE_STATION) {
1587                 _rtl8821ae_stop_tx_beacon(hw);
1588                 _rtl8821ae_enable_bcn_sub_func(hw);
1589         } else if (type == NL80211_IFTYPE_ADHOC ||
1590                 type == NL80211_IFTYPE_AP) {
1591                 _rtl8821ae_resume_tx_beacon(hw);
1592                 _rtl8821ae_disable_bcn_sub_func(hw);
1593         } else {
1594                 RT_TRACE(COMP_ERR, DBG_WARNING,("Set HW_VAR_MEDIA_STATUS: "
1595                           "No such media status(%x).\n", type));
1596         }
1597
1598         switch (type) {
1599         case NL80211_IFTYPE_UNSPECIFIED:
1600                 bt_msr |= MSR_NOLINK;
1601                 ledaction = LED_CTL_LINK;
1602                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to NO LINK!\n"));
1603                 break;
1604         case NL80211_IFTYPE_ADHOC:
1605                 bt_msr |= MSR_ADHOC;
1606                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to Ad Hoc!\n"));
1607                 break;
1608         case NL80211_IFTYPE_STATION:
1609                 bt_msr |= MSR_INFRA;
1610                 ledaction = LED_CTL_LINK;
1611                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to STA!\n"));
1612                 break;
1613         case NL80211_IFTYPE_AP:
1614                 bt_msr |= MSR_AP;
1615                 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to AP!\n"));
1616                 break;
1617         default:
1618                 RT_TRACE(COMP_ERR, DBG_EMERG, ("Network type %d not support!\n", type));
1619                 return 1;
1620                 break;
1621
1622         }
1623
1624         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1625         rtlpriv->cfg->ops->led_control(hw, ledaction);
1626         if ((bt_msr & ~0xfc) == MSR_AP)
1627                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1628         else
1629                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1630
1631         return 0;
1632 }
1633
1634 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1635 {
1636         struct rtl_priv *rtlpriv = rtl_priv(hw);
1637         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1638         u32 reg_rcr = rtlpci->receive_config;
1639
1640         if (rtlpriv->psc.rfpwr_state != ERFON)
1641                 return;
1642
1643         if (check_bssid == true) {
1644                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1645                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1646                                               (u8 *) (&reg_rcr));
1647                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
1648         } else if (check_bssid == false) {
1649                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1650                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
1651                 rtlpriv->cfg->ops->set_hw_reg(hw,
1652                         HW_VAR_RCR, (u8 *) (&reg_rcr));
1653         }
1654
1655 }
1656
1657 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1658 {
1659         struct rtl_priv *rtlpriv = rtl_priv(hw);
1660
1661         RT_TRACE(COMP_INIT, DBG_LOUD, ("rtl8821ae_set_network_type!\n"));
1662
1663         if (_rtl8821ae_set_media_status(hw, type))
1664                 return -EOPNOTSUPP;
1665
1666         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1667                 if (type != NL80211_IFTYPE_AP)
1668                         rtl8821ae_set_check_bssid(hw, true);
1669         } else {
1670                 rtl8821ae_set_check_bssid(hw, false);
1671         }
1672
1673         return 0;
1674 }
1675
1676 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1677 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
1678 {
1679         struct rtl_priv *rtlpriv = rtl_priv(hw);
1680         rtl8821ae_dm_init_edca_turbo(hw);
1681         switch (aci) {
1682         case AC1_BK:
1683                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1684                 break;
1685         case AC0_BE:
1686                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1687                 break;
1688         case AC2_VI:
1689                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1690                 break;
1691         case AC3_VO:
1692                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1693                 break;
1694         default:
1695                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1696                 break;
1697         }
1698 }
1699
1700 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
1701 {
1702         struct rtl_priv *rtlpriv = rtl_priv(hw);
1703         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1704
1705         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1706         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1707         rtlpci->irq_enabled = true;
1708         /* there are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM.
1709         *So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore.
1710         */
1711         //rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1712         /*enable system interrupt*/
1713         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1714 }
1715
1716 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
1717 {
1718         struct rtl_priv *rtlpriv = rtl_priv(hw);
1719         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1720
1721         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1722         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1723         rtlpci->irq_enabled = false;
1724         synchronize_irq(rtlpci->pdev->irq);
1725 }
1726
1727 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1728 {
1729         struct rtl_priv *rtlpriv = rtl_priv(hw);
1730         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1731         u8 u1b_tmp;
1732
1733         rtlhal->b_mac_func_enable = false;
1734
1735         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1736         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1737         /* 1. Run LPS WL RFOFF flow */
1738                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"));
1739                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1740                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1741         }
1742         /* 2. 0x1F[7:0] = 0 */
1743         /* turn off RF */
1744         //rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1745         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1746                 rtlhal->bfw_ready ) {
1747                 rtl8821ae_firmware_selfreset(hw);
1748         }
1749
1750         /* Reset MCU. Suggested by Filen. */
1751         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1752         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1753
1754         /* g.   MCUFWDL 0x80[1:0]=0      */
1755         /* reset MCU ready status */
1756         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1757
1758         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1759                 /* HW card disable configuration. */
1760                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1761                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1762         } else {
1763                 /* HW card disable configuration. */
1764                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1765                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1766         }
1767
1768         /* Reset MCU IO Wrapper */
1769         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1770         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1771         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1772         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1773
1774         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1775         /* lock ISO/CLK/Power control register */
1776         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1777 }
1778
1779 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
1780 {
1781         struct rtl_priv *rtlpriv = rtl_priv(hw);
1782         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1783         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1784         enum nl80211_iftype opmode;
1785
1786         RT_TRACE(COMP_INIT, DBG_LOUD,
1787                  ("rtl8821ae_card_disable.\n"));
1788
1789         mac->link_state = MAC80211_NOLINK;
1790         opmode = NL80211_IFTYPE_UNSPECIFIED;
1791         _rtl8821ae_set_media_status(hw, opmode);
1792         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1793             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1794                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1795         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1796         _rtl8821ae_poweroff_adapter(hw);
1797
1798         /* after power off we should do iqk again */
1799         rtlpriv->phy.iqk_initialized = false;
1800 }
1801
1802 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
1803                                   u32 *p_inta, u32 *p_intb)
1804 {
1805         struct rtl_priv *rtlpriv = rtl_priv(hw);
1806         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1807
1808         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1809         rtl_write_dword(rtlpriv, ISR, *p_inta);
1810
1811
1812         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1813         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1814
1815 }
1816
1817
1818 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1819 {
1820
1821         struct rtl_priv *rtlpriv = rtl_priv(hw);
1822         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1823         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1824         u16 bcn_interval, atim_window;
1825
1826         bcn_interval = mac->beacon_interval;
1827         atim_window = 2;        /*FIX MERGE */
1828         rtl8821ae_disable_interrupt(hw);
1829         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1830         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1831         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1832         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1833         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1834         rtl_write_byte(rtlpriv, 0x606, 0x30);
1835         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1836         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1837         rtl8821ae_enable_interrupt(hw);
1838 }
1839
1840 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
1841 {
1842         struct rtl_priv *rtlpriv = rtl_priv(hw);
1843         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1844         u16 bcn_interval = mac->beacon_interval;
1845
1846         RT_TRACE(COMP_BEACON, DBG_DMESG,
1847                  ("beacon_interval:%d\n", bcn_interval));
1848         rtl8821ae_disable_interrupt(hw);
1849         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1850         rtl8821ae_enable_interrupt(hw);
1851 }
1852
1853 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
1854                                    u32 add_msr, u32 rm_msr)
1855 {
1856         struct rtl_priv *rtlpriv = rtl_priv(hw);
1857         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1858
1859         RT_TRACE(COMP_INTR, DBG_LOUD,
1860                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1861
1862         if (add_msr)
1863                 rtlpci->irq_mask[0] |= add_msr;
1864         if (rm_msr)
1865                 rtlpci->irq_mask[0] &= (~rm_msr);
1866         rtl8821ae_disable_interrupt(hw);
1867         rtl8821ae_enable_interrupt(hw);
1868 }
1869
1870 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
1871 {
1872         u8 group = 0;
1873
1874         if (chnl <= 14) {
1875                 if (1 <= chnl && chnl <= 2 )
1876                         group = 0;
1877         else if (3 <= chnl && chnl <= 5 )
1878                         group = 1;
1879         else if (6 <= chnl && chnl <= 8 )
1880                         group = 2;
1881         else if (9 <= chnl && chnl <= 11)
1882                         group = 3;
1883         else /*if (12 <= chnl && chnl <= 14)*/
1884                         group = 4;
1885         } else {
1886                 if (36 <= chnl && chnl <= 42)
1887                         group = 0;
1888         else if (44 <= chnl && chnl <= 48)
1889                         group = 1;
1890         else if (50 <= chnl && chnl <= 58)
1891                         group = 2;
1892         else if (60 <= chnl && chnl <= 64)
1893                         group = 3;
1894         else if (100 <= chnl && chnl <= 106)
1895                         group = 4;
1896         else if (108 <= chnl && chnl <= 114)
1897                         group = 5;
1898         else if (116 <= chnl && chnl <= 122)
1899                         group = 6;
1900         else if (124 <= chnl && chnl <= 130)
1901                         group = 7;
1902         else if (132 <= chnl && chnl <= 138)
1903                         group = 8;
1904         else if (140 <= chnl && chnl <= 144)
1905                         group = 9;
1906         else if (149 <= chnl && chnl <= 155)
1907                         group = 10;
1908         else if (157 <= chnl && chnl <= 161)
1909                         group = 11;
1910         else if (165 <= chnl && chnl <= 171)
1911                         group = 12;
1912         else if (173 <= chnl && chnl <= 177)
1913                         group = 13;
1914                 else
1915                         /*RT_TRACE(COMP_EFUSE,DBG_LOUD,
1916                                 ("5G, Channel %d in Group not found \n",chnl));*/
1917                         RT_ASSERT(!COMP_EFUSE,
1918                                 ("5G, Channel %d in Group not found \n",chnl));
1919         }
1920         return group;
1921 }
1922
1923 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
1924         struct txpower_info_2g *pwrinfo24g,
1925         struct txpower_info_5g *pwrinfo5g,
1926         bool autoload_fail,
1927         u8 *hwinfo)
1928 {
1929         struct rtl_priv *rtlpriv = rtl_priv(hw);
1930         u32 rfPath, eeAddr=EEPROM_TX_PWR_INX, group,TxCount=0;
1931
1932         RT_TRACE(COMP_INIT, DBG_LOUD, ("hal_ReadPowerValueFromPROM8821ae(): PROMContent[0x%x]=0x%x\n", (eeAddr+1), hwinfo[eeAddr+1]));
1933         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
1934                 autoload_fail = true;
1935
1936         if (autoload_fail)
1937         {
1938                 RT_TRACE(COMP_INIT, DBG_LOUD, ("auto load fail : Use Default value!\n"));
1939                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1940                         /*2.4G default value*/
1941                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1942                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
1943                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
1944                         }
1945                         for (TxCount = 0;TxCount < MAX_TX_COUNT;TxCount++) {
1946                                 if (TxCount == 0) {
1947                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
1948                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
1949                                 } else {
1950                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
1951                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
1952                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
1953                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
1954                                 }
1955                         }
1956                         /*5G default value*/
1957                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1958                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
1959
1960                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1961                                 if (TxCount == 0) {
1962                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
1963                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
1964                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
1965                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
1966                                 } else {
1967                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
1968                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
1969                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
1970                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
1971                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
1972                                 }
1973                         }
1974                 }
1975                 return;
1976         }
1977
1978         rtl_priv(hw)->efuse.b_txpwr_fromeprom = true;
1979
1980         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1981                 /*2.4G default value*/
1982                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1983                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
1984                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
1985                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
1986                 }
1987                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1988                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
1989                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
1990                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
1991                 }
1992                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount ++) {
1993                         if (TxCount == 0) {
1994                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
1995                                 if (hwinfo[eeAddr] == 0xFF) {
1996                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0x02;
1997                                 } else {
1998                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
1999                                         if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))    /*bit sign number to 8 bit sign number*/
2000                                                 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2001                                 }
2002
2003                                 if (hwinfo[eeAddr] == 0xFF) {
2004                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0x04;
2005                                 } else {
2006                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2007                                         if(pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))             /*bit sign number to 8 bit sign number*/
2008                                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2009                                 }
2010                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2011                                 eeAddr++;
2012                         } else {
2013                                 if (hwinfo[eeAddr] == 0xFF) {
2014                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2015                                 } else {
2016                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2017                                         if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2018                                                 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2019                                 }
2020
2021                                 if (hwinfo[eeAddr] == 0xFF) {
2022                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2023                                 } else {
2024                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2025                                         if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2026                                                 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2027                                 }
2028
2029                                 eeAddr++;
2030
2031                                 if (hwinfo[eeAddr] == 0xFF) {
2032                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2033                                 } else {
2034                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2035                                         if(pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2036                                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2037                                 }
2038
2039                                 if (hwinfo[eeAddr] == 0xFF) {
2040                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2041                                 } else {
2042                                         pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2043                                         if(pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2044                                                 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2045                                 }
2046                                 eeAddr++;
2047                         }
2048                 }
2049
2050                 /*5G default value*/
2051                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group ++) {
2052                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2053                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2054                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2055                 }
2056
2057                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2058                         if (TxCount == 0) {
2059                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2060                                 if (hwinfo[eeAddr] == 0xFF) {
2061                                         pwrinfo5g->bw20_diff[rfPath][TxCount] = 0x0;
2062                                 } else {
2063                                         pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2064                                         if(pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2065                                                 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2066                                 }
2067
2068                                 if (hwinfo[eeAddr] == 0xFF) {
2069                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] = 0x4;
2070                                 } else {
2071                                         pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2072                                         if(pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2073                                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2074                                 }
2075                                 eeAddr++;
2076                         } else {
2077                                 if (hwinfo[eeAddr] == 0xFF) {
2078                                         pwrinfo5g->bw40_diff[rfPath][TxCount] = 0xFE;
2079                                 } else {
2080                                         pwrinfo5g->bw40_diff[rfPath][TxCount]= (hwinfo[eeAddr] & 0xf0) >> 4;
2081                                         if(pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2082                                                 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2083                                 }
2084
2085                                 if (hwinfo[eeAddr] == 0xFF) {
2086                                         pwrinfo5g->bw20_diff[rfPath][TxCount] = 0xFE;
2087                                 } else {
2088                                         pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2089                                         if(pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2090                                                 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2091                                 }
2092                                 eeAddr++;
2093                         }
2094                 }
2095
2096                 if (hwinfo[eeAddr] == 0xFF) {
2097                         pwrinfo5g->ofdm_diff[rfPath][1] = 0xFE;
2098                         pwrinfo5g->ofdm_diff[rfPath][2] = 0xFE;
2099                 } else {
2100                         pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2101                         pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2102                 }
2103                 eeAddr++;
2104                 if (hwinfo[eeAddr] == 0xFF)
2105                         pwrinfo5g->ofdm_diff[rfPath][3] = 0xFE;
2106                 else
2107                         pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2108
2109                 eeAddr++;
2110
2111                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2112                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] == 0xFF)
2113                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] = 0xFE;
2114                         else if(pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2115                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2116                 }
2117                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2118                         if (hwinfo[eeAddr] == 0xFF) {
2119                                 pwrinfo5g->bw80_diff[rfPath][TxCount] = 0xFE;
2120                         } else {
2121                                 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2122                                 if(pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))              //4bit sign number to 8 bit sign number
2123                                         pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2124                         }
2125
2126                         if (hwinfo[eeAddr] == 0xFF) {
2127                                 pwrinfo5g->bw160_diff[rfPath][TxCount] = 0xFE;
2128                         } else {
2129                                 pwrinfo5g->bw160_diff[rfPath][TxCount]= (hwinfo[eeAddr] & 0x0f);
2130                                 if(pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))             //4bit sign number to 8 bit sign number
2131                                         pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2132                         }
2133                         eeAddr++;
2134                 }
2135         }
2136 }
2137
2138 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2139                                                  bool autoload_fail,
2140                                                  u8 *hwinfo)
2141 {
2142         struct rtl_priv *rtlpriv = rtl_priv(hw);
2143         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2144         struct txpower_info_2g pwrinfo24g;
2145         struct txpower_info_5g pwrinfo5g;
2146         u8 channel5g[CHANNEL_MAX_NUMBER_5G] =
2147                                  {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
2148                           114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
2149                           153,155,157,159,161,163,165,167,168,169,171,173,175,177};
2150         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2151         u8 rf_path, index;
2152         u8 i;
2153
2154         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g, autoload_fail, hwinfo);
2155
2156         for (rf_path = 0; rf_path < 2; rf_path++) {
2157                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2158                         index = _rtl8821ae_get_chnl_group(i + 1);
2159
2160                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2161                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2162                                         pwrinfo24g.index_cck_base[rf_path][5];
2163                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2164                                         pwrinfo24g.index_bw40_base[rf_path][index];
2165                         } else {
2166                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2167                                         pwrinfo24g.index_cck_base[rf_path][index];
2168                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2169                                         pwrinfo24g.index_bw40_base[rf_path][index];
2170                         }
2171                 }
2172
2173                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2174                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2175                         rtlefuse->txpwr_5g_bw40base[rf_path][i] = pwrinfo5g.index_bw40_base[rf_path][index];
2176                 }
2177                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2178                         u8 upper, lower;
2179                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2180                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2181                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2182
2183                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2184                 }
2185                 for (i = 0; i < MAX_TX_COUNT; i++) {
2186                         rtlefuse->txpwr_cckdiff[rf_path][i] = pwrinfo24g.cck_diff[rf_path][i];
2187                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] = pwrinfo24g.ofdm_diff[rf_path][i];
2188                         rtlefuse->txpwr_ht20diff[rf_path][i] = pwrinfo24g.bw20_diff[rf_path][i];
2189                         rtlefuse->txpwr_ht40diff[rf_path][i] = pwrinfo24g.bw40_diff[rf_path][i];
2190
2191                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = pwrinfo5g.ofdm_diff[rf_path][i];
2192                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] = pwrinfo5g.bw20_diff[rf_path][i];
2193                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] = pwrinfo5g.bw40_diff[rf_path][i];
2194                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] = pwrinfo5g.bw80_diff[rf_path][i];
2195                 }
2196         }
2197
2198         if (!autoload_fail){
2199                 rtlefuse->eeprom_regulatory =
2200                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2201                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2202                         rtlefuse->eeprom_regulatory = 0;
2203         } else {
2204                 rtlefuse->eeprom_regulatory = 0;
2205         }
2206
2207         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
2208         ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory ));
2209 }
2210
2211 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2212                                                  bool autoload_fail,
2213                                                  u8 *hwinfo)
2214 {
2215         struct rtl_priv *rtlpriv = rtl_priv(hw);
2216         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2217         struct txpower_info_2g pwrinfo24g;
2218         struct txpower_info_5g pwrinfo5g;
2219         u8 channel5g[CHANNEL_MAX_NUMBER_5G] =
2220                                 {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
2221                  114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
2222                  153,155,157,159,161,163,165,167,168,169,171,173,175,177};
2223         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2224         u8 rf_path, index;
2225         u8 i;
2226
2227         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g, autoload_fail, hwinfo);
2228
2229         for (rf_path = 0; rf_path < 2; rf_path++) {
2230                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2231                         index = _rtl8821ae_get_chnl_group(i + 1);
2232
2233                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2234                                 rtlefuse->txpwrlevel_cck[rf_path][i] = pwrinfo24g.index_cck_base[rf_path][5];
2235                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = pwrinfo24g.index_bw40_base[rf_path][index];
2236                         } else {
2237                                 rtlefuse->txpwrlevel_cck[rf_path][i] = pwrinfo24g.index_cck_base[rf_path][index];
2238                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = pwrinfo24g.index_bw40_base[rf_path][index];
2239                         }
2240                 }
2241
2242                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2243                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2244                         rtlefuse->txpwr_5g_bw40base[rf_path][i] = pwrinfo5g.index_bw40_base[rf_path][index];
2245                 }
2246                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2247                         u8 upper, lower;
2248                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2249                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2250                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2251
2252                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2253                 }
2254                 for (i = 0; i < MAX_TX_COUNT; i++) {
2255                         rtlefuse->txpwr_cckdiff[rf_path][i] = pwrinfo24g.cck_diff[rf_path][i];
2256                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] = pwrinfo24g.ofdm_diff[rf_path][i];
2257                         rtlefuse->txpwr_ht20diff[rf_path][i] = pwrinfo24g.bw20_diff[rf_path][i];
2258                         rtlefuse->txpwr_ht40diff[rf_path][i] = pwrinfo24g.bw40_diff[rf_path][i];
2259
2260                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = pwrinfo5g.ofdm_diff[rf_path][i];
2261                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] = pwrinfo5g.bw20_diff[rf_path][i];
2262                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] = pwrinfo5g.bw40_diff[rf_path][i];
2263                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] = pwrinfo5g.bw80_diff[rf_path][i];
2264                 }
2265         }
2266
2267         if (!autoload_fail){
2268                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2269                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2270                         rtlefuse->eeprom_regulatory = 0;
2271         } else {
2272                 rtlefuse->eeprom_regulatory = 0;
2273         }
2274
2275         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
2276         ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory ));
2277 }
2278
2279 static void _rtl8812ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test )
2280 {
2281         struct rtl_priv *rtlpriv = rtl_priv(hw);
2282         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2283         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2284         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2285         u16 i, usvalue;
2286         u8 hwinfo[HWSET_MAX_SIZE];
2287         u16 eeprom_id;
2288
2289         if (b_pseudo_test) {
2290                 /* need add */
2291         }
2292
2293         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2294                 rtl_efuse_shadow_map_update(hw);
2295                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2296                        HWSET_MAX_SIZE);
2297         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2298                 RT_TRACE(COMP_ERR, DBG_EMERG,
2299                          ("RTL819X Not boot from eeprom, check it !!"));
2300         }
2301
2302         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP \n"),
2303                       hwinfo, HWSET_MAX_SIZE);
2304
2305         eeprom_id = *((u16 *) & hwinfo[0]);
2306         if (eeprom_id != RTL_EEPROM_ID) {
2307                 RT_TRACE(COMP_ERR, DBG_WARNING,
2308                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
2309                 rtlefuse->autoload_failflag = true;
2310         } else {
2311                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2312                 rtlefuse->autoload_failflag = false;
2313         }
2314
2315         if (rtlefuse->autoload_failflag == true) {
2316                 RT_TRACE(COMP_ERR, DBG_EMERG,
2317                          ("RTL8812AE autoload_failflag, check it !!"));
2318                 return;
2319         }
2320
2321         rtlefuse->eeprom_version = *(u8 *) & hwinfo[EEPROM_VERSION];
2322         if (rtlefuse->eeprom_version == 0xff)
2323                         rtlefuse->eeprom_version = 0;
2324
2325         RT_TRACE(COMP_INIT, DBG_LOUD,
2326                  ("EEPROM version: 0x%2x\n", rtlefuse->eeprom_version));
2327
2328         rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2329         rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2330         rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2331         rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2332         RT_TRACE(COMP_INIT, DBG_LOUD,
2333                  ("EEPROMId = 0x%4x\n", eeprom_id));
2334         RT_TRACE(COMP_INIT, DBG_LOUD,
2335                  ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
2336         RT_TRACE(COMP_INIT, DBG_LOUD,
2337                  ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
2338         RT_TRACE(COMP_INIT, DBG_LOUD,
2339                  ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
2340         RT_TRACE(COMP_INIT, DBG_LOUD,
2341                  ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
2342
2343         /*customer ID*/
2344         rtlefuse->eeprom_oemid = *(u8 *) & hwinfo[EEPROM_CUSTOMER_ID];
2345         if (rtlefuse->eeprom_oemid == 0xFF)
2346                 rtlefuse->eeprom_oemid = 0;
2347
2348         RT_TRACE(COMP_INIT, DBG_LOUD,
2349                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
2350
2351         for (i = 0; i < 6; i += 2) {
2352                 usvalue = *(u16 *) & hwinfo[EEPROM_MAC_ADDR + i];
2353                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2354         }
2355
2356         RT_TRACE(COMP_INIT, DBG_DMESG,
2357                  ("dev_addr: %pM\n", rtlefuse->dev_addr));
2358
2359         _rtl8812ae_read_txpower_info_from_hwpg(hw,
2360                 rtlefuse->autoload_failflag, hwinfo);
2361
2362         /*board type*/
2363         rtlefuse->board_type = (((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) & 0xE0 ) >> 5);
2364         if ((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) == 0xff )
2365                 rtlefuse->board_type = 0;
2366         rtlhal->boad_type = rtlefuse->board_type;
2367
2368         rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
2369                         rtlefuse->autoload_failflag, hwinfo);
2370
2371         rtlefuse->eeprom_channelplan = *(u8 *) & hwinfo[EEPROM_CHANNELPLAN];
2372         if (rtlefuse->eeprom_channelplan == 0xff)
2373                 rtlefuse->eeprom_channelplan = 0x7F;
2374
2375         /* set channel plan to world wide 13 */
2376         //rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
2377
2378         /*parse xtal*/
2379         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
2380         if ( rtlefuse->crystalcap == 0xFF )
2381                 rtlefuse->crystalcap = 0x20;
2382
2383         rtlefuse->eeprom_thermalmeter = *(u8 *) & hwinfo[EEPROM_THERMAL_METER];
2384         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||rtlefuse->autoload_failflag )
2385         {
2386                 rtlefuse->b_apk_thermalmeterignore = true;
2387                 rtlefuse->eeprom_thermalmeter = 0xff;
2388         }
2389
2390         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2391         RT_TRACE(COMP_INIT, DBG_LOUD,
2392                  ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
2393
2394         if (rtlefuse->autoload_failflag == false) {
2395                 rtlefuse->antenna_div_cfg = *(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18 >> 3;
2396                 if (*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
2397                         rtlefuse->antenna_div_cfg = 0x00;
2398                 /*if (BT_1ant())
2399                         rtlefuse->antenna_div_cfg = 0;*/
2400                 rtlefuse->antenna_div_type = *(u8 *) & hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
2401                 if (rtlefuse->antenna_div_type == 0xFF)
2402                 {
2403                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
2404                 }
2405         } else {
2406                 rtlefuse->antenna_div_cfg = 0;
2407                 rtlefuse->antenna_div_type = 0;
2408         }
2409
2410         RT_TRACE(COMP_INIT, DBG_LOUD,
2411                 ("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
2412                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type));
2413
2414         /*Hal_ReadPAType_8821A()*/
2415         /*Hal_EfuseParseRateIndicationOption8821A()*/
2416         /*Hal_ReadEfusePCIeCap8821AE()*/
2417
2418         pcipriv->ledctl.bled_opendrain = true;
2419
2420         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2421                 switch (rtlefuse->eeprom_oemid) {
2422                 case RT_CID_DEFAULT:
2423                         break;
2424                 case EEPROM_CID_TOSHIBA:
2425                         rtlhal->oem_id = RT_CID_TOSHIBA;
2426                         break;
2427                 case EEPROM_CID_CCX:
2428                         rtlhal->oem_id = RT_CID_CCX;
2429                         break;
2430                 case EEPROM_CID_QMI:
2431                         rtlhal->oem_id = RT_CID_819x_QMI;
2432                         break;
2433                 case EEPROM_CID_WHQL:
2434                         break;
2435                 default:
2436                         break;
2437
2438                 }
2439         }
2440 }
2441
2442 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test )
2443 {
2444         struct rtl_priv *rtlpriv = rtl_priv(hw);
2445         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2446         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2447         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2448         u16 i, usvalue;
2449         u8 hwinfo[HWSET_MAX_SIZE];
2450         u16 eeprom_id;
2451
2452         if (b_pseudo_test) {
2453                 /* need add */
2454         }
2455
2456         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2457                 rtl_efuse_shadow_map_update(hw);
2458                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2459                        HWSET_MAX_SIZE);
2460         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2461                 RT_TRACE(COMP_ERR, DBG_EMERG,
2462                          ("RTL819X Not boot from eeprom, check it !!"));
2463         }
2464
2465         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP \n"),
2466                       hwinfo, HWSET_MAX_SIZE);
2467
2468         eeprom_id = *((u16 *) & hwinfo[0]);
2469         if (eeprom_id != RTL_EEPROM_ID) {
2470                 RT_TRACE(COMP_ERR, DBG_WARNING,
2471                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
2472                 rtlefuse->autoload_failflag = true;
2473         } else {
2474                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2475                 rtlefuse->autoload_failflag = false;
2476         }
2477
2478         if (rtlefuse->autoload_failflag == true) {
2479                 RT_TRACE(COMP_ERR, DBG_EMERG,
2480                          ("RTL8812AE autoload_failflag, check it !!"));
2481                 return;
2482         }
2483
2484         rtlefuse->eeprom_version = *(u8 *) & hwinfo[EEPROM_VERSION];
2485         if (rtlefuse->eeprom_version == 0xff)
2486                         rtlefuse->eeprom_version = 0;
2487
2488         RT_TRACE(COMP_INIT, DBG_LOUD,
2489                  ("EEPROM version: 0x%2x\n", rtlefuse->eeprom_version));
2490
2491         rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2492         rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2493         rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2494         rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2495         RT_TRACE(COMP_INIT, DBG_LOUD,
2496                  ("EEPROMId = 0x%4x\n", eeprom_id));
2497         RT_TRACE(COMP_INIT, DBG_LOUD,
2498                  ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
2499         RT_TRACE(COMP_INIT, DBG_LOUD,
2500                  ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
2501         RT_TRACE(COMP_INIT, DBG_LOUD,
2502                  ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
2503         RT_TRACE(COMP_INIT, DBG_LOUD,
2504                  ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
2505
2506         /*customer ID*/
2507         rtlefuse->eeprom_oemid = *(u8 *) & hwinfo[EEPROM_CUSTOMER_ID];
2508         if (rtlefuse->eeprom_oemid == 0xFF)
2509                 rtlefuse->eeprom_oemid = 0;
2510
2511         RT_TRACE(COMP_INIT, DBG_LOUD,
2512                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
2513
2514         for (i = 0; i < 6; i += 2) {
2515                 usvalue = *(u16 *) & hwinfo[EEPROM_MAC_ADDR + i];
2516                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2517         }
2518
2519         RT_TRACE(COMP_INIT, DBG_DMESG,
2520                  ("dev_addr: %pM\n", rtlefuse->dev_addr));
2521
2522         _rtl8821ae_read_txpower_info_from_hwpg(hw,
2523                 rtlefuse->autoload_failflag, hwinfo);
2524
2525         /*board type*/
2526         rtlefuse->board_type = (((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) & 0xE0 ) >> 5);
2527         if ((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) == 0xff )
2528                 rtlefuse->board_type = 0;
2529         rtlhal->boad_type = rtlefuse->board_type;
2530
2531         rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
2532                         rtlefuse->autoload_failflag, hwinfo);
2533
2534         rtlefuse->eeprom_channelplan = *(u8 *) & hwinfo[EEPROM_CHANNELPLAN];
2535         if (rtlefuse->eeprom_channelplan == 0xff)
2536                 rtlefuse->eeprom_channelplan = 0x7F;
2537
2538         /* set channel plan to world wide 13 */
2539         //rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
2540
2541         /*parse xtal*/
2542         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
2543         if ( rtlefuse->crystalcap == 0xFF )
2544                 rtlefuse->crystalcap = 0x20;
2545
2546         rtlefuse->eeprom_thermalmeter = *(u8 *) & hwinfo[EEPROM_THERMAL_METER];
2547         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||rtlefuse->autoload_failflag )
2548         {
2549                 rtlefuse->b_apk_thermalmeterignore = true;
2550                 rtlefuse->eeprom_thermalmeter = 0x18;
2551         }
2552
2553         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2554         RT_TRACE(COMP_INIT, DBG_LOUD,
2555                  ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
2556
2557         if (rtlefuse->autoload_failflag == false) {
2558                 rtlefuse->antenna_div_cfg = (*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] & BIT(3))?true:false;
2559                 /*if (BT_1ant())
2560                         rtlefuse->antenna_div_cfg = 0;*/
2561
2562                 rtlefuse->antenna_div_type = CG_TRX_HW_ANTDIV;
2563         } else {
2564                 rtlefuse->antenna_div_cfg = 0;
2565                 rtlefuse->antenna_div_type = 0;
2566         }
2567
2568         RT_TRACE(COMP_INIT, DBG_LOUD,
2569                 ("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
2570                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type));
2571
2572         pcipriv->ledctl.bled_opendrain = true;
2573
2574         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2575                 switch (rtlefuse->eeprom_oemid) {
2576                 case RT_CID_DEFAULT:
2577                         break;
2578                 case EEPROM_CID_TOSHIBA:
2579                         rtlhal->oem_id = RT_CID_TOSHIBA;
2580                         break;
2581                 case EEPROM_CID_CCX:
2582                         rtlhal->oem_id = RT_CID_CCX;
2583                         break;
2584                 case EEPROM_CID_QMI:
2585                         rtlhal->oem_id = RT_CID_819x_QMI;
2586                         break;
2587                 case EEPROM_CID_WHQL:
2588                         break;
2589                 default:
2590                         break;
2591                 }
2592         }
2593 }
2594
2595
2596 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
2597 {
2598         struct rtl_priv *rtlpriv = rtl_priv(hw);
2599         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2600         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2601
2602         pcipriv->ledctl.bled_opendrain = true;
2603         switch (rtlhal->oem_id) {
2604         case RT_CID_819x_HP:
2605                 pcipriv->ledctl.bled_opendrain = true;
2606                 break;
2607         case RT_CID_819x_Lenovo:
2608         case RT_CID_DEFAULT:
2609         case RT_CID_TOSHIBA:
2610         case RT_CID_CCX:
2611         case RT_CID_819x_Acer:
2612         case RT_CID_WHQL:
2613         default:
2614                 break;
2615         }
2616         RT_TRACE(COMP_INIT, DBG_DMESG,
2617                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
2618 }*/
2619
2620 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
2621 {
2622         struct rtl_priv *rtlpriv = rtl_priv(hw);
2623         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2624         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2625         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2626         u8 tmp_u1b;
2627
2628         rtlhal->version = _rtl8821ae_read_chip_version(hw);
2629
2630         if (get_rf_type(rtlphy) == RF_1T1R)
2631                 rtlpriv->dm.brfpath_rxenable[0] = true;
2632         else
2633                 rtlpriv->dm.brfpath_rxenable[0] =
2634                     rtlpriv->dm.brfpath_rxenable[1] = true;
2635         RT_TRACE(COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
2636                                                 rtlhal->version));
2637
2638         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2639         if (tmp_u1b & BIT(4)) {
2640                 RT_TRACE(COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
2641                 rtlefuse->epromtype = EEPROM_93C46;
2642         } else {
2643                 RT_TRACE(COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
2644                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2645         }
2646
2647         if (tmp_u1b & BIT(5)) {
2648                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2649                 rtlefuse->autoload_failflag = false;
2650                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2651                         _rtl8812ae_read_adapter_info(hw, false);
2652                 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2653                         _rtl8821ae_read_adapter_info(hw, false);
2654         } else {
2655                         RT_TRACE(COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
2656         }
2657         /*hal_ReadRFType_8812A()*/
2658         //_rtl8821ae_hal_customized_behavior(hw);
2659 }
2660
2661 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
2662                 struct ieee80211_sta *sta)
2663 {
2664         struct rtl_priv *rtlpriv = rtl_priv(hw);
2665         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2666         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2667         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2668         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2669         u32 ratr_value;
2670         u8 ratr_index = 0;
2671         u8 b_nmode = mac->ht_enable;
2672         u8 mimo_ps = IEEE80211_SMPS_OFF;
2673         u16 shortgi_rate;
2674         u32 tmp_ratr_value;
2675         u8 b_curtxbw_40mhz = mac->bw_40;
2676         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2677                                 1 : 0;
2678         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2679                                 1 : 0;
2680         enum wireless_mode wirelessmode = mac->mode;
2681
2682         if (rtlhal->current_bandtype == BAND_ON_5G)
2683                 ratr_value = sta->supp_rates[1] << 4;
2684         else
2685                 ratr_value = sta->supp_rates[0];
2686         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2687                 ratr_value = 0xfff;
2688         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2689                         sta->ht_cap.mcs.rx_mask[0] << 12);
2690         switch (wirelessmode) {
2691         case WIRELESS_MODE_B:
2692                 if (ratr_value & 0x0000000c)
2693                         ratr_value &= 0x0000000d;
2694                 else
2695                         ratr_value &= 0x0000000f;
2696                 break;
2697         case WIRELESS_MODE_G:
2698                 ratr_value &= 0x00000FF5;
2699                 break;
2700         case WIRELESS_MODE_N_24G:
2701         case WIRELESS_MODE_N_5G:
2702                 b_nmode = 1;
2703                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2704                         ratr_value &= 0x0007F005;
2705                 } else {
2706                         u32 ratr_mask;
2707
2708                         if (get_rf_type(rtlphy) == RF_1T2R ||
2709                             get_rf_type(rtlphy) == RF_1T1R)
2710                                 ratr_mask = 0x000ff005;
2711                         else
2712                                 ratr_mask = 0x0f0ff005;
2713
2714                         ratr_value &= ratr_mask;
2715                 }
2716                 break;
2717         default:
2718                 if (rtlphy->rf_type == RF_1T2R)
2719                         ratr_value &= 0x000ff0ff;
2720                 else
2721                         ratr_value &= 0x0f0ff0ff;
2722
2723                 break;
2724         }
2725
2726         if ( (rtlpcipriv->btcoexist.bt_coexistence) &&
2727              (rtlpcipriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2728              (rtlpcipriv->btcoexist.bt_cur_state) &&
2729              (rtlpcipriv->btcoexist.bt_ant_isolation) &&
2730              ((rtlpcipriv->btcoexist.bt_service == BT_SCO)||
2731              (rtlpcipriv->btcoexist.bt_service == BT_BUSY)) )
2732                 ratr_value &= 0x0fffcfc0;
2733         else
2734                 ratr_value &= 0x0FFFFFFF;
2735
2736         if (b_nmode && ((b_curtxbw_40mhz &&
2737                          b_curshortgi_40mhz) || (!b_curtxbw_40mhz &&
2738                                                  b_curshortgi_20mhz))) {
2739
2740                 ratr_value |= 0x10000000;
2741                 tmp_ratr_value = (ratr_value >> 12);
2742
2743                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2744                         if ((1 << shortgi_rate) & tmp_ratr_value)
2745                                 break;
2746                 }
2747
2748                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2749                     (shortgi_rate << 4) | (shortgi_rate);
2750         }
2751
2752         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2753
2754         RT_TRACE(COMP_RATR, DBG_DMESG,
2755                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
2756 }
2757
2758
2759 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
2760         struct ieee80211_hw *hw, u8 rate_index,
2761         enum wireless_mode wirelessmode)
2762 {
2763         struct rtl_priv *rtlpriv = rtl_priv(hw);
2764         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2765         u8 ret = 0;
2766         switch(rate_index){
2767                 case RATR_INX_WIRELESS_NGB:
2768                         if(rtlphy->rf_type == RF_1T1R)
2769                                 ret = 1;
2770                         else
2771                                 ret = 0;
2772                         ;break;
2773                 case RATR_INX_WIRELESS_N:
2774                 case RATR_INX_WIRELESS_NG:
2775                         if(rtlphy->rf_type == RF_1T1R)
2776                                 ret = 5;
2777                         else
2778                                 ret = 4;
2779                         ;break;
2780                 case RATR_INX_WIRELESS_NB:
2781                         if(rtlphy->rf_type == RF_1T1R)
2782                                 ret = 3;
2783                         else
2784                                 ret = 2;
2785                         ;break;
2786                 case RATR_INX_WIRELESS_GB:
2787                         ret = 6;
2788                         break;
2789                 case RATR_INX_WIRELESS_G:
2790                         ret = 7;
2791                         break;
2792                 case RATR_INX_WIRELESS_B:
2793                         ret = 8;
2794                         break;
2795                 case RATR_INX_WIRELESS_MC:
2796                         if ((wirelessmode == WIRELESS_MODE_B)
2797                                 || (wirelessmode == WIRELESS_MODE_G)
2798                                 || (wirelessmode == WIRELESS_MODE_N_24G)
2799                                 || (wirelessmode == WIRELESS_MODE_AC_24G))
2800                                 ret = 6;
2801                         else
2802                                 ret = 7;
2803                 case RATR_INX_WIRELESS_AC_5N:
2804                         if(rtlphy->rf_type == RF_1T1R)
2805                                 ret = 10;
2806                         else
2807                                 ret = 9;
2808                         break;
2809                 case RATR_INX_WIRELESS_AC_24N:
2810                         if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
2811                         {
2812                                 if(rtlphy->rf_type == RF_1T1R)
2813                                         ret = 10;
2814                                 else
2815                                         ret = 9;
2816                         } else {
2817                                 if(rtlphy->rf_type == RF_1T1R)
2818                                         ret = 11;
2819                                 else
2820                                         ret = 12;
2821                         }
2822                         break;
2823                 default:
2824                         ret = 0;break;
2825         }
2826         return ret;
2827 }
2828
2829 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
2830                 struct ieee80211_sta *sta, u8 rssi_level)
2831 {
2832         struct rtl_priv *rtlpriv = rtl_priv(hw);
2833         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2834         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2835         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2836         struct rtl_sta_info * sta_entry = NULL;
2837         u32 ratr_bitmap;
2838         u8 ratr_index;
2839         u8 b_curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2840                                 ? 1 : 0;
2841         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2842                                 1 : 0;
2843         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2844                                 1 : 0;
2845         enum wireless_mode wirelessmode = 0;
2846         bool b_shortgi = false;
2847         u8 rate_mask[7];
2848         u8 macid = 0;
2849         u8 mimo_ps = IEEE80211_SMPS_OFF;
2850
2851         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2852         wirelessmode = sta_entry->wireless_mode;
2853         if (mac->opmode == NL80211_IFTYPE_STATION ||
2854                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2855                 b_curtxbw_40mhz = mac->bw_40;
2856         else if (mac->opmode == NL80211_IFTYPE_AP ||
2857                 mac->opmode == NL80211_IFTYPE_ADHOC)
2858                 macid = sta->aid + 1;
2859
2860         ratr_bitmap = sta->supp_rates[0];
2861
2862         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2863                 ratr_bitmap = 0xfff;
2864
2865         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2866                         sta->ht_cap.mcs.rx_mask[0] << 12);
2867 /*mac id owner*/
2868         switch (wirelessmode) {
2869         case WIRELESS_MODE_B:
2870                 ratr_index = RATR_INX_WIRELESS_B;
2871                 if (ratr_bitmap & 0x0000000c)
2872                         ratr_bitmap &= 0x0000000d;
2873                 else
2874                         ratr_bitmap &= 0x0000000f;
2875                 break;
2876         case WIRELESS_MODE_G:
2877                 ratr_index = RATR_INX_WIRELESS_GB;
2878
2879                 if (rssi_level == 1)
2880                         ratr_bitmap &= 0x00000f00;
2881                 else if (rssi_level == 2)
2882                         ratr_bitmap &= 0x00000ff0;
2883                 else
2884                         ratr_bitmap &= 0x00000ff5;
2885                 break;
2886         case WIRELESS_MODE_A:
2887                 ratr_index = RATR_INX_WIRELESS_G;
2888                 ratr_bitmap &= 0x00000ff0;
2889                 break;
2890         case WIRELESS_MODE_N_24G:
2891         case WIRELESS_MODE_N_5G:
2892                 if (wirelessmode == WIRELESS_MODE_N_24G)
2893                         ratr_index = RATR_INX_WIRELESS_NGB;
2894                 else
2895                         ratr_index = RATR_INX_WIRELESS_NG;
2896
2897                 if (mimo_ps == IEEE80211_SMPS_STATIC  || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
2898                         if (rssi_level == 1)
2899                                 ratr_bitmap &= 0x00070000;
2900                         else if (rssi_level == 2)
2901                                 ratr_bitmap &= 0x0007f000;
2902                         else
2903                                 ratr_bitmap &= 0x0007f005;
2904                 } else {
2905                         if ( rtlphy->rf_type == RF_1T1R) {
2906                                 if (b_curtxbw_40mhz) {
2907                                         if (rssi_level == 1)
2908                                                 ratr_bitmap &= 0x000f0000;
2909                                         else if (rssi_level == 2)
2910                                                 ratr_bitmap &= 0x000ff000;
2911                                         else
2912                                                 ratr_bitmap &= 0x000ff015;
2913                                 } else {
2914                                         if (rssi_level == 1)
2915                                                 ratr_bitmap &= 0x000f0000;
2916                                         else if (rssi_level == 2)
2917                                                 ratr_bitmap &= 0x000ff000;
2918                                         else
2919                                                 ratr_bitmap &= 0x000ff005;
2920                                 }
2921                         } else {
2922                                 if (b_curtxbw_40mhz) {
2923                                         if (rssi_level == 1)
2924                                                 ratr_bitmap &= 0x0fff0000;
2925                                         else if (rssi_level == 2)
2926                                                 ratr_bitmap &= 0x0ffff000;
2927                                         else
2928                                                 ratr_bitmap &= 0x0ffff015;
2929                                 } else {
2930                                         if (rssi_level == 1)
2931                                                 ratr_bitmap &= 0x0fff0000;
2932                                         else if (rssi_level == 2)
2933                                                 ratr_bitmap &= 0x0ffff000;
2934                                         else
2935                                                 ratr_bitmap &= 0x0ffff005;
2936                                 }
2937                         }
2938                 }
2939                 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
2940                     (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
2941
2942                         if (macid == 0)
2943                                 b_shortgi = true;
2944                         else if (macid == 1)
2945                                 b_shortgi = false;
2946                 }
2947                 break;
2948
2949         case WIRELESS_MODE_AC_24G:
2950                 ratr_index = RATR_INX_WIRELESS_AC_24N;
2951                 if(rssi_level == 1)
2952                         ratr_bitmap &= 0xfc3f0000;
2953                 else if(rssi_level == 2)
2954                         ratr_bitmap &= 0xfffff000;
2955                 else
2956                         ratr_bitmap &= 0xffffffff;
2957                 break;
2958
2959         case WIRELESS_MODE_AC_5G:
2960                 ratr_index = RATR_INX_WIRELESS_AC_5N;
2961
2962                 if (rtlphy->rf_type == RF_1T1R)
2963                 {
2964                         if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2965                         {
2966                                 if(rssi_level == 1)                             /*add by Gary for ac-series*/
2967                                         ratr_bitmap &= 0x003f8000;
2968                                 else if (rssi_level == 2)
2969                                         ratr_bitmap &= 0x003ff000;
2970                                 else
2971                                         ratr_bitmap &= 0x003ff010;
2972                         }
2973                         else
2974                                 ratr_bitmap &= 0x000ff010;
2975                 }
2976                 else
2977                 {
2978                         if(rssi_level == 1)                             /* add by Gary for ac-series*/
2979                                 ratr_bitmap &= 0xfe3f8000;       /*VHT 2SS MCS3~9*/
2980                         else if (rssi_level == 2)
2981                                 ratr_bitmap &= 0xfffff000;       /*VHT 2SS MCS0~9*/
2982                         else
2983                                 ratr_bitmap &= 0xfffff010;       /*All*/
2984                 }
2985                 break;
2986
2987         default:
2988                 ratr_index = RATR_INX_WIRELESS_NGB;
2989
2990                 if (rtlphy->rf_type == RF_1T2R)
2991                         ratr_bitmap &= 0x000ff0ff;
2992                 else
2993                         ratr_bitmap &= 0x0f0ff0ff;
2994                 break;
2995
2996         }
2997
2998         sta_entry->ratr_index = ratr_index;
2999
3000         RT_TRACE(COMP_RATR, DBG_DMESG,
3001                  ("ratr_bitmap :%x\n", ratr_bitmap));
3002         *(u32 *) & rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3003                                        (ratr_index << 28));
3004         rate_mask[0] = macid;
3005         rate_mask[1] = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode) | (b_shortgi ? 0x80 : 0x00);
3006         rate_mask[2] = b_curtxbw_40mhz;
3007         /* if (prox_priv->proxim_modeinfo->power_output > 0)
3008                 rate_mask[2] |= BIT(6); */
3009
3010         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3011         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >>8);
3012         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3013         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3014
3015         RT_TRACE(COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
3016                                                  "ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3017                                                  ratr_index, ratr_bitmap,
3018                                                  rate_mask[0], rate_mask[1],
3019                                                  rate_mask[2], rate_mask[3],
3020                                                  rate_mask[4], rate_mask[5],
3021                                                  rate_mask[6]));
3022         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3023         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3024 }
3025
3026 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3027                 struct ieee80211_sta *sta, u8 rssi_level)
3028 {
3029         struct rtl_priv *rtlpriv = rtl_priv(hw);
3030         if (rtlpriv->dm.b_useramask)
3031                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3032         else
3033                 /*RT_TRACE(COMP_RATR,DBG_LOUD,("rtl8821ae_update_hal_rate_tbl(): Error! 8821ae FW RA Only"));*/
3034                 rtl8821ae_update_hal_rate_table(hw, sta);
3035 }
3036
3037 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3038 {
3039         struct rtl_priv *rtlpriv = rtl_priv(hw);
3040         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3041         u16 sifs_timer;
3042
3043         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3044                                       (u8 *) & mac->slot_time);
3045         if (!mac->ht_enable)
3046                 sifs_timer = 0x0a0a;
3047         else
3048                 sifs_timer = 0x0e0e;
3049         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *) & sifs_timer);
3050 }
3051
3052 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
3053 {
3054         struct rtl_priv *rtlpriv = rtl_priv(hw);
3055         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3056         struct rtl_phy *rtlphy = &(rtlpriv->phy);
3057         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3058         u8 u1tmp = 0;
3059         bool b_actuallyset = false;
3060
3061         if (rtlpriv->rtlhal.being_init_adapter)
3062                 return false;
3063
3064         if (ppsc->b_swrf_processing)
3065                 return false;
3066
3067         spin_lock(&rtlpriv->locks.rf_ps_lock);
3068         if (ppsc->rfchange_inprogress) {
3069                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3070                 return false;
3071         } else {
3072                 ppsc->rfchange_inprogress = true;
3073                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3074         }
3075
3076         cur_rfstate = ppsc->rfpwr_state;
3077
3078         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3079                                         rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3080
3081         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3082
3083         if (rtlphy->polarity_ctl) {
3084                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3085         } else {
3086                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3087         }
3088
3089         if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
3090                 RT_TRACE(COMP_RF, DBG_DMESG,
3091                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
3092
3093                 e_rfpowerstate_toset = ERFON;
3094                 ppsc->b_hwradiooff = false;
3095                 b_actuallyset = true;
3096         } else if ((ppsc->b_hwradiooff == false)
3097                    && (e_rfpowerstate_toset == ERFOFF)) {
3098                 RT_TRACE(COMP_RF, DBG_DMESG,
3099                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
3100
3101                 e_rfpowerstate_toset = ERFOFF;
3102                 ppsc->b_hwradiooff = true;
3103                 b_actuallyset = true;
3104         }
3105
3106         if (b_actuallyset) {
3107                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3108                 ppsc->rfchange_inprogress = false;
3109                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3110         } else {
3111                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3112                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3113
3114                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3115                 ppsc->rfchange_inprogress = false;
3116                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3117         }
3118
3119         *valid = 1;
3120         return !ppsc->b_hwradiooff;
3121
3122 }
3123
3124 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3125                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3126                      bool is_wepkey, bool clear_all)
3127 {
3128         struct rtl_priv *rtlpriv = rtl_priv(hw);
3129         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3130         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3131         u8 *macaddr = p_macaddr;
3132         u32 entry_id = 0;
3133         bool is_pairwise = false;
3134
3135         static u8 cam_const_addr[4][6] = {
3136                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3137                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3138                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3139                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3140         };
3141         static u8 cam_const_broad[] = {
3142                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3143         };
3144
3145         if (clear_all) {
3146                 u8 idx = 0;
3147                 u8 cam_offset = 0;
3148                 u8 clear_number = 5;
3149
3150                 RT_TRACE(COMP_SEC, DBG_DMESG, ("clear_all\n"));
3151
3152                 for (idx = 0; idx < clear_number; idx++) {
3153                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3154                         rtl_cam_empty_entry(hw, cam_offset + idx);
3155
3156                         if (idx < 5) {
3157                                 memset(rtlpriv->sec.key_buf[idx], 0,
3158                                        MAX_KEY_LEN);
3159                                 rtlpriv->sec.key_len[idx] = 0;
3160                         }
3161                 }
3162
3163         } else {
3164                 switch (enc_algo) {
3165                 case WEP40_ENCRYPTION:
3166                         enc_algo = CAM_WEP40;
3167                         break;
3168                 case WEP104_ENCRYPTION:
3169                         enc_algo = CAM_WEP104;
3170                         break;
3171                 case TKIP_ENCRYPTION:
3172                         enc_algo = CAM_TKIP;
3173                         break;
3174                 case AESCCMP_ENCRYPTION:
3175                         enc_algo = CAM_AES;
3176                         break;
3177                 default:
3178                         RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case "
3179                                                                 "not process \n"));
3180                         enc_algo = CAM_TKIP;
3181                         break;
3182                 }
3183
3184                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3185                         macaddr = cam_const_addr[key_index];
3186                         entry_id = key_index;
3187                 } else {
3188                         if (is_group) {
3189                                 macaddr = cam_const_broad;
3190                                 entry_id = key_index;
3191                         } else {
3192                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3193                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3194                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3195                                                 RT_TRACE(COMP_SEC, DBG_EMERG,
3196                                                                 ("Can not find free hw security cam entry\n"));
3197                                                 return;
3198                                         }
3199                                 } else {
3200                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3201                                 }
3202
3203                                 key_index = PAIRWISE_KEYIDX;
3204                                 is_pairwise = true;
3205                         }
3206                 }
3207
3208                 if (rtlpriv->sec.key_len[key_index] == 0) {
3209                         RT_TRACE(COMP_SEC, DBG_DMESG,
3210                                  ("delete one entry, entry_id is %d\n",entry_id));
3211                         if (mac->opmode == NL80211_IFTYPE_AP)
3212                                 rtl_cam_del_entry(hw, p_macaddr);
3213                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3214                 } else {
3215                         RT_TRACE(COMP_SEC, DBG_DMESG, ("add one entry\n"));
3216                         if (is_pairwise) {
3217                                 RT_TRACE(COMP_SEC, DBG_DMESG, ("set Pairwiase key\n"));
3218
3219                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3220                                                       entry_id, enc_algo,
3221                                                       CAM_CONFIG_NO_USEDK,
3222                                                       rtlpriv->sec.key_buf[key_index]);
3223                         } else {
3224                                 RT_TRACE(COMP_SEC, DBG_DMESG, ("set group key\n"));
3225
3226                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3227                                         rtl_cam_add_one_entry(hw,
3228                                                         rtlefuse->dev_addr,
3229                                                         PAIRWISE_KEYIDX,
3230                                                         CAM_PAIRWISE_KEY_POSITION,
3231                                                         enc_algo,
3232                                                         CAM_CONFIG_NO_USEDK,
3233                                                         rtlpriv->sec.key_buf
3234                                                         [entry_id]);
3235                                 }
3236
3237                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3238                                                 entry_id, enc_algo,
3239                                                 CAM_CONFIG_NO_USEDK,
3240                                                 rtlpriv->sec.key_buf[entry_id]);
3241                         }
3242
3243                 }
3244         }
3245 }
3246
3247
3248 void rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3249                                               bool auto_load_fail, u8 *hwinfo)
3250 {
3251         struct rtl_priv *rtlpriv = rtl_priv(hw);
3252         u8 value;
3253
3254         if (!auto_load_fail) {
3255                 value = *(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION];
3256                 if (((value & 0xe0) >> 5) == 0x1)
3257                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3258                 else
3259                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3260                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3261
3262                 value = hwinfo[EEPROM_RF_BT_SETTING];
3263                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3264         } else {
3265                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3266                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3267                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3268         }
3269         /*move BT_InitHalVars() to init_sw_vars*/
3270 }
3271
3272 void rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3273                                               bool auto_load_fail, u8 *hwinfo)
3274 {
3275         struct rtl_priv *rtlpriv = rtl_priv(hw);
3276         u8 value;
3277         u32 tmpu_32;
3278
3279         if (!auto_load_fail) {
3280                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3281                 if(tmpu_32 & BIT(18))
3282                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3283                 else
3284                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3285                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3286
3287                 value = hwinfo[EEPROM_RF_BT_SETTING];
3288                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3289         } else {
3290                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3291                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3292                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3293         }
3294         /*move BT_InitHalVars() to init_sw_vars*/
3295 }
3296
3297 void rtl8821ae_bt_reg_init(struct ieee80211_hw* hw)
3298 {
3299         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
3300
3301         /* 0:Low, 1:High, 2:From Efuse. */
3302         rtlpcipriv->btcoexist.b_reg_bt_iso = 2;
3303         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3304         rtlpcipriv->btcoexist.b_reg_bt_sco= 3;
3305         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3306         rtlpcipriv->btcoexist.b_reg_bt_sco= 0;
3307 }
3308
3309
3310 void rtl8821ae_bt_hw_init(struct ieee80211_hw* hw)
3311 {
3312         struct rtl_priv *rtlpriv = rtl_priv(hw);
3313
3314         if (rtlpriv->cfg->ops->get_btc_status()){
3315                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3316         }
3317 }
3318
3319 void rtl8821ae_suspend(struct ieee80211_hw *hw)
3320 {
3321 }
3322
3323 void rtl8821ae_resume(struct ieee80211_hw *hw)
3324 {
3325 }
3326
3327 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
3328 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3329         bool allow_all_da, bool write_into_reg)
3330 {
3331         struct rtl_priv *rtlpriv = rtl_priv(hw);
3332         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3333
3334         if (allow_all_da) /* Set BIT0 */
3335                 rtlpci->receive_config |= RCR_AAP;
3336         else /* Clear BIT0 */
3337                 rtlpci->receive_config &= ~RCR_AAP;
3338
3339         if(write_into_reg)
3340                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
3341
3342
3343         RT_TRACE(COMP_TURBO | COMP_INIT, DBG_LOUD,
3344                 ("receive_config=0x%08X, write_into_reg=%d\n",
3345                 rtlpci->receive_config, write_into_reg ));
3346 }
3347