1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
29 #include "rtsx_transport.h"
30 #include "rtsx_scsi.h"
31 #include "rtsx_card.h"
34 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
35 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff,
36 u8 start_page, u8 end_page);
38 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
40 struct xd_info *xd_card = &chip->xd_card;
42 xd_card->err_code = err_code;
45 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
47 struct xd_info *xd_card = &chip->xd_card;
49 return (xd_card->err_code == err_code);
52 static int xd_set_init_para(struct rtsx_chip *chip)
54 struct xd_info *xd_card = &chip->xd_card;
58 xd_card->xd_clock = 47;
60 xd_card->xd_clock = CLK_50;
62 retval = switch_clock(chip, xd_card->xd_clock);
63 if (retval != STATUS_SUCCESS) {
68 return STATUS_SUCCESS;
71 static int xd_switch_clock(struct rtsx_chip *chip)
73 struct xd_info *xd_card = &chip->xd_card;
76 retval = select_card(chip, XD_CARD);
77 if (retval != STATUS_SUCCESS) {
82 retval = switch_clock(chip, xd_card->xd_clock);
83 if (retval != STATUS_SUCCESS) {
88 return STATUS_SUCCESS;
91 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
98 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
99 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
100 XD_TRANSFER_START | XD_READ_ID);
101 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
104 for (i = 0; i < 4; i++)
105 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
107 retval = rtsx_send_cmd(chip, XD_CARD, 20);
113 ptr = rtsx_get_cmd_data(chip) + 1;
114 if (id_buf && buf_len) {
117 memcpy(id_buf, ptr, buf_len);
120 return STATUS_SUCCESS;
123 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
125 struct xd_info *xd_card = &chip->xd_card;
129 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
130 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
131 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
132 0xFF, (u8)(addr >> 8));
133 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3,
134 0xFF, (u8)(addr >> 16));
135 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
136 xd_card->addr_cycle |
142 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
143 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1,
144 0xFF, (u8)(addr >> 8));
145 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
146 0xFF, (u8)(addr >> 16));
147 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
148 (xd_card->addr_cycle - 1) | XD_CALC_ECC |
157 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr,
158 u8 *buf, int buf_len)
164 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
166 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
167 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
168 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
169 XD_TRANSFER_END, XD_TRANSFER_END);
171 for (i = 0; i < 6; i++)
172 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i),
174 for (i = 0; i < 4; i++)
175 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i),
177 rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
179 retval = rtsx_send_cmd(chip, XD_CARD, 500);
185 if (buf && buf_len) {
186 u8 *ptr = rtsx_get_cmd_data(chip) + 1;
190 memcpy(buf, ptr, buf_len);
193 return STATUS_SUCCESS;
196 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset,
197 u8 *buf, int buf_len)
201 if (!buf || (buf_len < 0)) {
208 for (i = 0; i < buf_len; i++)
209 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i,
212 retval = rtsx_send_cmd(chip, 0, 250);
214 rtsx_clear_xd_error(chip);
219 memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
221 return STATUS_SUCCESS;
224 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf,
230 if (!buf || (buf_len < 10)) {
237 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
239 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
240 0x01, PINGPONG_BUFFER);
241 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
242 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
243 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
245 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
246 XD_TRANSFER_START | XD_READ_PAGES);
247 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
250 retval = rtsx_send_cmd(chip, XD_CARD, 250);
251 if (retval == -ETIMEDOUT) {
252 rtsx_clear_xd_error(chip);
257 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®);
263 rtsx_clear_xd_error(chip);
268 retval = rtsx_read_register(chip, XD_CTL, ®);
273 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
274 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
275 if (retval != STATUS_SUCCESS) {
279 if (reg & XD_ECC1_ERROR) {
280 u8 ecc_bit, ecc_byte;
282 retval = rtsx_read_register(chip, XD_ECC_BIT1,
288 retval = rtsx_read_register(chip, XD_ECC_BYTE1,
295 dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
297 if (ecc_byte < buf_len) {
298 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
300 buf[ecc_byte] ^= (1 << ecc_bit);
301 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
305 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
306 rtsx_clear_xd_error(chip);
308 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
309 if (retval != STATUS_SUCCESS) {
313 if (reg & XD_ECC2_ERROR) {
314 u8 ecc_bit, ecc_byte;
316 retval = rtsx_read_register(chip, XD_ECC_BIT2,
322 retval = rtsx_read_register(chip, XD_ECC_BYTE2,
329 dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
331 if (ecc_byte < buf_len) {
332 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
334 buf[ecc_byte] ^= (1 << ecc_bit);
335 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
340 rtsx_clear_xd_error(chip);
345 return STATUS_SUCCESS;
348 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
350 if (CHECK_PID(chip, 0x5208)) {
351 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
352 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
353 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
354 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
355 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
356 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
357 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
358 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
359 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
360 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
361 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
362 MS_D5_PD | MS_D4_PD);
363 } else if (CHECK_PID(chip, 0x5288)) {
364 if (CHECK_BARO_PKG(chip, QFN)) {
365 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
367 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
369 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
371 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
377 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
379 if (CHECK_BARO_PKG(chip, QFN)) {
380 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
381 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
382 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
383 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
387 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
389 if (CHECK_PID(chip, 0x5208)) {
390 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
391 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
392 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
393 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
394 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
395 XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
396 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
397 XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
398 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
399 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
400 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
401 MS_D5_PD | MS_D4_PD);
402 } else if (CHECK_PID(chip, 0x5288)) {
403 if (CHECK_BARO_PKG(chip, QFN)) {
404 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
406 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
408 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
410 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
416 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
420 if (CHECK_PID(chip, 0x5208)) {
421 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
430 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
439 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
448 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
457 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
466 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
467 MS_D5_PD | MS_D4_PD);
472 } else if (CHECK_PID(chip, 0x5288)) {
473 if (CHECK_BARO_PKG(chip, QFN)) {
474 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
480 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
486 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
492 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
501 return STATUS_SUCCESS;
504 static int reset_xd(struct rtsx_chip *chip)
506 struct xd_info *xd_card = &chip->xd_card;
508 u8 *ptr, id_buf[4], redunt[11];
510 retval = select_card(chip, XD_CARD);
511 if (retval != STATUS_SUCCESS) {
518 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
520 if (chip->asic_code) {
521 if (!CHECK_PID(chip, 0x5288))
522 xd_fill_pull_ctl_disable(chip);
524 xd_fill_pull_ctl_stage1_barossa(chip);
526 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
527 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) |
531 if (!chip->ft2_fast_mode)
532 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT,
533 XD_NO_AUTO_PWR_OFF, 0);
535 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
537 retval = rtsx_send_cmd(chip, XD_CARD, 100);
543 if (!chip->ft2_fast_mode) {
544 retval = card_power_off(chip, XD_CARD);
545 if (retval != STATUS_SUCCESS) {
554 if (chip->asic_code) {
555 xd_fill_pull_ctl_enable(chip);
557 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
558 (FPGA_XD_PULL_CTL_EN1 &
559 FPGA_XD_PULL_CTL_EN2) |
563 retval = rtsx_send_cmd(chip, XD_CARD, 100);
569 retval = card_power_on(chip, XD_CARD);
570 if (retval != STATUS_SUCCESS) {
577 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
578 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
588 if (chip->ft2_fast_mode) {
589 if (chip->asic_code) {
590 xd_fill_pull_ctl_enable(chip);
592 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
593 (FPGA_XD_PULL_CTL_EN1 &
594 FPGA_XD_PULL_CTL_EN2) |
599 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
600 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
602 retval = rtsx_send_cmd(chip, XD_CARD, 100);
608 if (!chip->ft2_fast_mode)
611 retval = xd_set_init_para(chip);
612 if (retval != STATUS_SUCCESS) {
617 /* Read ID to check if the timing setting is right */
618 for (i = 0; i < 4; i++) {
621 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
622 XD_TIME_SETUP_STEP * 3 +
623 XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
624 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
625 XD_TIME_SETUP_STEP * 3 +
626 XD_TIME_RW_STEP * (4 + i) +
627 XD_TIME_RWN_STEP * (3 + i));
629 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
630 XD_TRANSFER_START | XD_RESET);
631 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
632 XD_TRANSFER_END, XD_TRANSFER_END);
634 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
635 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
637 retval = rtsx_send_cmd(chip, XD_CARD, 100);
643 ptr = rtsx_get_cmd_data(chip) + 1;
645 dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n",
648 if (((ptr[0] & READY_FLAG) != READY_STATE) ||
652 retval = xd_read_id(chip, READ_ID, id_buf, 4);
653 if (retval != STATUS_SUCCESS) {
658 dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
659 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
661 xd_card->device_code = id_buf[1];
663 /* Check if the xD card is supported */
664 switch (xd_card->device_code) {
667 xd_card->block_shift = 4;
668 xd_card->page_off = 0x0F;
669 xd_card->addr_cycle = 3;
670 xd_card->zone_cnt = 1;
671 xd_card->capacity = 8000;
675 xd_card->block_shift = 4;
676 xd_card->page_off = 0x0F;
677 xd_card->addr_cycle = 3;
678 xd_card->zone_cnt = 1;
679 xd_card->capacity = 16000;
682 XD_PAGE_512(xd_card);
683 xd_card->addr_cycle = 3;
684 xd_card->zone_cnt = 1;
685 xd_card->capacity = 32000;
688 XD_PAGE_512(xd_card);
689 xd_card->addr_cycle = 3;
690 xd_card->zone_cnt = 2;
691 xd_card->capacity = 64000;
694 XD_PAGE_512(xd_card);
695 xd_card->addr_cycle = 4;
696 xd_card->zone_cnt = 4;
697 xd_card->capacity = 128000;
700 XD_PAGE_512(xd_card);
701 xd_card->addr_cycle = 4;
702 xd_card->zone_cnt = 8;
703 xd_card->capacity = 256000;
706 XD_PAGE_512(xd_card);
707 xd_card->addr_cycle = 4;
708 xd_card->zone_cnt = 16;
709 xd_card->capacity = 512000;
712 XD_PAGE_512(xd_card);
713 xd_card->addr_cycle = 4;
714 xd_card->zone_cnt = 32;
715 xd_card->capacity = 1024000;
718 XD_PAGE_512(xd_card);
719 xd_card->addr_cycle = 4;
720 xd_card->zone_cnt = 64;
721 xd_card->capacity = 2048000;
724 XD_PAGE_512(xd_card);
725 xd_card->addr_cycle = 4;
726 xd_card->zone_cnt = 128;
727 xd_card->capacity = 4096000;
733 /* Confirm timing setting */
734 for (j = 0; j < 10; j++) {
735 retval = xd_read_id(chip, READ_ID, id_buf, 4);
736 if (retval != STATUS_SUCCESS) {
741 if (id_buf[1] != xd_card->device_code)
750 xd_card->block_shift = 0;
751 xd_card->page_off = 0;
752 xd_card->addr_cycle = 0;
753 xd_card->capacity = 0;
759 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
760 if (retval != STATUS_SUCCESS) {
764 dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
765 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
766 if (id_buf[2] != XD_ID_CODE) {
771 /* Search CIS block */
772 for (i = 0; i < 24; i++) {
775 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
780 page_addr = (u32)i << xd_card->block_shift;
782 for (j = 0; j < 3; j++) {
783 retval = xd_read_redundant(chip, page_addr, redunt, 11);
784 if (retval == STATUS_SUCCESS)
790 if (redunt[BLOCK_STATUS] != XD_GBLK)
794 if (redunt[PAGE_STATUS] != XD_GPG) {
795 for (j = 1; j <= 8; j++) {
796 retval = xd_read_redundant(chip, page_addr + j,
798 if (retval == STATUS_SUCCESS) {
799 if (redunt[PAGE_STATUS] == XD_GPG)
809 if ((redunt[BLOCK_STATUS] == XD_GBLK) &&
810 (redunt[PARITY] & XD_BA1_ALL0)) {
815 retval = xd_read_cis(chip, page_addr, buf, 10);
816 if (retval != STATUS_SUCCESS) {
821 if ((buf[0] == 0x01) && (buf[1] == 0x03) &&
823 (buf[3] == 0x01) && (buf[4] == 0xFF) &&
824 (buf[5] == 0x18) && (buf[6] == 0x02) &&
825 (buf[7] == 0xDF) && (buf[8] == 0x01) &&
827 xd_card->cis_block = (u16)i;
834 dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block);
835 if (xd_card->cis_block == 0xFFFF) {
840 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
842 return STATUS_SUCCESS;
845 static int xd_check_data_blank(u8 *redunt)
849 for (i = 0; i < 6; i++) {
850 if (redunt[PAGE_STATUS + i] != 0xFF)
854 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1))
855 != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
858 for (i = 0; i < 4; i++) {
859 if (redunt[RESERVED0 + i] != 0xFF)
866 static u16 xd_load_log_block_addr(u8 *redunt)
870 if (redunt[PARITY] & XD_BA1_BA2_EQL)
871 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
872 redunt[BLOCK_ADDR1_L];
873 else if (redunt[PARITY] & XD_BA1_VALID)
874 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
875 redunt[BLOCK_ADDR1_L];
876 else if (redunt[PARITY] & XD_BA2_VALID)
877 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) |
878 redunt[BLOCK_ADDR2_L];
883 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
885 struct xd_info *xd_card = &chip->xd_card;
888 dev_dbg(rtsx_dev(chip), "xd_init_l2p_tbl: zone_cnt = %d\n",
891 if (xd_card->zone_cnt < 1) {
896 size = xd_card->zone_cnt * sizeof(struct zone_entry);
897 dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size);
899 xd_card->zone = vmalloc(size);
900 if (!xd_card->zone) {
905 for (i = 0; i < xd_card->zone_cnt; i++) {
906 xd_card->zone[i].build_flag = 0;
907 xd_card->zone[i].l2p_table = NULL;
908 xd_card->zone[i].free_table = NULL;
909 xd_card->zone[i].get_index = 0;
910 xd_card->zone[i].set_index = 0;
911 xd_card->zone[i].unused_blk_cnt = 0;
914 return STATUS_SUCCESS;
917 static inline void free_zone(struct zone_entry *zone)
922 zone->build_flag = 0;
925 zone->unused_blk_cnt = 0;
926 vfree(zone->l2p_table);
927 zone->l2p_table = NULL;
928 vfree(zone->free_table);
929 zone->free_table = NULL;
932 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
934 struct xd_info *xd_card = &chip->xd_card;
935 struct zone_entry *zone;
938 zone_no = (int)phy_blk >> 10;
939 if (zone_no >= xd_card->zone_cnt) {
940 dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
941 zone_no, xd_card->zone_cnt);
944 zone = &xd_card->zone[zone_no];
946 if (!zone->free_table) {
947 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
951 if ((zone->set_index >= XD_FREE_TABLE_CNT) ||
952 (zone->set_index < 0)) {
954 dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n");
958 dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n",
961 zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff);
962 if (zone->set_index >= XD_FREE_TABLE_CNT)
964 zone->unused_blk_cnt++;
967 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
969 struct xd_info *xd_card = &chip->xd_card;
970 struct zone_entry *zone;
973 if (zone_no >= xd_card->zone_cnt) {
974 dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
975 zone_no, xd_card->zone_cnt);
976 return BLK_NOT_FOUND;
978 zone = &xd_card->zone[zone_no];
980 if ((zone->unused_blk_cnt == 0) ||
981 (zone->set_index == zone->get_index)) {
983 dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n");
984 return BLK_NOT_FOUND;
986 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
988 dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n");
989 return BLK_NOT_FOUND;
992 dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n",
995 phy_blk = zone->free_table[zone->get_index];
996 zone->free_table[zone->get_index++] = 0xFFFF;
997 if (zone->get_index >= XD_FREE_TABLE_CNT)
999 zone->unused_blk_cnt--;
1001 phy_blk += ((u32)(zone_no) << 10);
1005 static void xd_set_l2p_tbl(struct rtsx_chip *chip,
1006 int zone_no, u16 log_off, u16 phy_off)
1008 struct xd_info *xd_card = &chip->xd_card;
1009 struct zone_entry *zone;
1011 zone = &xd_card->zone[zone_no];
1012 zone->l2p_table[log_off] = phy_off;
1015 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
1017 struct xd_info *xd_card = &chip->xd_card;
1018 struct zone_entry *zone;
1021 zone = &xd_card->zone[zone_no];
1022 if (zone->l2p_table[log_off] == 0xFFFF) {
1026 #ifdef XD_DELAY_WRITE
1027 retval = xd_delay_write(chip);
1028 if (retval != STATUS_SUCCESS) {
1029 dev_dbg(rtsx_dev(chip), "In xd_get_l2p_tbl, delay write fail!\n");
1030 return BLK_NOT_FOUND;
1034 if (zone->unused_blk_cnt <= 0) {
1035 dev_dbg(rtsx_dev(chip), "No unused block!\n");
1036 return BLK_NOT_FOUND;
1039 for (i = 0; i < zone->unused_blk_cnt; i++) {
1040 phy_blk = xd_get_unused_block(chip, zone_no);
1041 if (phy_blk == BLK_NOT_FOUND) {
1042 dev_dbg(rtsx_dev(chip), "No unused block available!\n");
1043 return BLK_NOT_FOUND;
1046 retval = xd_init_page(chip, phy_blk, log_off,
1047 0, xd_card->page_off + 1);
1048 if (retval == STATUS_SUCCESS)
1051 if (i >= zone->unused_blk_cnt) {
1052 dev_dbg(rtsx_dev(chip), "No good unused block available!\n");
1053 return BLK_NOT_FOUND;
1056 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
1060 return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
1063 int reset_xd_card(struct rtsx_chip *chip)
1065 struct xd_info *xd_card = &chip->xd_card;
1068 memset(xd_card, 0, sizeof(struct xd_info));
1070 xd_card->block_shift = 0;
1071 xd_card->page_off = 0;
1072 xd_card->addr_cycle = 0;
1073 xd_card->capacity = 0;
1074 xd_card->zone_cnt = 0;
1075 xd_card->cis_block = 0xFFFF;
1076 xd_card->delay_write.delay_write_flag = 0;
1078 retval = enable_card_clock(chip, XD_CARD);
1079 if (retval != STATUS_SUCCESS) {
1084 retval = reset_xd(chip);
1085 if (retval != STATUS_SUCCESS) {
1090 retval = xd_init_l2p_tbl(chip);
1091 if (retval != STATUS_SUCCESS) {
1096 return STATUS_SUCCESS;
1099 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
1101 struct xd_info *xd_card = &chip->xd_card;
1106 dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk);
1108 if (phy_blk == BLK_NOT_FOUND) {
1113 rtsx_init_cmd(chip);
1115 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1116 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
1117 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
1118 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
1119 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
1120 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
1121 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
1122 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1123 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1124 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1126 page_addr = phy_blk << xd_card->block_shift;
1128 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1130 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1131 xd_card->page_off + 1);
1133 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1134 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1135 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1136 XD_TRANSFER_END, XD_TRANSFER_END);
1138 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1140 rtsx_clear_xd_error(chip);
1141 rtsx_read_register(chip, XD_DAT, ®);
1142 if (reg & PROGRAM_ERROR)
1143 xd_set_err_code(chip, XD_PRG_ERROR);
1145 xd_set_err_code(chip, XD_TO_ERROR);
1150 return STATUS_SUCCESS;
1153 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk,
1154 u16 logoff, u8 start_page, u8 end_page)
1156 struct xd_info *xd_card = &chip->xd_card;
1161 dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk);
1163 if (start_page > end_page) {
1167 if (phy_blk == BLK_NOT_FOUND) {
1172 rtsx_init_cmd(chip);
1174 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1175 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1176 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1177 0xFF, (u8)(logoff >> 8));
1178 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1180 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1182 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1184 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1185 XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1187 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT,
1188 0xFF, (end_page - start_page));
1190 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1191 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1192 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1193 XD_TRANSFER_END, XD_TRANSFER_END);
1195 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1197 rtsx_clear_xd_error(chip);
1198 rtsx_read_register(chip, XD_DAT, ®);
1199 if (reg & PROGRAM_ERROR) {
1200 xd_mark_bad_block(chip, phy_blk);
1201 xd_set_err_code(chip, XD_PRG_ERROR);
1203 xd_set_err_code(chip, XD_TO_ERROR);
1209 return STATUS_SUCCESS;
1212 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk,
1213 u8 start_page, u8 end_page)
1215 struct xd_info *xd_card = &chip->xd_card;
1216 u32 old_page, new_page;
1220 dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n",
1223 if (start_page > end_page) {
1228 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) {
1233 old_page = (old_blk << xd_card->block_shift) + start_page;
1234 new_page = (new_blk << xd_card->block_shift) + start_page;
1236 XD_CLR_BAD_NEWBLK(xd_card);
1238 retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01,
1245 for (i = start_page; i < end_page; i++) {
1246 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1247 rtsx_clear_xd_error(chip);
1248 xd_set_err_code(chip, XD_NO_CARD);
1253 rtsx_init_cmd(chip);
1255 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1257 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1258 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1259 XD_AUTO_CHK_DATA_STATUS, 0);
1260 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1261 XD_TRANSFER_START | XD_READ_PAGES);
1262 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1263 XD_TRANSFER_END, XD_TRANSFER_END);
1265 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1267 rtsx_clear_xd_error(chip);
1269 rtsx_read_register(chip, XD_CTL, ®);
1270 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1273 if (detect_card_cd(chip,
1274 XD_CARD) != STATUS_SUCCESS) {
1275 xd_set_err_code(chip, XD_NO_CARD);
1280 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1281 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ||
1282 ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1283 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1284 rtsx_write_register(chip,
1288 rtsx_write_register(chip,
1292 XD_SET_BAD_OLDBLK(xd_card);
1293 dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n",
1297 xd_set_err_code(chip, XD_TO_ERROR);
1303 if (XD_CHK_BAD_OLDBLK(xd_card))
1304 rtsx_clear_xd_error(chip);
1306 rtsx_init_cmd(chip);
1308 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1309 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1310 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1311 XD_TRANSFER_START | XD_WRITE_PAGES);
1312 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1313 XD_TRANSFER_END, XD_TRANSFER_END);
1315 retval = rtsx_send_cmd(chip, XD_CARD, 300);
1317 rtsx_clear_xd_error(chip);
1319 rtsx_read_register(chip, XD_DAT, ®);
1320 if (reg & PROGRAM_ERROR) {
1321 xd_mark_bad_block(chip, new_blk);
1322 xd_set_err_code(chip, XD_PRG_ERROR);
1323 XD_SET_BAD_NEWBLK(xd_card);
1325 xd_set_err_code(chip, XD_TO_ERROR);
1335 return STATUS_SUCCESS;
1338 static int xd_reset_cmd(struct rtsx_chip *chip)
1343 rtsx_init_cmd(chip);
1345 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1346 0xFF, XD_TRANSFER_START | XD_RESET);
1347 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1348 XD_TRANSFER_END, XD_TRANSFER_END);
1349 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1350 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1352 retval = rtsx_send_cmd(chip, XD_CARD, 100);
1358 ptr = rtsx_get_cmd_data(chip) + 1;
1359 if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1360 return STATUS_SUCCESS;
1366 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1368 struct xd_info *xd_card = &chip->xd_card;
1373 if (phy_blk == BLK_NOT_FOUND) {
1378 page_addr = phy_blk << xd_card->block_shift;
1380 for (i = 0; i < 3; i++) {
1381 rtsx_init_cmd(chip);
1383 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1385 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1386 XD_TRANSFER_START | XD_ERASE);
1387 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1388 XD_TRANSFER_END, XD_TRANSFER_END);
1389 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1391 retval = rtsx_send_cmd(chip, XD_CARD, 250);
1393 rtsx_clear_xd_error(chip);
1394 rtsx_read_register(chip, XD_DAT, ®);
1395 if (reg & PROGRAM_ERROR) {
1396 xd_mark_bad_block(chip, phy_blk);
1397 xd_set_err_code(chip, XD_PRG_ERROR);
1401 xd_set_err_code(chip, XD_ERASE_FAIL);
1402 retval = xd_reset_cmd(chip);
1403 if (retval != STATUS_SUCCESS) {
1410 ptr = rtsx_get_cmd_data(chip) + 1;
1411 if (*ptr & PROGRAM_ERROR) {
1412 xd_mark_bad_block(chip, phy_blk);
1413 xd_set_err_code(chip, XD_PRG_ERROR);
1418 return STATUS_SUCCESS;
1421 xd_mark_bad_block(chip, phy_blk);
1422 xd_set_err_code(chip, XD_ERASE_FAIL);
1427 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1429 struct xd_info *xd_card = &chip->xd_card;
1430 struct zone_entry *zone;
1433 u16 max_logoff, cur_fst_page_logoff;
1434 u16 cur_lst_page_logoff, ent_lst_page_logoff;
1437 dev_dbg(rtsx_dev(chip), "xd_build_l2p_tbl: %d\n", zone_no);
1439 if (!xd_card->zone) {
1440 retval = xd_init_l2p_tbl(chip);
1441 if (retval != STATUS_SUCCESS)
1445 if (xd_card->zone[zone_no].build_flag) {
1446 dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n",
1448 return STATUS_SUCCESS;
1451 zone = &xd_card->zone[zone_no];
1453 if (!zone->l2p_table) {
1454 zone->l2p_table = vmalloc(2000);
1455 if (!zone->l2p_table) {
1460 memset((u8 *)(zone->l2p_table), 0xff, 2000);
1462 if (!zone->free_table) {
1463 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1464 if (!zone->free_table) {
1469 memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1472 if (xd_card->cis_block == 0xFFFF)
1475 start = xd_card->cis_block + 1;
1476 if (XD_CHK_4MB(xd_card)) {
1484 start = (u32)(zone_no) << 10;
1485 end = (u32)(zone_no + 1) << 10;
1489 dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n",
1492 zone->set_index = 0;
1493 zone->get_index = 0;
1494 zone->unused_blk_cnt = 0;
1496 for (i = start; i < end; i++) {
1497 u32 page_addr = i << xd_card->block_shift;
1500 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1501 if (retval != STATUS_SUCCESS)
1504 if (redunt[BLOCK_STATUS] != 0xFF) {
1505 dev_dbg(rtsx_dev(chip), "bad block\n");
1509 if (xd_check_data_blank(redunt)) {
1510 dev_dbg(rtsx_dev(chip), "blank block\n");
1511 xd_set_unused_block(chip, i);
1515 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1516 if ((cur_fst_page_logoff == 0xFFFF) ||
1517 (cur_fst_page_logoff > max_logoff)) {
1518 retval = xd_erase_block(chip, i);
1519 if (retval == STATUS_SUCCESS)
1520 xd_set_unused_block(chip, i);
1524 if ((zone_no == 0) && (cur_fst_page_logoff == 0) &&
1525 (redunt[PAGE_STATUS] != XD_GPG))
1526 XD_SET_MBR_FAIL(xd_card);
1528 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1529 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1533 phy_block = zone->l2p_table[cur_fst_page_logoff] +
1534 ((u32)((zone_no) << 10));
1536 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1538 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1539 if (retval != STATUS_SUCCESS)
1542 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1543 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1546 page_addr = ((phy_block + 1) <<
1547 xd_card->block_shift) - 1;
1549 for (m = 0; m < 3; m++) {
1550 retval = xd_read_redundant(chip, page_addr,
1552 if (retval == STATUS_SUCCESS)
1557 zone->l2p_table[cur_fst_page_logoff] =
1559 retval = xd_erase_block(chip, phy_block);
1560 if (retval == STATUS_SUCCESS)
1561 xd_set_unused_block(chip, phy_block);
1565 ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1566 if (ent_lst_page_logoff != cur_fst_page_logoff) {
1567 zone->l2p_table[cur_fst_page_logoff] =
1569 retval = xd_erase_block(chip, phy_block);
1570 if (retval == STATUS_SUCCESS)
1571 xd_set_unused_block(chip, phy_block);
1574 retval = xd_erase_block(chip, i);
1575 if (retval == STATUS_SUCCESS)
1576 xd_set_unused_block(chip, i);
1579 retval = xd_erase_block(chip, i);
1580 if (retval == STATUS_SUCCESS)
1581 xd_set_unused_block(chip, i);
1585 if (XD_CHK_4MB(xd_card))
1591 for (start = 0; start < end; start++) {
1592 if (zone->l2p_table[start] == 0xFFFF)
1596 dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n",
1598 dev_dbg(rtsx_dev(chip), "Total unused block: %d\n",
1599 zone->unused_blk_cnt);
1601 if ((zone->unused_blk_cnt - i) < 1)
1602 chip->card_wp |= XD_CARD;
1604 zone->build_flag = 1;
1606 return STATUS_SUCCESS;
1609 vfree(zone->l2p_table);
1610 zone->l2p_table = NULL;
1611 vfree(zone->free_table);
1612 zone->free_table = NULL;
1617 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1621 rtsx_init_cmd(chip);
1623 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1624 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1625 XD_TRANSFER_START | XD_SET_CMD);
1626 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1627 XD_TRANSFER_END, XD_TRANSFER_END);
1629 retval = rtsx_send_cmd(chip, XD_CARD, 200);
1635 return STATUS_SUCCESS;
1638 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk,
1639 u32 log_blk, u8 start_page, u8 end_page,
1640 u8 *buf, unsigned int *index,
1641 unsigned int *offset)
1643 struct xd_info *xd_card = &chip->xd_card;
1644 u32 page_addr, new_blk;
1646 u8 reg_val, page_cnt;
1647 int zone_no, retval, i;
1649 if (start_page > end_page)
1652 page_cnt = end_page - start_page;
1653 zone_no = (int)(log_blk / 1000);
1654 log_off = (u16)(log_blk % 1000);
1656 if ((phy_blk & 0x3FF) == 0x3FF) {
1657 for (i = 0; i < 256; i++) {
1658 page_addr = ((u32)i) << xd_card->block_shift;
1660 retval = xd_read_redundant(chip, page_addr, NULL, 0);
1661 if (retval == STATUS_SUCCESS)
1664 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1665 xd_set_err_code(chip, XD_NO_CARD);
1671 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1673 rtsx_init_cmd(chip);
1675 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1676 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1677 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1678 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1679 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1680 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1682 trans_dma_enable(chip->srb->sc_data_direction, chip,
1683 page_cnt * 512, DMA_512);
1685 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1686 XD_TRANSFER_START | XD_READ_PAGES);
1687 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1688 XD_TRANSFER_END | XD_PPB_EMPTY,
1689 XD_TRANSFER_END | XD_PPB_EMPTY);
1691 rtsx_send_cmd_no_wait(chip);
1693 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1694 scsi_sg_count(chip->srb),
1695 index, offset, DMA_FROM_DEVICE,
1698 rtsx_clear_xd_error(chip);
1700 if (retval == -ETIMEDOUT) {
1701 xd_set_err_code(chip, XD_TO_ERROR);
1709 return STATUS_SUCCESS;
1712 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val);
1718 if (reg_val != XD_GPG)
1719 xd_set_err_code(chip, XD_PRG_ERROR);
1721 retval = rtsx_read_register(chip, XD_CTL, ®_val);
1727 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1728 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ||
1729 ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1730 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1733 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1734 xd_set_err_code(chip, XD_NO_CARD);
1738 xd_set_err_code(chip, XD_ECC_ERROR);
1740 new_blk = xd_get_unused_block(chip, zone_no);
1741 if (new_blk == NO_NEW_BLK) {
1742 XD_CLR_BAD_OLDBLK(xd_card);
1746 retval = xd_copy_page(chip, phy_blk, new_blk, 0,
1747 xd_card->page_off + 1);
1748 if (retval != STATUS_SUCCESS) {
1749 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1750 retval = xd_erase_block(chip, new_blk);
1751 if (retval == STATUS_SUCCESS)
1752 xd_set_unused_block(chip, new_blk);
1754 XD_CLR_BAD_NEWBLK(xd_card);
1756 XD_CLR_BAD_OLDBLK(xd_card);
1759 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1760 xd_erase_block(chip, phy_blk);
1761 xd_mark_bad_block(chip, phy_blk);
1762 XD_CLR_BAD_OLDBLK(xd_card);
1770 static int xd_finish_write(struct rtsx_chip *chip,
1771 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1773 struct xd_info *xd_card = &chip->xd_card;
1774 int retval, zone_no;
1777 dev_dbg(rtsx_dev(chip), "xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1778 old_blk, new_blk, log_blk);
1780 if (page_off > xd_card->page_off) {
1785 zone_no = (int)(log_blk / 1000);
1786 log_off = (u16)(log_blk % 1000);
1788 if (old_blk == BLK_NOT_FOUND) {
1789 retval = xd_init_page(chip, new_blk, log_off,
1790 page_off, xd_card->page_off + 1);
1791 if (retval != STATUS_SUCCESS) {
1792 retval = xd_erase_block(chip, new_blk);
1793 if (retval == STATUS_SUCCESS)
1794 xd_set_unused_block(chip, new_blk);
1799 retval = xd_copy_page(chip, old_blk, new_blk,
1800 page_off, xd_card->page_off + 1);
1801 if (retval != STATUS_SUCCESS) {
1802 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1803 retval = xd_erase_block(chip, new_blk);
1804 if (retval == STATUS_SUCCESS)
1805 xd_set_unused_block(chip, new_blk);
1807 XD_CLR_BAD_NEWBLK(xd_card);
1812 retval = xd_erase_block(chip, old_blk);
1813 if (retval == STATUS_SUCCESS) {
1814 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1815 xd_mark_bad_block(chip, old_blk);
1816 XD_CLR_BAD_OLDBLK(xd_card);
1818 xd_set_unused_block(chip, old_blk);
1821 xd_set_err_code(chip, XD_NO_ERROR);
1822 XD_CLR_BAD_OLDBLK(xd_card);
1826 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1828 return STATUS_SUCCESS;
1831 static int xd_prepare_write(struct rtsx_chip *chip,
1832 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1836 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1837 __func__, old_blk, new_blk, log_blk, (int)page_off);
1840 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1841 if (retval != STATUS_SUCCESS) {
1847 return STATUS_SUCCESS;
1850 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk,
1851 u32 new_blk, u32 log_blk, u8 start_page,
1852 u8 end_page, u8 *buf, unsigned int *index,
1853 unsigned int *offset)
1855 struct xd_info *xd_card = &chip->xd_card;
1857 int zone_no, retval;
1859 u8 page_cnt, reg_val;
1861 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1862 __func__, old_blk, new_blk, log_blk);
1864 if (start_page > end_page)
1867 page_cnt = end_page - start_page;
1868 zone_no = (int)(log_blk / 1000);
1869 log_off = (u16)(log_blk % 1000);
1871 page_addr = (new_blk << xd_card->block_shift) + start_page;
1873 retval = xd_send_cmd(chip, READ1_1);
1874 if (retval != STATUS_SUCCESS)
1877 rtsx_init_cmd(chip);
1879 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1880 0xFF, (u8)(log_off >> 8));
1881 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1882 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1883 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1885 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1887 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1889 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1890 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1892 trans_dma_enable(chip->srb->sc_data_direction, chip,
1893 page_cnt * 512, DMA_512);
1895 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1896 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1897 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1898 XD_TRANSFER_END, XD_TRANSFER_END);
1900 rtsx_send_cmd_no_wait(chip);
1902 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1903 scsi_sg_count(chip->srb),
1904 index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1906 rtsx_clear_xd_error(chip);
1908 if (retval == -ETIMEDOUT) {
1909 xd_set_err_code(chip, XD_TO_ERROR);
1917 if (end_page == (xd_card->page_off + 1)) {
1918 xd_card->delay_write.delay_write_flag = 0;
1920 if (old_blk != BLK_NOT_FOUND) {
1921 retval = xd_erase_block(chip, old_blk);
1922 if (retval == STATUS_SUCCESS) {
1923 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1924 xd_mark_bad_block(chip, old_blk);
1925 XD_CLR_BAD_OLDBLK(xd_card);
1927 xd_set_unused_block(chip, old_blk);
1930 xd_set_err_code(chip, XD_NO_ERROR);
1931 XD_CLR_BAD_OLDBLK(xd_card);
1934 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1937 return STATUS_SUCCESS;
1940 retval = rtsx_read_register(chip, XD_DAT, ®_val);
1945 if (reg_val & PROGRAM_ERROR) {
1946 xd_set_err_code(chip, XD_PRG_ERROR);
1947 xd_mark_bad_block(chip, new_blk);
1955 #ifdef XD_DELAY_WRITE
1956 int xd_delay_write(struct rtsx_chip *chip)
1958 struct xd_info *xd_card = &chip->xd_card;
1959 struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1962 if (delay_write->delay_write_flag) {
1963 dev_dbg(rtsx_dev(chip), "xd_delay_write\n");
1964 retval = xd_switch_clock(chip);
1965 if (retval != STATUS_SUCCESS) {
1970 delay_write->delay_write_flag = 0;
1971 retval = xd_finish_write(chip,
1972 delay_write->old_phyblock,
1973 delay_write->new_phyblock,
1974 delay_write->logblock,
1975 delay_write->pageoff);
1976 if (retval != STATUS_SUCCESS) {
1982 return STATUS_SUCCESS;
1986 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
1987 u32 start_sector, u16 sector_cnt)
1989 struct xd_info *xd_card = &chip->xd_card;
1990 unsigned int lun = SCSI_LUN(srb);
1991 #ifdef XD_DELAY_WRITE
1992 struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1994 int retval, zone_no;
1995 unsigned int index = 0, offset = 0;
1996 u32 log_blk, old_blk = 0, new_blk = 0;
1997 u16 log_off, total_sec_cnt = sector_cnt;
1998 u8 start_page, end_page = 0, page_cnt;
2001 xd_set_err_code(chip, XD_NO_ERROR);
2003 xd_card->cleanup_counter = 0;
2005 dev_dbg(rtsx_dev(chip), "xd_rw: scsi_sg_count = %d\n",
2006 scsi_sg_count(srb));
2008 ptr = (u8 *)scsi_sglist(srb);
2010 retval = xd_switch_clock(chip);
2011 if (retval != STATUS_SUCCESS) {
2016 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2017 chip->card_fail |= XD_CARD;
2018 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2023 log_blk = start_sector >> xd_card->block_shift;
2024 start_page = (u8)start_sector & xd_card->page_off;
2025 zone_no = (int)(log_blk / 1000);
2026 log_off = (u16)(log_blk % 1000);
2028 if (xd_card->zone[zone_no].build_flag == 0) {
2029 retval = xd_build_l2p_tbl(chip, zone_no);
2030 if (retval != STATUS_SUCCESS) {
2031 chip->card_fail |= XD_CARD;
2032 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2038 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2039 #ifdef XD_DELAY_WRITE
2040 if (delay_write->delay_write_flag &&
2041 (delay_write->logblock == log_blk) &&
2042 (start_page > delay_write->pageoff)) {
2043 delay_write->delay_write_flag = 0;
2044 if (delay_write->old_phyblock != BLK_NOT_FOUND) {
2045 retval = xd_copy_page(chip,
2046 delay_write->old_phyblock,
2047 delay_write->new_phyblock,
2048 delay_write->pageoff,
2050 if (retval != STATUS_SUCCESS) {
2051 set_sense_type(chip, lun,
2052 SENSE_TYPE_MEDIA_WRITE_ERR);
2057 old_blk = delay_write->old_phyblock;
2058 new_blk = delay_write->new_phyblock;
2059 } else if (delay_write->delay_write_flag &&
2060 (delay_write->logblock == log_blk) &&
2061 (start_page == delay_write->pageoff)) {
2062 delay_write->delay_write_flag = 0;
2063 old_blk = delay_write->old_phyblock;
2064 new_blk = delay_write->new_phyblock;
2066 retval = xd_delay_write(chip);
2067 if (retval != STATUS_SUCCESS) {
2068 set_sense_type(chip, lun,
2069 SENSE_TYPE_MEDIA_WRITE_ERR);
2074 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2075 new_blk = xd_get_unused_block(chip, zone_no);
2076 if ((old_blk == BLK_NOT_FOUND) ||
2077 (new_blk == BLK_NOT_FOUND)) {
2078 set_sense_type(chip, lun,
2079 SENSE_TYPE_MEDIA_WRITE_ERR);
2084 retval = xd_prepare_write(chip, old_blk, new_blk,
2085 log_blk, start_page);
2086 if (retval != STATUS_SUCCESS) {
2087 if (detect_card_cd(chip, XD_CARD) !=
2089 set_sense_type(chip, lun,
2090 SENSE_TYPE_MEDIA_NOT_PRESENT);
2094 set_sense_type(chip, lun,
2095 SENSE_TYPE_MEDIA_WRITE_ERR);
2099 #ifdef XD_DELAY_WRITE
2103 #ifdef XD_DELAY_WRITE
2104 retval = xd_delay_write(chip);
2105 if (retval != STATUS_SUCCESS) {
2106 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2107 set_sense_type(chip, lun,
2108 SENSE_TYPE_MEDIA_NOT_PRESENT);
2112 set_sense_type(chip, lun,
2113 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2119 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2120 if (old_blk == BLK_NOT_FOUND) {
2121 set_sense_type(chip, lun,
2122 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2128 dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk);
2130 while (total_sec_cnt) {
2131 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2132 chip->card_fail |= XD_CARD;
2133 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2138 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
2139 end_page = xd_card->page_off + 1;
2141 end_page = start_page + (u8)total_sec_cnt;
2143 page_cnt = end_page - start_page;
2144 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2145 retval = xd_read_multiple_pages(chip, old_blk, log_blk,
2146 start_page, end_page,
2147 ptr, &index, &offset);
2148 if (retval != STATUS_SUCCESS) {
2149 set_sense_type(chip, lun,
2150 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2155 retval = xd_write_multiple_pages(chip, old_blk,
2157 start_page, end_page,
2158 ptr, &index, &offset);
2159 if (retval != STATUS_SUCCESS) {
2160 set_sense_type(chip, lun,
2161 SENSE_TYPE_MEDIA_WRITE_ERR);
2167 total_sec_cnt -= page_cnt;
2168 if (scsi_sg_count(srb) == 0)
2169 ptr += page_cnt * 512;
2171 if (total_sec_cnt == 0)
2175 zone_no = (int)(log_blk / 1000);
2176 log_off = (u16)(log_blk % 1000);
2178 if (xd_card->zone[zone_no].build_flag == 0) {
2179 retval = xd_build_l2p_tbl(chip, zone_no);
2180 if (retval != STATUS_SUCCESS) {
2181 chip->card_fail |= XD_CARD;
2182 set_sense_type(chip, lun,
2183 SENSE_TYPE_MEDIA_NOT_PRESENT);
2189 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2190 if (old_blk == BLK_NOT_FOUND) {
2191 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2192 set_sense_type(chip, lun,
2193 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2195 set_sense_type(chip, lun,
2196 SENSE_TYPE_MEDIA_WRITE_ERR);
2202 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2203 new_blk = xd_get_unused_block(chip, zone_no);
2204 if (new_blk == BLK_NOT_FOUND) {
2205 set_sense_type(chip, lun,
2206 SENSE_TYPE_MEDIA_WRITE_ERR);
2215 if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2216 (end_page != (xd_card->page_off + 1))) {
2217 #ifdef XD_DELAY_WRITE
2218 delay_write->delay_write_flag = 1;
2219 delay_write->old_phyblock = old_blk;
2220 delay_write->new_phyblock = new_blk;
2221 delay_write->logblock = log_blk;
2222 delay_write->pageoff = end_page;
2224 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2225 chip->card_fail |= XD_CARD;
2226 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2231 retval = xd_finish_write(chip, old_blk, new_blk,
2233 if (retval != STATUS_SUCCESS) {
2234 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2235 set_sense_type(chip, lun,
2236 SENSE_TYPE_MEDIA_NOT_PRESENT);
2240 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2247 scsi_set_resid(srb, 0);
2249 return STATUS_SUCCESS;
2252 void xd_free_l2p_tbl(struct rtsx_chip *chip)
2254 struct xd_info *xd_card = &chip->xd_card;
2257 if (xd_card->zone) {
2258 for (i = 0; i < xd_card->zone_cnt; i++) {
2259 vfree(xd_card->zone[i].l2p_table);
2260 xd_card->zone[i].l2p_table = NULL;
2261 vfree(xd_card->zone[i].free_table);
2262 xd_card->zone[i].free_table = NULL;
2264 vfree(xd_card->zone);
2265 xd_card->zone = NULL;
2269 void xd_cleanup_work(struct rtsx_chip *chip)
2271 #ifdef XD_DELAY_WRITE
2272 struct xd_info *xd_card = &chip->xd_card;
2274 if (xd_card->delay_write.delay_write_flag) {
2275 dev_dbg(rtsx_dev(chip), "xD: delay write\n");
2276 xd_delay_write(chip);
2277 xd_card->cleanup_counter = 0;
2282 int xd_power_off_card3v3(struct rtsx_chip *chip)
2286 retval = disable_card_clock(chip, XD_CARD);
2287 if (retval != STATUS_SUCCESS) {
2292 retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
2298 if (!chip->ft2_fast_mode) {
2299 retval = card_power_off(chip, XD_CARD);
2300 if (retval != STATUS_SUCCESS) {
2308 if (chip->asic_code) {
2309 retval = xd_pull_ctl_disable(chip);
2310 if (retval != STATUS_SUCCESS) {
2315 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2322 return STATUS_SUCCESS;
2325 int release_xd_card(struct rtsx_chip *chip)
2327 struct xd_info *xd_card = &chip->xd_card;
2330 chip->card_ready &= ~XD_CARD;
2331 chip->card_fail &= ~XD_CARD;
2332 chip->card_wp &= ~XD_CARD;
2334 xd_card->delay_write.delay_write_flag = 0;
2336 xd_free_l2p_tbl(chip);
2338 retval = xd_power_off_card3v3(chip);
2339 if (retval != STATUS_SUCCESS) {
2344 return STATUS_SUCCESS;