1 /******************************************************************************/
3 /* Bypass Control utility, Copyright (c) 2005-2011 Silicom */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009, 2013 Intel Corporation. All rights reserved. */
11 /******************************************************************************/
13 #include <linux/kernel.h> /* We're doing kernel work */
14 #include <linux/module.h> /* Specifically, a module */
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/netdevice.h>
19 #include <linux/rtnetlink.h>
20 #include <linux/rcupdate.h>
21 #include <linux/etherdevice.h>
23 #include <linux/uaccess.h> /* for get_user and put_user */
24 #include <linux/sched.h>
25 #include <linux/ethtool.h>
26 #include <linux/proc_fs.h>
34 #define BP_MOD_VER "9.0.4"
35 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36 #define BP_SYNC_FLAG 1
40 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
41 MODULE_LICENSE("GPL");
42 MODULE_DESCRIPTION(BP_MOD_DESCR);
43 MODULE_VERSION(BP_MOD_VER);
44 static spinlock_t bpvm_lock;
46 #define unlock_bpctl() \
57 struct bypass_pfs_sd {
59 struct proc_dir_entry *bypass_entry;
65 struct pci_dev *pdev; /* PCI device */
66 struct net_device *ndev; /* net device */
67 unsigned long mem_map;
81 unsigned long bypass_wdt_on_time;
82 uint32_t bypass_timer_interval;
83 struct timer_list bp_timer;
87 enum bp_media_type media_type;
89 struct timer_list bp_tpl_timer;
90 spinlock_t bypass_wr_lock;
97 int (*hard_start_xmit_save) (struct sk_buff *skb,
98 struct net_device *dev);
99 const struct net_device_ops *old_ops;
100 struct net_device_ops new_ops;
101 int bp_self_test_flag;
103 struct bypass_pfs_sd bypass_pfs_set;
107 static struct bpctl_dev *bpctl_dev_arr;
109 static struct semaphore bpctl_sema;
110 static int device_num;
112 static int get_dev_idx(int ifindex);
113 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev);
114 static int disc_status(struct bpctl_dev *pbpctl_dev);
115 static int bypass_status(struct bpctl_dev *pbpctl_dev);
116 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left);
117 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev);
118 static void if_scan_init(void);
120 static int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block);
121 static int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block);
123 static int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
124 static int get_dev_idx_bsf(int bus, int slot, int func);
126 static int bp_get_dev_idx_bsf(struct net_device *dev, int *index)
128 struct ethtool_drvinfo drvinfo = {0};
132 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo)
133 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
137 if (!strcmp(drvinfo.bus_info, "N/A"))
140 buf = strchr(drvinfo.bus_info, ':');
144 if (sscanf(buf, "%x:%x.%x", &bus, &slot, &func) != 3)
147 *index = get_dev_idx_bsf(bus, slot, func);
151 static int bp_device_event(struct notifier_block *unused,
152 unsigned long event, void *ptr)
154 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
155 static struct bpctl_dev *pbpctl_dev, *pbpctl_dev_m;
156 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
158 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
159 /* return NOTIFY_DONE; */
163 if (event == NETDEV_REGISTER) {
166 if (bp_get_dev_idx_bsf(dev, &idx_dev))
172 bpctl_dev_arr[idx_dev].ifindex = dev->ifindex;
173 bpctl_dev_arr[idx_dev].ndev = dev;
175 bypass_proc_remove_dev_sd(&bpctl_dev_arr[idx_dev]);
176 bypass_proc_create_dev_sd(&bpctl_dev_arr[idx_dev]);
179 if (event == NETDEV_UNREGISTER) {
182 ((bpctl_dev_arr[idx_dev].pdev != NULL)
183 && (idx_dev < device_num)); idx_dev++) {
184 if (bpctl_dev_arr[idx_dev].ndev == dev) {
185 bypass_proc_remove_dev_sd(&bpctl_dev_arr
187 bpctl_dev_arr[idx_dev].ndev = NULL;
196 if (event == NETDEV_CHANGENAME) {
199 ((bpctl_dev_arr[idx_dev].pdev != NULL)
200 && (idx_dev < device_num)); idx_dev++) {
201 if (bpctl_dev_arr[idx_dev].ndev == dev) {
202 bypass_proc_remove_dev_sd(&bpctl_dev_arr
204 bypass_proc_create_dev_sd(&bpctl_dev_arr
219 if (netif_carrier_ok(dev))
222 dev_num = get_dev_idx(dev->ifindex);
226 pbpctl_dev = &bpctl_dev_arr[dev_num];
230 if ((is_bypass_fn(pbpctl_dev)) == 1)
231 pbpctl_dev_m = pbpctl_dev;
233 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
236 ret = bypass_status(pbpctl_dev_m);
238 printk("bpmod: %s is in the Bypass mode now",
240 ret_d = disc_status(pbpctl_dev_m);
243 ("bpmod: %s is in the Disconnect mode now",
246 wdt_timer(pbpctl_dev_m, &time_left);
248 printk("; WDT has expired");
264 static struct notifier_block bp_notifier_block = {
265 .notifier_call = bp_device_event,
268 static int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
269 int wdt_time_left(struct bpctl_dev *pbpctl_dev);
271 static void write_pulse(struct bpctl_dev *pbpctl_dev,
272 unsigned int ctrl_ext,
273 unsigned char value, unsigned char len)
275 unsigned char ctrl_val = 0;
276 unsigned int i = len;
277 unsigned int ctrl = 0;
278 struct bpctl_dev *pbpctl_dev_c = NULL;
280 if (pbpctl_dev->bp_i80)
281 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
282 if (pbpctl_dev->bp_540)
283 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
285 if (pbpctl_dev->bp_10g9) {
286 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
289 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
293 ctrl_val = (value >> i) & 0x1;
295 if (pbpctl_dev->bp_10g9) {
297 /* To start management : MCLK 1, MDIO 1, output */
299 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
300 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
302 BP10G_MDIO_DATA_OUT9);
303 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
304 (ctrl | BP10G_MCLK_DATA_OUT9 |
305 BP10G_MCLK_DIR_OUT9));
307 } else if (pbpctl_dev->bp_fiber5) {
308 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
309 BPCTLI_CTRL_EXT_MCLK_DIR5
311 BPCTLI_CTRL_EXT_MDIO_DIR5
313 BPCTLI_CTRL_EXT_MDIO_DATA5
315 BPCTLI_CTRL_EXT_MCLK_DATA5));
317 } else if (pbpctl_dev->bp_i80) {
318 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
319 BPCTLI_CTRL_EXT_MDIO_DIR80
321 BPCTLI_CTRL_EXT_MDIO_DATA80));
323 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
324 BPCTLI_CTRL_EXT_MCLK_DIR80
326 BPCTLI_CTRL_EXT_MCLK_DATA80));
328 } else if (pbpctl_dev->bp_540) {
329 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
338 } else if (pbpctl_dev->bp_10gb) {
339 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
340 (ctrl_ext | BP10GB_MDIO_SET |
347 } else if (!pbpctl_dev->bp_10g)
348 /* To start management : MCLK 1, MDIO 1, output */
349 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
351 BPCTLI_CTRL_EXT_MCLK_DIR |
352 BPCTLI_CTRL_EXT_MDIO_DIR |
353 BPCTLI_CTRL_EXT_MDIO_DATA |
354 BPCTLI_CTRL_EXT_MCLK_DATA));
357 /* To start management : MCLK 1, MDIO 1, output*/
358 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
359 (ctrl_ext | BP10G_MCLK_DATA_OUT
360 | BP10G_MDIO_DATA_OUT));
364 usec_delay(PULSE_TIME);
365 if (pbpctl_dev->bp_10g9) {
367 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
369 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
371 BP10G_MDIO_DATA_OUT9);
372 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
373 (ctrl | BP10G_MCLK_DIR_OUT9) &
374 ~BP10G_MCLK_DATA_OUT9);
376 } else if (pbpctl_dev->bp_fiber5) {
377 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
379 BPCTLI_CTRL_EXT_MCLK_DIR5 |
380 BPCTLI_CTRL_EXT_MDIO_DIR5 |
381 BPCTLI_CTRL_EXT_MDIO_DATA5)
384 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
386 } else if (pbpctl_dev->bp_i80) {
387 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
388 BPCTLI_CTRL_EXT_MDIO_DIR80
390 BPCTLI_CTRL_EXT_MDIO_DATA80));
391 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
393 BPCTLI_CTRL_EXT_MCLK_DIR80)
396 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
398 } else if (pbpctl_dev->bp_540) {
399 BP10G_WRITE_REG(pbpctl_dev, ESDP,
400 (ctrl | BP540_MDIO_DIR |
405 } else if (pbpctl_dev->bp_10gb) {
407 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
408 (ctrl_ext | BP10GB_MDIO_SET |
415 } else if (!pbpctl_dev->bp_10g)
417 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
419 BPCTLI_CTRL_EXT_MCLK_DIR |
420 BPCTLI_CTRL_EXT_MDIO_DIR |
421 BPCTLI_CTRL_EXT_MDIO_DATA)
424 (BPCTLI_CTRL_EXT_MCLK_DATA)));
427 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
429 BP10G_MDIO_DATA_OUT) &
430 ~(BP10G_MCLK_DATA_OUT)));
433 usec_delay(PULSE_TIME);
436 if (pbpctl_dev->bp_10g9) {
438 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
439 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
441 ~BP10G_MDIO_DATA_OUT9));
442 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
443 (ctrl | BP10G_MCLK_DATA_OUT9 |
444 BP10G_MCLK_DIR_OUT9));
446 } else if (pbpctl_dev->bp_fiber5) {
447 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
449 BPCTLI_CTRL_EXT_MCLK_DIR5 |
450 BPCTLI_CTRL_EXT_MDIO_DIR5 |
451 BPCTLI_CTRL_EXT_MCLK_DATA5)
454 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
456 } else if (pbpctl_dev->bp_i80) {
457 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
459 BPCTLI_CTRL_EXT_MDIO_DIR80)
462 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
463 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
465 BPCTLI_CTRL_EXT_MCLK_DIR80 |
466 BPCTLI_CTRL_EXT_MCLK_DATA80));
468 } else if (pbpctl_dev->bp_540) {
469 BP10G_WRITE_REG(pbpctl_dev, ESDP,
470 ((ctrl | BP540_MCLK_DIR |
473 ~(BP540_MDIO_DATA)));
475 } else if (pbpctl_dev->bp_10gb) {
476 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
477 (ctrl_ext | BP10GB_MDIO_CLR |
484 } else if (!pbpctl_dev->bp_10g)
486 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
488 BPCTLI_CTRL_EXT_MCLK_DIR |
489 BPCTLI_CTRL_EXT_MDIO_DIR |
490 BPCTLI_CTRL_EXT_MCLK_DATA)
493 (BPCTLI_CTRL_EXT_MDIO_DATA)));
496 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
498 BP10G_MCLK_DATA_OUT) &
499 ~BP10G_MDIO_DATA_OUT));
502 usec_delay(PULSE_TIME);
503 if (pbpctl_dev->bp_10g9) {
505 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
506 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
508 ~BP10G_MDIO_DATA_OUT9));
509 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
510 ((ctrl | BP10G_MCLK_DIR_OUT9) &
511 ~(BP10G_MCLK_DATA_OUT9)));
513 } else if (pbpctl_dev->bp_fiber5) {
514 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
516 BPCTLI_CTRL_EXT_MCLK_DIR5 |
517 BPCTLI_CTRL_EXT_MDIO_DIR5)
519 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
521 BPCTLI_CTRL_EXT_MDIO_DATA5)));
523 } else if (pbpctl_dev->bp_i80) {
524 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
526 BPCTLI_CTRL_EXT_MDIO_DIR80)
528 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
529 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
531 BPCTLI_CTRL_EXT_MCLK_DIR80)
534 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
536 } else if (pbpctl_dev->bp_540) {
537 BP10G_WRITE_REG(pbpctl_dev, ESDP,
538 ((ctrl | BP540_MCLK_DIR |
542 } else if (pbpctl_dev->bp_10gb) {
544 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
545 (ctrl_ext | BP10GB_MDIO_CLR |
552 } else if (!pbpctl_dev->bp_10g)
553 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
555 BPCTLI_CTRL_EXT_MCLK_DIR |
556 BPCTLI_CTRL_EXT_MDIO_DIR) &
557 ~(BPCTLI_CTRL_EXT_MCLK_DATA
559 BPCTLI_CTRL_EXT_MDIO_DATA)));
562 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
564 ~(BP10G_MCLK_DATA_OUT |
565 BP10G_MDIO_DATA_OUT)));
568 usec_delay(PULSE_TIME);
574 static int read_pulse(struct bpctl_dev *pbpctl_dev, unsigned int ctrl_ext,
577 unsigned char ctrl_val = 0;
578 unsigned int i = len;
579 unsigned int ctrl = 0;
580 struct bpctl_dev *pbpctl_dev_c = NULL;
582 if (pbpctl_dev->bp_i80)
583 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
584 if (pbpctl_dev->bp_540)
585 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
586 if (pbpctl_dev->bp_10g9) {
587 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
590 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
595 if (pbpctl_dev->bp_10g9) {
596 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
598 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
599 ((ctrl | BP10G_MCLK_DIR_OUT9) &
600 ~(BP10G_MCLK_DATA_OUT9)));
602 } else if (pbpctl_dev->bp_fiber5) {
603 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
604 BPCTLI_CTRL_EXT_MCLK_DIR5)
607 (BPCTLI_CTRL_EXT_MDIO_DIR5
609 BPCTLI_CTRL_EXT_MCLK_DATA5)));
611 } else if (pbpctl_dev->bp_i80) {
612 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
614 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
615 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
616 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
617 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
619 } else if (pbpctl_dev->bp_540) {
620 BP10G_WRITE_REG(pbpctl_dev, ESDP,
621 ((ctrl | BP540_MCLK_DIR) &
622 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
624 } else if (pbpctl_dev->bp_10gb) {
626 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
627 (ctrl_ext | BP10GB_MDIO_DIR |
628 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
633 } else if (!pbpctl_dev->bp_10g)
634 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
635 BPCTLI_CTRL_EXT_MCLK_DIR)
638 (BPCTLI_CTRL_EXT_MDIO_DIR
640 BPCTLI_CTRL_EXT_MCLK_DATA)));
643 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
644 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
648 usec_delay(PULSE_TIME);
649 if (pbpctl_dev->bp_10g9) {
650 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
652 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
653 (ctrl | BP10G_MCLK_DATA_OUT9 |
654 BP10G_MCLK_DIR_OUT9));
656 } else if (pbpctl_dev->bp_fiber5) {
657 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
658 BPCTLI_CTRL_EXT_MCLK_DIR5
660 BPCTLI_CTRL_EXT_MCLK_DATA5)
663 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
665 } else if (pbpctl_dev->bp_i80) {
666 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
668 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
669 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
670 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
671 BPCTLI_CTRL_EXT_MCLK_DATA80));
673 } else if (pbpctl_dev->bp_540) {
674 BP10G_WRITE_REG(pbpctl_dev, ESDP,
675 ((ctrl | BP540_MCLK_DIR |
679 } else if (pbpctl_dev->bp_10gb) {
680 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
681 (ctrl_ext | BP10GB_MDIO_DIR |
682 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
687 } else if (!pbpctl_dev->bp_10g)
688 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
689 BPCTLI_CTRL_EXT_MCLK_DIR
691 BPCTLI_CTRL_EXT_MCLK_DATA)
694 (BPCTLI_CTRL_EXT_MDIO_DIR)));
697 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
698 (ctrl_ext | BP10G_MCLK_DATA_OUT |
699 BP10G_MDIO_DATA_OUT));
703 if (pbpctl_dev->bp_10g9)
704 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
705 else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80))
706 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
707 else if (pbpctl_dev->bp_540)
708 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
709 else if (pbpctl_dev->bp_10gb)
710 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
711 else if (!pbpctl_dev->bp_10g)
712 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
714 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
716 usec_delay(PULSE_TIME);
717 if (pbpctl_dev->bp_10g9) {
718 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
721 } else if (pbpctl_dev->bp_fiber5) {
722 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
724 } else if (pbpctl_dev->bp_i80) {
725 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
727 } else if (pbpctl_dev->bp_540) {
728 if (ctrl_ext & BP540_MDIO_DATA)
730 } else if (pbpctl_dev->bp_10gb) {
731 if (ctrl_ext & BP10GB_MDIO_DATA)
734 } else if (!pbpctl_dev->bp_10g) {
736 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
740 if (ctrl_ext & BP10G_MDIO_DATA_IN)
749 static void write_reg(struct bpctl_dev *pbpctl_dev, unsigned char value,
752 uint32_t ctrl_ext = 0, ctrl = 0;
753 struct bpctl_dev *pbpctl_dev_c = NULL;
756 if (pbpctl_dev->bp_10g9) {
757 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
761 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
762 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
763 wdt_time_left(pbpctl_dev);
766 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
768 atomic_set(&pbpctl_dev->wdt_busy, 1);
770 if (pbpctl_dev->bp_10g9) {
772 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
773 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
775 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
776 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
777 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
778 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
779 ((ctrl | BP10G_MCLK_DIR_OUT9) &
780 ~(BP10G_MCLK_DATA_OUT9)));
782 } else if (pbpctl_dev->bp_fiber5) {
783 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
784 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
785 BPCTLI_CTRL_EXT_MCLK_DIR5
787 BPCTLI_CTRL_EXT_MDIO_DIR5)
790 (BPCTLI_CTRL_EXT_MDIO_DATA5
792 BPCTLI_CTRL_EXT_MCLK_DATA5)));
793 } else if (pbpctl_dev->bp_i80) {
794 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
795 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
796 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
797 BPCTLI_CTRL_EXT_MDIO_DIR80)
799 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
800 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
801 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
802 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
804 } else if (pbpctl_dev->bp_540) {
805 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
806 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
812 } else if (pbpctl_dev->bp_10gb) {
813 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
815 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
816 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
817 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
818 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
820 } else if (!pbpctl_dev->bp_10g) {
822 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
823 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
824 BPCTLI_CTRL_EXT_MCLK_DIR
826 BPCTLI_CTRL_EXT_MDIO_DIR)
829 (BPCTLI_CTRL_EXT_MDIO_DATA
831 BPCTLI_CTRL_EXT_MCLK_DATA)));
833 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
834 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
835 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
837 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
839 usec_delay(CMND_INTERVAL);
842 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
844 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
845 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
848 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
849 if (pbpctl_dev->bp_10g9) {
850 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
852 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
853 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
854 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
855 ((ctrl | BP10G_MCLK_DIR_OUT9) &
856 ~(BP10G_MCLK_DATA_OUT9)));
858 } else if (pbpctl_dev->bp_fiber5) {
859 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
860 BPCTLI_CTRL_EXT_MCLK_DIR5
862 BPCTLI_CTRL_EXT_MDIO_DIR5)
865 (BPCTLI_CTRL_EXT_MDIO_DATA5
867 BPCTLI_CTRL_EXT_MCLK_DATA5)));
868 } else if (pbpctl_dev->bp_i80) {
869 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
870 BPCTLI_CTRL_EXT_MDIO_DIR80)
872 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
873 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
874 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
875 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
876 } else if (pbpctl_dev->bp_540) {
877 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
882 } else if (pbpctl_dev->bp_10gb) {
883 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
884 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
885 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
886 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
888 } else if (!pbpctl_dev->bp_10g)
890 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
891 BPCTLI_CTRL_EXT_MCLK_DIR
893 BPCTLI_CTRL_EXT_MDIO_DIR)
896 (BPCTLI_CTRL_EXT_MDIO_DATA
898 BPCTLI_CTRL_EXT_MCLK_DATA)));
900 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
902 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
906 usec_delay(CMND_INTERVAL * 4);
908 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
909 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
910 pbpctl_dev->bypass_wdt_on_time = jiffies;
912 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
914 atomic_set(&pbpctl_dev->wdt_busy, 0);
919 static void write_data(struct bpctl_dev *pbpctl_dev, unsigned char value)
921 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
924 static int read_reg(struct bpctl_dev *pbpctl_dev, unsigned char addr)
926 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
927 struct bpctl_dev *pbpctl_dev_c = NULL;
932 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
934 atomic_set(&pbpctl_dev->wdt_busy, 1);
936 if (pbpctl_dev->bp_10g9) {
937 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
942 if (pbpctl_dev->bp_10g9) {
943 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
944 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
946 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
948 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
949 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
950 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
951 ((ctrl | BP10G_MCLK_DIR_OUT9) &
952 ~(BP10G_MCLK_DATA_OUT9)));
954 } else if (pbpctl_dev->bp_fiber5) {
955 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
957 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
958 BPCTLI_CTRL_EXT_MCLK_DIR5
960 BPCTLI_CTRL_EXT_MDIO_DIR5)
963 (BPCTLI_CTRL_EXT_MDIO_DATA5
965 BPCTLI_CTRL_EXT_MCLK_DATA5)));
966 } else if (pbpctl_dev->bp_i80) {
967 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
968 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
970 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
971 BPCTLI_CTRL_EXT_MDIO_DIR80)
973 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
974 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
975 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
976 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
977 } else if (pbpctl_dev->bp_540) {
978 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
979 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
981 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
985 } else if (pbpctl_dev->bp_10gb) {
986 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
988 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
989 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
990 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
991 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
994 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
995 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
996 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
997 printk("1reg=%x\n", ctrl_ext); */
999 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1002 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1003 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1005 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1006 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1007 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1009 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1011 printk("2reg=%x\n", ctrl_ext);
1014 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1016 atomic_set(&pbpctl_dev->wdt_busy, 0);
1023 } else if (!pbpctl_dev->bp_10g) {
1025 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1027 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1028 BPCTLI_CTRL_EXT_MCLK_DIR
1030 BPCTLI_CTRL_EXT_MDIO_DIR)
1033 (BPCTLI_CTRL_EXT_MDIO_DATA
1035 BPCTLI_CTRL_EXT_MCLK_DATA)));
1038 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1039 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1040 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1042 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1046 usec_delay(CMND_INTERVAL);
1049 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1051 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1053 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1056 if (pbpctl_dev->bp_10g9) {
1058 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1059 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1060 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1061 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1062 (ctrl | BP10G_MCLK_DATA_OUT9 |
1063 BP10G_MCLK_DIR_OUT9));
1065 } else if (pbpctl_dev->bp_fiber5) {
1066 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1067 BPCTLI_CTRL_EXT_MCLK_DIR5
1069 BPCTLI_CTRL_EXT_MCLK_DATA5)
1072 (BPCTLI_CTRL_EXT_MDIO_DIR5
1074 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1076 } else if (pbpctl_dev->bp_i80) {
1077 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1079 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1080 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1081 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1082 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1083 BPCTLI_CTRL_EXT_MCLK_DATA80));
1085 } else if (pbpctl_dev->bp_540) {
1086 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1087 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1088 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1090 } else if (pbpctl_dev->bp_10gb) {
1092 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1093 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1094 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1095 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1097 } else if (!pbpctl_dev->bp_10g)
1098 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1099 BPCTLI_CTRL_EXT_MCLK_DIR
1101 BPCTLI_CTRL_EXT_MCLK_DATA)
1104 (BPCTLI_CTRL_EXT_MDIO_DIR
1106 BPCTLI_CTRL_EXT_MDIO_DATA)));
1109 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1110 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1111 BP10G_MDIO_DATA_OUT));
1115 usec_delay(PULSE_TIME);
1117 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1119 if (pbpctl_dev->bp_10g9) {
1120 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1121 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1123 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1125 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1126 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1127 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1128 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1129 ~(BP10G_MCLK_DATA_OUT9)));
1131 } else if (pbpctl_dev->bp_fiber5) {
1132 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1133 BPCTLI_CTRL_EXT_MCLK_DIR5
1135 BPCTLI_CTRL_EXT_MDIO_DIR5)
1138 (BPCTLI_CTRL_EXT_MDIO_DATA5
1140 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1141 } else if (pbpctl_dev->bp_i80) {
1142 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1143 BPCTLI_CTRL_EXT_MDIO_DIR80)
1145 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1146 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1147 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1148 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1150 } else if (pbpctl_dev->bp_540) {
1151 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1152 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1157 } else if (pbpctl_dev->bp_10gb) {
1158 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1159 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1160 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1161 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1162 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1164 } else if (!pbpctl_dev->bp_10g) {
1165 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1166 BPCTLI_CTRL_EXT_MCLK_DIR
1168 BPCTLI_CTRL_EXT_MDIO_DIR)
1171 (BPCTLI_CTRL_EXT_MDIO_DATA
1173 BPCTLI_CTRL_EXT_MCLK_DATA)));
1176 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1177 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1178 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1180 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1184 usec_delay(CMND_INTERVAL * 4);
1186 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1188 atomic_set(&pbpctl_dev->wdt_busy, 0);
1194 static int wdt_pulse(struct bpctl_dev *pbpctl_dev)
1196 uint32_t ctrl_ext = 0, ctrl = 0;
1197 struct bpctl_dev *pbpctl_dev_c = NULL;
1200 unsigned long flags;
1202 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1205 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1208 if (pbpctl_dev->bp_10g9) {
1209 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
1214 if (pbpctl_dev->bp_10g9) {
1215 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1216 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1218 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1220 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1221 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1222 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1223 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1224 ~(BP10G_MCLK_DATA_OUT9)));
1226 } else if (pbpctl_dev->bp_fiber5) {
1227 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1228 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1229 BPCTLI_CTRL_EXT_MCLK_DIR5
1231 BPCTLI_CTRL_EXT_MDIO_DIR5)
1234 (BPCTLI_CTRL_EXT_MDIO_DATA5
1236 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1237 } else if (pbpctl_dev->bp_i80) {
1238 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1239 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1240 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1241 BPCTLI_CTRL_EXT_MDIO_DIR80)
1243 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1244 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1245 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1246 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1247 } else if (pbpctl_dev->bp_540) {
1248 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1249 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1253 } else if (pbpctl_dev->bp_10gb) {
1254 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1255 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1256 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1257 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1258 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1260 } else if (!pbpctl_dev->bp_10g) {
1262 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1263 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1264 BPCTLI_CTRL_EXT_MCLK_DIR
1266 BPCTLI_CTRL_EXT_MDIO_DIR)
1269 (BPCTLI_CTRL_EXT_MDIO_DATA
1271 BPCTLI_CTRL_EXT_MCLK_DATA)));
1274 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1275 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1276 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1278 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1281 if (pbpctl_dev->bp_10g9) {
1282 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1284 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1285 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1286 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1287 (ctrl | BP10G_MCLK_DATA_OUT9 |
1288 BP10G_MCLK_DIR_OUT9));
1290 } else if (pbpctl_dev->bp_fiber5) {
1291 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1292 BPCTLI_CTRL_EXT_MCLK_DIR5
1294 BPCTLI_CTRL_EXT_MDIO_DIR5
1296 BPCTLI_CTRL_EXT_MCLK_DATA5)
1299 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1300 } else if (pbpctl_dev->bp_i80) {
1301 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1302 BPCTLI_CTRL_EXT_MDIO_DIR80)
1304 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1305 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1306 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1307 BPCTLI_CTRL_EXT_MCLK_DATA80));
1309 } else if (pbpctl_dev->bp_540) {
1310 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1316 } else if (pbpctl_dev->bp_10gb) {
1317 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1319 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1320 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1321 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1322 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1324 } else if (!pbpctl_dev->bp_10g)
1325 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1326 BPCTLI_CTRL_EXT_MCLK_DIR
1328 BPCTLI_CTRL_EXT_MDIO_DIR
1330 BPCTLI_CTRL_EXT_MCLK_DATA)
1333 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1336 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1337 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1338 ~BP10G_MDIO_DATA_OUT));
1342 usec_delay(WDT_INTERVAL);
1343 if (pbpctl_dev->bp_10g9) {
1344 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1346 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1347 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1348 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1349 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1350 ~(BP10G_MCLK_DATA_OUT9)));
1352 } else if (pbpctl_dev->bp_fiber5) {
1353 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1354 BPCTLI_CTRL_EXT_MCLK_DIR5
1356 BPCTLI_CTRL_EXT_MDIO_DIR5)
1359 (BPCTLI_CTRL_EXT_MCLK_DATA5
1361 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1362 } else if (pbpctl_dev->bp_i80) {
1363 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1364 BPCTLI_CTRL_EXT_MDIO_DIR80)
1366 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1367 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1368 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1369 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1371 } else if (pbpctl_dev->bp_540) {
1372 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1377 } else if (pbpctl_dev->bp_10gb) {
1378 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1379 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1380 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1381 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1382 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1384 } else if (!pbpctl_dev->bp_10g)
1385 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1386 BPCTLI_CTRL_EXT_MCLK_DIR
1388 BPCTLI_CTRL_EXT_MDIO_DIR)
1391 (BPCTLI_CTRL_EXT_MCLK_DATA
1393 BPCTLI_CTRL_EXT_MDIO_DATA)));
1396 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1398 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1400 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN))
1401 /*&& (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */
1402 pbpctl_dev->bypass_wdt_on_time = jiffies;
1404 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1406 usec_delay(CMND_INTERVAL * 4);
1410 static void data_pulse(struct bpctl_dev *pbpctl_dev, unsigned char value)
1413 uint32_t ctrl_ext = 0;
1415 unsigned long flags;
1417 wdt_time_left(pbpctl_dev);
1419 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1421 atomic_set(&pbpctl_dev->wdt_busy, 1);
1424 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1425 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1426 BPCTLI_CTRL_EXT_SDP6_DIR |
1427 BPCTLI_CTRL_EXT_SDP7_DIR) &
1428 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1429 BPCTLI_CTRL_EXT_SDP7_DATA)));
1431 usec_delay(INIT_CMND_INTERVAL);
1432 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1433 BPCTLI_CTRL_EXT_SDP6_DIR |
1434 BPCTLI_CTRL_EXT_SDP7_DIR |
1435 BPCTLI_CTRL_EXT_SDP6_DATA) &
1437 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1438 usec_delay(INIT_CMND_INTERVAL);
1441 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1442 BPCTLI_CTRL_EXT_SDP6_DIR |
1443 BPCTLI_CTRL_EXT_SDP7_DIR |
1444 BPCTLI_CTRL_EXT_SDP6_DATA |
1445 BPCTLI_CTRL_EXT_SDP7_DATA);
1446 usec_delay(PULSE_INTERVAL);
1447 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1448 BPCTLI_CTRL_EXT_SDP6_DIR
1450 BPCTLI_CTRL_EXT_SDP7_DIR
1452 BPCTLI_CTRL_EXT_SDP6_DATA)
1454 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1455 usec_delay(PULSE_INTERVAL);
1459 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1460 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1461 BPCTLI_CTRL_EXT_SDP6_DIR |
1462 BPCTLI_CTRL_EXT_SDP7_DIR) &
1463 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1464 BPCTLI_CTRL_EXT_SDP7_DATA)));
1465 usec_delay(WDT_TIME_CNT);
1466 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1467 pbpctl_dev->bypass_wdt_on_time = jiffies;
1469 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1471 atomic_set(&pbpctl_dev->wdt_busy, 0);
1476 static int send_wdt_pulse(struct bpctl_dev *pbpctl_dev)
1478 uint32_t ctrl_ext = 0;
1481 unsigned long flags;
1483 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1486 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1489 wdt_time_left(pbpctl_dev);
1490 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1492 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1493 BPCTLI_CTRL_EXT_SDP7_DIR |
1494 BPCTLI_CTRL_EXT_SDP7_DATA);
1495 usec_delay(PULSE_INTERVAL);
1496 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1497 BPCTLI_CTRL_EXT_SDP7_DIR) &
1498 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1500 usec_delay(PULSE_INTERVAL);
1501 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1502 pbpctl_dev->bypass_wdt_on_time = jiffies;
1504 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1510 static void send_bypass_clear_pulse(struct bpctl_dev *pbpctl_dev,
1513 uint32_t ctrl_ext = 0;
1515 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1516 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1517 BPCTLI_CTRL_EXT_SDP6_DIR) &
1518 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1520 usec_delay(PULSE_INTERVAL);
1522 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1523 BPCTLI_CTRL_EXT_SDP6_DIR |
1524 BPCTLI_CTRL_EXT_SDP6_DATA);
1525 usec_delay(PULSE_INTERVAL);
1528 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1529 BPCTLI_CTRL_EXT_SDP6_DIR) &
1530 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1531 usec_delay(PULSE_INTERVAL);
1537 int pulse_set_fn(struct bpctl_dev *pbpctl_dev, unsigned int counter)
1539 uint32_t ctrl_ext = 0;
1544 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1545 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1547 pbpctl_dev->bypass_wdt_status = 0;
1548 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1549 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1551 wdt_time_left(pbpctl_dev);
1552 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1553 pbpctl_dev->wdt_status = 0;
1554 data_pulse(pbpctl_dev, counter);
1555 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1556 pbpctl_dev->bypass_wdt_on_time = jiffies;
1559 data_pulse(pbpctl_dev, counter);
1565 int zero_set_fn(struct bpctl_dev *pbpctl_dev)
1567 uint32_t ctrl_ext = 0;
1572 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1575 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1577 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1578 BPCTLI_CTRL_EXT_MCLK_DIR)
1581 (BPCTLI_CTRL_EXT_MCLK_DATA
1583 BPCTLI_CTRL_EXT_MDIO_DIR
1585 BPCTLI_CTRL_EXT_MDIO_DATA)));
1591 int pulse_get2_fn(struct bpctl_dev *pbpctl_dev)
1593 uint32_t ctrl_ext = 0, ctrl_value = 0;
1598 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1599 printk("pulse_get_fn\n");
1600 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1601 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1602 printk("read:%d\n", ctrl_value);
1607 int pulse_get1_fn(struct bpctl_dev *pbpctl_dev)
1609 uint32_t ctrl_ext = 0, ctrl_value = 0;
1614 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1616 printk("pulse_get_fn\n");
1618 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1619 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1620 printk("read:%d\n", ctrl_value);
1625 int gpio6_set_fn(struct bpctl_dev *pbpctl_dev)
1627 uint32_t ctrl_ext = 0;
1629 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1630 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1631 BPCTLI_CTRL_EXT_SDP6_DIR |
1632 BPCTLI_CTRL_EXT_SDP6_DATA);
1636 int gpio7_set_fn(struct bpctl_dev *pbpctl_dev)
1638 uint32_t ctrl_ext = 0;
1640 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1641 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1642 BPCTLI_CTRL_EXT_SDP7_DIR |
1643 BPCTLI_CTRL_EXT_SDP7_DATA);
1647 int gpio7_clear_fn(struct bpctl_dev *pbpctl_dev)
1649 uint32_t ctrl_ext = 0;
1651 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1652 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1653 BPCTLI_CTRL_EXT_SDP7_DIR) &
1654 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1658 int gpio6_clear_fn(struct bpctl_dev *pbpctl_dev)
1660 uint32_t ctrl_ext = 0;
1662 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1663 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1664 BPCTLI_CTRL_EXT_SDP6_DIR) &
1665 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1668 #endif /*BYPASS_DEBUG */
1670 static struct bpctl_dev *lookup_port(struct bpctl_dev *dev)
1672 struct bpctl_dev *p;
1675 for (n = 0, p = bpctl_dev_arr; n < device_num && p->pdev; n++) {
1676 if (p->bus == dev->bus
1677 && p->slot == dev->slot
1678 && p->func == (dev->func ^ 1))
1684 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev)
1687 if (pbpctl_dev->func == 0 || pbpctl_dev->func == 2)
1688 return lookup_port(pbpctl_dev);
1693 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev)
1696 if (pbpctl_dev->func == 1 || pbpctl_dev->func == 3)
1697 return lookup_port(pbpctl_dev);
1702 /**************************************/
1703 /**************INTEL API***************/
1704 /**************************************/
1706 static void write_data_port_int(struct bpctl_dev *pbpctl_dev,
1707 unsigned char ctrl_value)
1711 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1712 /* Make SDP0 Pin Directonality to Output */
1713 value |= BPCTLI_CTRL_SDP0_DIR;
1714 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1716 value &= ~BPCTLI_CTRL_SDP0_DATA;
1717 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1718 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1720 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1721 /* Make SDP2 Pin Directonality to Output */
1722 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1723 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1725 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1726 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1727 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1731 static int write_data_int(struct bpctl_dev *pbpctl_dev, unsigned char value)
1733 struct bpctl_dev *pbpctl_dev_b = NULL;
1735 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1738 atomic_set(&pbpctl_dev->wdt_busy, 1);
1739 write_data_port_int(pbpctl_dev, value & 0x3);
1740 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1741 atomic_set(&pbpctl_dev->wdt_busy, 0);
1746 static int wdt_pulse_int(struct bpctl_dev *pbpctl_dev)
1749 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1752 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1754 msec_delay_bp(CMND_INTERVAL_INT);
1755 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1757 msec_delay_bp(CMND_INTERVAL_INT);
1759 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1760 pbpctl_dev->bypass_wdt_on_time = jiffies;
1765 /*************************************/
1766 /************* COMMANDS **************/
1767 /*************************************/
1769 /* CMND_ON 0x4 (100)*/
1770 static int cmnd_on(struct bpctl_dev *pbpctl_dev)
1772 int ret = BP_NOT_CAP;
1774 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1775 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1777 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1778 write_data(pbpctl_dev, CMND_ON);
1780 data_pulse(pbpctl_dev, CMND_ON);
1786 /* CMND_OFF 0x2 (10)*/
1787 static int cmnd_off(struct bpctl_dev *pbpctl_dev)
1789 int ret = BP_NOT_CAP;
1791 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1792 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1793 write_data_int(pbpctl_dev, CMND_OFF_INT);
1794 msec_delay_bp(CMND_INTERVAL_INT);
1795 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1796 write_data(pbpctl_dev, CMND_OFF);
1798 data_pulse(pbpctl_dev, CMND_OFF);
1804 /* BYPASS_ON (0xa)*/
1805 static int bypass_on(struct bpctl_dev *pbpctl_dev)
1807 int ret = BP_NOT_CAP;
1809 if (pbpctl_dev->bp_caps & BP_CAP) {
1810 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1811 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1812 msec_delay_bp(BYPASS_DELAY_INT);
1813 pbpctl_dev->bp_status_un = 0;
1814 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1815 write_data(pbpctl_dev, BYPASS_ON);
1816 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1817 msec_delay_bp(LATCH_DELAY);
1819 data_pulse(pbpctl_dev, BYPASS_ON);
1825 /* BYPASS_OFF (0x8 111)*/
1826 static int bypass_off(struct bpctl_dev *pbpctl_dev)
1828 int ret = BP_NOT_CAP;
1830 if (pbpctl_dev->bp_caps & BP_CAP) {
1831 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1832 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1833 msec_delay_bp(BYPASS_DELAY_INT);
1834 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1835 msec_delay_bp(BYPASS_DELAY_INT);
1836 pbpctl_dev->bp_status_un = 0;
1837 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1838 write_data(pbpctl_dev, BYPASS_OFF);
1839 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1840 msec_delay_bp(LATCH_DELAY);
1842 data_pulse(pbpctl_dev, BYPASS_OFF);
1849 static int tap_off(struct bpctl_dev *pbpctl_dev)
1851 int ret = BP_NOT_CAP;
1853 if ((pbpctl_dev->bp_caps & TAP_CAP)
1854 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1855 write_data(pbpctl_dev, TAP_OFF);
1856 msec_delay_bp(LATCH_DELAY);
1863 static int tap_on(struct bpctl_dev *pbpctl_dev)
1865 int ret = BP_NOT_CAP;
1867 if ((pbpctl_dev->bp_caps & TAP_CAP)
1868 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1869 write_data(pbpctl_dev, TAP_ON);
1870 msec_delay_bp(LATCH_DELAY);
1877 static int disc_off(struct bpctl_dev *pbpctl_dev)
1881 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1882 write_data(pbpctl_dev, DISC_OFF);
1883 msec_delay_bp(LATCH_DELAY);
1890 static int disc_on(struct bpctl_dev *pbpctl_dev)
1894 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1895 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1896 msec_delay_bp(LATCH_DELAY);
1902 /*TWO_PORT_LINK_HW_EN (0xe)*/
1903 static int tpl_hw_on(struct bpctl_dev *pbpctl_dev)
1905 int ret = 0, ctrl = 0;
1906 struct bpctl_dev *pbpctl_dev_b = NULL;
1908 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1912 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1913 cmnd_on(pbpctl_dev);
1914 write_data(pbpctl_dev, TPL2_ON);
1915 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1916 cmnd_off(pbpctl_dev);
1920 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1921 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1922 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1923 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
1924 ~BPCTLI_CTRL_SWDPIN0));
1930 /*TWO_PORT_LINK_HW_DIS (0xc)*/
1931 static int tpl_hw_off(struct bpctl_dev *pbpctl_dev)
1933 int ret = 0, ctrl = 0;
1934 struct bpctl_dev *pbpctl_dev_b = NULL;
1936 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1939 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1940 cmnd_on(pbpctl_dev);
1941 write_data(pbpctl_dev, TPL2_OFF);
1942 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1943 cmnd_off(pbpctl_dev);
1946 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1947 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1948 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1949 (ctrl | BPCTLI_CTRL_SWDPIO0 |
1950 BPCTLI_CTRL_SWDPIN0));
1956 /* WDT_OFF (0x6 110)*/
1957 static int wdt_off(struct bpctl_dev *pbpctl_dev)
1959 int ret = BP_NOT_CAP;
1961 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
1962 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1963 bypass_off(pbpctl_dev);
1964 else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1965 write_data(pbpctl_dev, WDT_OFF);
1967 data_pulse(pbpctl_dev, WDT_OFF);
1968 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
1978 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
1980 static int wdt_on(struct bpctl_dev *pbpctl_dev, unsigned int timeout)
1983 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
1984 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
1985 pbpctl_dev->wdt_status = 0;
1987 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1988 for (; wdt_val_array[temp_cnt]; temp_cnt++)
1989 if (timeout <= wdt_val_array[temp_cnt])
1992 if (!wdt_val_array[temp_cnt])
1995 timeout = wdt_val_array[temp_cnt];
1998 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1999 msec_delay_bp(BYPASS_DELAY_INT);
2000 pbpctl_dev->bp_status_un = 0;
2001 write_data_int(pbpctl_dev, temp_cnt);
2002 pbpctl_dev->bypass_wdt_on_time = jiffies;
2003 msec_delay_bp(CMND_INTERVAL_INT);
2004 pbpctl_dev->bypass_timer_interval = timeout;
2008 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2012 temp_value = timeout / 100;
2013 while ((temp_value >>= 1))
2015 if (timeout > ((1 << temp_cnt) * 100))
2017 pbpctl_dev->bypass_wdt_on_time = jiffies;
2018 pulse = (WDT_ON | temp_cnt);
2019 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2020 data_pulse(pbpctl_dev, pulse);
2022 write_data(pbpctl_dev, pulse);
2023 pbpctl_dev->bypass_timer_interval =
2024 (1 << temp_cnt) * 100;
2026 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2032 static void bp75_put_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2036 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2038 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2040 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2043 static s32 bp75_get_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2047 s32 timeout = 8192 + 1;
2050 /* Get the SW semaphore */
2051 while (i < timeout) {
2052 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2053 if (!(swsm & BPCTLI_SWSM_SMBI))
2062 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2067 /* Get the FW semaphore. */
2068 for (i = 0; i < timeout; i++) {
2069 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2070 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2072 /* Semaphore acquired if bit latched */
2073 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2080 /* Release semaphores */
2081 bp75_put_hw_semaphore_generic(pbpctl_dev);
2082 printk("bpctl_mod: Driver can't access the NVM\n");
2091 static void bp75_release_phy(struct bpctl_dev *pbpctl_dev)
2093 u16 mask = BPCTLI_SWFW_PHY0_SM;
2097 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2098 mask = BPCTLI_SWFW_PHY1_SM;
2101 ret_val = bp75_get_hw_semaphore_generic(pbpctl_dev);
2102 while (ret_val != 0);
2104 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2106 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2108 bp75_put_hw_semaphore_generic(pbpctl_dev);
2111 static s32 bp75_acquire_phy(struct bpctl_dev *pbpctl_dev)
2113 u16 mask = BPCTLI_SWFW_PHY0_SM;
2118 s32 i = 0, timeout = 200;
2120 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2121 mask = BPCTLI_SWFW_PHY1_SM;
2124 fwmask = mask << 16;
2126 while (i < timeout) {
2127 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2132 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2133 if (!(swfw_sync & (fwmask | swmask)))
2136 bp75_put_hw_semaphore_generic(pbpctl_dev);
2143 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2148 swfw_sync |= swmask;
2149 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2151 bp75_put_hw_semaphore_generic(pbpctl_dev);
2157 static s32 bp75_read_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset,
2164 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2165 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2167 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2169 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2171 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2172 if (mdic & BPCTLI_MDIC_READY)
2175 if (!(mdic & BPCTLI_MDIC_READY)) {
2176 printk("bpctl_mod: MDI Read did not complete\n");
2180 if (mdic & BPCTLI_MDIC_ERROR) {
2181 printk("bpctl_mod: MDI Error\n");
2191 static s32 bp75_write_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset,
2198 mdic = (((u32) data) |
2199 (offset << BPCTLI_MDIC_REG_SHIFT) |
2200 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2202 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2204 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2206 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2207 if (mdic & BPCTLI_MDIC_READY)
2210 if (!(mdic & BPCTLI_MDIC_READY)) {
2211 printk("bpctl_mod: MDI Write did not complete\n");
2215 if (mdic & BPCTLI_MDIC_ERROR) {
2216 printk("bpctl_mod: MDI Error\n");
2225 static s32 bp75_read_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2229 ret_val = bp75_acquire_phy(pbpctl_dev);
2233 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2234 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2235 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2242 bp75_read_phy_reg_mdic(pbpctl_dev,
2243 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2246 bp75_release_phy(pbpctl_dev);
2251 static s32 bp75_write_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2255 ret_val = bp75_acquire_phy(pbpctl_dev);
2259 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2260 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2261 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2268 bp75_write_phy_reg_mdic(pbpctl_dev,
2269 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2272 bp75_release_phy(pbpctl_dev);
2278 /* SET_TX (non-Bypass command :)) */
2279 static int set_tx(struct bpctl_dev *pbpctl_dev, int tx_state)
2281 int ret = 0, ctrl = 0;
2282 struct bpctl_dev *pbpctl_dev_m;
2284 if ((is_bypass_fn(pbpctl_dev)) == 1)
2285 pbpctl_dev_m = pbpctl_dev;
2287 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2288 if (pbpctl_dev_m == NULL)
2290 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2291 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2293 if (pbpctl_dev->bp_540) {
2294 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2295 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2296 (ctrl | BP10G_SDP1_DIR |
2300 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2301 (ctrl | BPCTLI_CTRL_SDP1_DIR
2302 | BPCTLI_CTRL_SWDPIN1));
2305 if (pbpctl_dev->bp_540) {
2306 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2307 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2308 ((ctrl | BP10G_SDP1_DIR) &
2311 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2313 BPCTLI_CTRL_SDP1_DIR) &
2314 ~BPCTLI_CTRL_SWDPIN1));
2319 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2320 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2323 ret = bp75_read_phy_reg(pbpctl_dev,
2327 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2333 ~BPCTLI_MII_CR_POWER_DOWN);
2338 ret = bp75_read_phy_reg(pbpctl_dev,
2343 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2344 ret = bp75_write_phy_reg(pbpctl_dev,
2351 if (pbpctl_dev->bp_fiber5)
2352 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2353 else if (pbpctl_dev->bp_10gb)
2354 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2355 else if (!pbpctl_dev->bp_10g)
2356 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2358 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2361 if (pbpctl_dev->bp_10g9) {
2362 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2363 (ctrl | BP10G_SDP3_DATA |
2366 } else if (pbpctl_dev->bp_fiber5) {
2367 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2369 BPCTLI_CTRL_EXT_SDP6_DIR |
2370 BPCTLI_CTRL_EXT_SDP6_DATA));
2372 } else if (pbpctl_dev->bp_10gb) {
2373 if ((pbpctl_dev->func == 1)
2374 || (pbpctl_dev->func == 3))
2375 BP10GB_WRITE_REG(pbpctl_dev,
2378 BP10GB_GPIO0_SET_P1) &
2379 ~(BP10GB_GPIO0_CLR_P1 |
2380 BP10GB_GPIO0_OE_P1));
2382 BP10GB_WRITE_REG(pbpctl_dev,
2385 BP10GB_GPIO0_OE_P0 |
2386 BP10GB_GPIO0_SET_P0));
2388 } else if (pbpctl_dev->bp_i80) {
2389 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2390 (ctrl | BPCTLI_CTRL_SDP1_DIR
2391 | BPCTLI_CTRL_SWDPIN1));
2393 } else if (pbpctl_dev->bp_540) {
2394 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2395 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2396 (ctrl | BP10G_SDP1_DIR |
2401 else if (!pbpctl_dev->bp_10g)
2402 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2403 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2404 BPCTLI_CTRL_SWDPIN0));
2407 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2408 (ctrl | BP10G_SDP0_DATA |
2412 if (pbpctl_dev->bp_10g9) {
2413 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2414 ((ctrl | BP10G_SDP3_DIR) &
2417 } else if (pbpctl_dev->bp_fiber5) {
2418 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2420 BPCTLI_CTRL_EXT_SDP6_DIR) &
2421 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2423 } else if (pbpctl_dev->bp_10gb) {
2424 if ((bpctl_dev_arr->func == 1)
2425 || (bpctl_dev_arr->func == 3))
2426 BP10GB_WRITE_REG(pbpctl_dev,
2429 BP10GB_GPIO0_CLR_P1) &
2430 ~(BP10GB_GPIO0_SET_P1 |
2431 BP10GB_GPIO0_OE_P1));
2433 BP10GB_WRITE_REG(pbpctl_dev,
2436 BP10GB_GPIO0_OE_P0 |
2437 BP10GB_GPIO0_CLR_P0));
2439 } else if (pbpctl_dev->bp_i80) {
2440 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2442 BPCTLI_CTRL_SDP1_DIR) &
2443 ~BPCTLI_CTRL_SWDPIN1));
2444 } else if (pbpctl_dev->bp_540) {
2445 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2446 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2447 ((ctrl | BP10G_SDP1_DIR) &
2451 else if (!pbpctl_dev->bp_10g) {
2452 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2453 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2454 & ~BPCTLI_CTRL_SWDPIN0));
2455 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2456 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2459 (BPCTLI_CTRL_SDP0_DATA
2461 BPCTLI_CTRL_SDP0_DIR)));
2464 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2465 ((ctrl | BP10G_SDP0_DIR) &
2476 /* SET_FORCE_LINK (non-Bypass command :)) */
2477 static int set_bp_force_link(struct bpctl_dev *pbpctl_dev, int tx_state)
2479 int ret = 0, ctrl = 0;
2481 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2483 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2485 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2487 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2488 ctrl & ~BP10G_SDP1_DIR);
2490 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2491 ((ctrl | BP10G_SDP1_DIR) &
2500 /*RESET_CONT 0x20 */
2501 static int reset_cont(struct bpctl_dev *pbpctl_dev)
2503 int ret = BP_NOT_CAP;
2505 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2506 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2508 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2509 write_data(pbpctl_dev, RESET_CONT);
2511 data_pulse(pbpctl_dev, RESET_CONT);
2517 /*DIS_BYPASS_CAP 0x22 */
2518 static int dis_bypass_cap(struct bpctl_dev *pbpctl_dev)
2521 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2522 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2523 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2524 msec_delay_bp(BYPASS_DELAY_INT);
2526 write_data(pbpctl_dev, BYPASS_OFF);
2527 msec_delay_bp(LATCH_DELAY);
2528 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2529 msec_delay_bp(BYPASS_CAP_DELAY);
2536 /*EN_BYPASS_CAP 0x24 */
2537 static int en_bypass_cap(struct bpctl_dev *pbpctl_dev)
2539 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2540 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2541 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2542 msec_delay_bp(BYPASS_DELAY_INT);
2544 write_data(pbpctl_dev, EN_BYPASS_CAP);
2545 msec_delay_bp(BYPASS_CAP_DELAY);
2552 /* BYPASS_STATE_PWRON 0x26*/
2553 static int bypass_state_pwron(struct bpctl_dev *pbpctl_dev)
2555 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2556 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2557 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2558 msec_delay_bp(DFLT_PWRON_DELAY);
2560 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2566 /* NORMAL_STATE_PWRON 0x28*/
2567 static int normal_state_pwron(struct bpctl_dev *pbpctl_dev)
2569 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2570 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2571 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2572 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2573 msec_delay_bp(DFLT_PWRON_DELAY);
2575 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2581 /* BYPASS_STATE_PWROFF 0x27*/
2582 static int bypass_state_pwroff(struct bpctl_dev *pbpctl_dev)
2584 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2585 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2586 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2592 /* NORMAL_STATE_PWROFF 0x29*/
2593 static int normal_state_pwroff(struct bpctl_dev *pbpctl_dev)
2595 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2596 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2597 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2603 /*TAP_STATE_PWRON 0x2a*/
2604 static int tap_state_pwron(struct bpctl_dev *pbpctl_dev)
2606 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2607 write_data(pbpctl_dev, TAP_STATE_PWRON);
2608 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2614 /*DIS_TAP_CAP 0x2c*/
2615 static int dis_tap_cap(struct bpctl_dev *pbpctl_dev)
2617 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2618 write_data(pbpctl_dev, DIS_TAP_CAP);
2619 msec_delay_bp(BYPASS_CAP_DELAY);
2626 static int en_tap_cap(struct bpctl_dev *pbpctl_dev)
2628 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2629 write_data(pbpctl_dev, EN_TAP_CAP);
2630 msec_delay_bp(BYPASS_CAP_DELAY);
2636 /*DISC_STATE_PWRON 0x2a*/
2637 static int disc_state_pwron(struct bpctl_dev *pbpctl_dev)
2639 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2640 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2641 write_data(pbpctl_dev, DISC_STATE_PWRON);
2642 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2649 /*DIS_DISC_CAP 0x2c*/
2650 static int dis_disc_cap(struct bpctl_dev *pbpctl_dev)
2652 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2653 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2654 write_data(pbpctl_dev, DIS_DISC_CAP);
2655 msec_delay_bp(BYPASS_CAP_DELAY);
2663 static int en_disc_cap(struct bpctl_dev *pbpctl_dev)
2665 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2666 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2667 write_data(pbpctl_dev, EN_DISC_CAP);
2668 msec_delay_bp(BYPASS_CAP_DELAY);
2675 static int std_nic_on(struct bpctl_dev *pbpctl_dev)
2678 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2680 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2681 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2682 msec_delay_bp(BYPASS_DELAY_INT);
2683 pbpctl_dev->bp_status_un = 0;
2687 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2688 write_data(pbpctl_dev, STD_NIC_ON);
2689 msec_delay_bp(BYPASS_CAP_DELAY);
2694 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2695 wdt_off(pbpctl_dev);
2697 if (pbpctl_dev->bp_caps & BP_CAP) {
2698 write_data(pbpctl_dev, BYPASS_OFF);
2699 msec_delay_bp(LATCH_DELAY);
2702 if (pbpctl_dev->bp_caps & TAP_CAP) {
2703 write_data(pbpctl_dev, TAP_OFF);
2704 msec_delay_bp(LATCH_DELAY);
2707 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2708 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2709 msec_delay_bp(DFLT_PWRON_DELAY);
2711 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2713 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2714 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2715 msec_delay_bp(BYPASS_CAP_DELAY);
2718 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2719 write_data(pbpctl_dev, DIS_TAP_CAP);
2720 msec_delay_bp(BYPASS_CAP_DELAY);
2729 static int std_nic_off(struct bpctl_dev *pbpctl_dev)
2732 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2733 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2734 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2735 msec_delay_bp(BYPASS_DELAY_INT);
2738 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2739 write_data(pbpctl_dev, STD_NIC_OFF);
2740 msec_delay_bp(BYPASS_CAP_DELAY);
2745 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2747 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2748 write_data(pbpctl_dev, TAP_STATE_PWRON);
2749 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2752 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2753 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2754 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2755 msec_delay_bp(LATCH_DELAY +
2758 msec_delay_bp(DFLT_PWRON_DELAY);
2761 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2762 write_data(pbpctl_dev, EN_TAP_CAP);
2763 msec_delay_bp(BYPASS_CAP_DELAY);
2765 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2766 write_data(pbpctl_dev, EN_DISC_CAP);
2767 msec_delay_bp(BYPASS_CAP_DELAY);
2770 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2771 write_data(pbpctl_dev, EN_BYPASS_CAP);
2772 msec_delay_bp(BYPASS_CAP_DELAY);
2781 int wdt_time_left(struct bpctl_dev *pbpctl_dev)
2784 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2785 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2786 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2789 switch (pbpctl_dev->wdt_status) {
2790 case WDT_STATUS_DIS:
2796 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2798 delta_time_msec = jiffies_to_msecs(delta_time);
2799 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2800 if (time_left < 0) {
2802 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2805 case WDT_STATUS_EXP:
2813 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left)
2817 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2819 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
2822 *time_left = wdt_time_left(pbpctl_dev);
2830 static int wdt_timer_reload(struct bpctl_dev *pbpctl_dev)
2835 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
2836 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
2837 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
2839 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2840 ret = wdt_pulse(pbpctl_dev);
2841 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2842 ret = wdt_pulse_int(pbpctl_dev);
2844 ret = send_wdt_pulse(pbpctl_dev);
2846 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
2852 static void wd_reset_timer(unsigned long param)
2854 struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
2856 struct sk_buff *skb_tmp;
2859 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
2860 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
2861 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
2866 if (pbpctl_dev->bp_self_test_flag == 1) {
2867 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
2868 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
2869 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
2870 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
2871 skb_tmp->dev = pbpctl_dev->ndev;
2873 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
2874 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
2875 netif_receive_skb(skb_tmp);
2876 goto bp_timer_reload;
2882 wdt_timer_reload(pbpctl_dev);
2886 if (pbpctl_dev->reset_time) {
2887 mod_timer(&pbpctl_dev->bp_timer,
2888 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
2892 /*WAIT_AT_PWRUP 0x80 */
2893 static int bp_wait_at_pwup_en(struct bpctl_dev *pbpctl_dev)
2896 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2897 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
2898 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
2899 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2907 /*DIS_WAIT_AT_PWRUP 0x81 */
2908 static int bp_wait_at_pwup_dis(struct bpctl_dev *pbpctl_dev)
2911 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2913 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
2914 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
2915 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2923 /*EN_HW_RESET 0x82 */
2925 static int bp_hw_reset_en(struct bpctl_dev *pbpctl_dev)
2928 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2929 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
2930 write_data(pbpctl_dev, BP_HW_RESET_EN);
2931 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2939 /*DIS_HW_RESET 0x83 */
2941 static int bp_hw_reset_dis(struct bpctl_dev *pbpctl_dev)
2944 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2945 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
2946 write_data(pbpctl_dev, BP_HW_RESET_DIS);
2947 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2956 static int wdt_exp_mode(struct bpctl_dev *pbpctl_dev, int mode)
2958 uint32_t status_reg = 0, status_reg1 = 0;
2960 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
2961 (pbpctl_dev->bp_caps & BP_CAP)) {
2962 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
2964 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
2965 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
2967 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
2968 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
2969 write_reg(pbpctl_dev,
2972 STATUS_DISC_REG_ADDR);
2976 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
2978 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
2979 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2981 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
2982 if (status_reg1 & WDTE_DISC_BPN_MASK)
2983 write_reg(pbpctl_dev,
2985 ~WDTE_DISC_BPN_MASK,
2986 STATUS_DISC_REG_ADDR);
2988 if (status_reg & WDTE_TAP_BPN_MASK)
2989 write_reg(pbpctl_dev,
2990 status_reg & ~WDTE_TAP_BPN_MASK,
2991 STATUS_TAP_REG_ADDR);
2994 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
2995 if (!(status_reg & WDTE_TAP_BPN_MASK))
2996 write_reg(pbpctl_dev,
2997 status_reg | WDTE_TAP_BPN_MASK,
2998 STATUS_TAP_REG_ADDR);
2999 /*else return BP_NOT_CAP; */
3007 static int bypass_fw_ver(struct bpctl_dev *pbpctl_dev)
3009 if (is_bypass_fn(pbpctl_dev))
3010 return read_reg(pbpctl_dev, VER_REG_ADDR);
3015 static int bypass_sign_check(struct bpctl_dev *pbpctl_dev)
3018 if (is_bypass_fn(pbpctl_dev))
3019 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3020 PIC_SIGN_VALUE) ? 1 : 0);
3025 static int tx_status(struct bpctl_dev *pbpctl_dev)
3028 struct bpctl_dev *pbpctl_dev_m;
3030 if ((is_bypass_fn(pbpctl_dev)) == 1)
3031 pbpctl_dev_m = pbpctl_dev;
3033 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3034 if (pbpctl_dev_m == NULL)
3036 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3038 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3039 if (pbpctl_dev->bp_i80)
3040 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3041 if (pbpctl_dev->bp_540) {
3042 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3044 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3049 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3050 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3054 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3055 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3064 if (pbpctl_dev->bp_10g9) {
3065 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3066 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3068 } else if (pbpctl_dev->bp_fiber5) {
3069 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3070 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3073 } else if (pbpctl_dev->bp_10gb) {
3074 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3075 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3076 (ctrl | BP10GB_GPIO0_OE_P1) &
3077 ~(BP10GB_GPIO0_SET_P1 |
3078 BP10GB_GPIO0_CLR_P1));
3080 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3081 return (((BP10GB_READ_REG
3083 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3086 return (((BP10GB_READ_REG
3088 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3092 if (!pbpctl_dev->bp_10g) {
3094 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3095 if (pbpctl_dev->bp_i80)
3096 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3098 if (pbpctl_dev->bp_540) {
3099 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3101 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3104 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3106 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3107 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3113 static int bp_force_link_status(struct bpctl_dev *pbpctl_dev)
3116 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3118 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3119 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3120 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3127 static int bypass_from_last_read(struct bpctl_dev *pbpctl_dev)
3129 uint32_t ctrl_ext = 0;
3130 struct bpctl_dev *pbpctl_dev_b = NULL;
3132 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3133 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3136 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3137 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3138 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3139 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3140 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3147 static int bypass_status_clear(struct bpctl_dev *pbpctl_dev)
3149 struct bpctl_dev *pbpctl_dev_b = NULL;
3151 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3152 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3155 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3161 static int bypass_flag_status(struct bpctl_dev *pbpctl_dev)
3164 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3165 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3166 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3167 BYPASS_FLAG_MASK) ==
3168 BYPASS_FLAG_MASK) ? 1 : 0);
3174 static int bypass_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3177 if (pbpctl_dev->bp_caps & BP_CAP) {
3178 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3179 uint32_t status_reg = 0;
3180 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3181 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3189 static int bypass_change_status(struct bpctl_dev *pbpctl_dev)
3191 int ret = BP_NOT_CAP;
3193 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3194 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3195 ret = bypass_flag_status(pbpctl_dev);
3196 bypass_flag_status_clear(pbpctl_dev);
3197 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3198 ret = bypass_flag_status(pbpctl_dev);
3199 bypass_flag_status_clear(pbpctl_dev);
3201 ret = bypass_from_last_read(pbpctl_dev);
3202 bypass_status_clear(pbpctl_dev);
3208 static int bypass_status(struct bpctl_dev *pbpctl_dev)
3212 if (pbpctl_dev->bp_caps & BP_CAP) {
3214 struct bpctl_dev *pbpctl_dev_b = NULL;
3216 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3220 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3222 if (!pbpctl_dev->bp_status_un)
3223 return (((BPCTL_READ_REG
3226 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3231 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3233 if (pbpctl_dev->bp_10g9) {
3234 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3235 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3236 (ctrl_ext | BP10G_I2C_CLK_OUT));
3237 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3238 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3240 } else if (pbpctl_dev->bp_540) {
3241 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3242 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3245 else if ((pbpctl_dev->bp_fiber5)
3246 || (pbpctl_dev->bp_i80)) {
3247 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3248 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3249 } else if (pbpctl_dev->bp_10gb) {
3251 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3252 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3253 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3254 & ~(BP10GB_GPIO3_SET_P0 |
3255 BP10GB_GPIO3_CLR_P0));
3257 return (((BP10GB_READ_REG
3259 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3263 else if (!pbpctl_dev->bp_10g)
3264 return (((BPCTL_READ_REG
3267 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3271 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3272 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3274 BP10G_SDP7_DATA_OUT));
3275 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3276 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3279 } else if (pbpctl_dev->media_type == BP_COPPER) {
3281 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3282 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3284 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3285 return bypass_from_last_read(pbpctl_dev);
3292 static int default_pwron_status(struct bpctl_dev *pbpctl_dev)
3295 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3296 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3297 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3300 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3301 == DFLT_PWRON_MASK) ? 0 : 1);
3303 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3304 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3310 static int default_pwroff_status(struct bpctl_dev *pbpctl_dev)
3313 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3314 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3316 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3317 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3318 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3319 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3324 static int dis_bypass_cap_status(struct bpctl_dev *pbpctl_dev)
3327 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3328 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3329 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3330 DIS_BYPASS_CAP_MASK) ==
3331 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3337 static int wdt_programmed(struct bpctl_dev *pbpctl_dev, int *timeout)
3341 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3342 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3343 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3346 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3347 *timeout = (1 << wdt_val) * 100;
3351 int curr_wdt_status = pbpctl_dev->wdt_status;
3352 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3357 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3364 static int normal_support(struct bpctl_dev *pbpctl_dev)
3366 int ret = BP_NOT_CAP;
3368 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3369 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3371 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3372 NORMAL_UNSUPPORT_MASK) ==
3373 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3380 static int get_bp_prod_caps(struct bpctl_dev *pbpctl_dev)
3382 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3383 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3384 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3389 static int tap_flag_status(struct bpctl_dev *pbpctl_dev)
3392 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3393 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3394 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3395 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3401 static int tap_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3403 uint32_t status_reg = 0;
3405 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3406 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3407 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3408 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3409 STATUS_TAP_REG_ADDR);
3416 static int tap_change_status(struct bpctl_dev *pbpctl_dev)
3418 int ret = BP_NOT_CAP;
3420 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3421 if (pbpctl_dev->bp_caps & TAP_CAP) {
3422 if (pbpctl_dev->bp_caps & BP_CAP) {
3423 ret = tap_flag_status(pbpctl_dev);
3424 tap_flag_status_clear(pbpctl_dev);
3426 ret = bypass_from_last_read(pbpctl_dev);
3427 bypass_status_clear(pbpctl_dev);
3434 static int tap_status(struct bpctl_dev *pbpctl_dev)
3438 if (pbpctl_dev->bp_caps & TAP_CAP) {
3439 struct bpctl_dev *pbpctl_dev_b = NULL;
3441 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3445 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3446 if (!pbpctl_dev->bp_10g)
3447 return (((BPCTL_READ_REG
3450 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3453 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3454 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3456 BP10G_SDP6_DATA_OUT));
3457 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3458 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3461 } else if (pbpctl_dev->media_type == BP_COPPER)
3462 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3463 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3465 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3466 return bypass_from_last_read(pbpctl_dev);
3473 static int default_pwron_tap_status(struct bpctl_dev *pbpctl_dev)
3475 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3476 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3477 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3478 DFLT_PWRON_TAP_MASK) ==
3479 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3484 static int dis_tap_cap_status(struct bpctl_dev *pbpctl_dev)
3486 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3487 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3488 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3489 DIS_TAP_CAP_MASK) ==
3490 DIS_TAP_CAP_MASK) ? 1 : 0);
3495 static int disc_flag_status(struct bpctl_dev *pbpctl_dev)
3498 if (pbpctl_dev->bp_caps & DISC_CAP) {
3499 if (pbpctl_dev->bp_ext_ver >= 0x8)
3500 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3501 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3507 static int disc_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3509 uint32_t status_reg = 0;
3511 if (pbpctl_dev->bp_caps & DISC_CAP) {
3512 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3513 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3514 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3515 STATUS_DISC_REG_ADDR);
3522 static int disc_change_status(struct bpctl_dev *pbpctl_dev)
3524 int ret = BP_NOT_CAP;
3526 if (pbpctl_dev->bp_caps & DISC_CAP) {
3527 ret = disc_flag_status(pbpctl_dev);
3528 disc_flag_status_clear(pbpctl_dev);
3534 static int disc_off_status(struct bpctl_dev *pbpctl_dev)
3536 struct bpctl_dev *pbpctl_dev_b = NULL;
3539 if (pbpctl_dev->bp_caps & DISC_CAP) {
3540 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3543 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3544 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3545 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3547 if (pbpctl_dev->bp_i80) {
3548 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3549 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3552 if (pbpctl_dev->bp_540) {
3553 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3554 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3555 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3558 if (pbpctl_dev->media_type == BP_COPPER) {
3561 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3562 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3564 if (!pbpctl_dev->bp_10g)
3565 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3566 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3568 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3569 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3573 if (pbpctl_dev->bp_10g9) {
3574 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3575 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3577 BP10G_I2C_DATA_OUT));
3578 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3579 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3581 } else if (pbpctl_dev->bp_fiber5) {
3582 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3583 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3584 } else if (pbpctl_dev->bp_10gb) {
3586 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3587 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3588 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3589 & ~(BP10GB_GPIO3_SET_P1 |
3590 BP10GB_GPIO3_CLR_P1));
3592 return (((BP10GB_READ_REG
3594 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3597 if (!pbpctl_dev->bp_10g) {
3599 return (((BPCTL_READ_REG
3602 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3605 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3606 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3608 BP10G_SDP6_DATA_OUT));
3609 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3610 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3618 static int disc_status(struct bpctl_dev *pbpctl_dev)
3622 if (pbpctl_dev->bp_caps & DISC_CAP) {
3623 ctrl = disc_off_status(pbpctl_dev);
3626 return ((ctrl == 0) ? 1 : 0);
3631 static int default_pwron_disc_status(struct bpctl_dev *pbpctl_dev)
3633 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3634 if (pbpctl_dev->bp_ext_ver >= 0x8)
3635 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3636 DFLT_PWRON_DISC_MASK) ==
3637 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3642 static int dis_disc_cap_status(struct bpctl_dev *pbpctl_dev)
3644 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3645 if (pbpctl_dev->bp_ext_ver >= 0x8)
3646 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3647 DIS_DISC_CAP_MASK) ==
3648 DIS_DISC_CAP_MASK) ? 1 : 0);
3653 static int wdt_exp_mode_status(struct bpctl_dev *pbpctl_dev)
3655 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3656 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3657 return 0; /* bypass mode */
3658 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3659 return 1; /* tap mode */
3660 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3661 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3664 STATUS_DISC_REG_ADDR)) &
3665 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3668 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3669 WDTE_TAP_BPN_MASK) ==
3670 WDTE_TAP_BPN_MASK) ? 1 : 0);
3676 static int tpl2_flag_status(struct bpctl_dev *pbpctl_dev)
3679 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3680 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3681 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3687 static int bp_wait_at_pwup_status(struct bpctl_dev *pbpctl_dev)
3689 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3690 if (pbpctl_dev->bp_ext_ver >= 0x8)
3691 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3692 WAIT_AT_PWUP_MASK) ==
3693 WAIT_AT_PWUP_MASK) ? 1 : 0);
3698 static int bp_hw_reset_status(struct bpctl_dev *pbpctl_dev)
3701 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3703 if (pbpctl_dev->bp_ext_ver >= 0x8)
3704 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3705 EN_HW_RESET_MASK) ==
3706 EN_HW_RESET_MASK) ? 1 : 0);
3712 static int std_nic_status(struct bpctl_dev *pbpctl_dev)
3716 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
3717 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3719 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3720 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3721 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
3724 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3725 if (pbpctl_dev->bp_caps & BP_CAP) {
3727 read_reg(pbpctl_dev, STATUS_REG_ADDR);
3728 if (((!(status_val & WDT_EN_MASK))
3729 && ((status_val & STD_NIC_MASK) ==
3735 if (pbpctl_dev->bp_caps & TAP_CAP) {
3737 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3738 if ((status_val & STD_NIC_TAP_MASK) ==
3744 if (pbpctl_dev->bp_caps & TAP_CAP) {
3745 if ((disc_off_status(pbpctl_dev)))
3757 /******************************************************/
3758 /**************SW_INIT*********************************/
3759 /******************************************************/
3760 static void bypass_caps_init(struct bpctl_dev *pbpctl_dev)
3762 u_int32_t ctrl_ext = 0;
3763 struct bpctl_dev *pbpctl_dev_m = NULL;
3768 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
3769 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
3770 printk("VER_REG reg1=%x\n", ret);
3771 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3772 printk("PRODUCT_CAP reg=%x\n", ret);
3773 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3774 printk("STATUS_TAP reg1=%x\n", ret);
3775 ret = read_reg(pbpctl_dev, 0x7);
3776 printk("SIG_REG reg1=%x\n", ret);
3777 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3778 printk("STATUS_REG_ADDR=%x\n", ret);
3779 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
3780 printk("WDT_REG_ADDR=%x\n", ret);
3781 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
3782 printk("TMRL_REG_ADDR=%x\n", ret);
3783 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
3784 printk("TMRH_REG_ADDR=%x\n", ret);
3787 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
3788 pbpctl_dev->media_type = BP_FIBER;
3789 } else if (pbpctl_dev->bp_10gb) {
3790 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
3791 pbpctl_dev->media_type = BP_CX4;
3793 pbpctl_dev->media_type = BP_FIBER;
3797 else if (pbpctl_dev->bp_540)
3798 pbpctl_dev->media_type = BP_NONE;
3799 else if (!pbpctl_dev->bp_10g) {
3801 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3802 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
3803 pbpctl_dev->media_type = BP_COPPER;
3805 pbpctl_dev->media_type = BP_FIBER;
3808 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
3809 pbpctl_dev->media_type = BP_CX4;
3811 pbpctl_dev->media_type = BP_FIBER;
3814 if (is_bypass_fn(pbpctl_dev)) {
3816 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
3817 if (pbpctl_dev->media_type == BP_FIBER)
3818 pbpctl_dev->bp_caps |=
3819 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
3821 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3822 pbpctl_dev->bp_caps |= TPL_CAP;
3824 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3825 pbpctl_dev->bp_caps |=
3826 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
3827 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
3828 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
3831 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
3835 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
3836 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
3838 pbpctl_dev->bp_caps |=
3839 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
3840 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
3841 WD_STATUS_CAP | WD_TIMEOUT_CAP);
3843 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
3848 switch (pbpctl_dev->bp_fw_ver) {
3851 pbpctl_dev->bp_ext_ver =
3853 bp_fw_ver & EXT_VER_MASK);
3857 if ((bypass_sign_check(pbpctl_dev)) !=
3859 pbpctl_dev->bp_caps = 0;
3862 pbpctl_dev->bp_ext_ver =
3864 bp_fw_ver & EXT_VER_MASK);
3869 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3870 pbpctl_dev->bp_caps |=
3871 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
3872 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
3873 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
3874 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
3876 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3879 pbpctl_dev->bp_caps |=
3880 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
3882 cap_reg = get_bp_prod_caps(pbpctl_dev);
3884 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
3885 NORMAL_UNSUPPORT_MASK)
3886 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
3888 pbpctl_dev->bp_caps |= STD_NIC_CAP;
3890 if ((normal_support(pbpctl_dev)) == 1)
3892 pbpctl_dev->bp_caps |= STD_NIC_CAP;
3895 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
3896 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
3897 BYPASS_SUPPORT_MASK) {
3898 pbpctl_dev->bp_caps |=
3899 (BP_CAP | BP_STATUS_CAP |
3900 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
3901 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
3902 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
3903 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
3904 pbpctl_dev->bp_caps |=
3905 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
3908 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
3909 pbpctl_dev->bp_caps |=
3910 (TAP_CAP | TAP_STATUS_CAP |
3911 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
3912 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
3913 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
3915 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3916 if ((cap_reg & DISC_SUPPORT_MASK) ==
3918 pbpctl_dev->bp_caps |=
3919 (DISC_CAP | DISC_DIS_CAP |
3921 if ((cap_reg & TPL2_SUPPORT_MASK) ==
3922 TPL2_SUPPORT_MASK) {
3923 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
3924 pbpctl_dev->bp_caps |= TPL_CAP;
3925 pbpctl_dev->bp_tpl_flag =
3926 tpl2_flag_status(pbpctl_dev);
3931 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
3932 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
3933 DISC_PORT_SUPPORT_MASK) {
3934 pbpctl_dev->bp_caps_ex |=
3936 pbpctl_dev->bp_caps |=
3937 (TX_CTL_CAP | TX_STATUS_CAP);
3943 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3944 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3946 pbpctl_dev->wdt_status = WDT_STATUS_EN;
3948 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
3951 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
3952 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
3953 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
3954 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
3955 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
3957 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
3958 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
3959 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
3960 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
3962 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice))
3963 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
3965 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3966 if (pbpctl_dev_m != NULL) {
3968 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
3969 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
3970 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
3971 DISC_PORT_SUPPORT_MASK)
3972 pbpctl_dev->bp_caps |=
3973 (TX_CTL_CAP | TX_STATUS_CAP);
3974 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
3979 static void remove_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
3982 struct bpctl_dev *pbpctl_dev_sl = NULL;
3985 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3987 del_timer_sync(&pbpctl_dev->bp_timer);
3989 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
3990 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
3991 if ((pbpctl_dev_sl->ndev->netdev_ops)
3992 && (pbpctl_dev_sl->old_ops)) {
3994 pbpctl_dev_sl->ndev->netdev_ops =
3995 pbpctl_dev_sl->old_ops;
3996 pbpctl_dev_sl->old_ops = NULL;
4008 static int init_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4010 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4011 init_timer(&pbpctl_dev->bp_timer);
4012 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4013 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4020 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4022 struct bpctl_dev *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4024 struct ethhdr *eth = (struct ethhdr *)skb->data;
4027 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4029 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4030 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4036 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4038 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4041 if (bypass_status(pbpctl_dev_m)) {
4042 cmnd_on(pbpctl_dev_m);
4043 bypass_off(pbpctl_dev_m);
4044 cmnd_off(pbpctl_dev_m);
4046 wdt_timer_reload(pbpctl_dev_m);
4048 dev_kfree_skb_irq(skb);
4051 return pbpctl_dev->hard_start_xmit_save(skb, dev);
4055 static int set_bypass_wd_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
4057 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4058 if (pbpctl_dev->reset_time != param) {
4059 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4060 pbpctl_dev->reset_time =
4062 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4065 pbpctl_dev->reset_time = param;
4067 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4074 static int get_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4076 if (pbpctl_dev->bp_caps & WD_CTL_CAP)
4077 return pbpctl_dev->reset_time;
4084 int set_bp_self_test(struct bpctl_dev *pbpctl_dev, unsigned int param)
4086 struct bpctl_dev *pbpctl_dev_sl = NULL;
4088 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4089 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4090 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4092 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4094 if (pbpctl_dev->bp_self_test_flag == 1) {
4096 pbpctl_dev_sl->old_ops =
4097 pbpctl_dev_sl->ndev->netdev_ops;
4098 pbpctl_dev_sl->new_ops =
4099 *pbpctl_dev_sl->old_ops;
4100 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4102 pbpctl_dev_sl->ndev->netdev_ops =
4103 &pbpctl_dev_sl->new_ops;
4105 } else if (pbpctl_dev_sl->old_ops) {
4106 pbpctl_dev_sl->ndev->netdev_ops =
4107 pbpctl_dev_sl->old_ops;
4108 pbpctl_dev_sl->old_ops = NULL;
4113 set_bypass_wd_auto(pbpctl_dev, param);
4119 int get_bp_self_test(struct bpctl_dev *pbpctl_dev)
4122 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4123 if (pbpctl_dev->bp_self_test_flag == 1)
4124 return pbpctl_dev->reset_time;
4133 /**************************************************************/
4134 /************************* API ********************************/
4135 /**************************************************************/
4137 int is_bypass_fn(struct bpctl_dev *pbpctl_dev)
4142 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4145 static int set_bypass_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4149 if (!(pbpctl_dev->bp_caps & BP_CAP))
4151 ret = cmnd_on(pbpctl_dev);
4155 ret = bypass_off(pbpctl_dev);
4157 ret = bypass_on(pbpctl_dev);
4158 cmnd_off(pbpctl_dev);
4163 static int get_bypass_fn(struct bpctl_dev *pbpctl_dev)
4165 return bypass_status(pbpctl_dev);
4168 static int get_bypass_change_fn(struct bpctl_dev *pbpctl_dev)
4173 return bypass_change_status(pbpctl_dev);
4176 static int set_dis_bypass_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4183 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4185 ret = cmnd_on(pbpctl_dev);
4189 ret = dis_bypass_cap(pbpctl_dev);
4191 ret = en_bypass_cap(pbpctl_dev);
4192 cmnd_off(pbpctl_dev);
4196 static int get_dis_bypass_fn(struct bpctl_dev *pbpctl_dev)
4201 return dis_bypass_cap_status(pbpctl_dev);
4204 static int set_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4211 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4213 ret = cmnd_on(pbpctl_dev);
4217 ret = bypass_state_pwroff(pbpctl_dev);
4219 ret = normal_state_pwroff(pbpctl_dev);
4220 cmnd_off(pbpctl_dev);
4224 static int get_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev)
4229 return default_pwroff_status(pbpctl_dev);
4232 static int set_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4239 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4241 ret = cmnd_on(pbpctl_dev);
4245 ret = bypass_state_pwron(pbpctl_dev);
4247 ret = normal_state_pwron(pbpctl_dev);
4248 cmnd_off(pbpctl_dev);
4252 static int get_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev)
4257 return default_pwron_status(pbpctl_dev);
4260 static int set_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int timeout)
4267 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4270 ret = cmnd_on(pbpctl_dev);
4274 ret = wdt_off(pbpctl_dev);
4276 wdt_on(pbpctl_dev, timeout);
4277 ret = pbpctl_dev->bypass_timer_interval;
4279 cmnd_off(pbpctl_dev);
4283 static int get_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int *timeout)
4288 return wdt_programmed(pbpctl_dev, timeout);
4291 static int get_wd_expire_time_fn(struct bpctl_dev *pbpctl_dev, int *time_left)
4296 return wdt_timer(pbpctl_dev, time_left);
4299 static int reset_bypass_wd_timer_fn(struct bpctl_dev *pbpctl_dev)
4304 return wdt_timer_reload(pbpctl_dev);
4307 static int get_wd_set_caps_fn(struct bpctl_dev *pbpctl_dev)
4310 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4315 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4318 while ((step_value >>= 1))
4321 if (is_bypass_fn(pbpctl_dev)) {
4323 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4324 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4331 static int set_std_nic_fn(struct bpctl_dev *pbpctl_dev, int nic_mode)
4338 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4341 ret = cmnd_on(pbpctl_dev);
4345 ret = std_nic_on(pbpctl_dev);
4347 ret = std_nic_off(pbpctl_dev);
4348 cmnd_off(pbpctl_dev);
4352 static int get_std_nic_fn(struct bpctl_dev *pbpctl_dev)
4357 return std_nic_status(pbpctl_dev);
4360 static int set_tap_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4365 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4367 tap_off(pbpctl_dev);
4370 cmnd_off(pbpctl_dev);
4376 static int get_tap_fn(struct bpctl_dev *pbpctl_dev)
4381 return tap_status(pbpctl_dev);
4384 static int set_tap_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4391 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4392 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4394 ret = tap_state_pwron(pbpctl_dev);
4396 ret = normal_state_pwron(pbpctl_dev);
4397 cmnd_off(pbpctl_dev);
4403 static int get_tap_pwup_fn(struct bpctl_dev *pbpctl_dev)
4410 ret = default_pwron_tap_status(pbpctl_dev);
4413 return ((ret == 0) ? 1 : 0);
4416 static int get_tap_change_fn(struct bpctl_dev *pbpctl_dev)
4421 return tap_change_status(pbpctl_dev);
4424 static int set_dis_tap_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4431 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4433 ret = dis_tap_cap(pbpctl_dev);
4435 ret = en_tap_cap(pbpctl_dev);
4436 cmnd_off(pbpctl_dev);
4442 static int get_dis_tap_fn(struct bpctl_dev *pbpctl_dev)
4447 return dis_tap_cap_status(pbpctl_dev);
4450 static int set_disc_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4455 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4457 disc_off(pbpctl_dev);
4459 disc_on(pbpctl_dev);
4460 cmnd_off(pbpctl_dev);
4467 static int get_disc_fn(struct bpctl_dev *pbpctl_dev)
4474 ret = disc_status(pbpctl_dev);
4479 static int set_disc_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4486 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4487 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4489 ret = disc_state_pwron(pbpctl_dev);
4491 ret = normal_state_pwron(pbpctl_dev);
4492 cmnd_off(pbpctl_dev);
4498 static int get_disc_pwup_fn(struct bpctl_dev *pbpctl_dev)
4505 ret = default_pwron_disc_status(pbpctl_dev);
4506 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4509 static int get_disc_change_fn(struct bpctl_dev *pbpctl_dev)
4516 ret = disc_change_status(pbpctl_dev);
4520 static int set_dis_disc_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4527 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4528 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4530 ret = dis_disc_cap(pbpctl_dev);
4532 ret = en_disc_cap(pbpctl_dev);
4533 cmnd_off(pbpctl_dev);
4539 static int get_dis_disc_fn(struct bpctl_dev *pbpctl_dev)
4546 ret = dis_disc_cap_status(pbpctl_dev);
4551 static int get_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev)
4556 return wdt_exp_mode_status(pbpctl_dev);
4559 static int set_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev, int param)
4564 return wdt_exp_mode(pbpctl_dev, param);
4567 static int set_tx_fn(struct bpctl_dev *pbpctl_dev, int tx_state)
4569 struct bpctl_dev *pbpctl_dev_b = NULL;
4574 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4575 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4576 if ((pbpctl_dev->bp_tpl_flag))
4579 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4581 (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4582 (pbpctl_dev_b->bp_tpl_flag))
4585 return set_tx(pbpctl_dev, tx_state);
4588 static int set_bp_force_link_fn(int dev_num, int tx_state)
4590 static struct bpctl_dev *bpctl_dev_curr;
4592 if ((dev_num < 0) || (dev_num > device_num)
4593 || (bpctl_dev_arr[dev_num].pdev == NULL))
4595 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4597 return set_bp_force_link(bpctl_dev_curr, tx_state);
4600 static int set_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev, int param)
4605 return set_bypass_wd_auto(pbpctl_dev, param);
4608 static int get_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev)
4613 return get_bypass_wd_auto(pbpctl_dev);
4617 int set_bp_self_test_fn(struct bpctl_dev *pbpctl_dev, int param)
4622 return set_bp_self_test(pbpctl_dev, param);
4625 int get_bp_self_test_fn(struct bpctl_dev *pbpctl_dev)
4630 return get_bp_self_test(pbpctl_dev);
4635 static int get_bypass_caps_fn(struct bpctl_dev *pbpctl_dev)
4640 return pbpctl_dev->bp_caps;
4644 static int get_bypass_slave_fn(struct bpctl_dev *pbpctl_dev,
4645 struct bpctl_dev **pbpctl_dev_out)
4652 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
4654 ((bpctl_dev_arr[idx_dev].pdev != NULL)
4655 && (idx_dev < device_num)); idx_dev++) {
4656 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
4657 && (bpctl_dev_arr[idx_dev].slot ==
4658 pbpctl_dev->slot)) {
4659 if ((pbpctl_dev->func == 0)
4660 && (bpctl_dev_arr[idx_dev].func == 1)) {
4662 &bpctl_dev_arr[idx_dev];
4665 if ((pbpctl_dev->func == 2) &&
4666 (bpctl_dev_arr[idx_dev].func == 3)) {
4668 &bpctl_dev_arr[idx_dev];
4678 static int is_bypass(struct bpctl_dev *pbpctl_dev)
4683 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
4689 static int get_tx_fn(struct bpctl_dev *pbpctl_dev)
4691 struct bpctl_dev *pbpctl_dev_b = NULL;
4696 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4697 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4698 if ((pbpctl_dev->bp_tpl_flag))
4701 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4703 (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4704 (pbpctl_dev_b->bp_tpl_flag))
4707 return tx_status(pbpctl_dev);
4710 static int get_bp_force_link_fn(int dev_num)
4712 static struct bpctl_dev *bpctl_dev_curr;
4714 if ((dev_num < 0) || (dev_num > device_num)
4715 || (bpctl_dev_arr[dev_num].pdev == NULL))
4717 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4719 return bp_force_link_status(bpctl_dev_curr);
4722 static int get_bypass_link_status(struct bpctl_dev *pbpctl_dev)
4727 if (pbpctl_dev->media_type == BP_FIBER)
4728 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
4729 BPCTLI_CTRL_SWDPIN1));
4731 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
4736 static void bp_tpl_timer_fn(unsigned long param)
4738 struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
4739 uint32_t link1, link2;
4740 struct bpctl_dev *pbpctl_dev_b = NULL;
4742 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
4746 if (!pbpctl_dev->bp_tpl_flag) {
4747 set_tx(pbpctl_dev_b, 1);
4748 set_tx(pbpctl_dev, 1);
4751 link1 = get_bypass_link_status(pbpctl_dev);
4753 link2 = get_bypass_link_status(pbpctl_dev_b);
4754 if ((link1) && (tx_status(pbpctl_dev))) {
4755 if ((!link2) && (tx_status(pbpctl_dev_b)))
4756 set_tx(pbpctl_dev, 0);
4757 else if (!tx_status(pbpctl_dev_b))
4758 set_tx(pbpctl_dev_b, 1);
4759 } else if ((!link1) && (tx_status(pbpctl_dev))) {
4760 if ((link2) && (tx_status(pbpctl_dev_b)))
4761 set_tx(pbpctl_dev_b, 0);
4762 } else if ((link1) && (!tx_status(pbpctl_dev))) {
4763 if ((link2) && (tx_status(pbpctl_dev_b)))
4764 set_tx(pbpctl_dev, 1);
4765 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
4766 if ((link2) && (tx_status(pbpctl_dev_b)))
4767 set_tx(pbpctl_dev, 1);
4770 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
4773 static void remove_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
4775 struct bpctl_dev *pbpctl_dev_b;
4779 if (pbpctl_dev->bp_caps & TPL_CAP) {
4780 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
4781 pbpctl_dev->bp_tpl_flag = 0;
4782 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
4784 set_tx(pbpctl_dev_b, 1);
4785 set_tx(pbpctl_dev, 1);
4790 static int init_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
4794 if (pbpctl_dev->bp_caps & TPL_CAP) {
4795 init_timer(&pbpctl_dev->bp_tpl_timer);
4796 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
4797 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
4803 static int set_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
4807 if (pbpctl_dev->bp_caps & TPL_CAP) {
4808 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
4809 pbpctl_dev->bp_tpl_flag = param;
4810 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
4813 if ((!param) && (pbpctl_dev->bp_tpl_flag))
4814 remove_bypass_tpl_auto(pbpctl_dev);
4821 static int set_tpl_fn(struct bpctl_dev *pbpctl_dev, int tpl_mode)
4824 struct bpctl_dev *pbpctl_dev_b;
4828 if (pbpctl_dev->bp_caps & TPL_CAP) {
4830 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
4832 set_tx(pbpctl_dev_b, 1);
4833 set_tx(pbpctl_dev, 1);
4835 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
4836 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
4837 pbpctl_dev->bp_tpl_flag = tpl_mode;
4839 tpl_hw_off(pbpctl_dev);
4841 tpl_hw_on(pbpctl_dev);
4843 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
4849 static int get_tpl_fn(struct bpctl_dev *pbpctl_dev)
4851 int ret = BP_NOT_CAP;
4856 if (pbpctl_dev->bp_caps & TPL_CAP) {
4857 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
4858 return tpl2_flag_status(pbpctl_dev);
4859 ret = pbpctl_dev->bp_tpl_flag;
4864 static int set_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4869 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4870 /* bp_lock(pbp_device_block); */
4871 cmnd_on(pbpctl_dev);
4873 bp_wait_at_pwup_dis(pbpctl_dev);
4875 bp_wait_at_pwup_en(pbpctl_dev);
4876 cmnd_off(pbpctl_dev);
4878 /* bp_unlock(pbp_device_block); */
4884 static int get_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev)
4891 /* bp_lock(pbp_device_block); */
4892 ret = bp_wait_at_pwup_status(pbpctl_dev);
4893 /* bp_unlock(pbp_device_block); */
4898 static int set_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4903 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4904 /* bp_lock(pbp_device_block); */
4905 cmnd_on(pbpctl_dev);
4908 bp_hw_reset_dis(pbpctl_dev);
4910 bp_hw_reset_en(pbpctl_dev);
4911 cmnd_off(pbpctl_dev);
4912 /* bp_unlock(pbp_device_block); */
4918 static int get_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev)
4925 /* bp_lock(pbp_device_block); */
4926 ret = bp_hw_reset_status(pbpctl_dev);
4928 /* bp_unlock(pbp_device_block); */
4934 static int get_bypass_info_fn(struct bpctl_dev *pbpctl_dev, char *dev_name,
4939 if (!is_bypass_fn(pbpctl_dev))
4941 strcpy(dev_name, pbpctl_dev->name);
4942 *add_param = pbpctl_dev->bp_fw_ver;
4946 static int get_dev_idx_bsf(int bus, int slot, int func)
4951 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
4953 if ((bus == bpctl_dev_arr[idx_dev].bus)
4954 && (slot == bpctl_dev_arr[idx_dev].slot)
4955 && (func == bpctl_dev_arr[idx_dev].func))
4962 static int get_dev_idx(int ifindex)
4967 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
4969 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
4976 static struct bpctl_dev *get_dev_idx_p(int ifindex)
4981 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
4983 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
4984 return &bpctl_dev_arr[idx_dev];
4990 static void if_scan_init(void)
4992 struct net_device *dev;
4994 /* rcu_read_lock(); */
4996 /* rcu_read_lock(); */
4998 for_each_netdev(&init_net, dev) {
5001 if (bp_get_dev_idx_bsf(dev, &idx_dev))
5007 bpctl_dev_arr[idx_dev].ifindex = dev->ifindex;
5008 bpctl_dev_arr[idx_dev].ndev = dev;
5010 /* rtnl_unlock(); */
5011 /* rcu_read_unlock(); */
5014 static long device_ioctl(struct file *file, /* see include/linux/fs.h */
5015 unsigned int ioctl_num, /* number and param for ioctl */
5016 unsigned long ioctl_param)
5018 struct bpctl_cmd bpctl_cmd;
5020 struct bpctl_dev *pbpctl_dev_out;
5021 void __user *argp = (void __user *)ioctl_param;
5023 unsigned long flags;
5025 static struct bpctl_dev *pbpctl_dev;
5027 /* lock_kernel(); */
5028 if (down_interruptible(&bpctl_sema))
5029 return -ERESTARTSYS;
5030 /* local_irq_save(flags); */
5031 /* if(!spin_trylock_irqsave(&bpvm_lock)){
5032 local_irq_restore(flags);
5037 /* spin_lock_irqsave(&bpvm_lock, flags); */
5040 * Switch according to the ioctl called
5042 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5047 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5053 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5054 bpctl_cmd.out_param[0] = device_num;
5056 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5065 /* preempt_disable(); */
5066 local_irq_save(flags);
5067 if (!spin_trylock(&bpvm_lock)) {
5068 local_irq_restore(flags);
5073 /* preempt_disable();
5075 spin_lock_irqsave(&bpvm_lock, flags);
5077 if ((bpctl_cmd.in_param[5]) ||
5078 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5079 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5080 bpctl_cmd.in_param[6],
5081 bpctl_cmd.in_param[7]);
5082 else if (bpctl_cmd.in_param[1] == 0)
5083 dev_idx = bpctl_cmd.in_param[0];
5085 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5087 if (dev_idx < 0 || dev_idx > device_num) {
5089 preempt_enable(); */
5091 /* preempt_enable();
5092 rcu_read_unlock(); */
5093 spin_unlock_irqrestore(&bpvm_lock, flags);
5097 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5098 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5099 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5100 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5102 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5103 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5104 printk("Please load network driver for %s adapter!\n",
5105 bpctl_dev_arr[dev_idx].name);
5106 bpctl_cmd.status = -1;
5108 /* preempt_enable(); */
5109 /* rcu_read_unlock(); */
5110 spin_unlock_irqrestore(&bpvm_lock, flags);
5114 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5115 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5116 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5118 ("Please bring up network interfaces for %s adapter!\n",
5119 bpctl_dev_arr[dev_idx].name);
5120 bpctl_cmd.status = -1;
5122 /* preempt_enable(); */
5123 /* rcu_read_unlock(); */
5124 spin_unlock_irqrestore(&bpvm_lock, flags);
5131 if ((dev_idx < 0) || (dev_idx > device_num)
5132 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5133 bpctl_cmd.status = -1;
5137 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5139 switch (ioctl_num) {
5140 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5142 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5145 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5146 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5149 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5151 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5154 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5155 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5158 case IOCTL_TX_MSG(SET_BYPASS_WD):
5160 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5163 case IOCTL_TX_MSG(GET_BYPASS_WD):
5165 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5168 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5170 get_wd_expire_time_fn(pbpctl_dev,
5171 (int *)&(bpctl_cmd.data[0]));
5174 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5175 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5178 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5179 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5182 case IOCTL_TX_MSG(SET_STD_NIC):
5184 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5187 case IOCTL_TX_MSG(GET_STD_NIC):
5188 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5191 case IOCTL_TX_MSG(SET_TAP):
5193 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5196 case IOCTL_TX_MSG(GET_TAP):
5197 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5200 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5201 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5204 case IOCTL_TX_MSG(SET_DIS_TAP):
5206 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5209 case IOCTL_TX_MSG(GET_DIS_TAP):
5210 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5213 case IOCTL_TX_MSG(SET_TAP_PWUP):
5215 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5218 case IOCTL_TX_MSG(GET_TAP_PWUP):
5219 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5222 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5224 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5227 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5228 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5231 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5232 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5235 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5237 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5240 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5241 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5244 case IOCTL_TX_MSG(GET_BYPASS):
5245 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5248 case IOCTL_TX_MSG(SET_BYPASS):
5250 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5253 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5254 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5255 /*preempt_enable(); */
5256 /*rcu_read_unlock();*/
5257 spin_unlock_irqrestore(&bpvm_lock, flags);
5259 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5260 /*unlock_bpctl(); */
5261 /*preempt_enable(); */
5267 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5269 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5270 if (bpctl_cmd.status == 1) {
5271 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5272 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5273 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5274 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5278 case IOCTL_TX_MSG(IS_BYPASS):
5279 bpctl_cmd.status = is_bypass(pbpctl_dev);
5281 case IOCTL_TX_MSG(SET_TX):
5282 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5284 case IOCTL_TX_MSG(GET_TX):
5285 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5287 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5289 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5292 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5294 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5296 case IOCTL_TX_MSG(SET_DISC):
5298 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5300 case IOCTL_TX_MSG(GET_DISC):
5301 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5303 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5304 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5306 case IOCTL_TX_MSG(SET_DIS_DISC):
5308 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5310 case IOCTL_TX_MSG(GET_DIS_DISC):
5311 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5313 case IOCTL_TX_MSG(SET_DISC_PWUP):
5315 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5317 case IOCTL_TX_MSG(GET_DISC_PWUP):
5318 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5321 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5324 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5325 (char *)&bpctl_cmd.out_param[4]);
5328 case IOCTL_TX_MSG(SET_TPL):
5330 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5333 case IOCTL_TX_MSG(GET_TPL):
5334 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5336 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5338 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5341 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5342 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5344 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5346 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5349 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5350 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5353 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5355 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5358 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5359 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5364 case IOCTL_TX_MSG(SET_DISC_PORT):
5366 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5369 case IOCTL_TX_MSG(GET_DISC_PORT):
5370 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5373 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5375 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5378 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5379 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5382 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5384 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5387 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5388 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5392 /* unlock_bpctl(); */
5395 /* preempt_enable(); */
5396 /* rcu_read_unlock();*/
5397 spin_unlock_irqrestore(&bpvm_lock, flags);
5400 /* unlock_bpctl(); */
5401 /* preempt_enable(); */
5403 /* rcu_read_unlock(); */
5404 spin_unlock_irqrestore(&bpvm_lock, flags);
5405 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5409 /* unlock_kernel(); */
5410 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5412 /* unlock_kernel(); */
5416 static const struct file_operations Fops = {
5417 .owner = THIS_MODULE,
5418 .unlocked_ioctl = device_ioctl,
5422 #define PCI_DEVICE(vend, dev) \
5423 .vendor = (vend), .device = (dev), \
5424 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5427 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5428 PCI_DEVICE(SILICOM_VID, device_id)}
5591 unsigned int vendor;
5592 unsigned int device;
5593 unsigned int subvendor;
5594 unsigned int subdevice;
5603 {"Silicom Bypass PXG2BPFI-SD series adapter"},
5604 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
5605 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
5606 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
5607 {"Silicom Bypass PXG2BPI-SD series adapter"},
5608 {"Silicom Bypass PXG2BPIG-SD series adapter"},
5609 {"Silicom Bypass PXG2TBFI-SD series adapter"},
5610 {"Silicom Bypass PXG4BPI-SD series adapter"},
5611 {"Silicom Bypass PXG4BPFI-SD series adapter"},
5612 {"Silicom Bypass PEG4BPI-SD series adapter"},
5613 {"Silicom Bypass PEG2BPI-SD series adapter"},
5614 {"Silicom Bypass PEG4BPIN-SD series adapter"},
5615 {"Silicom Bypass PEG2BPFI-SD series adapter"},
5616 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
5617 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
5618 {"Silicom Bypass PMCX2BPFI-N series adapter"},
5619 {"Intel Bypass PEG2BPII series adapter"},
5620 {"Intel Bypass PEG2BPFII series adapter"},
5621 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
5622 {"Silicom Bypass PMCX2BPI-N series adapter"},
5623 {"Silicom Bypass PMCX4BPI-N series adapter"},
5624 {"Silicom Bypass PXG2BISC1-SD series adapter"},
5625 {"Silicom Bypass PEG2TBFI-SD series adapter"},
5626 {"Silicom Bypass PXG2TBI-SD series adapter"},
5627 {"Silicom Bypass PXG4BPFID-SD series adapter"},
5628 {"Silicom Bypass PEG4BPFI-SD series adapter"},
5629 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
5630 {"Silicom Bypass PXG6BPI-SD series adapter"},
5631 {"Silicom Bypass PEG4BPIL-SD series adapter"},
5632 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
5633 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
5634 {"Silicom Bypass PMCX2BPI-SD series adapter"},
5635 {"Silicom Bypass PEG2BPFID-SD series adapter"},
5636 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
5637 {"Silicom Bypass PMCX4BPI-SD series adapter"},
5638 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
5639 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
5640 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
5641 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
5642 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
5643 {"Silicom Bypass MHIO8AD-SD series adapter"},
5644 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
5645 {"Silicom Bypass PEG2BPI5-SD series adapter"},
5646 {"Silicom Bypass PEG6BPI5-SD series adapter"},
5647 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
5648 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
5649 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
5650 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
5651 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
5652 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
5653 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
5654 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
5655 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
5656 {"Intel Bypass PEG2BPFII0 series adapter"},
5657 {"Silicom Bypass XE10G2BPIXR series adapter"},
5658 {"Silicom Bypass PE10G2DBISR series adapter"},
5659 {"Silicom Bypass PEG2BI5SC6 series adapter"},
5660 {"Silicom Bypass PEG6BPI5FC series adapter"},
5662 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
5663 {"Silicom Bypass PE10G2BPTSR series adapter"},
5664 {"Silicom Bypass PE10G2BPTLR series adapter"},
5665 {"Silicom Bypass PE10G2BPTT series adapter"},
5666 {"Silicom Bypass PEG4BPI6 series adapter"},
5667 {"Silicom Bypass PEG4BPFI6 series adapter"},
5668 {"Silicom Bypass PEG4BPFI6LX series adapter"},
5669 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
5670 {"Silicom Bypass PEG2BPI6 series adapter"},
5671 {"Silicom Bypass PEG2BPFI6 series adapter"},
5672 {"Silicom Bypass PEG2BPFI6LX series adapter"},
5673 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
5674 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
5675 {"Silicom Bypass PEG4BPI6FC series adapter"},
5676 {"Silicom Bypass PEG4BPFI6FC series adapter"},
5677 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
5678 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
5679 {"Silicom Bypass PEG6BPI6 series adapter"},
5680 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
5681 {"Silicom Bypass MEG2BPI6 series adapter"},
5682 {"Silicom Bypass XEG2BPI6 series adapter"},
5683 {"Silicom Bypass MEG4BPI6 series adapter"},
5684 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
5685 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
5686 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
5687 {"Silicom Bypass MxEG2BPI6 series adapter"},
5688 {"Silicom Bypass MxEG2BPFI6 series adapter"},
5689 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
5690 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
5691 {"Silicom Bypass MxEG4BPI6 series adapter"},
5692 {"Silicom Bypass MxEG4BPFI6 series adapter"},
5693 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
5694 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
5695 {"Silicom Bypass MxEG6BPI6 series adapter"},
5696 {"Silicom Bypass MxE2G4BPi80 series adapter"},
5697 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
5698 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
5699 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
5701 {"Silicom Bypass PE210G2SPI9 series adapter"},
5703 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
5704 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
5705 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
5706 {"Silicom Bypass MxE210G2BPI9T series adapter"},
5708 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
5709 {"Silicom Bypass PE210G2BPI9SR series adapter"},
5710 {"Silicom Bypass PE210G2BPI9LR series adapter"},
5711 {"Silicom Bypass PE210G2BPI9T series adapter"},
5713 {"Silicom Bypass M2EG2BPFI6 series adapter"},
5714 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
5715 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
5716 {"Silicom Bypass M2EG4BPI6 series adapter"},
5717 {"Silicom Bypass M2EG4BPFI6 series adapter"},
5718 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
5719 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
5720 {"Silicom Bypass M2EG6BPI6 series adapter"},
5722 {"Silicom Bypass PEG2DBI6 series adapter"},
5723 {"Silicom Bypass PEG2DBFI6 series adapter"},
5724 {"Silicom Bypass PEG2DBFI6LX series adapter"},
5725 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
5727 {"Silicom Bypass PE2G4BPi80 series adapter"},
5728 {"Silicom Bypass PE2G4BPFi80 series adapter"},
5729 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
5730 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
5732 {"Silicom Bypass PE2G4BPi80L series adapter"},
5733 {"Silicom Bypass MxE2G8BPi80A series adapter"},
5735 {"Silicom Bypass PE2G2BPi35 series adapter"},
5736 {"Silicom Bypass PAC1200BPi35 series adapter"},
5737 {"Silicom Bypass PE2G2BPFi35 series adapter"},
5738 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
5739 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
5741 {"Silicom Bypass PE2G4BPi35 series adapter"},
5742 {"Silicom Bypass PE2G4BPi35L series adapter"},
5743 {"Silicom Bypass PE2G4BPFi35 series adapter"},
5744 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
5745 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
5747 {"Silicom Bypass PE2G6BPi35 series adapter"},
5748 {"Silicom Bypass PE2G6BPi35CX series adapter"},
5750 {"Silicom Bypass PE2G2BPi80 series adapter"},
5751 {"Silicom Bypass PE2G2BPFi80 series adapter"},
5752 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
5753 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
5755 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
5756 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
5757 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
5758 {"Silicom Bypass M2E10G2BPI9T series adapter"},
5759 {"Silicom Bypass MxE2G8BPi80 series adapter"},
5760 {"Silicom Bypass PE210G2DBi9SR series adapter"},
5761 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
5762 {"Silicom Bypass PE210G2DBi9LR series adapter"},
5763 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
5764 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
5765 {"Silicom Bypass PE310G4BPi9T series adapter"},
5766 {"Silicom Bypass PE310G4BPi9SR series adapter"},
5767 {"Silicom Bypass PE310G4BPi9LR series adapter"},
5768 {"Silicom Bypass PE210G2BPi40T series adapter"},
5772 static struct bpmod_info tx_ctl_pci_tbl[] = {
5773 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
5775 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
5777 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
5779 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
5781 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
5783 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
5785 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
5787 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
5789 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
5791 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
5793 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
5795 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
5797 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
5799 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
5801 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
5803 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
5805 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
5806 PMCXG2BPFIN, "PMCX2BPFI-N"},
5807 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
5809 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
5811 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
5813 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
5814 PMCXG2BPIN, "PMCX2BPI-N"},
5815 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
5816 PMCXG4BPIN, "PMCX4BPI-N"},
5817 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
5819 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
5821 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
5823 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
5825 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
5827 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
5829 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
5831 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
5832 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
5833 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
5834 PMCXG2BPIN2, "PMCX2BPI-N2"},
5835 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
5836 PMCXG4BPIN2, "PMCX4BPI-N2"},
5837 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
5839 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
5841 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
5843 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
5845 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
5847 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
5849 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
5851 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
5852 PE10G2BPISR, "PE10G2BPISR"},
5853 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
5854 PE10G2BPILR, "PE10G2BPILR"},
5855 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
5857 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
5858 PE10G2BPISR, "PE10G2BPICX4"},
5859 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
5860 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
5861 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
5862 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
5863 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
5864 PEG4BPFI5, "PEG4BPFI5"},
5865 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
5866 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
5867 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
5869 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
5871 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
5873 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
5875 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
5876 XE10G2BPICX4, "XE10G2BPICX4"},
5877 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
5879 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
5881 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
5882 XE10G2BPIXR, "XE10G2BPIXR"},
5883 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
5885 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
5887 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
5888 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
5889 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
5890 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
5892 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
5893 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
5894 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
5895 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
5896 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
5897 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
5898 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
5899 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
5901 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
5903 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5904 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
5905 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5906 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
5907 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5908 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
5909 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5910 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
5911 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5912 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
5913 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5914 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
5915 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5916 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
5917 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5918 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
5919 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
5920 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
5922 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5923 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
5924 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5925 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
5926 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5927 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
5929 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
5930 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
5932 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5933 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
5934 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5935 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
5937 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5938 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
5939 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5940 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
5941 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
5942 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
5944 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
5945 PEG2BPFI5, "PEG2BPFI5"},
5946 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
5947 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
5949 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
5952 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5953 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
5955 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5956 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
5957 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5958 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
5960 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5961 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
5964 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5965 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
5967 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5968 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
5969 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5970 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
5972 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5973 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
5976 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5977 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
5979 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5980 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
5981 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5982 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
5984 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5985 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
5987 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5988 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
5991 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5992 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
5993 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5994 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
5996 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
5997 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6000 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6001 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6003 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6004 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6005 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6006 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6008 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6009 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6012 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6013 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6015 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6016 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6017 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6018 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6019 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6020 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6021 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6022 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6024 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6025 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6026 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6027 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6028 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6029 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6031 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6032 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6033 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6034 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6035 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6036 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6038 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6039 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6040 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6041 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6042 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6043 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6045 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6046 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6049 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6050 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6052 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6053 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6056 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6057 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6058 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6059 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6062 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6063 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6064 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6065 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6067 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6068 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6071 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6072 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6074 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6075 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6077 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6078 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6079 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6080 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6082 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6083 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6086 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6087 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6090 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6092 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6094 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6096 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6098 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6100 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6102 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6104 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6106 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6108 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6110 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6112 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6114 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6116 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6118 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6120 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6122 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6124 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6126 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6128 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6130 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6132 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6134 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6136 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6138 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6140 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6142 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6144 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6146 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6148 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6150 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6152 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6155 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6156 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6157 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6158 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6159 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6160 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6162 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6163 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6166 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6167 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6168 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6169 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6172 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6175 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6176 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6178 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6179 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6181 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6182 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6184 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6185 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6188 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6189 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6191 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6192 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6194 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6195 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6197 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6198 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6201 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6202 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6203 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6204 PE210G2BPI9SR, "PE210G2BPI9SR"},
6205 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6206 PE210G2BPI9LR, "PE210G2BPI9LR"},
6207 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6211 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6214 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6217 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6220 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6223 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6227 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6230 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6231 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6232 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6233 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6236 /* required last entry */
6240 static void find_fw(struct bpctl_dev *dev)
6242 unsigned long mmio_start, mmio_len;
6243 struct pci_dev *pdev1 = dev->pdev;
6245 if ((OLD_IF_SERIES(dev->subdevice)) ||
6246 (INTEL_IF_SERIES(dev->subdevice)))
6247 dev->bp_fw_ver = 0xff;
6249 dev->bp_fw_ver = bypass_fw_ver(dev);
6251 if (dev->bp_10gb == 1 && dev->bp_fw_ver == 0xff) {
6254 iounmap((void *)dev->mem_map);
6255 mmio_start = pci_resource_start(pdev1, 0);
6256 mmio_len = pci_resource_len(pdev1, 0);
6258 dev->mem_map = (unsigned long)
6259 ioremap(mmio_start, mmio_len);
6261 dev->bp_fw_ver = bypass_fw_ver(dev);
6262 if (dev->bp_fw_ver == 0xa8)
6266 /* dev->bp_fw_ver=0xa8; */
6267 printk("firmware version: 0x%x\n", dev->bp_fw_ver);
6270 static int init_one(struct bpctl_dev *dev, struct bpmod_info *info, struct pci_dev *pdev1)
6272 unsigned long mmio_start, mmio_len;
6275 mmio_start = pci_resource_start(pdev1, 0);
6276 mmio_len = pci_resource_len(pdev1, 0);
6278 dev->desc = dev_desc[info->index].name;
6279 dev->name = info->bp_name;
6280 dev->device = info->device;
6281 dev->vendor = info->vendor;
6282 dev->subdevice = info->subdevice;
6283 dev->subvendor = info->subvendor;
6284 dev->func = PCI_FUNC(pdev1->devfn);
6285 dev->slot = PCI_SLOT(pdev1->devfn);
6286 dev->bus = pdev1->bus->number;
6287 dev->mem_map = (unsigned long)ioremap(mmio_start, mmio_len);
6289 spin_lock_init(&dev->bypass_wr_lock);
6291 if (BP10G9_IF_SERIES(dev->subdevice))
6293 if (BP10G_IF_SERIES(dev->subdevice))
6295 if (PEG540_IF_SERIES(dev->subdevice))
6297 if (PEGF5_IF_SERIES(dev->subdevice))
6299 if (PEG80_IF_SERIES(dev->subdevice))
6301 if (PEGF80_IF_SERIES(dev->subdevice))
6303 if ((dev->subdevice & 0xa00) == 0xa00)
6305 if (BP10GB_IF_SERIES(dev->subdevice)) {
6306 if (dev->ifindex == 0) {
6307 unregister_chrdev(major_num, DEVICE_NAME);
6308 printk("Please load network driver for %s adapter!\n",
6313 if (dev->ndev && !(dev->ndev->flags & IFF_UP)) {
6314 unregister_chrdev(major_num, DEVICE_NAME);
6315 printk("Please bring up network interfaces for %s adapter!\n",
6322 if (!dev->bp_10g9) {
6323 if (is_bypass_fn(dev)) {
6324 printk(KERN_INFO "%s found, ",
6328 dev->wdt_status = WDT_STATUS_UNKNOWN;
6329 dev->reset_time = 0;
6330 atomic_set(&dev->wdt_busy, 0);
6331 dev->bp_status_un = 1;
6333 bypass_caps_init(dev);
6335 init_bypass_wd_auto(dev);
6336 init_bypass_tpl_auto(dev);
6337 if (NOKIA_SERIES(dev->subdevice))
6341 dev->bp_tx_data = kzalloc(BPTEST_DATA_LEN, GFP_KERNEL);
6342 if (dev->bp_tx_data) {
6343 memset(dev->bp_tx_data, 0xff, 6);
6344 memset(dev->bp_tx_data + 6, 0x0, 1);
6345 memset(dev->bp_tx_data + 7, 0xaa, 5);
6346 *(__be16 *)(dev->bp_tx_data + 12) = htons(ETH_P_BPTEST);
6348 printk("bp_ctl: Memory allocation error!\n");
6354 * Initialize the module - Register the character device
6357 static int __init bypass_init_module(void)
6359 int ret_val, idx, idx_dev = 0;
6360 struct pci_dev *pdev1 = NULL;
6361 struct bpctl_dev *dev;
6363 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6364 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6366 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6369 major_num = ret_val; /* dynamic */
6370 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6371 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6372 tx_ctl_pci_tbl[idx].device,
6373 tx_ctl_pci_tbl[idx].subvendor,
6374 tx_ctl_pci_tbl[idx].subdevice,
6381 printk("No such device\n");
6382 unregister_chrdev(major_num, DEVICE_NAME);
6386 bpctl_dev_arr = kmalloc((device_num) * sizeof(struct bpctl_dev), GFP_KERNEL);
6388 if (!bpctl_dev_arr) {
6389 printk("Allocation error\n");
6390 unregister_chrdev(major_num, DEVICE_NAME);
6393 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(struct bpctl_dev)));
6396 dev = bpctl_dev_arr;
6397 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6398 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6399 tx_ctl_pci_tbl[idx].device,
6400 tx_ctl_pci_tbl[idx].subvendor,
6401 tx_ctl_pci_tbl[idx].subdevice,
6403 if (init_one(dev, &tx_ctl_pci_tbl[idx], pdev1) < 0)
6410 sema_init(&bpctl_sema, 1);
6411 spin_lock_init(&bpvm_lock);
6413 for (idx_dev = 0, dev = bpctl_dev_arr;
6414 idx_dev < device_num && dev->pdev;
6417 if (is_bypass_fn(dev)) {
6418 printk(KERN_INFO "%s found, ", dev->name);
6419 dev->bp_fw_ver = bypass_fw_ver(dev);
6420 printk("firmware version: 0x%x\n",
6423 dev->wdt_status = WDT_STATUS_UNKNOWN;
6424 dev->reset_time = 0;
6425 atomic_set(&dev->wdt_busy, 0);
6426 dev->bp_status_un = 1;
6428 bypass_caps_init(dev);
6430 init_bypass_wd_auto(dev);
6431 init_bypass_tpl_auto(dev);
6435 register_netdevice_notifier(&bp_notifier_block);
6440 * Cleanup - unregister the appropriate file from /proc
6442 static void __exit bypass_cleanup_module(void)
6446 unregister_netdevice_notifier(&bp_notifier_block);
6448 for (i = 0; i < device_num; i++) {
6449 /* unsigned long flags; */
6450 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6451 bpctl_dev_arr[i].reset_time = 0;
6453 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6456 /* unmap all devices */
6457 for (i = 0; i < device_num; i++) {
6459 kfree(bpctl_dev_arr[i].bp_tx_data);
6461 iounmap((void *)(bpctl_dev_arr[i].mem_map));
6464 /* free all devices space */
6465 kfree(bpctl_dev_arr);
6468 * Unregister the device
6470 unregister_chrdev(major_num, DEVICE_NAME);
6473 module_init(bypass_init_module);
6474 module_exit(bypass_cleanup_module);
6476 int is_bypass_sd(int ifindex)
6478 return is_bypass(get_dev_idx_p(ifindex));
6480 EXPORT_SYMBOL(is_bypass_sd);
6482 int set_bypass_sd(int ifindex, int bypass_mode)
6485 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
6487 EXPORT_SYMBOL(set_bypass_sd);
6489 int get_bypass_sd(int ifindex)
6492 return get_bypass_fn(get_dev_idx_p(ifindex));
6494 EXPORT_SYMBOL(get_bypass_sd);
6496 int get_bypass_change_sd(int ifindex)
6499 return get_bypass_change_fn(get_dev_idx_p(ifindex));
6501 EXPORT_SYMBOL(get_bypass_change_sd);
6503 int set_dis_bypass_sd(int ifindex, int dis_param)
6505 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
6507 EXPORT_SYMBOL(set_dis_bypass_sd);
6509 int get_dis_bypass_sd(int ifindex)
6512 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
6514 EXPORT_SYMBOL(get_dis_bypass_sd);
6516 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
6518 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
6521 EXPORT_SYMBOL(set_bypass_pwoff_sd);
6523 int get_bypass_pwoff_sd(int ifindex)
6525 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
6528 EXPORT_SYMBOL(get_bypass_pwoff_sd);
6530 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
6532 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
6535 EXPORT_SYMBOL(set_bypass_pwup_sd);
6537 int get_bypass_pwup_sd(int ifindex)
6539 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
6542 EXPORT_SYMBOL(get_bypass_pwup_sd);
6544 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
6546 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
6548 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
6551 EXPORT_SYMBOL(set_bypass_wd_sd);
6553 int get_bypass_wd_sd(int ifindex, int *timeout)
6555 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
6558 EXPORT_SYMBOL(get_bypass_wd_sd);
6560 int get_wd_expire_time_sd(int ifindex, int *time_left)
6562 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
6564 EXPORT_SYMBOL(get_wd_expire_time_sd);
6566 int reset_bypass_wd_timer_sd(int ifindex)
6568 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
6571 EXPORT_SYMBOL(reset_bypass_wd_timer_sd);
6573 int get_wd_set_caps_sd(int ifindex)
6575 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
6578 EXPORT_SYMBOL(get_wd_set_caps_sd);
6580 int set_std_nic_sd(int ifindex, int nic_mode)
6582 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
6585 EXPORT_SYMBOL(set_std_nic_sd);
6587 int get_std_nic_sd(int ifindex)
6589 return get_std_nic_fn(get_dev_idx_p(ifindex));
6592 EXPORT_SYMBOL(get_std_nic_sd);
6594 int set_tap_sd(int ifindex, int tap_mode)
6596 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
6599 EXPORT_SYMBOL(set_tap_sd);
6601 int get_tap_sd(int ifindex)
6603 return get_tap_fn(get_dev_idx_p(ifindex));
6606 EXPORT_SYMBOL(get_tap_sd);
6608 int set_tap_pwup_sd(int ifindex, int tap_mode)
6610 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
6613 EXPORT_SYMBOL(set_tap_pwup_sd);
6615 int get_tap_pwup_sd(int ifindex)
6617 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
6620 EXPORT_SYMBOL(get_tap_pwup_sd);
6622 int get_tap_change_sd(int ifindex)
6624 return get_tap_change_fn(get_dev_idx_p(ifindex));
6627 EXPORT_SYMBOL(get_tap_change_sd);
6629 int set_dis_tap_sd(int ifindex, int dis_param)
6631 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
6634 EXPORT_SYMBOL(set_dis_tap_sd);
6636 int get_dis_tap_sd(int ifindex)
6638 return get_dis_tap_fn(get_dev_idx_p(ifindex));
6641 EXPORT_SYMBOL(get_dis_tap_sd);
6643 int set_bp_disc_sd(int ifindex, int disc_mode)
6645 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
6648 EXPORT_SYMBOL(set_bp_disc_sd);
6650 int get_bp_disc_sd(int ifindex)
6652 return get_disc_fn(get_dev_idx_p(ifindex));
6655 EXPORT_SYMBOL(get_bp_disc_sd);
6657 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
6659 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
6662 EXPORT_SYMBOL(set_bp_disc_pwup_sd);
6664 int get_bp_disc_pwup_sd(int ifindex)
6666 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
6669 EXPORT_SYMBOL(get_bp_disc_pwup_sd);
6671 int get_bp_disc_change_sd(int ifindex)
6673 return get_disc_change_fn(get_dev_idx_p(ifindex));
6676 EXPORT_SYMBOL(get_bp_disc_change_sd);
6678 int set_bp_dis_disc_sd(int ifindex, int dis_param)
6680 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
6683 EXPORT_SYMBOL(set_bp_dis_disc_sd);
6685 int get_bp_dis_disc_sd(int ifindex)
6687 return get_dis_disc_fn(get_dev_idx_p(ifindex));
6690 EXPORT_SYMBOL(get_bp_dis_disc_sd);
6692 int get_wd_exp_mode_sd(int ifindex)
6694 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
6696 EXPORT_SYMBOL(get_wd_exp_mode_sd);
6698 int set_wd_exp_mode_sd(int ifindex, int param)
6700 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
6703 EXPORT_SYMBOL(set_wd_exp_mode_sd);
6705 int set_tx_sd(int ifindex, int tx_state)
6707 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
6710 EXPORT_SYMBOL(set_tx_sd);
6712 int set_tpl_sd(int ifindex, int tpl_state)
6714 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
6717 EXPORT_SYMBOL(set_tpl_sd);
6719 int set_bp_hw_reset_sd(int ifindex, int status)
6721 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
6724 EXPORT_SYMBOL(set_bp_hw_reset_sd);
6726 int set_wd_autoreset_sd(int ifindex, int param)
6728 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
6731 EXPORT_SYMBOL(set_wd_autoreset_sd);
6733 int get_wd_autoreset_sd(int ifindex)
6735 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
6738 EXPORT_SYMBOL(get_wd_autoreset_sd);
6740 int get_bypass_caps_sd(int ifindex)
6742 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
6744 EXPORT_SYMBOL(get_bypass_caps_sd);
6746 int get_bypass_slave_sd(int ifindex)
6748 struct bpctl_dev *pbpctl_dev_out;
6749 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
6752 return pbpctl_dev_out->ifindex;
6756 EXPORT_SYMBOL(get_bypass_slave_sd);
6758 int get_tx_sd(int ifindex)
6760 return get_tx_fn(get_dev_idx_p(ifindex));
6763 EXPORT_SYMBOL(get_tx_sd);
6765 int get_tpl_sd(int ifindex)
6767 return get_tpl_fn(get_dev_idx_p(ifindex));
6770 EXPORT_SYMBOL(get_tpl_sd);
6772 int get_bp_hw_reset_sd(int ifindex)
6774 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
6777 EXPORT_SYMBOL(get_bp_hw_reset_sd);
6779 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
6781 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
6783 EXPORT_SYMBOL(get_bypass_info_sd);
6785 int bp_if_scan_sd(void)
6790 EXPORT_SYMBOL(bp_if_scan_sd);
6792 #define BP_PROC_DIR "bypass"
6794 static struct proc_dir_entry *bp_procfs_dir;
6796 static int procfs_add(char *proc_name, const struct file_operations *fops,
6797 struct bpctl_dev *dev)
6799 struct bypass_pfs_sd *pfs = &dev->bypass_pfs_set;
6801 if (!proc_create_data(proc_name, 0644, pfs->bypass_entry, fops, dev))
6806 #define RO_FOPS(name) \
6807 static int name##_open(struct inode *inode, struct file *file) \
6809 return single_open(file, show_##name, PDE_DATA(inode));\
6811 static const struct file_operations name##_ops = { \
6812 .open = name##_open, \
6814 .llseek = seq_lseek, \
6815 .release = single_release, \
6818 #define RW_FOPS(name) \
6819 static int name##_open(struct inode *inode, struct file *file) \
6821 return single_open(file, show_##name, PDE_DATA(inode));\
6823 static const struct file_operations name##_ops = { \
6824 .open = name##_open, \
6826 .write = name##_write, \
6827 .llseek = seq_lseek, \
6828 .release = single_release, \
6831 static int show_bypass_info(struct seq_file *m, void *v)
6833 struct bpctl_dev *dev = m->private;
6835 seq_printf(m, "Name\t\t\t%s\n", dev->name);
6836 seq_printf(m, "Firmware version\t0x%x\n", dev->bp_fw_ver);
6839 RO_FOPS(bypass_info)
6841 static int show_bypass_slave(struct seq_file *m, void *v)
6843 struct bpctl_dev *dev = m->private;
6844 struct bpctl_dev *slave = get_status_port_fn(dev);
6849 seq_puts(m, "fail\n");
6850 else if (slave->ndev)
6851 seq_printf(m, "%s\n", slave->ndev->name);
6854 RO_FOPS(bypass_slave)
6856 static int show_bypass_caps(struct seq_file *m, void *v)
6858 struct bpctl_dev *dev = m->private;
6859 int ret = get_bypass_caps_fn(dev);
6861 if (ret == BP_NOT_CAP)
6862 seq_puts(m, "-1\n");
6864 seq_printf(m, "0x%x\n", ret);
6867 RO_FOPS(bypass_caps)
6869 static int show_wd_set_caps(struct seq_file *m, void *v)
6871 struct bpctl_dev *dev = m->private;
6872 int ret = get_wd_set_caps_fn(dev);
6874 if (ret == BP_NOT_CAP)
6875 seq_puts(m, "-1\n");
6877 seq_printf(m, "0x%x\n", ret);
6880 RO_FOPS(wd_set_caps)
6882 static int user_on_off(const void __user *buffer, size_t count)
6888 if (count > (sizeof(kbuf) - 1))
6891 if (copy_from_user(&kbuf, buffer, count))
6895 length = strlen(kbuf);
6896 if (kbuf[length - 1] == '\n')
6897 kbuf[--length] = '\0';
6899 if (strcmp(kbuf, "on") == 0)
6901 if (strcmp(kbuf, "off") == 0)
6906 static ssize_t bypass_write(struct file *file, const char __user *buffer,
6907 size_t count, loff_t *pos)
6909 int bypass_param = user_on_off(buffer, count);
6911 if (bypass_param < 0)
6914 set_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
6917 static int show_bypass(struct seq_file *m, void *v)
6919 struct bpctl_dev *dev = m->private;
6920 int ret = get_bypass_fn(dev);
6922 if (ret == BP_NOT_CAP)
6923 seq_puts(m, "fail\n");
6925 seq_puts(m, "on\n");
6927 seq_puts(m, "off\n");
6932 static ssize_t tap_write(struct file *file, const char __user *buffer,
6933 size_t count, loff_t *pos)
6935 int tap_param = user_on_off(buffer, count);
6940 set_tap_fn(PDE_DATA(file_inode(file)), tap_param);
6943 static int show_tap(struct seq_file *m, void *v)
6945 struct bpctl_dev *dev = m->private;
6946 int ret = get_tap_fn(dev);
6948 if (ret == BP_NOT_CAP)
6949 seq_puts(m, "fail\n");
6951 seq_puts(m, "on\n");
6953 seq_puts(m, "off\n");
6958 static ssize_t disc_write(struct file *file, const char __user *buffer,
6959 size_t count, loff_t *pos)
6961 int tap_param = user_on_off(buffer, count);
6966 set_disc_fn(PDE_DATA(file_inode(file)), tap_param);
6969 static int show_disc(struct seq_file *m, void *v)
6971 struct bpctl_dev *dev = m->private;
6972 int ret = get_disc_fn(dev);
6974 if (ret == BP_NOT_CAP)
6975 seq_puts(m, "fail\n");
6977 seq_puts(m, "on\n");
6979 seq_puts(m, "off\n");
6984 static int show_bypass_change(struct seq_file *m, void *v)
6986 struct bpctl_dev *dev = m->private;
6987 int ret = get_bypass_change_fn(dev);
6990 seq_puts(m, "on\n");
6992 seq_puts(m, "off\n");
6994 seq_puts(m, "fail\n");
6997 RO_FOPS(bypass_change)
6999 static int show_tap_change(struct seq_file *m, void *v)
7001 struct bpctl_dev *dev = m->private;
7002 int ret = get_tap_change_fn(dev);
7005 seq_puts(m, "on\n");
7007 seq_puts(m, "off\n");
7009 seq_puts(m, "fail\n");
7014 static int show_disc_change(struct seq_file *m, void *v)
7016 struct bpctl_dev *dev = m->private;
7017 int ret = get_disc_change_fn(dev);
7020 seq_puts(m, "on\n");
7022 seq_puts(m, "off\n");
7024 seq_puts(m, "fail\n");
7027 RO_FOPS(disc_change)
7029 static ssize_t bypass_wd_write(struct file *file, const char __user *buffer,
7030 size_t count, loff_t *pos)
7032 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7034 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7038 set_bypass_wd_fn(dev, timeout);
7041 static int show_bypass_wd(struct seq_file *m, void *v)
7043 struct bpctl_dev *dev = m->private;
7044 int ret = 0, timeout = 0;
7046 ret = get_bypass_wd_fn(dev, &timeout);
7047 if (ret == BP_NOT_CAP)
7048 seq_puts(m, "fail\n");
7049 else if (timeout == -1)
7050 seq_puts(m, "unknown\n");
7051 else if (timeout == 0)
7052 seq_puts(m, "disable\n");
7054 seq_printf(m, "%d\n", timeout);
7059 static int show_wd_expire_time(struct seq_file *m, void *v)
7061 struct bpctl_dev *dev = m->private;
7062 int ret = 0, timeout = 0;
7064 ret = get_wd_expire_time_fn(dev, &timeout);
7065 if (ret == BP_NOT_CAP)
7066 seq_puts(m, "fail\n");
7067 else if (timeout == -1)
7068 seq_puts(m, "expire\n");
7069 else if (timeout == 0)
7070 seq_puts(m, "disable\n");
7072 seq_printf(m, "%d\n", timeout);
7075 RO_FOPS(wd_expire_time)
7077 static ssize_t tpl_write(struct file *file, const char __user *buffer,
7078 size_t count, loff_t *pos)
7080 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7081 int tpl_param = user_on_off(buffer, count);
7086 set_tpl_fn(dev, tpl_param);
7089 static int show_tpl(struct seq_file *m, void *v)
7091 struct bpctl_dev *dev = m->private;
7092 int ret = get_tpl_fn(dev);
7094 if (ret == BP_NOT_CAP)
7095 seq_puts(m, "fail\n");
7097 seq_puts(m, "on\n");
7099 seq_puts(m, "off\n");
7105 static ssize_t wait_at_pwup_write(struct file *file, const char __user *buffer,
7106 size_t count, loff_t *pos)
7108 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7109 int tpl_param = user_on_off(buffer, count);
7114 set_bp_wait_at_pwup_fn(dev, tpl_param);
7117 static int show_wait_at_pwup(struct seq_file *m, void *v)
7119 struct bpctl_dev *dev = m->private;
7120 int ret = get_bp_wait_at_pwup_fn(dev);
7122 if (ret == BP_NOT_CAP)
7123 seq_puts(m, "fail\n");
7125 seq_puts(m, "on\n");
7127 seq_puts(m, "off\n");
7130 RW_FOPS(wait_at_pwup)
7132 static ssize_t hw_reset_write(struct file *file, const char __user *buffer,
7133 size_t count, loff_t *pos)
7135 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7136 int tpl_param = user_on_off(buffer, count);
7141 set_bp_hw_reset_fn(dev, tpl_param);
7144 static int show_hw_reset(struct seq_file *m, void *v)
7146 struct bpctl_dev *dev = m->private;
7147 int ret = get_bp_hw_reset_fn(dev);
7149 if (ret == BP_NOT_CAP)
7150 seq_puts(m, "fail\n");
7152 seq_puts(m, "on\n");
7154 seq_puts(m, "off\n");
7159 #endif /*PMC_WAIT_FLAG */
7161 static int show_reset_bypass_wd(struct seq_file *m, void *v)
7163 struct bpctl_dev *dev = m->private;
7164 int ret = reset_bypass_wd_timer_fn(dev);
7166 if (ret == BP_NOT_CAP)
7167 seq_puts(m, "fail\n");
7169 seq_puts(m, "disable\n");
7171 seq_puts(m, "success\n");
7174 RO_FOPS(reset_bypass_wd)
7176 static ssize_t dis_bypass_write(struct file *file, const char __user *buffer,
7177 size_t count, loff_t *pos)
7179 int bypass_param = user_on_off(buffer, count);
7181 if (bypass_param < 0)
7184 set_dis_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7187 static int show_dis_bypass(struct seq_file *m, void *v)
7189 struct bpctl_dev *dev = m->private;
7190 int ret = get_dis_bypass_fn(dev);
7192 if (ret == BP_NOT_CAP)
7193 seq_puts(m, "fail\n");
7195 seq_puts(m, "off\n");
7197 seq_puts(m, "on\n");
7202 static ssize_t dis_tap_write(struct file *file, const char __user *buffer,
7203 size_t count, loff_t *pos)
7205 int tap_param = user_on_off(buffer, count);
7210 set_dis_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7213 static int show_dis_tap(struct seq_file *m, void *v)
7215 struct bpctl_dev *dev = m->private;
7216 int ret = get_dis_tap_fn(dev);
7218 if (ret == BP_NOT_CAP)
7219 seq_puts(m, "fail\n");
7221 seq_puts(m, "off\n");
7223 seq_puts(m, "on\n");
7228 static ssize_t dis_disc_write(struct file *file, const char __user *buffer,
7229 size_t count, loff_t *pos)
7231 int tap_param = user_on_off(buffer, count);
7236 set_dis_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7239 static int show_dis_disc(struct seq_file *m, void *v)
7241 struct bpctl_dev *dev = m->private;
7242 int ret = get_dis_disc_fn(dev);
7244 if (ret == BP_NOT_CAP)
7245 seq_puts(m, "fail\n");
7247 seq_puts(m, "off\n");
7249 seq_puts(m, "on\n");
7254 static ssize_t bypass_pwup_write(struct file *file, const char __user *buffer,
7255 size_t count, loff_t *pos)
7257 int bypass_param = user_on_off(buffer, count);
7259 if (bypass_param < 0)
7262 set_bypass_pwup_fn(PDE_DATA(file_inode(file)), bypass_param);
7265 static int show_bypass_pwup(struct seq_file *m, void *v)
7267 struct bpctl_dev *dev = m->private;
7268 int ret = get_bypass_pwup_fn(dev);
7270 if (ret == BP_NOT_CAP)
7271 seq_puts(m, "fail\n");
7273 seq_puts(m, "off\n");
7275 seq_puts(m, "on\n");
7278 RW_FOPS(bypass_pwup)
7280 static ssize_t bypass_pwoff_write(struct file *file, const char __user *buffer,
7281 size_t count, loff_t *pos)
7283 int bypass_param = user_on_off(buffer, count);
7285 if (bypass_param < 0)
7288 set_bypass_pwoff_fn(PDE_DATA(file_inode(file)), bypass_param);
7291 static int show_bypass_pwoff(struct seq_file *m, void *v)
7293 struct bpctl_dev *dev = m->private;
7294 int ret = get_bypass_pwoff_fn(dev);
7296 if (ret == BP_NOT_CAP)
7297 seq_puts(m, "fail\n");
7299 seq_puts(m, "off\n");
7301 seq_puts(m, "on\n");
7304 RW_FOPS(bypass_pwoff)
7306 static ssize_t tap_pwup_write(struct file *file, const char __user *buffer,
7307 size_t count, loff_t *pos)
7309 int tap_param = user_on_off(buffer, count);
7314 set_tap_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7317 static int show_tap_pwup(struct seq_file *m, void *v)
7319 struct bpctl_dev *dev = m->private;
7320 int ret = get_tap_pwup_fn(dev);
7322 if (ret == BP_NOT_CAP)
7323 seq_puts(m, "fail\n");
7325 seq_puts(m, "off\n");
7327 seq_puts(m, "on\n");
7332 static ssize_t disc_pwup_write(struct file *file, const char __user *buffer,
7333 size_t count, loff_t *pos)
7335 int tap_param = user_on_off(buffer, count);
7340 set_disc_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7343 static int show_disc_pwup(struct seq_file *m, void *v)
7345 struct bpctl_dev *dev = m->private;
7346 int ret = get_disc_pwup_fn(dev);
7348 if (ret == BP_NOT_CAP)
7349 seq_puts(m, "fail\n");
7351 seq_puts(m, "off\n");
7353 seq_puts(m, "on\n");
7358 static ssize_t std_nic_write(struct file *file, const char __user *buffer,
7359 size_t count, loff_t *pos)
7361 int bypass_param = user_on_off(buffer, count);
7363 if (bypass_param < 0)
7366 set_std_nic_fn(PDE_DATA(file_inode(file)), bypass_param);
7369 static int show_std_nic(struct seq_file *m, void *v)
7371 struct bpctl_dev *dev = m->private;
7372 int ret = get_std_nic_fn(dev);
7374 if (ret == BP_NOT_CAP)
7375 seq_puts(m, "fail\n");
7377 seq_puts(m, "off\n");
7379 seq_puts(m, "on\n");
7384 static ssize_t wd_exp_mode_write(struct file *file, const char __user *buffer,
7385 size_t count, loff_t *pos)
7388 int bypass_param = 0, length = 0;
7390 if (count > (sizeof(kbuf) - 1))
7393 if (copy_from_user(&kbuf, buffer, count))
7397 length = strlen(kbuf);
7398 if (kbuf[length - 1] == '\n')
7399 kbuf[--length] = '\0';
7401 if (strcmp(kbuf, "tap") == 0)
7403 else if (strcmp(kbuf, "bypass") == 0)
7405 else if (strcmp(kbuf, "disc") == 0)
7408 set_wd_exp_mode_fn(PDE_DATA(file_inode(file)), bypass_param);
7412 static int show_wd_exp_mode(struct seq_file *m, void *v)
7414 struct bpctl_dev *dev = m->private;
7415 int ret = get_wd_exp_mode_fn(dev);
7418 seq_puts(m, "tap\n");
7420 seq_puts(m, "bypass\n");
7422 seq_puts(m, "disc\n");
7424 seq_puts(m, "fail\n");
7427 RW_FOPS(wd_exp_mode)
7429 static ssize_t wd_autoreset_write(struct file *file, const char __user *buffer,
7430 size_t count, loff_t *pos)
7433 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7437 set_wd_autoreset_fn(PDE_DATA(file_inode(file)), timeout);
7440 static int show_wd_autoreset(struct seq_file *m, void *v)
7442 struct bpctl_dev *dev = m->private;
7443 int ret = get_wd_autoreset_fn(dev);
7446 seq_printf(m, "%d\n", ret);
7448 seq_puts(m, "fail\n");
7451 RW_FOPS(wd_autoreset)
7453 static int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block)
7455 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
7456 static struct proc_dir_entry *procfs_dir;
7459 if (!pbp_device_block->ndev)
7461 sprintf(current_pfs->dir_name, "bypass_%s",
7462 pbp_device_block->ndev->name);
7467 /* create device proc dir */
7468 procfs_dir = proc_mkdir(current_pfs->dir_name, bp_procfs_dir);
7470 printk(KERN_DEBUG "Could not create procfs directory %s\n",
7471 current_pfs->dir_name);
7474 current_pfs->bypass_entry = procfs_dir;
7476 #define ENTRY(x) (ret |= procfs_add(#x, &x##_ops, pbp_device_block))
7479 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
7480 /* Create set param proc's */
7481 ENTRY(bypass_slave);
7485 ENTRY(wd_expire_time);
7486 ENTRY(reset_bypass_wd);
7488 if (pbp_device_block->bp_caps & BP_CAP) {
7492 ENTRY(bypass_pwoff);
7493 ENTRY(bypass_change);
7495 if (pbp_device_block->bp_caps & TAP_CAP) {
7501 if (pbp_device_block->bp_caps & DISC_CAP) {
7509 ENTRY(wd_autoreset);
7512 ENTRY(wait_at_pwup);
7518 printk(KERN_DEBUG "Create proc entry failed\n");
7523 static int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block)
7525 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
7527 remove_proc_subtree(current_pfs->dir_name, bp_procfs_dir);
7528 current_pfs->bypass_entry = NULL;