1 #ifndef DDK750_DISPLAY_H__
2 #define DDK750_DISPLAY_H__
10 #define PNL_2_MASK (3 << PNL_2_OFFSET)
11 #define PNL_2_USAGE (PNL_2_MASK << 16)
12 #define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE)
13 #define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE)
17 * primary timing & plane enable bit
18 * 1: 80000[8] & 80000[2] on
21 #define PRI_TP_OFFSET 4
22 #define PRI_TP_MASK BIT(PRI_TP_OFFSET)
23 #define PRI_TP_USAGE (PRI_TP_MASK << 16)
24 #define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE)
25 #define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)
29 * panel sequency status
32 #define PNL_SEQ_OFFSET 6
33 #define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
34 #define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
35 #define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
36 #define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
42 #define DUAL_TFT_OFFSET 8
43 #define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
44 #define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
45 #define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
46 #define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
49 * secondary timing & plane enable bit
50 * 1:80200[8] & 80200[2] on
53 #define SEC_TP_OFFSET 5
54 #define SEC_TP_MASK BIT(SEC_TP_OFFSET)
55 #define SEC_TP_USAGE (SEC_TP_MASK << 16)
56 #define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
57 #define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
63 #define CRT_2_OFFSET 2
64 #define CRT_2_MASK (3 << CRT_2_OFFSET)
65 #define CRT_2_USAGE (CRT_2_MASK << 16)
66 #define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE)
67 #define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)
71 * DAC affect both DVI and DSUB
75 #define DAC_MASK BIT(DAC_OFFSET)
76 #define DAC_USAGE (DAC_MASK << 16)
77 #define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
78 #define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
81 * DPMS only affect D-SUB head
85 #define DPMS_MASK (3 << DPMS_OFFSET)
86 #define DPMS_USAGE (DPMS_MASK << 16)
87 #define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE)
88 #define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE)
93 * LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
94 * CRT means crt path DSUB
96 typedef enum _disp_output_t {
97 do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON,
98 do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
99 do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
100 do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
102 * do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
103 * do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON,
105 do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
106 do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON,
110 void ddk750_setLogicalDispOut(disp_output_t);