2 * Silicon Motion SM712 frame buffer device
4 * Copyright (C) 2006 Silicon Motion Technology Corp.
5 * Authors: Ge Wang, gewang@siliconmotion.com
6 * Boyod boyod.yang@siliconmotion.com.cn
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive for
16 #define NR_PALETTE 256
18 #define FB_ACCEL_SMI_LYNX 88
20 #define SCREEN_X_RES 1024
21 #define SCREEN_Y_RES 600
24 /*Assume SM712 graphics chip has 4MB VRAM */
25 #define SM712_VIDEOMEMORYSIZE 0x00400000
26 /*Assume SM722 graphics chip has 8MB VRAM */
27 #define SM722_VIDEOMEMORYSIZE 0x00800000
29 #define dac_reg (0x3c8)
30 #define dac_val (0x3c9)
32 extern void __iomem *smtc_regbaseaddress;
33 #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
34 #define smtc_mmioww(dat, reg) writew(dat, smtc_regbaseaddress + reg)
35 #define smtc_mmiowl(dat, reg) writel(dat, smtc_regbaseaddress + reg)
37 #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
38 #define smtc_mmiorw(reg) readw(smtc_regbaseaddress + reg)
39 #define smtc_mmiorl(reg) readl(smtc_regbaseaddress + reg)
41 #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
42 #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
43 #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
44 #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
45 #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
46 #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
47 #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
48 #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
49 #define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
50 #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
51 #define SIZE_VPR (0x6C + 1)
52 #define SIZE_DPR (0x44 + 1)
54 static inline void smtc_crtcw(int reg, int val)
56 smtc_mmiowb(reg, 0x3d4);
57 smtc_mmiowb(val, 0x3d5);
60 static inline unsigned int smtc_crtcr(int reg)
62 smtc_mmiowb(reg, 0x3d4);
63 return smtc_mmiorb(0x3d5);
66 static inline void smtc_grphw(int reg, int val)
68 smtc_mmiowb(reg, 0x3ce);
69 smtc_mmiowb(val, 0x3cf);
72 static inline unsigned int smtc_grphr(int reg)
74 smtc_mmiowb(reg, 0x3ce);
75 return smtc_mmiorb(0x3cf);
78 static inline void smtc_attrw(int reg, int val)
81 smtc_mmiowb(reg, 0x3c0);
83 smtc_mmiowb(val, 0x3c0);
86 static inline void smtc_seqw(int reg, int val)
88 smtc_mmiowb(reg, 0x3c4);
89 smtc_mmiowb(val, 0x3c5);
92 static inline unsigned int smtc_seqr(int reg)
94 smtc_mmiowb(reg, 0x3c4);
95 return smtc_mmiorb(0x3c5);
98 /* The next structure holds all information relevant for a specific video mode.
106 unsigned char init_misc;
107 unsigned char init_sr00_sr04[SIZE_SR00_SR04];
108 unsigned char init_sr10_sr24[SIZE_SR10_SR24];
109 unsigned char init_sr30_sr75[SIZE_SR30_SR75];
110 unsigned char init_sr80_sr93[SIZE_SR80_SR93];
111 unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
112 unsigned char init_gr00_gr08[SIZE_GR00_GR08];
113 unsigned char init_ar00_ar14[SIZE_AR00_AR14];
114 unsigned char init_cr00_cr18[SIZE_CR00_CR18];
115 unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
116 unsigned char init_cr90_cra7[SIZE_CR90_CRA7];