4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
6 * IO dispatcher for a shared memory channel driver.
7 * Also, includes macros to simulate shm via port io calls.
9 * Copyright (C) 2005-2006 Texas Instruments, Inc.
11 * This package is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
17 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 #include <dspbridge/_chnl_sm.h>
24 #include <dspbridge/host_os.h>
26 #include <dspbridge/iodefs.h>
31 #define IO_MAXSERVICE IO_SERVICE
33 #define DSP_FIELD_ADDR(type, field, base, wordsize) \
34 ((((s32)&(((type *)0)->field)) / wordsize) + (u32)base)
36 /* Access can be different SM access word size (e.g. 16/32 bit words) */
37 #define IO_SET_VALUE(pContext, type, base, field, value) (base->field = value)
38 #define IO_GET_VALUE(pContext, type, base, field) (base->field)
39 #define IO_OR_VALUE(pContext, type, base, field, value) (base->field |= value)
40 #define IO_AND_VALUE(pContext, type, base, field, value) (base->field &= value)
41 #define IO_SET_LONG(pContext, type, base, field, value) (base->field = value)
42 #define IO_GET_LONG(pContext, type, base, field) (base->field)
44 #ifdef CONFIG_TIDSPBRIDGE_DVFS
45 /* The maximum number of OPPs that are supported */
46 extern s32 dsp_max_opps;
47 /* The Vdd1 opp table information */
48 extern u32 vdd1_dsp_freq[6][4];
52 * ======== io_cancel_chnl ========
54 * Cancel IO on a given channel.
56 * hio_mgr: IO Manager.
57 * ulChnl: Index of channel to cancel IO on.
63 extern void io_cancel_chnl(struct io_mgr *hio_mgr, u32 ulChnl);
66 * ======== io_dpc ========
68 * Deferred procedure call for shared memory channel driver ISR. Carries
69 * out the dispatch of I/O.
71 * pRefData: Pointer to reference data registered via a call to
76 * Must not acquire resources.
77 * All data touched must be locked in memory if running in kernel mode.
79 * Non-preemptible (but interruptible).
81 extern void io_dpc(IN OUT unsigned long pRefData);
84 * ======== io_mbox_msg ========
86 * Main interrupt handler for the shared memory Bridge channel manager.
87 * Calls the Bridge's chnlsm_isr to determine if this interrupt is ours,
88 * then schedules a DPC to dispatch I/O.
90 * pRefData: Pointer to the channel manager object for this board.
91 * Set in an initial call to ISR_Install().
93 * TRUE if interrupt handled; FALSE otherwise.
95 * Must be in locked memory if executing in kernel mode.
96 * Must only call functions which are in locked memory if Kernel mode.
97 * Must only call asynchronous services.
98 * Interrupts are disabled and EOI for this interrupt has been sent.
101 void io_mbox_msg(u32 msg);
104 * ======== io_request_chnl ========
106 * Request I/O from the DSP. Sets flags in shared memory, then interrupts
109 * hio_mgr: IO manager handle.
110 * pchnl: Ptr to the channel requesting I/O.
111 * iMode: Mode of channel: {IO_INPUT | IO_OUTPUT}.
117 extern void io_request_chnl(struct io_mgr *hio_mgr,
118 struct chnl_object *pchnl,
119 u8 iMode, OUT u16 *pwMbVal);
122 * ======== iosm_schedule ========
124 * Schedule DPC for IO.
126 * pio_mgr: Ptr to a I/O manager.
132 extern void iosm_schedule(struct io_mgr *hio_mgr);
135 * DSP-DMA IO functions
139 * ======== io_ddma_init_chnl_desc ========
141 * Initialize DSP DMA channel descriptor.
143 * hio_mgr: Handle to a I/O manager.
144 * uDDMAChnlId: DDMA channel identifier.
145 * uNumDesc: Number of buffer descriptors(equals # of IOReqs &
150 * uDDMAChnlId < DDMA_MAXDDMACHNLS
157 extern void io_ddma_init_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId,
158 u32 uNumDesc, void *pDsp);
161 * ======== io_ddma_clear_chnl_desc ========
163 * Clear DSP DMA channel descriptor.
165 * hio_mgr: Handle to a I/O manager.
166 * uDDMAChnlId: DDMA channel identifier.
169 * uDDMAChnlId < DDMA_MAXDDMACHNLS
172 extern void io_ddma_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uDDMAChnlId);
175 * ======== io_ddma_request_chnl ========
177 * Request channel DSP-DMA from the DSP. Sets up SM descriptors and
178 * control fields in shared memory.
180 * hio_mgr: Handle to a I/O manager.
181 * pchnl: Ptr to channel object
182 * chnl_packet_obj: Ptr to channel i/o request packet.
186 * pchnl->cio_reqs > 0
187 * chnl_packet_obj != NULL
190 extern void io_ddma_request_chnl(struct io_mgr *hio_mgr,
191 struct chnl_object *pchnl,
192 struct chnl_irp *chnl_packet_obj,
196 * Zero-copy IO functions
200 * ======== io_ddzc_init_chnl_desc ========
202 * Initialize ZCPY channel descriptor.
204 * hio_mgr: Handle to a I/O manager.
205 * uZId: zero-copy channel identifier.
208 * uDDMAChnlId < DDMA_MAXZCPYCHNLS
212 extern void io_ddzc_init_chnl_desc(struct io_mgr *hio_mgr, u32 uZId);
215 * ======== io_ddzc_clear_chnl_desc ========
217 * Clear DSP ZC channel descriptor.
219 * hio_mgr: Handle to a I/O manager.
220 * uChnlId: ZC channel identifier.
224 * uChnlId < DDMA_MAXZCPYCHNLS
227 extern void io_ddzc_clear_chnl_desc(struct io_mgr *hio_mgr, u32 uChnlId);
230 * ======== io_ddzc_request_chnl ========
232 * Request zero-copy channel transfer. Sets up SM descriptors and
233 * control fields in shared memory.
235 * hio_mgr: Handle to a I/O manager.
236 * pchnl: Ptr to channel object
237 * chnl_packet_obj: Ptr to channel i/o request packet.
241 * pchnl->cio_reqs > 0
242 * chnl_packet_obj != NULL
245 extern void io_ddzc_request_chnl(struct io_mgr *hio_mgr,
246 struct chnl_object *pchnl,
247 struct chnl_irp *chnl_packet_obj,
251 * ======== io_sh_msetting ========
253 * Sets the shared memory setting
255 * hio_mgr: Handle to a I/O manager.
256 * desc: Shared memory type
257 * pargs: Ptr to shm setting
264 extern int io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs);
267 * Misc functions for the CHNL_IO shared memory library:
270 /* Maximum channel bufsize that can be used. */
271 extern u32 io_buf_size(struct io_mgr *hio_mgr);
273 extern u32 io_read_value(struct bridge_dev_context *hDevContext, u32 dwDSPAddr);
275 extern void io_write_value(struct bridge_dev_context *hDevContext,
276 u32 dwDSPAddr, u32 dwValue);
278 extern u32 io_read_value_long(struct bridge_dev_context *hDevContext,
281 extern void io_write_value_long(struct bridge_dev_context *hDevContext,
282 u32 dwDSPAddr, u32 dwValue);
284 extern void io_or_set_value(struct bridge_dev_context *hDevContext,
285 u32 dwDSPAddr, u32 dwValue);
287 extern void io_and_set_value(struct bridge_dev_context *hDevContext,
288 u32 dwDSPAddr, u32 dwValue);
290 extern void io_intr_dsp2(IN struct io_mgr *pio_mgr, IN u16 mb_val);
292 extern void io_sm_init(void);
295 * ========print_dsp_trace_buffer ========
296 * Print DSP tracebuffer.
298 extern int print_dsp_trace_buffer(struct bridge_dev_context
301 int dump_dsp_stack(struct bridge_dev_context *bridge_context);
303 void dump_dl_modules(struct bridge_dev_context *bridge_context);
305 #ifdef CONFIG_TIDSPBRIDGE_DEBUG
306 void print_dsp_debug_trace(struct io_mgr *hio_mgr);