drivers/staging/vt6655/rf.c

   1 /*
   2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *
  20  * File: rf.c
  21  *
  22  * Purpose: rf function code
  23  *
  24  * Author: Jerry Chen
  25  *
  26  * Date: Feb. 19, 2004
  27  *
  28  * Functions:
  29  *      IFRFbWriteEmbedded      - Embedded write RF register via MAC
  30  *
  31  * Revision History:
  32  *
  33  */
  34
  35 #include "mac.h"
  36 #include "srom.h"
  37 #include "rf.h"
  38 #include "baseband.h"
  39
  40 /*---------------------  Static Definitions -------------------------*/
  41
  42 //static int          msglevel                =MSG_LEVEL_INFO;
  43
  44 #define BY_AL2230_REG_LEN     23 //24bit
  45 #define CB_AL2230_INIT_SEQ    15
  46 #define SWITCH_CHANNEL_DELAY_AL2230 200 //us
  47 #define AL2230_PWR_IDX_LEN    64
  48
  49 #define BY_AL7230_REG_LEN     23 //24bit
  50 #define CB_AL7230_INIT_SEQ    16
  51 #define SWITCH_CHANNEL_DELAY_AL7230 200 //us
  52 #define AL7230_PWR_IDX_LEN    64
  53
  54 /*---------------------  Static Classes  ----------------------------*/
  55
  56 /*---------------------  Static Variables  --------------------------*/
  57
  58 const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
  59         0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  60         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  61         0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  62         0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  63         0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  64         0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  65         0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  66         0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  67         0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  68         0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  69         0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  70         0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
  71         0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
  72         0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
  73         0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
  74 };
  75
  76 const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
  77         0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
  78         0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
  79         0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
  80         0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
  81         0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
  82         0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
  83         0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
  84         0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
  85         0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
  86         0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
  87         0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
  88         0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
  89         0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
  90         0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW  // channel = 14, Tf = 2412M
  91 };
  92
  93 const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = {
  94         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
  95         0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
  96         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
  97         0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
  98         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
  99         0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
 100         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
 101         0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
 102         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
 103         0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
 104         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
 105         0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
 106         0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
 107         0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW  // channel = 14, Tf = 2412M
 108 };
 109
 110 unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
 111         0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 112         0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 113         0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 114         0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 115         0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 116         0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 117         0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 118         0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 119         0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 120         0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 121         0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 122         0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 123         0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 124         0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 125         0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 126         0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 127         0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 128         0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 129         0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 130         0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 131         0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 132         0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 133         0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 134         0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 135         0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 136         0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 137         0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 138         0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 139         0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 140         0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 141         0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 142         0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 143         0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 144         0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 145         0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 146         0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 147         0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 148         0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 149         0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 150         0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 151         0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 152         0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 153         0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 154         0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 155         0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 156         0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 157         0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 158         0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 159         0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 160         0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 161         0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 162         0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 163         0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 164         0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 165         0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 166         0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 167         0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 168         0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 169         0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 170         0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 171         0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 172         0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 173         0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 174         0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
 175 };
 176
 177 //{{ RobertYu:20050104
 178 // 40MHz reference frequency
 179 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
 180 const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = {
 181         0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
 182         0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
 183         0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2
 184         0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3
 185         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g    // Need modify for 11a
 186         //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
 187         // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
 188         0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55
 189         0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 190         0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207
 191         0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 192         0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 193         0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A
 194         0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
 195         //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
 196         // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
 197         0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
 198         0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 199         0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 200         0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW  // Need modify for 11a: 12BACF
 201 };
 202
 203 const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = {
 204         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
 205         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
 206         0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
 207         0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
 208         0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a    // Need modify for 11b/g
 209         0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113
 210         0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 211         0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
 212         0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 213         0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 214         0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
 215         0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
 216         0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
 217         0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 218         0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
 219         0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW  // Need modify for 11b/g
 220 };
 221
 222 const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = {
 223         0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  1, Tf = 2412MHz
 224         0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  2, Tf = 2417MHz
 225         0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  3, Tf = 2422MHz
 226         0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  4, Tf = 2427MHz
 227         0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  5, Tf = 2432MHz
 228         0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  6, Tf = 2437MHz
 229         0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  7, Tf = 2442MHz
 230         0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
 231         0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
 232         0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
 233         0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
 234         0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
 235         0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
 236         0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
 237
 238         // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 239         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
 240         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
 241         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
 242         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
 243         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
 244         0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
 245         0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
 246         0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
 247
 248         // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 249         // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 250
 251         0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   7, Tf = 5035MHz (23)
 252         0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   8, Tf = 5040MHz (24)
 253         0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   9, Tf = 5045MHz (25)
 254         0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  11, Tf = 5055MHz (26)
 255         0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  12, Tf = 5060MHz (27)
 256         0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  16, Tf = 5080MHz (28)
 257         0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  34, Tf = 5170MHz (29)
 258         0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  36, Tf = 5180MHz (30)
 259         0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
 260         0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  40, Tf = 5200MHz (32)
 261         0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  42, Tf = 5210MHz (33)
 262         0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  44, Tf = 5220MHz (34)
 263         0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  46, Tf = 5230MHz (35)
 264         0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  48, Tf = 5240MHz (36)
 265         0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  52, Tf = 5260MHz (37)
 266         0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  56, Tf = 5280MHz (38)
 267         0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  60, Tf = 5300MHz (39)
 268         0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  64, Tf = 5320MHz (40)
 269
 270         0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
 271         0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
 272         0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
 273         0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
 274         0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
 275         0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
 276         0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
 277         0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
 278         0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
 279         0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
 280         0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
 281         0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
 282         0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
 283         0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
 284         0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
 285         0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW  // channel = 165, Tf = 5825MHz (56)
 286 };
 287
 288 const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = {
 289         0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  1, Tf = 2412MHz
 290         0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  2, Tf = 2417MHz
 291         0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  3, Tf = 2422MHz
 292         0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  4, Tf = 2427MHz
 293         0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  5, Tf = 2432MHz
 294         0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  6, Tf = 2437MHz
 295         0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  7, Tf = 2442MHz
 296         0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  8, Tf = 2447MHz
 297         0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  9, Tf = 2452MHz
 298         0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
 299         0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
 300         0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
 301         0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
 302         0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
 303
 304         // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 305         0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
 306         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
 307         0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
 308         0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
 309         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
 310         0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
 311         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
 312         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
 313
 314         // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 315         // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 316         0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   7, Tf = 5035MHz (23)
 317         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   8, Tf = 5040MHz (24)
 318         0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   9, Tf = 5045MHz (25)
 319         0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  11, Tf = 5055MHz (26)
 320         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  12, Tf = 5060MHz (27)
 321         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  16, Tf = 5080MHz (28)
 322         0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  34, Tf = 5170MHz (29)
 323         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  36, Tf = 5180MHz (30)
 324         0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  38, Tf = 5190MHz (31)
 325         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  40, Tf = 5200MHz (32)
 326         0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  42, Tf = 5210MHz (33)
 327         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  44, Tf = 5220MHz (34)
 328         0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  46, Tf = 5230MHz (35)
 329         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  48, Tf = 5240MHz (36)
 330         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  52, Tf = 5260MHz (37)
 331         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  56, Tf = 5280MHz (38)
 332         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  60, Tf = 5300MHz (39)
 333         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  64, Tf = 5320MHz (40)
 334         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
 335         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
 336         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
 337         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
 338         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
 339         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
 340         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
 341         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
 342         0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
 343         0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
 344         0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
 345         0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
 346         0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
 347         0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
 348         0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
 349         0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW  // channel = 165, Tf = 5825MHz (56)
 350 };
 351
 352 const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = {
 353         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  1, Tf = 2412MHz
 354         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  2, Tf = 2417MHz
 355         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  3, Tf = 2422MHz
 356         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  4, Tf = 2427MHz
 357         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  5, Tf = 2432MHz
 358         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  6, Tf = 2437MHz
 359         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  7, Tf = 2442MHz
 360         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  8, Tf = 2447MHz
 361         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  9, Tf = 2452MHz
 362         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
 363         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
 364         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
 365         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
 366         0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
 367
 368         // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 369         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
 370         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
 371         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
 372         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
 373         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
 374         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
 375         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
 376         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
 377
 378         // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 379         // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 380         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   7, Tf = 5035MHz (23)
 381         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   8, Tf = 5040MHz (24)
 382         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =   9, Tf = 5045MHz (25)
 383         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  11, Tf = 5055MHz (26)
 384         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  12, Tf = 5060MHz (27)
 385         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  16, Tf = 5080MHz (28)
 386         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  34, Tf = 5170MHz (29)
 387         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  36, Tf = 5180MHz (30)
 388         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  38, Tf = 5190MHz (31)
 389         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  40, Tf = 5200MHz (32)
 390         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  42, Tf = 5210MHz (33)
 391         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  44, Tf = 5220MHz (34)
 392         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  46, Tf = 5230MHz (35)
 393         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  48, Tf = 5240MHz (36)
 394         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  52, Tf = 5260MHz (37)
 395         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  56, Tf = 5280MHz (38)
 396         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  60, Tf = 5300MHz (39)
 397         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel =  64, Tf = 5320MHz (40)
 398         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
 399         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
 400         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
 401         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
 402         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
 403         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
 404         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
 405         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
 406         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
 407         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
 408         0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
 409         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
 410         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
 411         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
 412         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
 413         0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW  // channel = 165, Tf = 5825MHz (56)
 414 };
 415 //}} RobertYu
 416
 417 /*---------------------  Static Functions  --------------------------*/
 418
 419 /*
 420  * Description: AIROHA IFRF chip init function
 421  *
 422  * Parameters:
 423  *  In:
 424  *      dwIoBase    - I/O base address
 425  *  Out:
 426  *      none
 427  *
 428  * Return Value: true if succeeded; false if failed.
 429  *
 430  */
 431 bool s_bAL7230Init(unsigned long dwIoBase)
 432 {
 433         int     ii;
 434         bool bResult;
 435
 436         bResult = true;
 437
 438         //3-wire control for normal mode
 439         VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
 440
 441         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |
 442                                                          SOFTPWRCTL_TXPEINV));
 443         BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration
 444
 445         for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
 446                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[ii]);
 447
 448         // PLL On
 449         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 450
 451         //Calibration
 452         MACvTimer0MicroSDelay(dwIoBase, 150);//150us
 453         bResult &= IFRFbWriteEmbedded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:disable
 454         MACvTimer0MicroSDelay(dwIoBase, 30);//30us
 455         bResult &= IFRFbWriteEmbedded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:disable, RCK:active
 456         MACvTimer0MicroSDelay(dwIoBase, 30);//30us
 457         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:disable, RCK:disable
 458
 459         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |
 460                                                          SOFTPWRCTL_SWPE2    |
 461                                                          SOFTPWRCTL_SWPECTI  |
 462                                                          SOFTPWRCTL_TXPEINV));
 463
 464         BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106
 465
 466         // PE1: TX_ON, PE2: RX_ON, PE3: PLLON
 467         //3-wire control for power saving mode
 468         VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
 469
 470         return bResult;
 471 }
 472
 473 // Need to Pull PLLON low when writing channel registers through 3-wire interface
 474 bool s_bAL7230SelectChannel(unsigned long dwIoBase, unsigned char byChannel)
 475 {
 476         bool bResult;
 477
 478         bResult = true;
 479
 480         // PLLON Off
 481         MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 482
 483         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable0[byChannel - 1]); //Reg0
 484         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable1[byChannel - 1]); //Reg1
 485         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230ChannelTable2[byChannel - 1]); //Reg4
 486
 487         // PLLOn On
 488         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 489
 490         // Set Channel[7] = 0 to tell H/W channel is changing now.
 491         VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
 492         MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230);
 493         // Set Channel[7] = 1 to tell H/W channel change is done.
 494         VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
 495
 496         return bResult;
 497 }
 498
 499 /*
 500  * Description: Select channel with UW2452 chip
 501  *
 502  * Parameters:
 503  *  In:
 504  *      dwIoBase    - I/O base address
 505  *      uChannel    - Channel number
 506  *  Out:
 507  *      none
 508  *
 509  * Return Value: true if succeeded; false if failed.
 510  *
 511  */
 512
 513 //{{ RobertYu: 20041210
 514 /*
 515  * Description: UW2452 IFRF chip init function
 516  *
 517  * Parameters:
 518  *  In:
 519  *      dwIoBase    - I/O base address
 520  *  Out:
 521  *      none
 522  *
 523  * Return Value: true if succeeded; false if failed.
 524  *
 525  */
 526
 527 //}} RobertYu
 528 ////////////////////////////////////////////////////////////////////////////////
 529
 530 /*
 531  * Description: VT3226 IFRF chip init function
 532  *
 533  * Parameters:
 534  *  In:
 535  *      dwIoBase    - I/O base address
 536  *  Out:
 537  *      none
 538  *
 539  * Return Value: true if succeeded; false if failed.
 540  *
 541  */
 542
 543 /*
 544  * Description: Select channel with VT3226 chip
 545  *
 546  * Parameters:
 547  *  In:
 548  *      dwIoBase    - I/O base address
 549  *      uChannel    - Channel number
 550  *  Out:
 551  *      none
 552  *
 553  * Return Value: true if succeeded; false if failed.
 554  *
 555  */
 556
 557 /*---------------------  Export Variables  --------------------------*/
 558
 559 /*---------------------  Export Functions  --------------------------*/
 560
 561 /*
 562  * Description: Write to IF/RF, by embedded programming
 563  *
 564  * Parameters:
 565  *  In:
 566  *      dwIoBase    - I/O base address
 567  *      dwData      - data to write
 568  *  Out:
 569  *      none
 570  *
 571  * Return Value: true if succeeded; false if failed.
 572  *
 573  */
 574 bool IFRFbWriteEmbedded(unsigned long dwIoBase, unsigned long dwData)
 575 {
 576         unsigned short ww;
 577         unsigned long dwValue;
 578
 579         VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);
 580
 581         // W_MAX_TIMEOUT is the timeout period
 582         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 583                 VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);
 584                 if (dwValue & IFREGCTL_DONE)
 585                         break;
 586         }
 587
 588         if (ww == W_MAX_TIMEOUT) {
 589 //        DBG_PORT80_ALWAYS(0x32);
 590                 return false;
 591         }
 592         return true;
 593 }
 594
 595 /*
 596  * Description: RFMD RF2959 IFRF chip init function
 597  *
 598  * Parameters:
 599  *  In:
 600  *      dwIoBase    - I/O base address
 601  *  Out:
 602  *      none
 603  *
 604  * Return Value: true if succeeded; false if failed.
 605  *
 606  */
 607
 608 /*
 609  * Description: Select channel with RFMD 2959 chip
 610  *
 611  * Parameters:
 612  *  In:
 613  *      dwIoBase    - I/O base address
 614  *      uChannel    - Channel number
 615  *  Out:
 616  *      none
 617  *
 618  * Return Value: true if succeeded; false if failed.
 619  *
 620  */
 621
 622 /*
 623  * Description: AIROHA IFRF chip init function
 624  *
 625  * Parameters:
 626  *  In:
 627  *      dwIoBase    - I/O base address
 628  *  Out:
 629  *      none
 630  *
 631  * Return Value: true if succeeded; false if failed.
 632  *
 633  */
 634 bool RFbAL2230Init(unsigned long dwIoBase)
 635 {
 636         int     ii;
 637         bool bResult;
 638
 639         bResult = true;
 640
 641         //3-wire control for normal mode
 642         VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
 643
 644         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |
 645                                                          SOFTPWRCTL_TXPEINV));
 646 //2008-8-21 chester <add>
 647         // PLL  Off
 648
 649         MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 650
 651         //patch abnormal AL2230 frequency output
 652 //2008-8-21 chester <add>
 653         IFRFbWriteEmbedded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
 654
 655         for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
 656                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[ii]);
 657 //2008-8-21 chester <add>
 658         MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us
 659
 660         // PLL On
 661         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 662
 663         MACvTimer0MicroSDelay(dwIoBase, 150);//150us
 664         bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
 665         MACvTimer0MicroSDelay(dwIoBase, 30);//30us
 666         bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
 667         MACvTimer0MicroSDelay(dwIoBase, 30);//30us
 668         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
 669
 670         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |
 671                                                          SOFTPWRCTL_SWPE2    |
 672                                                          SOFTPWRCTL_SWPECTI  |
 673                                                          SOFTPWRCTL_TXPEINV));
 674
 675         //3-wire control for power saving mode
 676         VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
 677
 678         return bResult;
 679 }
 680
 681 bool RFbAL2230SelectChannel(unsigned long dwIoBase, unsigned char byChannel)
 682 {
 683         bool bResult;
 684
 685         bResult = true;
 686
 687         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230ChannelTable0[byChannel - 1]);
 688         bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230ChannelTable1[byChannel - 1]);
 689
 690         // Set Channel[7] = 0 to tell H/W channel is changing now.
 691         VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
 692         MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230);
 693         // Set Channel[7] = 1 to tell H/W channel change is done.
 694         VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
 695
 696         return bResult;
 697 }
 698
 699 /*
 700  * Description: UW2451 IFRF chip init function
 701  *
 702  * Parameters:
 703  *  In:
 704  *      dwIoBase    - I/O base address
 705  *  Out:
 706  *      none
 707  *
 708  * Return Value: true if succeeded; false if failed.
 709  *
 710  */
 711
 712 /*
 713  * Description: Select channel with UW2451 chip
 714  *
 715  * Parameters:
 716  *  In:
 717  *      dwIoBase    - I/O base address
 718  *      uChannel    - Channel number
 719  *  Out:
 720  *      none
 721  *
 722  * Return Value: true if succeeded; false if failed.
 723  *
 724  */
 725
 726 /*
 727  * Description: Set sleep mode to UW2451 chip
 728  *
 729  * Parameters:
 730  *  In:
 731  *      dwIoBase    - I/O base address
 732  *      uChannel    - Channel number
 733  *  Out:
 734  *      none
 735  *
 736  * Return Value: true if succeeded; false if failed.
 737  *
 738  */
 739
 740 /*
 741  * Description: RF init function
 742  *
 743  * Parameters:
 744  *  In:
 745  *      byBBType
 746  *      byRFType
 747  *  Out:
 748  *      none
 749  *
 750  * Return Value: true if succeeded; false if failed.
 751  *
 752  */
 753 bool RFbInit(
 754         PSDevice  pDevice
 755 )
 756 {
 757         bool bResult = true;
 758         switch (pDevice->byRFType) {
 759         case RF_AIROHA:
 760         case RF_AL2230S:
 761                 pDevice->byMaxPwrLevel = AL2230_PWR_IDX_LEN;
 762                 bResult = RFbAL2230Init(pDevice->PortOffset);
 763                 break;
 764         case RF_AIROHA7230:
 765                 pDevice->byMaxPwrLevel = AL7230_PWR_IDX_LEN;
 766                 bResult = s_bAL7230Init(pDevice->PortOffset);
 767                 break;
 768         case RF_NOTHING:
 769                 bResult = true;
 770                 break;
 771         default:
 772                 bResult = false;
 773                 break;
 774         }
 775         return bResult;
 776 }
 777
 778 /*
 779  * Description: RF ShutDown function
 780  *
 781  * Parameters:
 782  *  In:
 783  *      byBBType
 784  *      byRFType
 785  *  Out:
 786  *      none
 787  *
 788  * Return Value: true if succeeded; false if failed.
 789  *
 790  */
 791 bool RFbShutDown(
 792         PSDevice  pDevice
 793 )
 794 {
 795         bool bResult = true;
 796
 797         switch (pDevice->byRFType) {
 798         case RF_AIROHA7230:
 799                 bResult = IFRFbWriteEmbedded(pDevice->PortOffset, 0x1ABAEF00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW);
 800                 break;
 801         default:
 802                 bResult = true;
 803                 break;
 804         }
 805         return bResult;
 806 }
 807
 808 /*
 809  * Description: Select channel
 810  *
 811  * Parameters:
 812  *  In:
 813  *      byRFType
 814  *      byChannel    - Channel number
 815  *  Out:
 816  *      none
 817  *
 818  * Return Value: true if succeeded; false if failed.
 819  *
 820  */
 821 bool RFbSelectChannel(unsigned long dwIoBase, unsigned char byRFType, unsigned char byChannel)
 822 {
 823         bool bResult = true;
 824         switch (byRFType) {
 825         case RF_AIROHA:
 826         case RF_AL2230S:
 827                 bResult = RFbAL2230SelectChannel(dwIoBase, byChannel);
 828                 break;
 829                 //{{ RobertYu: 20050104
 830         case RF_AIROHA7230:
 831                 bResult = s_bAL7230SelectChannel(dwIoBase, byChannel);
 832                 break;
 833                 //}} RobertYu
 834         case RF_NOTHING:
 835                 bResult = true;
 836                 break;
 837         default:
 838                 bResult = false;
 839                 break;
 840         }
 841         return bResult;
 842 }
 843
 844 /*
 845  * Description: Write WakeProgSyn
 846  *
 847  * Parameters:
 848  *  In:
 849  *      dwIoBase    - I/O base address
 850  *      uChannel    - channel number
 851  *      bySleepCnt  - SleepProgSyn count
 852  *
 853  * Return Value: None.
 854  *
 855  */
 856 bool RFvWriteWakeProgSyn(unsigned long dwIoBase, unsigned char byRFType, unsigned int uChannel)
 857 {
 858         int   ii;
 859         unsigned char byInitCount = 0;
 860         unsigned char bySleepCount = 0;
 861
 862         VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0);
 863         switch (byRFType) {
 864         case RF_AIROHA:
 865         case RF_AL2230S:
 866
 867                 if (uChannel > CB_MAX_CHANNEL_24G)
 868                         return false;
 869
 870                 byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2)
 871                 bySleepCount = 0;
 872                 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
 873                         return false;
 874                 }
 875
 876                 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) {
 877                         MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
 878                 }
 879                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
 880                 ii++;
 881                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
 882                 break;
 883
 884                 //{{ RobertYu: 20050104
 885                 // Need to check, PLLON need to be low for channel setting
 886         case RF_AIROHA7230:
 887                 byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3)
 888                 bySleepCount = 0;
 889                 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
 890                         return false;
 891                 }
 892
 893                 if (uChannel <= CB_MAX_CHANNEL_24G) {
 894                         for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) {
 895                                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
 896                         }
 897                 } else {
 898                         for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) {
 899                                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
 900                         }
 901                 }
 902
 903                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
 904                 ii++;
 905                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
 906                 ii++;
 907                 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
 908                 break;
 909                 //}} RobertYu
 910
 911         case RF_NOTHING:
 912                 return true;
 913                 break;
 914
 915         default:
 916                 return false;
 917                 break;
 918         }
 919
 920         MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount));
 921
 922         return true;
 923 }
 924
 925 /*
 926  * Description: Set Tx power
 927  *
 928  * Parameters:
 929  *  In:
 930  *      dwIoBase       - I/O base address
 931  *      dwRFPowerTable - RF Tx Power Setting
 932  *  Out:
 933  *      none
 934  *
 935  * Return Value: true if succeeded; false if failed.
 936  *
 937  */
 938 bool RFbSetPower(
 939         PSDevice  pDevice,
 940         unsigned int uRATE,
 941         unsigned int uCH
 942 )
 943 {
 944         bool bResult = true;
 945         unsigned char byPwr = 0;
 946         unsigned char byDec = 0;
 947         unsigned char byPwrdBm = 0;
 948
 949         if (pDevice->dwDiagRefCount != 0) {
 950                 return true;
 951         }
 952         if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) {
 953                 return false;
 954         }
 955
 956         switch (uRATE) {
 957         case RATE_1M:
 958         case RATE_2M:
 959         case RATE_5M:
 960         case RATE_11M:
 961                 byPwr = pDevice->abyCCKPwrTbl[uCH];
 962                 byPwrdBm = pDevice->abyCCKDefaultPwr[uCH];
 963 //PLICE_DEBUG->
 964                 //byPwr+=5;
 965 //PLICE_DEBUG <-
 966                 break;
 967         case RATE_6M:
 968         case RATE_9M:
 969         case RATE_18M:
 970                 byPwr = pDevice->abyOFDMPwrTbl[uCH];
 971                 if (pDevice->byRFType == RF_UW2452) {
 972                         byDec = byPwr + 14;
 973                 } else {
 974                         byDec = byPwr + 10;
 975                 }
 976                 if (byDec >= pDevice->byMaxPwrLevel) {
 977                         byDec = pDevice->byMaxPwrLevel-1;
 978                 }
 979                 if (pDevice->byRFType == RF_UW2452) {
 980                         byPwrdBm = byDec - byPwr;
 981                         byPwrdBm /= 3;
 982                 } else {
 983                         byPwrdBm = byDec - byPwr;
 984                         byPwrdBm >>= 1;
 985                 }
 986                 byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH];
 987                 byPwr = byDec;
 988 //PLICE_DEBUG->
 989                 //byPwr+=5;
 990 //PLICE_DEBUG<-
 991                 break;
 992         case RATE_24M:
 993         case RATE_36M:
 994         case RATE_48M:
 995         case RATE_54M:
 996                 byPwr = pDevice->abyOFDMPwrTbl[uCH];
 997                 byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH];
 998 //PLICE_DEBUG->
 999                 //byPwr+=5;
1000 //PLICE_DEBUG<-
1001                 break;
1002         }
1003
1004         if (pDevice->byCurPwr == byPwr) {
1005                 return true;
1006         }
1007
1008         bResult = RFbRawSetPower(pDevice, byPwr, uRATE);
1009         if (bResult == true) {
1010                 pDevice->byCurPwr = byPwr;
1011         }
1012         return bResult;
1013 }
1014
1015 /*
1016  * Description: Set Tx power
1017  *
1018  * Parameters:
1019  *  In:
1020  *      dwIoBase       - I/O base address
1021  *      dwRFPowerTable - RF Tx Power Setting
1022  *  Out:
1023  *      none
1024  *
1025  * Return Value: true if succeeded; false if failed.
1026  *
1027  */
1028
1029 bool RFbRawSetPower(
1030         PSDevice  pDevice,
1031         unsigned char byPwr,
1032         unsigned int uRATE
1033 )
1034 {
1035         bool bResult = true;
1036         unsigned long dwMax7230Pwr = 0;
1037
1038         if (byPwr >=  pDevice->byMaxPwrLevel) {
1039                 return false;
1040         }
1041         switch (pDevice->byRFType) {
1042         case RF_AIROHA:
1043                 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1044                 if (uRATE <= RATE_11M) {
1045                         bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1046                 } else {
1047                         bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1048                 }
1049                 break;
1050
1051         case RF_AL2230S:
1052                 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1053                 if (uRATE <= RATE_11M) {
1054                         bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1055                         bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1056                 } else {
1057                         bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1058                         bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1059                 }
1060
1061                 break;
1062
1063         case RF_AIROHA7230:
1064                 //  0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
1065                 dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) |
1066                         (BY_AL7230_REG_LEN << 3)  | IFREGCTL_REGW;
1067
1068                 bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwMax7230Pwr);
1069                 break;
1070
1071         default:
1072                 break;
1073         }
1074         return bResult;
1075 }
1076
1077 /*+
1078  *
1079  * Routine Description:
1080  *     Translate RSSI to dBm
1081  *
1082  * Parameters:
1083  *  In:
1084  *      pDevice         - The adapter to be translated
1085  *      byCurrRSSI      - RSSI to be translated
1086  *  Out:
1087  *      pdwdbm          - Translated dbm number
1088  *
1089  * Return Value: none
1090  *
1091  -*/
1092 void
1093 RFvRSSITodBm(
1094         PSDevice pDevice,
1095         unsigned char byCurrRSSI,
1096         long *pldBm
1097         )
1098 {
1099         unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
1100         long b = (byCurrRSSI & 0x3F);
1101         long a = 0;
1102         unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
1103
1104         switch (pDevice->byRFType) {
1105         case RF_AIROHA:
1106         case RF_AL2230S:
1107         case RF_AIROHA7230: //RobertYu: 20040104
1108                 a = abyAIROHARF[byIdx];
1109                 break;
1110         default:
1111                 break;
1112         }
1113
1114         *pldBm = -1 * (a + b * 2);
1115 }
1116
1117 ////////////////////////////////////////////////////////////////////////////////
1118 //{{ RobertYu: 20050104
1119
1120 // Post processing for the 11b/g and 11a.
1121 // for save time on changing Reg2,3,5,7,10,12,15
1122 bool RFbAL7230SelectChannelPostProcess(unsigned long dwIoBase, unsigned char byOldChannel, unsigned char byNewChannel)
1123 {
1124         bool bResult;
1125
1126         bResult = true;
1127
1128         // if change between 11 b/g and 11a need to update the following register
1129         // Channel Index 1~14
1130
1131         if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) {
1132                 // Change from 2.4G to 5G
1133                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2
1134                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3
1135                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5
1136                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7
1137                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10
1138                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12
1139                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15
1140         } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) {
1141                 // change from 5G to 2.4G
1142                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[2]); //Reg2
1143                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[3]); //Reg3
1144                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[5]); //Reg5
1145                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[7]); //Reg7
1146                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[10]);//Reg10
1147                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[12]);//Reg12
1148                 bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[15]);//Reg15
1149         }
1150
1151         return bResult;
1152 }
1153
1154 //}} RobertYu
1155 ////////////////////////////////////////////////////////////////////////////////