drivers/staging/wilc1000/wilc_spi.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_spi.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9
  10 #include <linux/string.h>
  11 #include "wilc_wlan_if.h"
  12 #include "wilc_wlan.h"
  13 #include "linux_wlan_spi.h"
  14 #include "wilc_wfi_netdevice.h"
  15
  16 typedef struct {
  17         wilc_debug_func dPrint;
  18         int crc_off;
  19         int nint;
  20         int has_thrpt_enh;
  21 } wilc_spi_t;
  22
  23 static wilc_spi_t g_spi;
  24
  25 static int wilc_spi_read(u32, u8 *, u32);
  26 static int wilc_spi_write(u32, u8 *, u32);
  27
  28 /********************************************
  29  *
  30  *      Crc7
  31  *
  32  ********************************************/
  33
  34 static const u8 crc7_syndrome_table[256] = {
  35         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  36         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  37         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  38         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  39         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  40         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  41         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  42         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  43         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  44         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  45         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  46         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  47         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  48         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  49         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  50         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  51         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  52         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  53         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  54         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  55         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  56         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  57         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  58         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  59         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  60         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  61         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  62         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  63         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  64         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  65         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  66         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  67 };
  68
  69 static u8 crc7_byte(u8 crc, u8 data)
  70 {
  71         return crc7_syndrome_table[(crc << 1) ^ data];
  72 }
  73
  74 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  75 {
  76         while (len--)
  77                 crc = crc7_byte(crc, *buffer++);
  78         return crc;
  79 }
  80
  81 /********************************************
  82  *
  83  *      Spi protocol Function
  84  *
  85  ********************************************/
  86
  87 #define CMD_DMA_WRITE                           0xc1
  88 #define CMD_DMA_READ                            0xc2
  89 #define CMD_INTERNAL_WRITE              0xc3
  90 #define CMD_INTERNAL_READ               0xc4
  91 #define CMD_TERMINATE                           0xc5
  92 #define CMD_REPEAT                                      0xc6
  93 #define CMD_DMA_EXT_WRITE               0xc7
  94 #define CMD_DMA_EXT_READ                0xc8
  95 #define CMD_SINGLE_WRITE                        0xc9
  96 #define CMD_SINGLE_READ                 0xca
  97 #define CMD_RESET                                               0xcf
  98
  99 #define N_OK                                                            1
 100 #define N_FAIL                                                          0
 101 #define N_RESET                                                 -1
 102 #define N_RETRY                                                 -2
 103
 104 #define DATA_PKT_SZ_256                         256
 105 #define DATA_PKT_SZ_512                 512
 106 #define DATA_PKT_SZ_1K                          1024
 107 #define DATA_PKT_SZ_4K                          (4 * 1024)
 108 #define DATA_PKT_SZ_8K                          (8 * 1024)
 109 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 110
 111 static int spi_cmd(u8 cmd, u32 adr, u32 data, u32 sz, u8 clockless)
 112 {
 113         u8 bc[9];
 114         int len = 5;
 115         int result = N_OK;
 116
 117         bc[0] = cmd;
 118         switch (cmd) {
 119         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 120                 bc[1] = (u8)(adr >> 16);
 121                 bc[2] = (u8)(adr >> 8);
 122                 bc[3] = (u8)adr;
 123                 len = 5;
 124                 break;
 125
 126         case CMD_INTERNAL_READ:                 /* internal register read */
 127                 bc[1] = (u8)(adr >> 8);
 128                 if (clockless)
 129                         bc[1] |= BIT(7);
 130                 bc[2] = (u8)adr;
 131                 bc[3] = 0x00;
 132                 len = 5;
 133                 break;
 134
 135         case CMD_TERMINATE:                                     /* termination */
 136                 bc[1] = 0x00;
 137                 bc[2] = 0x00;
 138                 bc[3] = 0x00;
 139                 len = 5;
 140                 break;
 141
 142         case CMD_REPEAT:                                                /* repeat */
 143                 bc[1] = 0x00;
 144                 bc[2] = 0x00;
 145                 bc[3] = 0x00;
 146                 len = 5;
 147                 break;
 148
 149         case CMD_RESET:                                                 /* reset */
 150                 bc[1] = 0xff;
 151                 bc[2] = 0xff;
 152                 bc[3] = 0xff;
 153                 len = 5;
 154                 break;
 155
 156         case CMD_DMA_WRITE:                                     /* dma write */
 157         case CMD_DMA_READ:                                      /* dma read */
 158                 bc[1] = (u8)(adr >> 16);
 159                 bc[2] = (u8)(adr >> 8);
 160                 bc[3] = (u8)adr;
 161                 bc[4] = (u8)(sz >> 8);
 162                 bc[5] = (u8)(sz);
 163                 len = 7;
 164                 break;
 165
 166         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 167         case CMD_DMA_EXT_READ:                  /* dma extended read */
 168                 bc[1] = (u8)(adr >> 16);
 169                 bc[2] = (u8)(adr >> 8);
 170                 bc[3] = (u8)adr;
 171                 bc[4] = (u8)(sz >> 16);
 172                 bc[5] = (u8)(sz >> 8);
 173                 bc[6] = (u8)(sz);
 174                 len = 8;
 175                 break;
 176
 177         case CMD_INTERNAL_WRITE:                /* internal register write */
 178                 bc[1] = (u8)(adr >> 8);
 179                 if (clockless)
 180                         bc[1] |= BIT(7);
 181                 bc[2] = (u8)(adr);
 182                 bc[3] = (u8)(data >> 24);
 183                 bc[4] = (u8)(data >> 16);
 184                 bc[5] = (u8)(data >> 8);
 185                 bc[6] = (u8)(data);
 186                 len = 8;
 187                 break;
 188
 189         case CMD_SINGLE_WRITE:                  /* single word write */
 190                 bc[1] = (u8)(adr >> 16);
 191                 bc[2] = (u8)(adr >> 8);
 192                 bc[3] = (u8)(adr);
 193                 bc[4] = (u8)(data >> 24);
 194                 bc[5] = (u8)(data >> 16);
 195                 bc[6] = (u8)(data >> 8);
 196                 bc[7] = (u8)(data);
 197                 len = 9;
 198                 break;
 199
 200         default:
 201                 result = N_FAIL;
 202                 break;
 203         }
 204
 205         if (result) {
 206                 if (!g_spi.crc_off)
 207                         bc[len - 1] = (crc7(0x7f, (const u8 *)&bc[0], len - 1)) << 1;
 208                 else
 209                         len -= 1;
 210
 211                 if (!linux_spi_write(bc, len)) {
 212                         PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
 213                         result = N_FAIL;
 214                 }
 215         }
 216
 217         return result;
 218 }
 219
 220 static int spi_cmd_rsp(u8 cmd)
 221 {
 222         u8 rsp;
 223         int result = N_OK;
 224
 225         /**
 226          *      Command/Control response
 227          **/
 228         if ((cmd == CMD_RESET) ||
 229             (cmd == CMD_TERMINATE) ||
 230             (cmd == CMD_REPEAT)) {
 231                 if (!linux_spi_read(&rsp, 1)) {
 232                         result = N_FAIL;
 233                         goto _fail_;
 234                 }
 235         }
 236
 237         if (!linux_spi_read(&rsp, 1)) {
 238                 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
 239                 result = N_FAIL;
 240                 goto _fail_;
 241         }
 242
 243         if (rsp != cmd) {
 244                 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
 245                 result = N_FAIL;
 246                 goto _fail_;
 247         }
 248
 249         /**
 250          *      State response
 251          **/
 252         if (!linux_spi_read(&rsp, 1)) {
 253                 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
 254                 result = N_FAIL;
 255                 goto _fail_;
 256         }
 257
 258         if (rsp != 0x00) {
 259                 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp);
 260                 result = N_FAIL;
 261         }
 262
 263 _fail_:
 264
 265         return result;
 266 }
 267
 268 static int spi_cmd_complete(u8 cmd, u32 adr, u8 *b, u32 sz, u8 clockless)
 269 {
 270         u8 wb[32], rb[32];
 271         u8 wix, rix;
 272         u32 len2;
 273         u8 rsp;
 274         int len = 0;
 275         int result = N_OK;
 276
 277         wb[0] = cmd;
 278         switch (cmd) {
 279         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 280                 wb[1] = (u8)(adr >> 16);
 281                 wb[2] = (u8)(adr >> 8);
 282                 wb[3] = (u8)adr;
 283                 len = 5;
 284                 break;
 285
 286         case CMD_INTERNAL_READ:                 /* internal register read */
 287                 wb[1] = (u8)(adr >> 8);
 288                 if (clockless == 1)
 289                         wb[1] |= BIT(7);
 290                 wb[2] = (u8)adr;
 291                 wb[3] = 0x00;
 292                 len = 5;
 293                 break;
 294
 295         case CMD_TERMINATE:                                     /* termination */
 296                 wb[1] = 0x00;
 297                 wb[2] = 0x00;
 298                 wb[3] = 0x00;
 299                 len = 5;
 300                 break;
 301
 302         case CMD_REPEAT:                                                /* repeat */
 303                 wb[1] = 0x00;
 304                 wb[2] = 0x00;
 305                 wb[3] = 0x00;
 306                 len = 5;
 307                 break;
 308
 309         case CMD_RESET:                                                 /* reset */
 310                 wb[1] = 0xff;
 311                 wb[2] = 0xff;
 312                 wb[3] = 0xff;
 313                 len = 5;
 314                 break;
 315
 316         case CMD_DMA_WRITE:                                     /* dma write */
 317         case CMD_DMA_READ:                                      /* dma read */
 318                 wb[1] = (u8)(adr >> 16);
 319                 wb[2] = (u8)(adr >> 8);
 320                 wb[3] = (u8)adr;
 321                 wb[4] = (u8)(sz >> 8);
 322                 wb[5] = (u8)(sz);
 323                 len = 7;
 324                 break;
 325
 326         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 327         case CMD_DMA_EXT_READ:                  /* dma extended read */
 328                 wb[1] = (u8)(adr >> 16);
 329                 wb[2] = (u8)(adr >> 8);
 330                 wb[3] = (u8)adr;
 331                 wb[4] = (u8)(sz >> 16);
 332                 wb[5] = (u8)(sz >> 8);
 333                 wb[6] = (u8)(sz);
 334                 len = 8;
 335                 break;
 336
 337         case CMD_INTERNAL_WRITE:                /* internal register write */
 338                 wb[1] = (u8)(adr >> 8);
 339                 if (clockless == 1)
 340                         wb[1] |= BIT(7);
 341                 wb[2] = (u8)(adr);
 342                 wb[3] = b[3];
 343                 wb[4] = b[2];
 344                 wb[5] = b[1];
 345                 wb[6] = b[0];
 346                 len = 8;
 347                 break;
 348
 349         case CMD_SINGLE_WRITE:                  /* single word write */
 350                 wb[1] = (u8)(adr >> 16);
 351                 wb[2] = (u8)(adr >> 8);
 352                 wb[3] = (u8)(adr);
 353                 wb[4] = b[3];
 354                 wb[5] = b[2];
 355                 wb[6] = b[1];
 356                 wb[7] = b[0];
 357                 len = 9;
 358                 break;
 359
 360         default:
 361                 result = N_FAIL;
 362                 break;
 363         }
 364
 365         if (result != N_OK) {
 366                 return result;
 367         }
 368
 369         if (!g_spi.crc_off)
 370                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 371         else
 372                 len -= 1;
 373
 374 #define NUM_SKIP_BYTES (1)
 375 #define NUM_RSP_BYTES (2)
 376 #define NUM_DATA_HDR_BYTES (1)
 377 #define NUM_DATA_BYTES (4)
 378 #define NUM_CRC_BYTES (2)
 379 #define NUM_DUMMY_BYTES (3)
 380         if ((cmd == CMD_RESET) ||
 381             (cmd == CMD_TERMINATE) ||
 382             (cmd == CMD_REPEAT)) {
 383                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 384         } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 385                 if (!g_spi.crc_off) {
 386                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 387                                       + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
 388                 } else {
 389                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 390                                       + NUM_DUMMY_BYTES);
 391                 }
 392         } else {
 393                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 394         }
 395 #undef NUM_DUMMY_BYTES
 396
 397         if (len2 > ARRAY_SIZE(wb)) {
 398                 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%zu)\n",
 399                          len2, ARRAY_SIZE(wb));
 400                 result = N_FAIL;
 401                 return result;
 402         }
 403         /* zero spi write buffers. */
 404         for (wix = len; wix < len2; wix++) {
 405                 wb[wix] = 0;
 406         }
 407         rix = len;
 408
 409         if (!linux_spi_write_read(wb, rb, len2)) {
 410                 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
 411                 result = N_FAIL;
 412                 return result;
 413         }
 414
 415         /**
 416          * Command/Control response
 417          **/
 418         if ((cmd == CMD_RESET) ||
 419             (cmd == CMD_TERMINATE) ||
 420             (cmd == CMD_REPEAT)) {
 421                 rix++;         /* skip 1 byte */
 422         }
 423
 424         /* do { */
 425         rsp = rb[rix++];
 426         /*      if(rsp == cmd) break; */
 427         /* } while(&rptr[1] <= &rb[len2]); */
 428
 429         if (rsp != cmd) {
 430                 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
 431                          ", resp (%02x)\n", cmd, rsp);
 432                 result = N_FAIL;
 433                 return result;
 434         }
 435
 436         /**
 437          * State response
 438          **/
 439         rsp = rb[rix++];
 440         if (rsp != 0x00) {
 441                 PRINT_ER("[wilc spi]: Failed cmd state response "
 442                          "state (%02x)\n", rsp);
 443                 result = N_FAIL;
 444                 return result;
 445         }
 446
 447         if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
 448             || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 449                 int retry;
 450                 /* u16 crc1, crc2; */
 451                 u8 crc[2];
 452                 /**
 453                  * Data Respnose header
 454                  **/
 455                 retry = 100;
 456                 do {
 457                         /* ensure there is room in buffer later to read data and crc */
 458                         if (rix < len2) {
 459                                 rsp = rb[rix++];
 460                         } else {
 461                                 retry = 0;
 462                                 break;
 463                         }
 464                         if (((rsp >> 4) & 0xf) == 0xf)
 465                                 break;
 466                 } while (retry--);
 467
 468                 if (retry <= 0) {
 469                         PRINT_ER("[wilc spi]: Error, data read "
 470                                  "response (%02x)\n", rsp);
 471                         result = N_RESET;
 472                         return result;
 473                 }
 474
 475                 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 476                         /**
 477                          * Read bytes
 478                          **/
 479                         if ((rix + 3) < len2) {
 480                                 b[0] = rb[rix++];
 481                                 b[1] = rb[rix++];
 482                                 b[2] = rb[rix++];
 483                                 b[3] = rb[rix++];
 484                         } else {
 485                                 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
 486                                 result = N_FAIL;
 487                                 return result;
 488                         }
 489
 490                         if (!g_spi.crc_off) {
 491                                 /**
 492                                  * Read Crc
 493                                  **/
 494                                 if ((rix + 1) < len2) {
 495                                         crc[0] = rb[rix++];
 496                                         crc[1] = rb[rix++];
 497                                 } else {
 498                                         PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
 499                                         result = N_FAIL;
 500                                         return result;
 501                                 }
 502                         }
 503                 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 504                         int ix;
 505
 506                         /* some data may be read in response to dummy bytes. */
 507                         for (ix = 0; (rix < len2) && (ix < sz); ) {
 508                                 b[ix++] = rb[rix++];
 509                         }
 510
 511                         sz -= ix;
 512
 513                         if (sz > 0) {
 514                                 int nbytes;
 515
 516                                 if (sz <= (DATA_PKT_SZ - ix))
 517                                         nbytes = sz;
 518                                 else
 519                                         nbytes = DATA_PKT_SZ - ix;
 520
 521                                 /**
 522                                  * Read bytes
 523                                  **/
 524                                 if (!linux_spi_read(&b[ix], nbytes)) {
 525                                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 526                                         result = N_FAIL;
 527                                         goto _error_;
 528                                 }
 529
 530                                 /**
 531                                  * Read Crc
 532                                  **/
 533                                 if (!g_spi.crc_off) {
 534                                         if (!linux_spi_read(crc, 2)) {
 535                                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 536                                                 result = N_FAIL;
 537                                                 goto _error_;
 538                                         }
 539                                 }
 540
 541
 542                                 ix += nbytes;
 543                                 sz -= nbytes;
 544                         }
 545
 546                         /*  if any data in left unread, then read the rest using normal DMA code.*/
 547                         while (sz > 0) {
 548                                 int nbytes;
 549
 550                                 if (sz <= DATA_PKT_SZ)
 551                                         nbytes = sz;
 552                                 else
 553                                         nbytes = DATA_PKT_SZ;
 554
 555                                 /**
 556                                  * read data response only on the next DMA cycles not
 557                                  * the first DMA since data response header is already
 558                                  * handled above for the first DMA.
 559                                  **/
 560                                 /**
 561                                  * Data Respnose header
 562                                  **/
 563                                 retry = 10;
 564                                 do {
 565                                         if (!linux_spi_read(&rsp, 1)) {
 566                                                 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
 567                                                 result = N_FAIL;
 568                                                 break;
 569                                         }
 570                                         if (((rsp >> 4) & 0xf) == 0xf)
 571                                                 break;
 572                                 } while (retry--);
 573
 574                                 if (result == N_FAIL)
 575                                         break;
 576
 577
 578                                 /**
 579                                  * Read bytes
 580                                  **/
 581                                 if (!linux_spi_read(&b[ix], nbytes)) {
 582                                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 583                                         result = N_FAIL;
 584                                         break;
 585                                 }
 586
 587                                 /**
 588                                  * Read Crc
 589                                  **/
 590                                 if (!g_spi.crc_off) {
 591                                         if (!linux_spi_read(crc, 2)) {
 592                                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 593                                                 result = N_FAIL;
 594                                                 break;
 595                                         }
 596                                 }
 597
 598                                 ix += nbytes;
 599                                 sz -= nbytes;
 600                         }
 601                 }
 602         }
 603 _error_:
 604         return result;
 605 }
 606
 607 static int spi_data_read(u8 *b, u32 sz)
 608 {
 609         int retry, ix, nbytes;
 610         int result = N_OK;
 611         u8 crc[2];
 612         u8 rsp;
 613
 614         /**
 615          *      Data
 616          **/
 617         ix = 0;
 618         do {
 619                 if (sz <= DATA_PKT_SZ)
 620                         nbytes = sz;
 621                 else
 622                         nbytes = DATA_PKT_SZ;
 623
 624                 /**
 625                  *      Data Respnose header
 626                  **/
 627                 retry = 10;
 628                 do {
 629                         if (!linux_spi_read(&rsp, 1)) {
 630                                 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
 631                                 result = N_FAIL;
 632                                 break;
 633                         }
 634                         if (((rsp >> 4) & 0xf) == 0xf)
 635                                 break;
 636                 } while (retry--);
 637
 638                 if (result == N_FAIL)
 639                         break;
 640
 641                 if (retry <= 0) {
 642                         PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp);
 643                         result = N_FAIL;
 644                         break;
 645                 }
 646
 647                 /**
 648                  *      Read bytes
 649                  **/
 650                 if (!linux_spi_read(&b[ix], nbytes)) {
 651                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 652                         result = N_FAIL;
 653                         break;
 654                 }
 655
 656                 /**
 657                  *      Read Crc
 658                  **/
 659                 if (!g_spi.crc_off) {
 660                         if (!linux_spi_read(crc, 2)) {
 661                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 662                                 result = N_FAIL;
 663                                 break;
 664                         }
 665                 }
 666
 667                 ix += nbytes;
 668                 sz -= nbytes;
 669
 670         } while (sz);
 671
 672         return result;
 673 }
 674
 675 static int spi_data_write(u8 *b, u32 sz)
 676 {
 677         int ix, nbytes;
 678         int result = 1;
 679         u8 cmd, order, crc[2] = {0};
 680         /* u8 rsp; */
 681
 682         /**
 683          *      Data
 684          **/
 685         ix = 0;
 686         do {
 687                 if (sz <= DATA_PKT_SZ)
 688                         nbytes = sz;
 689                 else
 690                         nbytes = DATA_PKT_SZ;
 691
 692                 /**
 693                  *      Write command
 694                  **/
 695                 cmd = 0xf0;
 696                 if (ix == 0) {
 697                         if (sz <= DATA_PKT_SZ)
 698
 699                                 order = 0x3;
 700                         else
 701                                 order = 0x1;
 702                 } else {
 703                         if (sz <= DATA_PKT_SZ)
 704                                 order = 0x3;
 705                         else
 706                                 order = 0x2;
 707                 }
 708                 cmd |= order;
 709                 if (!linux_spi_write(&cmd, 1)) {
 710                         PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
 711                         result = N_FAIL;
 712                         break;
 713                 }
 714
 715                 /**
 716                  *      Write data
 717                  **/
 718                 if (!linux_spi_write(&b[ix], nbytes)) {
 719                         PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
 720                         result = N_FAIL;
 721                         break;
 722                 }
 723
 724                 /**
 725                  *      Write Crc
 726                  **/
 727                 if (!g_spi.crc_off) {
 728                         if (!linux_spi_write(crc, 2)) {
 729                                 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
 730                                 result = N_FAIL;
 731                                 break;
 732                         }
 733                 }
 734
 735                 /**
 736                  *      No need to wait for response
 737                  **/
 738                 ix += nbytes;
 739                 sz -= nbytes;
 740         } while (sz);
 741
 742
 743         return result;
 744 }
 745
 746 /********************************************
 747  *
 748  *      Spi Internal Read/Write Function
 749  *
 750  ********************************************/
 751
 752 static int spi_internal_write(u32 adr, u32 dat)
 753 {
 754         int result;
 755
 756 #ifdef BIG_ENDIAN
 757         dat = BYTE_SWAP(dat);
 758 #endif
 759         result = spi_cmd_complete(CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4, 0);
 760         if (result != N_OK) {
 761                 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
 762         }
 763
 764         return result;
 765 }
 766
 767 static int spi_internal_read(u32 adr, u32 *data)
 768 {
 769         int result;
 770
 771         result = spi_cmd_complete(CMD_INTERNAL_READ, adr, (u8 *)data, 4, 0);
 772         if (result != N_OK) {
 773                 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
 774                 return 0;
 775         }
 776
 777 #ifdef BIG_ENDIAN
 778         *data = BYTE_SWAP(*data);
 779 #endif
 780
 781         return 1;
 782 }
 783
 784 /********************************************
 785  *
 786  *      Spi interfaces
 787  *
 788  ********************************************/
 789
 790 static int wilc_spi_write_reg(u32 addr, u32 data)
 791 {
 792         int result = N_OK;
 793         u8 cmd = CMD_SINGLE_WRITE;
 794         u8 clockless = 0;
 795
 796 #ifdef BIG_ENDIAN
 797         data = BYTE_SWAP(data);
 798 #endif
 799         if (addr < 0x30) {
 800                 /* Clockless register*/
 801                 cmd = CMD_INTERNAL_WRITE;
 802                 clockless = 1;
 803         }
 804
 805         result = spi_cmd_complete(cmd, addr, (u8 *)&data, 4, clockless);
 806         if (result != N_OK) {
 807                 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
 808         }
 809
 810         return result;
 811 }
 812
 813 static int wilc_spi_write(u32 addr, u8 *buf, u32 size)
 814 {
 815         int result;
 816         u8 cmd = CMD_DMA_EXT_WRITE;
 817
 818         /**
 819          *      has to be greated than 4
 820          **/
 821         if (size <= 4)
 822                 return 0;
 823
 824         result = spi_cmd_complete(cmd, addr, NULL, size, 0);
 825         if (result != N_OK) {
 826                 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
 827                 return 0;
 828         }
 829
 830         /**
 831          *      Data
 832          **/
 833         result = spi_data_write(buf, size);
 834         if (result != N_OK) {
 835                 PRINT_ER("[wilc spi]: Failed block data write...\n");
 836         }
 837
 838         return 1;
 839 }
 840
 841 static int wilc_spi_read_reg(u32 addr, u32 *data)
 842 {
 843         int result = N_OK;
 844         u8 cmd = CMD_SINGLE_READ;
 845         u8 clockless = 0;
 846
 847         if (addr < 0x30) {
 848                 /* PRINT_ER("***** read addr %d\n\n", addr); */
 849                 /* Clockless register*/
 850                 cmd = CMD_INTERNAL_READ;
 851                 clockless = 1;
 852         }
 853
 854         result = spi_cmd_complete(cmd, addr, (u8 *)data, 4, clockless);
 855         if (result != N_OK) {
 856                 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
 857                 return 0;
 858         }
 859
 860 #ifdef BIG_ENDIAN
 861         *data = BYTE_SWAP(*data);
 862 #endif
 863
 864         return 1;
 865 }
 866
 867 static int wilc_spi_read(u32 addr, u8 *buf, u32 size)
 868 {
 869         u8 cmd = CMD_DMA_EXT_READ;
 870         int result;
 871
 872         if (size <= 4)
 873                 return 0;
 874
 875         result = spi_cmd_complete(cmd, addr, buf, size, 0);
 876         if (result != N_OK) {
 877                 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
 878                 return 0;
 879         }
 880
 881         return 1;
 882 }
 883
 884 /********************************************
 885  *
 886  *      Bus interfaces
 887  *
 888  ********************************************/
 889
 890 static int wilc_spi_clear_int(void)
 891 {
 892         u32 reg;
 893
 894         if (!wilc_spi_read_reg(WILC_HOST_RX_CTRL_0, &reg)) {
 895                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0);
 896                 return 0;
 897         }
 898         reg &= ~0x1;
 899         wilc_spi_write_reg(WILC_HOST_RX_CTRL_0, reg);
 900         return 1;
 901 }
 902
 903 static int wilc_spi_deinit(void *pv)
 904 {
 905         /**
 906          *      TODO:
 907          **/
 908         return 1;
 909 }
 910
 911 static int wilc_spi_sync(void)
 912 {
 913         u32 reg;
 914         int ret;
 915
 916         /**
 917          *      interrupt pin mux select
 918          **/
 919         ret = wilc_spi_read_reg(WILC_PIN_MUX_0, &reg);
 920         if (!ret) {
 921                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
 922                 return 0;
 923         }
 924         reg |= BIT(8);
 925         ret = wilc_spi_write_reg(WILC_PIN_MUX_0, reg);
 926         if (!ret) {
 927                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
 928                 return 0;
 929         }
 930
 931         /**
 932          *      interrupt enable
 933          **/
 934         ret = wilc_spi_read_reg(WILC_INTR_ENABLE, &reg);
 935         if (!ret) {
 936                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
 937                 return 0;
 938         }
 939         reg |= BIT(16);
 940         ret = wilc_spi_write_reg(WILC_INTR_ENABLE, reg);
 941         if (!ret) {
 942                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
 943                 return 0;
 944         }
 945
 946         return 1;
 947 }
 948
 949 static int wilc_spi_init(struct wilc *wilc, wilc_debug_func func)
 950 {
 951         u32 reg;
 952         u32 chipid;
 953
 954         static int isinit;
 955
 956         if (isinit) {
 957
 958                 if (!wilc_spi_read_reg(0x1000, &chipid)) {
 959                         PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
 960                         return 0;
 961                 }
 962                 return 1;
 963         }
 964
 965         memset(&g_spi, 0, sizeof(wilc_spi_t));
 966
 967         g_spi.dPrint = func;
 968         if (!linux_spi_init()) {
 969                 PRINT_ER("[wilc spi]: Failed io init bus...\n");
 970                 return 0;
 971         } else {
 972                 return 0;
 973         }
 974
 975         /**
 976          *      configure protocol
 977          **/
 978         g_spi.crc_off = 0;
 979
 980         /* TODO: We can remove the CRC trials if there is a definite way to reset */
 981         /* the SPI to it's initial value. */
 982         if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 983                 /* Read failed. Try with CRC off. This might happen when module
 984                  * is removed but chip isn't reset*/
 985                 g_spi.crc_off = 1;
 986                 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
 987                 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 988                         /* Reaad failed with both CRC on and off, something went bad */
 989                         PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
 990                         return 0;
 991                 }
 992         }
 993         if (g_spi.crc_off == 0) {
 994                 reg &= ~0xc;    /* disable crc checking */
 995                 reg &= ~0x70;
 996                 reg |= (0x5 << 4);
 997                 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET, reg)) {
 998                         PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
 999                         return 0;
1000                 }
1001                 g_spi.crc_off = 1;
1002         }
1003
1004
1005         /**
1006          *      make sure can read back chip id correctly
1007          **/
1008         if (!wilc_spi_read_reg(0x1000, &chipid)) {
1009                 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1010                 return 0;
1011         }
1012         /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1013
1014         g_spi.has_thrpt_enh = 1;
1015
1016         isinit = 1;
1017
1018         return 1;
1019 }
1020
1021 static void wilc_spi_max_bus_speed(void)
1022 {
1023         linux_spi_set_max_speed();
1024 }
1025
1026 static void wilc_spi_default_bus_speed(void)
1027 {
1028 }
1029
1030 static int wilc_spi_read_size(u32 *size)
1031 {
1032         int ret;
1033
1034         if (g_spi.has_thrpt_enh) {
1035                 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, size);
1036                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
1037         } else {
1038                 u32 tmp;
1039                 u32 byte_cnt;
1040
1041                 ret = wilc_spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1042                 if (!ret) {
1043                         PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1044                         goto _fail_;
1045                 }
1046                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1047                 *size = tmp;
1048         }
1049
1050
1051
1052 _fail_:
1053         return ret;
1054 }
1055
1056
1057
1058 static int wilc_spi_read_int(u32 *int_status)
1059 {
1060         int ret;
1061
1062         if (g_spi.has_thrpt_enh) {
1063                 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, int_status);
1064         } else {
1065                 u32 tmp;
1066                 u32 byte_cnt;
1067
1068                 ret = wilc_spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1069                 if (!ret) {
1070                         PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1071                         goto _fail_;
1072                 }
1073                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1074
1075                 {
1076                         int happended, j;
1077
1078                         j = 0;
1079                         do {
1080                                 u32 irq_flags;
1081
1082                                 happended = 0;
1083
1084                                 wilc_spi_read_reg(0x1a90, &irq_flags);
1085                                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
1086
1087                                 if (g_spi.nint > 5) {
1088                                         wilc_spi_read_reg(0x1a94, &irq_flags);
1089                                         tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
1090                                 }
1091
1092                                 {
1093                                         u32 unkmown_mask;
1094
1095                                         unkmown_mask = ~((1ul << g_spi.nint) - 1);
1096
1097                                         if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
1098                                                 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
1099                                                 happended = 1;
1100                                         }
1101                                 }
1102                                 j++;
1103                         } while (happended);
1104                 }
1105
1106                 *int_status = tmp;
1107
1108         }
1109
1110 _fail_:
1111         return ret;
1112 }
1113
1114 static int wilc_spi_clear_int_ext(u32 val)
1115 {
1116         int ret;
1117
1118         if (g_spi.has_thrpt_enh) {
1119                 ret = spi_internal_write(0xe844 - WILC_SPI_REG_BASE, val);
1120         } else {
1121                 u32 flags;
1122
1123                 flags = val & (BIT(MAX_NUM_INT) - 1);
1124                 if (flags) {
1125                         int i;
1126
1127                         ret = 1;
1128                         for (i = 0; i < g_spi.nint; i++) {
1129                                 /* No matter what you write 1 or 0, it will clear interrupt. */
1130                                 if (flags & 1)
1131                                         ret = wilc_spi_write_reg(0x10c8 + i * 4, 1);
1132                                 if (!ret)
1133                                         break;
1134                                 flags >>= 1;
1135                         }
1136                         if (!ret) {
1137                                 PRINT_ER("[wilc spi]: Failed wilc_spi_write_reg, set reg %x ...\n", 0x10c8 + i * 4);
1138                                 goto _fail_;
1139                         }
1140                         for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1141                                 if (flags & 1)
1142                                         PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i);
1143                                 flags >>= 1;
1144                         }
1145                 }
1146
1147                 {
1148                         u32 tbl_ctl;
1149
1150                         tbl_ctl = 0;
1151                         /* select VMM table 0 */
1152                         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1153                                 tbl_ctl |= BIT(0);
1154                         /* select VMM table 1 */
1155                         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1156                                 tbl_ctl |= BIT(1);
1157
1158                         ret = wilc_spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);
1159                         if (!ret) {
1160                                 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1161                                 goto _fail_;
1162                         }
1163
1164                         if ((val & EN_VMM) == EN_VMM) {
1165                                 /**
1166                                  *      enable vmm transfer.
1167                                  **/
1168                                 ret = wilc_spi_write_reg(WILC_VMM_CORE_CTL, 1);
1169                                 if (!ret) {
1170                                         PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1171                                         goto _fail_;
1172                                 }
1173                         }
1174                 }
1175         }
1176 _fail_:
1177         return ret;
1178 }
1179
1180 static int wilc_spi_sync_ext(int nint /*  how mant interrupts to enable. */)
1181 {
1182         u32 reg;
1183         int ret, i;
1184
1185         if (nint > MAX_NUM_INT) {
1186                 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint);
1187                 return 0;
1188         }
1189
1190         g_spi.nint = nint;
1191
1192         /**
1193          *      interrupt pin mux select
1194          **/
1195         ret = wilc_spi_read_reg(WILC_PIN_MUX_0, &reg);
1196         if (!ret) {
1197                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1198                 return 0;
1199         }
1200         reg |= BIT(8);
1201         ret = wilc_spi_write_reg(WILC_PIN_MUX_0, reg);
1202         if (!ret) {
1203                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1204                 return 0;
1205         }
1206
1207         /**
1208          *      interrupt enable
1209          **/
1210         ret = wilc_spi_read_reg(WILC_INTR_ENABLE, &reg);
1211         if (!ret) {
1212                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1213                 return 0;
1214         }
1215
1216         for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1217                 reg |= (BIT((27 + i)));
1218         }
1219         ret = wilc_spi_write_reg(WILC_INTR_ENABLE, reg);
1220         if (!ret) {
1221                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1222                 return 0;
1223         }
1224         if (nint) {
1225                 ret = wilc_spi_read_reg(WILC_INTR2_ENABLE, &reg);
1226                 if (!ret) {
1227                         PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE);
1228                         return 0;
1229                 }
1230
1231                 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1232                         reg |= BIT(i);
1233                 }
1234
1235                 ret = wilc_spi_read_reg(WILC_INTR2_ENABLE, &reg);
1236                 if (!ret) {
1237                         PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE);
1238                         return 0;
1239                 }
1240         }
1241
1242         return 1;
1243 }
1244 /********************************************
1245  *
1246  *      Global spi HIF function table
1247  *
1248  ********************************************/
1249 struct wilc_hif_func hif_spi = {
1250         wilc_spi_init,
1251         wilc_spi_deinit,
1252         wilc_spi_read_reg,
1253         wilc_spi_write_reg,
1254         wilc_spi_read,
1255         wilc_spi_write,
1256         wilc_spi_sync,
1257         wilc_spi_clear_int,
1258         wilc_spi_read_int,
1259         wilc_spi_clear_int_ext,
1260         wilc_spi_read_size,
1261         wilc_spi_write,
1262         wilc_spi_read,
1263         wilc_spi_sync_ext,
1264         wilc_spi_max_bus_speed,
1265         wilc_spi_default_bus_speed,
1266 };