drivers/staging/wilc1000/wilc_spi.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_spi.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9
  10 #include "wilc_wlan_if.h"
  11 #include "wilc_wlan.h"
  12
  13 extern unsigned int int_clrd;
  14
  15 /*
  16  * #include <linux/kernel.h>
  17  * #include <linux/string.h>
  18  */
  19 typedef struct {
  20         void *os_context;
  21         int (*spi_tx)(uint8_t *, uint32_t);
  22         int (*spi_rx)(uint8_t *, uint32_t);
  23         int (*spi_trx)(uint8_t *, uint8_t *, uint32_t);
  24         int (*spi_max_speed)(void);
  25         wilc_debug_func dPrint;
  26         int crc_off;
  27         int nint;
  28         int has_thrpt_enh;
  29 } wilc_spi_t;
  30
  31 static wilc_spi_t g_spi;
  32
  33 static int spi_read(uint32_t, uint8_t *, uint32_t);
  34 static int spi_write(uint32_t, uint8_t *, uint32_t);
  35
  36 /********************************************
  37  *
  38  *      Crc7
  39  *
  40  ********************************************/
  41
  42 static const uint8_t crc7_syndrome_table[256] = {
  43         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  44         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  45         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  46         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  47         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  48         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  49         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  50         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  51         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  52         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  53         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  54         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  55         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  56         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  57         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  58         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  59         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  60         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  61         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  62         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  63         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  64         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  65         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  66         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  67         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  68         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  69         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  70         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  71         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  72         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  73         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  74         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  75 };
  76
  77 static uint8_t crc7_byte(uint8_t crc, uint8_t data)
  78 {
  79         return crc7_syndrome_table[(crc << 1) ^ data];
  80 }
  81
  82 static uint8_t crc7(uint8_t crc, const uint8_t *buffer, uint32_t len)
  83 {
  84         while (len--)
  85                 crc = crc7_byte(crc, *buffer++);
  86         return crc;
  87 }
  88
  89 /********************************************
  90  *
  91  *      Spi protocol Function
  92  *
  93  ********************************************/
  94
  95 #define CMD_DMA_WRITE                           0xc1
  96 #define CMD_DMA_READ                            0xc2
  97 #define CMD_INTERNAL_WRITE              0xc3
  98 #define CMD_INTERNAL_READ               0xc4
  99 #define CMD_TERMINATE                           0xc5
 100 #define CMD_REPEAT                                      0xc6
 101 #define CMD_DMA_EXT_WRITE               0xc7
 102 #define CMD_DMA_EXT_READ                0xc8
 103 #define CMD_SINGLE_WRITE                        0xc9
 104 #define CMD_SINGLE_READ                 0xca
 105 #define CMD_RESET                                               0xcf
 106
 107 #define N_OK                                                            1
 108 #define N_FAIL                                                          0
 109 #define N_RESET                                                 -1
 110 #define N_RETRY                                                 -2
 111
 112 #define DATA_PKT_SZ_256                         256
 113 #define DATA_PKT_SZ_512                 512
 114 #define DATA_PKT_SZ_1K                          1024
 115 #define DATA_PKT_SZ_4K                          (4 * 1024)
 116 #define DATA_PKT_SZ_8K                          (8 * 1024)
 117 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 118
 119 static int spi_cmd(uint8_t cmd, uint32_t adr, uint32_t data, uint32_t sz, uint8_t clockless)
 120 {
 121         uint8_t bc[9];
 122         int len = 5;
 123         int result = N_OK;
 124
 125         bc[0] = cmd;
 126         switch (cmd) {
 127         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 128                 bc[1] = (uint8_t)(adr >> 16);
 129                 bc[2] = (uint8_t)(adr >> 8);
 130                 bc[3] = (uint8_t)adr;
 131                 len = 5;
 132                 break;
 133
 134         case CMD_INTERNAL_READ:                 /* internal register read */
 135                 bc[1] = (uint8_t)(adr >> 8);
 136                 if (clockless)
 137                         bc[1] |= (1 << 7);
 138                 bc[2] = (uint8_t)adr;
 139                 bc[3] = 0x00;
 140                 len = 5;
 141                 break;
 142
 143         case CMD_TERMINATE:                                     /* termination */
 144                 bc[1] = 0x00;
 145                 bc[2] = 0x00;
 146                 bc[3] = 0x00;
 147                 len = 5;
 148                 break;
 149
 150         case CMD_REPEAT:                                                /* repeat */
 151                 bc[1] = 0x00;
 152                 bc[2] = 0x00;
 153                 bc[3] = 0x00;
 154                 len = 5;
 155                 break;
 156
 157         case CMD_RESET:                                                 /* reset */
 158                 bc[1] = 0xff;
 159                 bc[2] = 0xff;
 160                 bc[3] = 0xff;
 161                 len = 5;
 162                 break;
 163
 164         case CMD_DMA_WRITE:                                     /* dma write */
 165         case CMD_DMA_READ:                                      /* dma read */
 166                 bc[1] = (uint8_t)(adr >> 16);
 167                 bc[2] = (uint8_t)(adr >> 8);
 168                 bc[3] = (uint8_t)adr;
 169                 bc[4] = (uint8_t)(sz >> 8);
 170                 bc[5] = (uint8_t)(sz);
 171                 len = 7;
 172                 break;
 173
 174         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 175         case CMD_DMA_EXT_READ:                  /* dma extended read */
 176                 bc[1] = (uint8_t)(adr >> 16);
 177                 bc[2] = (uint8_t)(adr >> 8);
 178                 bc[3] = (uint8_t)adr;
 179                 bc[4] = (uint8_t)(sz >> 16);
 180                 bc[5] = (uint8_t)(sz >> 8);
 181                 bc[6] = (uint8_t)(sz);
 182                 len = 8;
 183                 break;
 184
 185         case CMD_INTERNAL_WRITE:                /* internal register write */
 186                 bc[1] = (uint8_t)(adr >> 8);
 187                 if (clockless)
 188                         bc[1] |= (1 << 7);
 189                 bc[2] = (uint8_t)(adr);
 190                 bc[3] = (uint8_t)(data >> 24);
 191                 bc[4] = (uint8_t)(data >> 16);
 192                 bc[5] = (uint8_t)(data >> 8);
 193                 bc[6] = (uint8_t)(data);
 194                 len = 8;
 195                 break;
 196
 197         case CMD_SINGLE_WRITE:                  /* single word write */
 198                 bc[1] = (uint8_t)(adr >> 16);
 199                 bc[2] = (uint8_t)(adr >> 8);
 200                 bc[3] = (uint8_t)(adr);
 201                 bc[4] = (uint8_t)(data >> 24);
 202                 bc[5] = (uint8_t)(data >> 16);
 203                 bc[6] = (uint8_t)(data >> 8);
 204                 bc[7] = (uint8_t)(data);
 205                 len = 9;
 206                 break;
 207
 208         default:
 209                 result = N_FAIL;
 210                 break;
 211         }
 212
 213         if (result) {
 214                 if (!g_spi.crc_off)
 215                         bc[len - 1] = (crc7(0x7f, (const uint8_t *)&bc[0], len - 1)) << 1;
 216                 else
 217                         len -= 1;
 218
 219                 if (!g_spi.spi_tx(bc, len)) {
 220                         PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
 221                         result = N_FAIL;
 222                 }
 223         }
 224
 225         return result;
 226 }
 227
 228 static int spi_cmd_rsp(uint8_t cmd)
 229 {
 230         uint8_t rsp;
 231         int result = N_OK;
 232
 233         /**
 234          *      Command/Control response
 235          **/
 236         if ((cmd == CMD_RESET) ||
 237             (cmd == CMD_TERMINATE) ||
 238             (cmd == CMD_REPEAT)) {
 239                 if (!g_spi.spi_rx(&rsp, 1)) {
 240                         result = N_FAIL;
 241                         goto _fail_;
 242                 }
 243         }
 244
 245         if (!g_spi.spi_rx(&rsp, 1)) {
 246                 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
 247                 result = N_FAIL;
 248                 goto _fail_;
 249         }
 250
 251         if (rsp != cmd) {
 252                 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
 253                 result = N_FAIL;
 254                 goto _fail_;
 255         }
 256
 257         /**
 258          *      State response
 259          **/
 260         if (!g_spi.spi_rx(&rsp, 1)) {
 261                 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
 262                 result = N_FAIL;
 263                 goto _fail_;
 264         }
 265
 266         if (rsp != 0x00) {
 267                 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp);
 268                 result = N_FAIL;
 269         }
 270
 271 _fail_:
 272
 273         return result;
 274 }
 275
 276 static int spi_cmd_complete(uint8_t cmd, uint32_t adr, uint8_t *b, uint32_t sz, uint8_t clockless)
 277 {
 278         uint8_t wb[32], rb[32];
 279         uint8_t wix, rix;
 280         uint32_t len2;
 281         uint8_t rsp;
 282         int len = 0;
 283         int result = N_OK;
 284
 285         wb[0] = cmd;
 286         switch (cmd) {
 287         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 288                 wb[1] = (uint8_t)(adr >> 16);
 289                 wb[2] = (uint8_t)(adr >> 8);
 290                 wb[3] = (uint8_t)adr;
 291                 len = 5;
 292                 break;
 293
 294         case CMD_INTERNAL_READ:                 /* internal register read */
 295                 wb[1] = (uint8_t)(adr >> 8);
 296                 if (clockless == 1)
 297                         wb[1] |= (1 << 7);
 298                 wb[2] = (uint8_t)adr;
 299                 wb[3] = 0x00;
 300                 len = 5;
 301                 break;
 302
 303         case CMD_TERMINATE:                                     /* termination */
 304                 wb[1] = 0x00;
 305                 wb[2] = 0x00;
 306                 wb[3] = 0x00;
 307                 len = 5;
 308                 break;
 309
 310         case CMD_REPEAT:                                                /* repeat */
 311                 wb[1] = 0x00;
 312                 wb[2] = 0x00;
 313                 wb[3] = 0x00;
 314                 len = 5;
 315                 break;
 316
 317         case CMD_RESET:                                                 /* reset */
 318                 wb[1] = 0xff;
 319                 wb[2] = 0xff;
 320                 wb[3] = 0xff;
 321                 len = 5;
 322                 break;
 323
 324         case CMD_DMA_WRITE:                                     /* dma write */
 325         case CMD_DMA_READ:                                      /* dma read */
 326                 wb[1] = (uint8_t)(adr >> 16);
 327                 wb[2] = (uint8_t)(adr >> 8);
 328                 wb[3] = (uint8_t)adr;
 329                 wb[4] = (uint8_t)(sz >> 8);
 330                 wb[5] = (uint8_t)(sz);
 331                 len = 7;
 332                 break;
 333
 334         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 335         case CMD_DMA_EXT_READ:                  /* dma extended read */
 336                 wb[1] = (uint8_t)(adr >> 16);
 337                 wb[2] = (uint8_t)(adr >> 8);
 338                 wb[3] = (uint8_t)adr;
 339                 wb[4] = (uint8_t)(sz >> 16);
 340                 wb[5] = (uint8_t)(sz >> 8);
 341                 wb[6] = (uint8_t)(sz);
 342                 len = 8;
 343                 break;
 344
 345         case CMD_INTERNAL_WRITE:                /* internal register write */
 346                 wb[1] = (uint8_t)(adr >> 8);
 347                 if (clockless == 1)
 348                         wb[1] |= (1 << 7);
 349                 wb[2] = (uint8_t)(adr);
 350                 wb[3] = b[3];
 351                 wb[4] = b[2];
 352                 wb[5] = b[1];
 353                 wb[6] = b[0];
 354                 len = 8;
 355                 break;
 356
 357         case CMD_SINGLE_WRITE:                  /* single word write */
 358                 wb[1] = (uint8_t)(adr >> 16);
 359                 wb[2] = (uint8_t)(adr >> 8);
 360                 wb[3] = (uint8_t)(adr);
 361                 wb[4] = b[3];
 362                 wb[5] = b[2];
 363                 wb[6] = b[1];
 364                 wb[7] = b[0];
 365                 len = 9;
 366                 break;
 367
 368         default:
 369                 result = N_FAIL;
 370                 break;
 371         }
 372
 373         if (result != N_OK) {
 374                 return result;
 375         }
 376
 377         if (!g_spi.crc_off) {
 378                 wb[len - 1] = (crc7(0x7f, (const uint8_t *)&wb[0], len - 1)) << 1;
 379         } else {
 380                 len -= 1;
 381         }
 382
 383 #define NUM_SKIP_BYTES (1)
 384 #define NUM_RSP_BYTES (2)
 385 #define NUM_DATA_HDR_BYTES (1)
 386 #define NUM_DATA_BYTES (4)
 387 #define NUM_CRC_BYTES (2)
 388 #define NUM_DUMMY_BYTES (3)
 389         if ((cmd == CMD_RESET) ||
 390             (cmd == CMD_TERMINATE) ||
 391             (cmd == CMD_REPEAT)) {
 392                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 393         } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 394                 if (!g_spi.crc_off) {
 395                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 396                                       + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
 397                 } else {
 398                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 399                                       + NUM_DUMMY_BYTES);
 400                 }
 401         } else {
 402                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 403         }
 404 #undef NUM_DUMMY_BYTES
 405
 406         if (len2 > (sizeof(wb) / sizeof(wb[0]))) {
 407                 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%lu)\n",
 408                          len2, (sizeof(wb) / sizeof(wb[0])));
 409                 result = N_FAIL;
 410                 return result;
 411         }
 412         /* zero spi write buffers. */
 413         for (wix = len; wix < len2; wix++) {
 414                 wb[wix] = 0;
 415         }
 416         rix = len;
 417
 418         if (!g_spi.spi_trx(wb, rb, len2)) {
 419                 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
 420                 result = N_FAIL;
 421                 return result;
 422         }
 423
 424 #if 0
 425         {
 426                 int jj;
 427                 PRINT_D(BUS_DBG, "--- cnd = %x, len=%d, len2=%d\n", cmd, len, len2);
 428                 for (jj = 0; jj < sizeof(wb) / sizeof(wb[0]); jj++) {
 429
 430                         if (jj >= len2)
 431                                 break;
 432                         if (((jj + 1) % 16) != 0) {
 433                                 if ((jj % 16) == 0) {
 434                                         PRINT_D(BUS_DBG, "wb[%02x]: %02x ", jj, wb[jj]);
 435                                 } else {
 436                                         PRINT_D(BUS_DBG, "%02x ", wb[jj]);
 437                                 }
 438                         } else {
 439                                 PRINT_D(BUS_DBG, "%02x\n", wb[jj]);
 440                         }
 441                 }
 442
 443                 for (jj = 0; jj < sizeof(rb) / sizeof(rb[0]); jj++) {
 444
 445                         if (jj >= len2)
 446                                 break;
 447                         if (((jj + 1) % 16) != 0) {
 448                                 if ((jj % 16) == 0) {
 449                                         PRINT_D(BUS_DBG, "rb[%02x]: %02x ", jj, rb[jj]);
 450                                 } else {
 451                                         PRINT_D(BUS_DBG, "%02x ", rb[jj]);
 452                                 }
 453                         } else {
 454                                 PRINT_D(BUS_DBG, "%02x\n", rb[jj]);
 455                         }
 456                 }
 457         }
 458 #endif
 459
 460         /**
 461          * Command/Control response
 462          **/
 463         if ((cmd == CMD_RESET) ||
 464             (cmd == CMD_TERMINATE) ||
 465             (cmd == CMD_REPEAT)) {
 466                 rix++;         /* skip 1 byte */
 467         }
 468
 469         /* do { */
 470         rsp = rb[rix++];
 471         /*      if(rsp == cmd) break; */
 472         /* } while(&rptr[1] <= &rb[len2]); */
 473
 474         if (rsp != cmd) {
 475                 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
 476                          ", resp (%02x)\n", cmd, rsp);
 477                 result = N_FAIL;
 478                 return result;
 479         }
 480
 481         /**
 482          * State response
 483          **/
 484         rsp = rb[rix++];
 485         if (rsp != 0x00) {
 486                 PRINT_ER("[wilc spi]: Failed cmd state response "
 487                          "state (%02x)\n", rsp);
 488                 result = N_FAIL;
 489                 return result;
 490         }
 491
 492         if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
 493             || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 494                 int retry;
 495                 /* uint16_t crc1, crc2; */
 496                 uint8_t crc[2];
 497                 /**
 498                  * Data Respnose header
 499                  **/
 500                 retry = 100;
 501                 do {
 502                         /* ensure there is room in buffer later to read data and crc */
 503                         if (rix < len2) {
 504                                 rsp = rb[rix++];
 505                         } else {
 506                                 retry = 0;
 507                                 break;
 508                         }
 509                         if (((rsp >> 4) & 0xf) == 0xf)
 510                                 break;
 511                 } while (retry--);
 512
 513                 if (retry <= 0) {
 514                         PRINT_ER("[wilc spi]: Error, data read "
 515                                  "response (%02x)\n", rsp);
 516                         result = N_RESET;
 517                         return result;
 518                 }
 519
 520                 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 521                         /**
 522                          * Read bytes
 523                          **/
 524                         if ((rix + 3) < len2) {
 525                                 b[0] = rb[rix++];
 526                                 b[1] = rb[rix++];
 527                                 b[2] = rb[rix++];
 528                                 b[3] = rb[rix++];
 529                         } else {
 530                                 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
 531                                 result = N_FAIL;
 532                                 return result;
 533                         }
 534
 535                         if (!g_spi.crc_off) {
 536                                 /**
 537                                  * Read Crc
 538                                  **/
 539                                 if ((rix + 1) < len2) {
 540                                         crc[0] = rb[rix++];
 541                                         crc[1] = rb[rix++];
 542                                 } else {
 543                                         PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
 544                                         result = N_FAIL;
 545                                         return result;
 546                                 }
 547                         }
 548                 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 549                         int ix;
 550
 551                         /* some data may be read in response to dummy bytes. */
 552                         for (ix = 0; (rix < len2) && (ix < sz); ) {
 553                                 b[ix++] = rb[rix++];
 554                         }
 555 #if 0
 556                         if (ix)
 557                                 PRINT_D(BUS_DBG, "ttt %d %d\n", sz, ix);
 558 #endif
 559                         sz -= ix;
 560
 561                         if (sz > 0) {
 562                                 int nbytes;
 563
 564                                 if (sz <= (DATA_PKT_SZ - ix)) {
 565                                         nbytes = sz;
 566                                 } else {
 567                                         nbytes = DATA_PKT_SZ - ix;
 568                                 }
 569
 570                                 /**
 571                                  * Read bytes
 572                                  **/
 573                                 if (!g_spi.spi_rx(&b[ix], nbytes)) {
 574                                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 575                                         result = N_FAIL;
 576                                         goto _error_;
 577                                 }
 578
 579                                 /**
 580                                  * Read Crc
 581                                  **/
 582                                 if (!g_spi.crc_off) {
 583                                         if (!g_spi.spi_rx(crc, 2)) {
 584                                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 585                                                 result = N_FAIL;
 586                                                 goto _error_;
 587                                         }
 588                                 }
 589
 590
 591                                 ix += nbytes;
 592                                 sz -= nbytes;
 593                         }
 594
 595                         /*  if any data in left unread, then read the rest using normal DMA code.*/
 596                         while (sz > 0) {
 597                                 int nbytes;
 598
 599 #if 0
 600                                 PRINT_INFO(BUS_DBG, "rrr %d %d\n", sz, ix);
 601 #endif
 602                                 if (sz <= DATA_PKT_SZ) {
 603                                         nbytes = sz;
 604                                 } else {
 605                                         nbytes = DATA_PKT_SZ;
 606                                 }
 607
 608                                 /**
 609                                  * read data response only on the next DMA cycles not
 610                                  * the first DMA since data response header is already
 611                                  * handled above for the first DMA.
 612                                  **/
 613                                 /**
 614                                  * Data Respnose header
 615                                  **/
 616                                 retry = 10;
 617                                 do {
 618                                         if (!g_spi.spi_rx(&rsp, 1)) {
 619                                                 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
 620                                                 result = N_FAIL;
 621                                                 break;
 622                                         }
 623                                         if (((rsp >> 4) & 0xf) == 0xf)
 624                                                 break;
 625                                 } while (retry--);
 626
 627                                 if (result == N_FAIL)
 628                                         break;
 629
 630
 631                                 /**
 632                                  * Read bytes
 633                                  **/
 634                                 if (!g_spi.spi_rx(&b[ix], nbytes)) {
 635                                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 636                                         result = N_FAIL;
 637                                         break;
 638                                 }
 639
 640                                 /**
 641                                  * Read Crc
 642                                  **/
 643                                 if (!g_spi.crc_off) {
 644                                         if (!g_spi.spi_rx(crc, 2)) {
 645                                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 646                                                 result = N_FAIL;
 647                                                 break;
 648                                         }
 649                                 }
 650
 651                                 ix += nbytes;
 652                                 sz -= nbytes;
 653                         }
 654                 }
 655         }
 656 _error_:
 657         return result;
 658 }
 659
 660 static int spi_data_read(uint8_t *b, uint32_t sz)
 661 {
 662         int retry, ix, nbytes;
 663         int result = N_OK;
 664         uint8_t crc[2];
 665         uint8_t rsp;
 666
 667         /**
 668          *      Data
 669          **/
 670         ix = 0;
 671         do {
 672                 if (sz <= DATA_PKT_SZ)
 673                         nbytes = sz;
 674                 else
 675                         nbytes = DATA_PKT_SZ;
 676
 677                 /**
 678                  *      Data Respnose header
 679                  **/
 680                 retry = 10;
 681                 do {
 682                         if (!g_spi.spi_rx(&rsp, 1)) {
 683                                 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
 684                                 result = N_FAIL;
 685                                 break;
 686                         }
 687                         if (((rsp >> 4) & 0xf) == 0xf)
 688                                 break;
 689                 } while (retry--);
 690
 691                 if (result == N_FAIL)
 692                         break;
 693
 694                 if (retry <= 0) {
 695                         PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp);
 696                         result = N_FAIL;
 697                         break;
 698                 }
 699
 700                 /**
 701                  *      Read bytes
 702                  **/
 703                 if (!g_spi.spi_rx(&b[ix], nbytes)) {
 704                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 705                         result = N_FAIL;
 706                         break;
 707                 }
 708
 709                 /**
 710                  *      Read Crc
 711                  **/
 712                 if (!g_spi.crc_off) {
 713                         if (!g_spi.spi_rx(crc, 2)) {
 714                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 715                                 result = N_FAIL;
 716                                 break;
 717                         }
 718                 }
 719
 720                 ix += nbytes;
 721                 sz -= nbytes;
 722
 723         } while (sz);
 724
 725         return result;
 726 }
 727
 728 static int spi_data_write(uint8_t *b, uint32_t sz)
 729 {
 730         int ix, nbytes;
 731         int result = 1;
 732         uint8_t cmd, order, crc[2] = {0};
 733         /* uint8_t rsp; */
 734
 735         /**
 736          *      Data
 737          **/
 738         ix = 0;
 739         do {
 740                 if (sz <= DATA_PKT_SZ)
 741                         nbytes = sz;
 742                 else
 743                         nbytes = DATA_PKT_SZ;
 744
 745                 /**
 746                  *      Write command
 747                  **/
 748                 cmd = 0xf0;
 749                 if (ix == 0) {
 750                         if (sz <= DATA_PKT_SZ)
 751
 752                                 order = 0x3;
 753                         else
 754                                 order = 0x1;
 755                 } else {
 756                         if (sz <= DATA_PKT_SZ)
 757                                 order = 0x3;
 758                         else
 759                                 order = 0x2;
 760                 }
 761                 cmd |= order;
 762                 if (!g_spi.spi_tx(&cmd, 1)) {
 763                         PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
 764                         result = N_FAIL;
 765                         break;
 766                 }
 767
 768                 /**
 769                  *      Write data
 770                  **/
 771                 if (!g_spi.spi_tx(&b[ix], nbytes)) {
 772                         PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
 773                         result = N_FAIL;
 774                         break;
 775                 }
 776
 777                 /**
 778                  *      Write Crc
 779                  **/
 780                 if (!g_spi.crc_off) {
 781                         if (!g_spi.spi_tx(crc, 2)) {
 782                                 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
 783                                 result = N_FAIL;
 784                                 break;
 785                         }
 786                 }
 787
 788                 /**
 789                  *      No need to wait for response
 790                  **/
 791 #if 0
 792                 /**
 793                  *      Respnose
 794                  **/
 795                 if (!g_spi.spi_rx(&rsp, 1)) {
 796                         PRINT_ER("[wilc spi]: Failed data block write, response read, bus error...\n");
 797                         result = N_FAIL;
 798                         break;
 799                 }
 800
 801                 if (((rsp >> 4) & 0xf) != 0xc) {
 802                         result = N_FAIL;
 803                         PRINT_ER("[wilc spi]: Failed data block write response...(%02x)\n", rsp);
 804                         break;
 805                 }
 806
 807                 /**
 808                  *      State
 809                  **/
 810                 if (!g_spi.spi_rx(&rsp, 1)) {
 811                         PRINT_ER("[wilc spi]: Failed data block write, read state, bus error...\n");
 812                         result = N_FAIL;
 813                         break;
 814                 }
 815 #endif
 816
 817                 ix += nbytes;
 818                 sz -= nbytes;
 819         } while (sz);
 820
 821
 822         return result;
 823 }
 824
 825 /********************************************
 826  *
 827  *      Spi Internal Read/Write Function
 828  *
 829  ********************************************/
 830
 831 static int spi_internal_write(uint32_t adr, uint32_t dat)
 832 {
 833         int result;
 834
 835 #if defined USE_OLD_SPI_SW
 836         /**
 837          *      Command
 838          **/
 839         result = spi_cmd(CMD_INTERNAL_WRITE, adr, dat, 4, 0);
 840         if (result != N_OK) {
 841                 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
 842                 return 0;
 843         }
 844
 845         result = spi_cmd_rsp(CMD_INTERNAL_WRITE, 0);
 846         if (result != N_OK) {
 847                 PRINT_ER("[wilc spi]: Failed internal write cmd response...\n");
 848         }
 849 #else
 850
 851 #ifdef BIG_ENDIAN
 852         dat = BYTE_SWAP(dat);
 853 #endif
 854         result = spi_cmd_complete(CMD_INTERNAL_WRITE, adr, (uint8_t *)&dat, 4, 0);
 855         if (result != N_OK) {
 856                 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
 857         }
 858
 859 #endif
 860         return result;
 861 }
 862
 863 static int spi_internal_read(uint32_t adr, uint32_t *data)
 864 {
 865         int result;
 866
 867 #if defined USE_OLD_SPI_SW
 868         result = spi_cmd(CMD_INTERNAL_READ, adr, 0, 4, 0);
 869         if (result != N_OK) {
 870                 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
 871                 return 0;
 872         }
 873
 874         result = spi_cmd_rsp(CMD_INTERNAL_READ, 0);
 875         if (result != N_OK) {
 876                 PRINT_ER("[wilc spi]: Failed internal read cmd response...\n");
 877                 return 0;
 878         }
 879
 880         /**
 881          *      Data
 882          **/
 883         result = spi_data_read((uint8_t *)data, 4);
 884         if (result != N_OK) {
 885                 PRINT_ER("[wilc spi]: Failed internal read data...\n");
 886                 return 0;
 887         }
 888 #else
 889         result = spi_cmd_complete(CMD_INTERNAL_READ, adr, (uint8_t *)data, 4, 0);
 890         if (result != N_OK) {
 891                 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
 892                 return 0;
 893         }
 894 #endif
 895
 896
 897 #ifdef BIG_ENDIAN
 898         *data = BYTE_SWAP(*data);
 899 #endif
 900
 901         return 1;
 902 }
 903
 904 /********************************************
 905  *
 906  *      Spi interfaces
 907  *
 908  ********************************************/
 909
 910 static int spi_write_reg(uint32_t addr, uint32_t data)
 911 {
 912         int result = N_OK;
 913         uint8_t cmd = CMD_SINGLE_WRITE;
 914         uint8_t clockless = 0;
 915
 916
 917 #if defined USE_OLD_SPI_SW
 918         {
 919                 result = spi_cmd(cmd, addr, data, 4, 0);
 920                 if (result != N_OK) {
 921                         PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
 922                         return 0;
 923                 }
 924
 925                 result = spi_cmd_rsp(cmd, 0);
 926                 if (result != N_OK) {
 927                         PRINT_ER("[wilc spi]: Failed cmd response, write reg (%08x)...\n", addr);
 928                         return 0;
 929                 }
 930
 931                 return 1;
 932         }
 933 #else
 934 #ifdef BIG_ENDIAN
 935         data = BYTE_SWAP(data);
 936 #endif
 937         if (addr < 0x30) {
 938                 /* Clockless register*/
 939                 cmd = CMD_INTERNAL_WRITE;
 940                 clockless = 1;
 941         }
 942
 943         result = spi_cmd_complete(cmd, addr, (uint8_t *)&data, 4, clockless);
 944         if (result != N_OK) {
 945                 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
 946         }
 947
 948         return result;
 949 #endif
 950
 951 }
 952
 953 static int spi_write(uint32_t addr, uint8_t *buf, uint32_t size)
 954 {
 955         int result;
 956         uint8_t cmd = CMD_DMA_EXT_WRITE;
 957
 958         /**
 959          *      has to be greated than 4
 960          **/
 961         if (size <= 4)
 962                 return 0;
 963
 964 #if defined USE_OLD_SPI_SW
 965         /**
 966          *      Command
 967          **/
 968         result = spi_cmd(cmd, addr, 0, size, 0);
 969         if (result != N_OK) {
 970                 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
 971                 return 0;
 972         }
 973
 974         result = spi_cmd_rsp(cmd, 0);
 975         if (result != N_OK) {
 976                 PRINT_ER("[wilc spi ]: Failed cmd response, write block (%08x)...\n", addr);
 977                 return 0;
 978         }
 979 #else
 980         result = spi_cmd_complete(cmd, addr, NULL, size, 0);
 981         if (result != N_OK) {
 982                 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
 983                 return 0;
 984         }
 985 #endif
 986
 987         /**
 988          *      Data
 989          **/
 990         result = spi_data_write(buf, size);
 991         if (result != N_OK) {
 992                 PRINT_ER("[wilc spi]: Failed block data write...\n");
 993         }
 994
 995         return 1;
 996 }
 997
 998 static int spi_read_reg(uint32_t addr, uint32_t *data)
 999 {
1000         int result = N_OK;
1001         uint8_t cmd = CMD_SINGLE_READ;
1002         uint8_t clockless = 0;
1003
1004 #if defined USE_OLD_SPI_SW
1005         result = spi_cmd(cmd, addr, 0, 4, 0);
1006         if (result != N_OK) {
1007                 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
1008                 return 0;
1009         }
1010         result = spi_cmd_rsp(cmd, 0);
1011         if (result != N_OK) {
1012                 PRINT_ER("[wilc spi]: Failed cmd response, read reg (%08x)...\n", addr);
1013                 return 0;
1014         }
1015
1016         result = spi_data_read((uint8_t *)data, 4);
1017         if (result != N_OK) {
1018                 PRINT_ER("[wilc spi]: Failed data read...\n");
1019                 return 0;
1020         }
1021 #else
1022         if (addr < 0x30) {
1023                 /* PRINT_ER("***** read addr %d\n\n", addr); */
1024                 /* Clockless register*/
1025                 cmd = CMD_INTERNAL_READ;
1026                 clockless = 1;
1027         }
1028
1029         result = spi_cmd_complete(cmd, addr, (uint8_t *)data, 4, clockless);
1030         if (result != N_OK) {
1031                 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
1032                 return 0;
1033         }
1034 #endif
1035
1036
1037 #ifdef BIG_ENDIAN
1038         *data = BYTE_SWAP(*data);
1039 #endif
1040
1041         return 1;
1042 }
1043
1044 static int spi_read(uint32_t addr, uint8_t *buf, uint32_t size)
1045 {
1046         uint8_t cmd = CMD_DMA_EXT_READ;
1047         int result;
1048
1049         if (size <= 4)
1050                 return 0;
1051
1052 #if defined USE_OLD_SPI_SW
1053         /**
1054          *      Command
1055          **/
1056         result = spi_cmd(cmd, addr, 0, size, 0);
1057         if (result != N_OK) {
1058                 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
1059                 return 0;
1060         }
1061
1062         result = spi_cmd_rsp(cmd, 0);
1063         if (result != N_OK) {
1064                 PRINT_ER("[wilc spi]: Failed cmd response, read block (%08x)...\n", addr);
1065                 return 0;
1066         }
1067
1068         /**
1069          *      Data
1070          **/
1071         result = spi_data_read(buf, size);
1072         if (result != N_OK) {
1073                 PRINT_ER("[wilc spi]: Failed block data read...\n");
1074                 return 0;
1075         }
1076 #else
1077         result = spi_cmd_complete(cmd, addr, buf, size, 0);
1078         if (result != N_OK) {
1079                 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
1080                 return 0;
1081         }
1082 #endif
1083
1084
1085         return 1;
1086 }
1087
1088 /********************************************
1089  *
1090  *      Bus interfaces
1091  *
1092  ********************************************/
1093
1094 static int spi_clear_int(void)
1095 {
1096         uint32_t reg;
1097         if (!spi_read_reg(WILC_HOST_RX_CTRL_0, &reg)) {
1098                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0);
1099                 return 0;
1100         }
1101         reg &= ~0x1;
1102         spi_write_reg(WILC_HOST_RX_CTRL_0, reg);
1103         int_clrd++;
1104         return 1;
1105 }
1106
1107 static int spi_deinit(void *pv)
1108 {
1109         /**
1110          *      TODO:
1111          **/
1112         return 1;
1113 }
1114
1115 static int spi_sync(void)
1116 {
1117         uint32_t reg;
1118         int ret;
1119
1120         /**
1121          *      interrupt pin mux select
1122          **/
1123         ret = spi_read_reg(WILC_PIN_MUX_0, &reg);
1124         if (!ret) {
1125                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1126                 return 0;
1127         }
1128         reg |= (1 << 8);
1129         ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1130         if (!ret) {
1131                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1132                 return 0;
1133         }
1134
1135         /**
1136          *      interrupt enable
1137          **/
1138         ret = spi_read_reg(WILC_INTR_ENABLE, &reg);
1139         if (!ret) {
1140                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1141                 return 0;
1142         }
1143         reg |= (1 << 16);
1144         ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1145         if (!ret) {
1146                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1147                 return 0;
1148         }
1149
1150         return 1;
1151 }
1152
1153 static int spi_init(wilc_wlan_inp_t *inp, wilc_debug_func func)
1154 {
1155         uint32_t reg;
1156         uint32_t chipid;
1157
1158         static int isinit;
1159
1160         if (isinit) {
1161
1162                 if (!spi_read_reg(0x1000, &chipid)) {
1163                         PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1164                         return 0;
1165                 }
1166                 return 1;
1167         }
1168
1169         memset(&g_spi, 0, sizeof(wilc_spi_t));
1170
1171         g_spi.dPrint = func;
1172         g_spi.os_context = inp->os_context.os_private;
1173         if (inp->io_func.io_init) {
1174                 if (!inp->io_func.io_init(g_spi.os_context)) {
1175                         PRINT_ER("[wilc spi]: Failed io init bus...\n");
1176                         return 0;
1177                 }
1178         } else {
1179                 return 0;
1180         }
1181         g_spi.spi_tx = inp->io_func.u.spi.spi_tx;
1182         g_spi.spi_rx = inp->io_func.u.spi.spi_rx;
1183         g_spi.spi_trx = inp->io_func.u.spi.spi_trx;
1184         g_spi.spi_max_speed = inp->io_func.u.spi.spi_max_speed;
1185
1186         /**
1187          *      configure protocol
1188          **/
1189         g_spi.crc_off = 0;
1190
1191         /* TODO: We can remove the CRC trials if there is a definite way to reset */
1192         /* the SPI to it's initial value. */
1193         if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, &reg)) {
1194                 /* Read failed. Try with CRC off. This might happen when module
1195                  * is removed but chip isn't reset*/
1196                 g_spi.crc_off = 1;
1197                 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
1198                 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, &reg)) {
1199                         /* Reaad failed with both CRC on and off, something went bad */
1200                         PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
1201                         return 0;
1202                 }
1203         }
1204         if (g_spi.crc_off == 0) {
1205                 reg &= ~0xc;    /* disable crc checking */
1206                 reg &= ~0x70;
1207                 reg |= (0x5 << 4);
1208                 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET, reg)) {
1209                         PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
1210                         return 0;
1211                 }
1212                 g_spi.crc_off = 1;
1213         }
1214
1215
1216         /**
1217          *      make sure can read back chip id correctly
1218          **/
1219         if (!spi_read_reg(0x1000, &chipid)) {
1220                 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1221                 return 0;
1222         }
1223         /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1224
1225         g_spi.has_thrpt_enh = 1;
1226
1227         isinit = 1;
1228
1229         return 1;
1230 }
1231
1232 static void spi_max_bus_speed(void)
1233 {
1234         g_spi.spi_max_speed();
1235 }
1236
1237 static void spi_default_bus_speed(void)
1238 {
1239 }
1240
1241 static int spi_read_size(uint32_t *size)
1242 {
1243         int ret;
1244         if (g_spi.has_thrpt_enh) {
1245                 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, size);
1246                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
1247         } else {
1248                 uint32_t tmp;
1249                 uint32_t byte_cnt;
1250
1251                 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1252                 if (!ret) {
1253                         PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1254                         goto _fail_;
1255                 }
1256                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1257                 *size = tmp;
1258         }
1259
1260
1261
1262 _fail_:
1263         return ret;
1264 }
1265
1266
1267
1268 static int spi_read_int(uint32_t *int_status)
1269 {
1270         int ret;
1271         if (g_spi.has_thrpt_enh) {
1272                 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, int_status);
1273         } else {
1274                 uint32_t tmp;
1275                 uint32_t byte_cnt;
1276
1277                 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1278                 if (!ret) {
1279                         PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1280                         goto _fail_;
1281                 }
1282                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1283
1284                 {
1285                         int happended, j;
1286
1287                         j = 0;
1288                         do {
1289                                 uint32_t irq_flags;
1290
1291                                 happended = 0;
1292
1293                                 spi_read_reg(0x1a90, &irq_flags);
1294                                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
1295
1296                                 if (g_spi.nint > 5) {
1297                                         spi_read_reg(0x1a94, &irq_flags);
1298                                         tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
1299                                 }
1300
1301                                 {
1302                                         uint32_t unkmown_mask;
1303
1304                                         unkmown_mask = ~((1ul << g_spi.nint) - 1);
1305
1306                                         if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
1307                                                 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
1308                                                 happended = 1;
1309                                         }
1310                                 }
1311                                 j++;
1312                         } while (happended);
1313                 }
1314
1315                 *int_status = tmp;
1316
1317         }
1318
1319 _fail_:
1320         return ret;
1321 }
1322
1323 static int spi_clear_int_ext(uint32_t val)
1324 {
1325         int ret;
1326
1327         if (g_spi.has_thrpt_enh) {
1328                 ret = spi_internal_write(0xe844 - WILC_SPI_REG_BASE, val);
1329         } else {
1330                 uint32_t flags;
1331                 flags = val & ((1 << MAX_NUM_INT) - 1);
1332                 if (flags) {
1333                         int i;
1334
1335                         ret = 1;
1336                         for (i = 0; i < g_spi.nint; i++) {
1337                                 /* No matter what you write 1 or 0, it will clear interrupt. */
1338                                 if (flags & 1)
1339                                         ret = spi_write_reg(0x10c8 + i * 4, 1);
1340                                 if (!ret)
1341                                         break;
1342                                 flags >>= 1;
1343                         }
1344                         if (!ret) {
1345                                 PRINT_ER("[wilc spi]: Failed spi_write_reg, set reg %x ...\n", 0x10c8 + i * 4);
1346                                 goto _fail_;
1347                         }
1348                         for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1349                                 if (flags & 1)
1350                                         PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i);
1351                                 flags >>= 1;
1352                         }
1353                 }
1354
1355                 {
1356                         uint32_t tbl_ctl;
1357
1358                         tbl_ctl = 0;
1359                         /* select VMM table 0 */
1360                         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1361                                 tbl_ctl |= (1 << 0);
1362                         /* select VMM table 1 */
1363                         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1364                                 tbl_ctl |= (1 << 1);
1365
1366                         ret = spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);
1367                         if (!ret) {
1368                                 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1369                                 goto _fail_;
1370                         }
1371
1372                         if ((val & EN_VMM) == EN_VMM) {
1373                                 /**
1374                                  *      enable vmm transfer.
1375                                  **/
1376                                 ret = spi_write_reg(WILC_VMM_CORE_CTL, 1);
1377                                 if (!ret) {
1378                                         PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1379                                         goto _fail_;
1380                                 }
1381                         }
1382                 }
1383         }
1384 _fail_:
1385         return ret;
1386 }
1387
1388 static int spi_sync_ext(int nint /*  how mant interrupts to enable. */)
1389 {
1390         uint32_t reg;
1391         int ret, i;
1392
1393         if (nint > MAX_NUM_INT) {
1394                 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint);
1395                 return 0;
1396         }
1397
1398         g_spi.nint = nint;
1399
1400         /**
1401          *      interrupt pin mux select
1402          **/
1403         ret = spi_read_reg(WILC_PIN_MUX_0, &reg);
1404         if (!ret) {
1405                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1406                 return 0;
1407         }
1408         reg |= (1 << 8);
1409         ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1410         if (!ret) {
1411                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1412                 return 0;
1413         }
1414
1415         /**
1416          *      interrupt enable
1417          **/
1418         ret = spi_read_reg(WILC_INTR_ENABLE, &reg);
1419         if (!ret) {
1420                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1421                 return 0;
1422         }
1423
1424         for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1425                 reg |= (1 << (27 + i));
1426         }
1427         ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1428         if (!ret) {
1429                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1430                 return 0;
1431         }
1432         if (nint) {
1433                 ret = spi_read_reg(WILC_INTR2_ENABLE, &reg);
1434                 if (!ret) {
1435                         PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE);
1436                         return 0;
1437                 }
1438
1439                 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1440                         reg |= (1 << i);
1441                 }
1442
1443                 ret = spi_read_reg(WILC_INTR2_ENABLE, &reg);
1444                 if (!ret) {
1445                         PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE);
1446                         return 0;
1447                 }
1448         }
1449
1450         return 1;
1451 }
1452 /********************************************
1453  *
1454  *      Global spi HIF function table
1455  *
1456  ********************************************/
1457 wilc_hif_func_t hif_spi = {
1458         spi_init,
1459         spi_deinit,
1460         spi_read_reg,
1461         spi_write_reg,
1462         spi_read,
1463         spi_write,
1464         spi_sync,
1465         spi_clear_int,
1466         spi_read_int,
1467         spi_clear_int_ext,
1468         spi_read_size,
1469         spi_write,
1470         spi_read,
1471         spi_sync_ext,
1472         spi_max_bus_speed,
1473         spi_default_bus_speed,
1474 };
1475