1 /* ////////////////////////////////////////////////////////////////////////// */
3 /* Copyright (c) Atmel Corporation. All rights reserved. */
5 /* Module Name: wilc_spi.c */
8 /* //////////////////////////////////////////////////////////////////////////// */
10 #include "wilc_wlan_if.h"
11 #include "wilc_wlan.h"
13 extern unsigned int int_clrd;
16 * #include <linux/kernel.h>
17 * #include <linux/string.h>
21 int (*spi_tx)(uint8_t *, uint32_t);
22 int (*spi_rx)(uint8_t *, uint32_t);
23 int (*spi_trx)(uint8_t *, uint8_t *, uint32_t);
24 int (*spi_max_speed)(void);
25 wilc_debug_func dPrint;
31 static wilc_spi_t g_spi;
33 static int spi_read(uint32_t, uint8_t *, uint32_t);
34 static int spi_write(uint32_t, uint8_t *, uint32_t);
36 /********************************************
40 ********************************************/
42 static const uint8_t crc7_syndrome_table[256] = {
43 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
44 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
45 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
46 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
47 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
48 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
49 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
50 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
51 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
52 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
53 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
54 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
55 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
56 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
57 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
58 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
59 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
60 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
61 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
62 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
63 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
64 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
65 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
66 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
67 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
68 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
69 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
70 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
71 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
72 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
73 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
74 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
77 static uint8_t crc7_byte(uint8_t crc, uint8_t data)
79 return crc7_syndrome_table[(crc << 1) ^ data];
82 static uint8_t crc7(uint8_t crc, const uint8_t *buffer, uint32_t len)
85 crc = crc7_byte(crc, *buffer++);
89 /********************************************
91 * Spi protocol Function
93 ********************************************/
95 #define CMD_DMA_WRITE 0xc1
96 #define CMD_DMA_READ 0xc2
97 #define CMD_INTERNAL_WRITE 0xc3
98 #define CMD_INTERNAL_READ 0xc4
99 #define CMD_TERMINATE 0xc5
100 #define CMD_REPEAT 0xc6
101 #define CMD_DMA_EXT_WRITE 0xc7
102 #define CMD_DMA_EXT_READ 0xc8
103 #define CMD_SINGLE_WRITE 0xc9
104 #define CMD_SINGLE_READ 0xca
105 #define CMD_RESET 0xcf
112 #define DATA_PKT_SZ_256 256
113 #define DATA_PKT_SZ_512 512
114 #define DATA_PKT_SZ_1K 1024
115 #define DATA_PKT_SZ_4K (4 * 1024)
116 #define DATA_PKT_SZ_8K (8 * 1024)
117 #define DATA_PKT_SZ DATA_PKT_SZ_8K
119 static int spi_cmd(uint8_t cmd, uint32_t adr, uint32_t data, uint32_t sz, uint8_t clockless)
127 case CMD_SINGLE_READ: /* single word (4 bytes) read */
128 bc[1] = (uint8_t)(adr >> 16);
129 bc[2] = (uint8_t)(adr >> 8);
130 bc[3] = (uint8_t)adr;
134 case CMD_INTERNAL_READ: /* internal register read */
135 bc[1] = (uint8_t)(adr >> 8);
138 bc[2] = (uint8_t)adr;
143 case CMD_TERMINATE: /* termination */
150 case CMD_REPEAT: /* repeat */
157 case CMD_RESET: /* reset */
164 case CMD_DMA_WRITE: /* dma write */
165 case CMD_DMA_READ: /* dma read */
166 bc[1] = (uint8_t)(adr >> 16);
167 bc[2] = (uint8_t)(adr >> 8);
168 bc[3] = (uint8_t)adr;
169 bc[4] = (uint8_t)(sz >> 8);
170 bc[5] = (uint8_t)(sz);
174 case CMD_DMA_EXT_WRITE: /* dma extended write */
175 case CMD_DMA_EXT_READ: /* dma extended read */
176 bc[1] = (uint8_t)(adr >> 16);
177 bc[2] = (uint8_t)(adr >> 8);
178 bc[3] = (uint8_t)adr;
179 bc[4] = (uint8_t)(sz >> 16);
180 bc[5] = (uint8_t)(sz >> 8);
181 bc[6] = (uint8_t)(sz);
185 case CMD_INTERNAL_WRITE: /* internal register write */
186 bc[1] = (uint8_t)(adr >> 8);
189 bc[2] = (uint8_t)(adr);
190 bc[3] = (uint8_t)(data >> 24);
191 bc[4] = (uint8_t)(data >> 16);
192 bc[5] = (uint8_t)(data >> 8);
193 bc[6] = (uint8_t)(data);
197 case CMD_SINGLE_WRITE: /* single word write */
198 bc[1] = (uint8_t)(adr >> 16);
199 bc[2] = (uint8_t)(adr >> 8);
200 bc[3] = (uint8_t)(adr);
201 bc[4] = (uint8_t)(data >> 24);
202 bc[5] = (uint8_t)(data >> 16);
203 bc[6] = (uint8_t)(data >> 8);
204 bc[7] = (uint8_t)(data);
215 bc[len - 1] = (crc7(0x7f, (const uint8_t *)&bc[0], len - 1)) << 1;
219 if (!g_spi.spi_tx(bc, len)) {
220 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
228 static int spi_cmd_rsp(uint8_t cmd)
234 * Command/Control response
236 if ((cmd == CMD_RESET) ||
237 (cmd == CMD_TERMINATE) ||
238 (cmd == CMD_REPEAT)) {
239 if (!g_spi.spi_rx(&rsp, 1)) {
245 if (!g_spi.spi_rx(&rsp, 1)) {
246 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
252 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
260 if (!g_spi.spi_rx(&rsp, 1)) {
261 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
267 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp);
276 static int spi_cmd_complete(uint8_t cmd, uint32_t adr, uint8_t *b, uint32_t sz, uint8_t clockless)
278 uint8_t wb[32], rb[32];
287 case CMD_SINGLE_READ: /* single word (4 bytes) read */
288 wb[1] = (uint8_t)(adr >> 16);
289 wb[2] = (uint8_t)(adr >> 8);
290 wb[3] = (uint8_t)adr;
294 case CMD_INTERNAL_READ: /* internal register read */
295 wb[1] = (uint8_t)(adr >> 8);
298 wb[2] = (uint8_t)adr;
303 case CMD_TERMINATE: /* termination */
310 case CMD_REPEAT: /* repeat */
317 case CMD_RESET: /* reset */
324 case CMD_DMA_WRITE: /* dma write */
325 case CMD_DMA_READ: /* dma read */
326 wb[1] = (uint8_t)(adr >> 16);
327 wb[2] = (uint8_t)(adr >> 8);
328 wb[3] = (uint8_t)adr;
329 wb[4] = (uint8_t)(sz >> 8);
330 wb[5] = (uint8_t)(sz);
334 case CMD_DMA_EXT_WRITE: /* dma extended write */
335 case CMD_DMA_EXT_READ: /* dma extended read */
336 wb[1] = (uint8_t)(adr >> 16);
337 wb[2] = (uint8_t)(adr >> 8);
338 wb[3] = (uint8_t)adr;
339 wb[4] = (uint8_t)(sz >> 16);
340 wb[5] = (uint8_t)(sz >> 8);
341 wb[6] = (uint8_t)(sz);
345 case CMD_INTERNAL_WRITE: /* internal register write */
346 wb[1] = (uint8_t)(adr >> 8);
349 wb[2] = (uint8_t)(adr);
357 case CMD_SINGLE_WRITE: /* single word write */
358 wb[1] = (uint8_t)(adr >> 16);
359 wb[2] = (uint8_t)(adr >> 8);
360 wb[3] = (uint8_t)(adr);
373 if (result != N_OK) {
377 if (!g_spi.crc_off) {
378 wb[len - 1] = (crc7(0x7f, (const uint8_t *)&wb[0], len - 1)) << 1;
383 #define NUM_SKIP_BYTES (1)
384 #define NUM_RSP_BYTES (2)
385 #define NUM_DATA_HDR_BYTES (1)
386 #define NUM_DATA_BYTES (4)
387 #define NUM_CRC_BYTES (2)
388 #define NUM_DUMMY_BYTES (3)
389 if ((cmd == CMD_RESET) ||
390 (cmd == CMD_TERMINATE) ||
391 (cmd == CMD_REPEAT)) {
392 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
393 } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
394 if (!g_spi.crc_off) {
395 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
396 + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
398 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
402 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
404 #undef NUM_DUMMY_BYTES
406 if (len2 > (sizeof(wb) / sizeof(wb[0]))) {
407 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%lu)\n",
408 len2, (sizeof(wb) / sizeof(wb[0])));
412 /* zero spi write buffers. */
413 for (wix = len; wix < len2; wix++) {
418 if (!g_spi.spi_trx(wb, rb, len2)) {
419 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
427 PRINT_D(BUS_DBG, "--- cnd = %x, len=%d, len2=%d\n", cmd, len, len2);
428 for (jj = 0; jj < sizeof(wb) / sizeof(wb[0]); jj++) {
432 if (((jj + 1) % 16) != 0) {
433 if ((jj % 16) == 0) {
434 PRINT_D(BUS_DBG, "wb[%02x]: %02x ", jj, wb[jj]);
436 PRINT_D(BUS_DBG, "%02x ", wb[jj]);
439 PRINT_D(BUS_DBG, "%02x\n", wb[jj]);
443 for (jj = 0; jj < sizeof(rb) / sizeof(rb[0]); jj++) {
447 if (((jj + 1) % 16) != 0) {
448 if ((jj % 16) == 0) {
449 PRINT_D(BUS_DBG, "rb[%02x]: %02x ", jj, rb[jj]);
451 PRINT_D(BUS_DBG, "%02x ", rb[jj]);
454 PRINT_D(BUS_DBG, "%02x\n", rb[jj]);
461 * Command/Control response
463 if ((cmd == CMD_RESET) ||
464 (cmd == CMD_TERMINATE) ||
465 (cmd == CMD_REPEAT)) {
466 rix++; /* skip 1 byte */
471 /* if(rsp == cmd) break; */
472 /* } while(&rptr[1] <= &rb[len2]); */
475 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
476 ", resp (%02x)\n", cmd, rsp);
486 PRINT_ER("[wilc spi]: Failed cmd state response "
487 "state (%02x)\n", rsp);
492 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
493 || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
495 /* uint16_t crc1, crc2; */
498 * Data Respnose header
502 /* ensure there is room in buffer later to read data and crc */
509 if (((rsp >> 4) & 0xf) == 0xf)
514 PRINT_ER("[wilc spi]: Error, data read "
515 "response (%02x)\n", rsp);
520 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
524 if ((rix + 3) < len2) {
530 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
535 if (!g_spi.crc_off) {
539 if ((rix + 1) < len2) {
543 PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
548 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
551 /* some data may be read in response to dummy bytes. */
552 for (ix = 0; (rix < len2) && (ix < sz); ) {
557 PRINT_D(BUS_DBG, "ttt %d %d\n", sz, ix);
564 if (sz <= (DATA_PKT_SZ - ix)) {
567 nbytes = DATA_PKT_SZ - ix;
573 if (!g_spi.spi_rx(&b[ix], nbytes)) {
574 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
582 if (!g_spi.crc_off) {
583 if (!g_spi.spi_rx(crc, 2)) {
584 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
595 /* if any data in left unread, then read the rest using normal DMA code.*/
600 PRINT_INFO(BUS_DBG, "rrr %d %d\n", sz, ix);
602 if (sz <= DATA_PKT_SZ) {
605 nbytes = DATA_PKT_SZ;
609 * read data response only on the next DMA cycles not
610 * the first DMA since data response header is already
611 * handled above for the first DMA.
614 * Data Respnose header
618 if (!g_spi.spi_rx(&rsp, 1)) {
619 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
623 if (((rsp >> 4) & 0xf) == 0xf)
627 if (result == N_FAIL)
634 if (!g_spi.spi_rx(&b[ix], nbytes)) {
635 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
643 if (!g_spi.crc_off) {
644 if (!g_spi.spi_rx(crc, 2)) {
645 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
660 static int spi_data_read(uint8_t *b, uint32_t sz)
662 int retry, ix, nbytes;
672 if (sz <= DATA_PKT_SZ)
675 nbytes = DATA_PKT_SZ;
678 * Data Respnose header
682 if (!g_spi.spi_rx(&rsp, 1)) {
683 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
687 if (((rsp >> 4) & 0xf) == 0xf)
691 if (result == N_FAIL)
695 PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp);
703 if (!g_spi.spi_rx(&b[ix], nbytes)) {
704 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
712 if (!g_spi.crc_off) {
713 if (!g_spi.spi_rx(crc, 2)) {
714 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
728 static int spi_data_write(uint8_t *b, uint32_t sz)
732 uint8_t cmd, order, crc[2] = {0};
740 if (sz <= DATA_PKT_SZ)
743 nbytes = DATA_PKT_SZ;
750 if (sz <= DATA_PKT_SZ)
756 if (sz <= DATA_PKT_SZ)
762 if (!g_spi.spi_tx(&cmd, 1)) {
763 PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
771 if (!g_spi.spi_tx(&b[ix], nbytes)) {
772 PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
780 if (!g_spi.crc_off) {
781 if (!g_spi.spi_tx(crc, 2)) {
782 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
789 * No need to wait for response
795 if (!g_spi.spi_rx(&rsp, 1)) {
796 PRINT_ER("[wilc spi]: Failed data block write, response read, bus error...\n");
801 if (((rsp >> 4) & 0xf) != 0xc) {
803 PRINT_ER("[wilc spi]: Failed data block write response...(%02x)\n", rsp);
810 if (!g_spi.spi_rx(&rsp, 1)) {
811 PRINT_ER("[wilc spi]: Failed data block write, read state, bus error...\n");
825 /********************************************
827 * Spi Internal Read/Write Function
829 ********************************************/
831 static int spi_internal_write(uint32_t adr, uint32_t dat)
835 #if defined USE_OLD_SPI_SW
839 result = spi_cmd(CMD_INTERNAL_WRITE, adr, dat, 4, 0);
840 if (result != N_OK) {
841 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
845 result = spi_cmd_rsp(CMD_INTERNAL_WRITE, 0);
846 if (result != N_OK) {
847 PRINT_ER("[wilc spi]: Failed internal write cmd response...\n");
852 dat = BYTE_SWAP(dat);
854 result = spi_cmd_complete(CMD_INTERNAL_WRITE, adr, (uint8_t *)&dat, 4, 0);
855 if (result != N_OK) {
856 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
863 static int spi_internal_read(uint32_t adr, uint32_t *data)
867 #if defined USE_OLD_SPI_SW
868 result = spi_cmd(CMD_INTERNAL_READ, adr, 0, 4, 0);
869 if (result != N_OK) {
870 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
874 result = spi_cmd_rsp(CMD_INTERNAL_READ, 0);
875 if (result != N_OK) {
876 PRINT_ER("[wilc spi]: Failed internal read cmd response...\n");
883 result = spi_data_read((uint8_t *)data, 4);
884 if (result != N_OK) {
885 PRINT_ER("[wilc spi]: Failed internal read data...\n");
889 result = spi_cmd_complete(CMD_INTERNAL_READ, adr, (uint8_t *)data, 4, 0);
890 if (result != N_OK) {
891 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
898 *data = BYTE_SWAP(*data);
904 /********************************************
908 ********************************************/
910 static int spi_write_reg(uint32_t addr, uint32_t data)
913 uint8_t cmd = CMD_SINGLE_WRITE;
914 uint8_t clockless = 0;
917 #if defined USE_OLD_SPI_SW
919 result = spi_cmd(cmd, addr, data, 4, 0);
920 if (result != N_OK) {
921 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
925 result = spi_cmd_rsp(cmd, 0);
926 if (result != N_OK) {
927 PRINT_ER("[wilc spi]: Failed cmd response, write reg (%08x)...\n", addr);
935 data = BYTE_SWAP(data);
938 /* Clockless register*/
939 cmd = CMD_INTERNAL_WRITE;
943 result = spi_cmd_complete(cmd, addr, (uint8_t *)&data, 4, clockless);
944 if (result != N_OK) {
945 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
953 static int spi_write(uint32_t addr, uint8_t *buf, uint32_t size)
956 uint8_t cmd = CMD_DMA_EXT_WRITE;
959 * has to be greated than 4
964 #if defined USE_OLD_SPI_SW
968 result = spi_cmd(cmd, addr, 0, size, 0);
969 if (result != N_OK) {
970 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
974 result = spi_cmd_rsp(cmd, 0);
975 if (result != N_OK) {
976 PRINT_ER("[wilc spi ]: Failed cmd response, write block (%08x)...\n", addr);
980 result = spi_cmd_complete(cmd, addr, NULL, size, 0);
981 if (result != N_OK) {
982 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
990 result = spi_data_write(buf, size);
991 if (result != N_OK) {
992 PRINT_ER("[wilc spi]: Failed block data write...\n");
998 static int spi_read_reg(uint32_t addr, uint32_t *data)
1001 uint8_t cmd = CMD_SINGLE_READ;
1002 uint8_t clockless = 0;
1004 #if defined USE_OLD_SPI_SW
1005 result = spi_cmd(cmd, addr, 0, 4, 0);
1006 if (result != N_OK) {
1007 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
1010 result = spi_cmd_rsp(cmd, 0);
1011 if (result != N_OK) {
1012 PRINT_ER("[wilc spi]: Failed cmd response, read reg (%08x)...\n", addr);
1016 result = spi_data_read((uint8_t *)data, 4);
1017 if (result != N_OK) {
1018 PRINT_ER("[wilc spi]: Failed data read...\n");
1023 /* PRINT_ER("***** read addr %d\n\n", addr); */
1024 /* Clockless register*/
1025 cmd = CMD_INTERNAL_READ;
1029 result = spi_cmd_complete(cmd, addr, (uint8_t *)data, 4, clockless);
1030 if (result != N_OK) {
1031 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
1038 *data = BYTE_SWAP(*data);
1044 static int spi_read(uint32_t addr, uint8_t *buf, uint32_t size)
1046 uint8_t cmd = CMD_DMA_EXT_READ;
1052 #if defined USE_OLD_SPI_SW
1056 result = spi_cmd(cmd, addr, 0, size, 0);
1057 if (result != N_OK) {
1058 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
1062 result = spi_cmd_rsp(cmd, 0);
1063 if (result != N_OK) {
1064 PRINT_ER("[wilc spi]: Failed cmd response, read block (%08x)...\n", addr);
1071 result = spi_data_read(buf, size);
1072 if (result != N_OK) {
1073 PRINT_ER("[wilc spi]: Failed block data read...\n");
1077 result = spi_cmd_complete(cmd, addr, buf, size, 0);
1078 if (result != N_OK) {
1079 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
1088 /********************************************
1092 ********************************************/
1094 static int spi_clear_int(void)
1097 if (!spi_read_reg(WILC_HOST_RX_CTRL_0, ®)) {
1098 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0);
1102 spi_write_reg(WILC_HOST_RX_CTRL_0, reg);
1107 static int spi_deinit(void *pv)
1115 static int spi_sync(void)
1121 * interrupt pin mux select
1123 ret = spi_read_reg(WILC_PIN_MUX_0, ®);
1125 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1129 ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1131 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1138 ret = spi_read_reg(WILC_INTR_ENABLE, ®);
1140 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1144 ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1146 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1153 static int spi_init(wilc_wlan_inp_t *inp, wilc_debug_func func)
1162 if (!spi_read_reg(0x1000, &chipid)) {
1163 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1169 memset(&g_spi, 0, sizeof(wilc_spi_t));
1171 g_spi.dPrint = func;
1172 g_spi.os_context = inp->os_context.os_private;
1173 if (inp->io_func.io_init) {
1174 if (!inp->io_func.io_init(g_spi.os_context)) {
1175 PRINT_ER("[wilc spi]: Failed io init bus...\n");
1181 g_spi.spi_tx = inp->io_func.u.spi.spi_tx;
1182 g_spi.spi_rx = inp->io_func.u.spi.spi_rx;
1183 g_spi.spi_trx = inp->io_func.u.spi.spi_trx;
1184 g_spi.spi_max_speed = inp->io_func.u.spi.spi_max_speed;
1187 * configure protocol
1191 /* TODO: We can remove the CRC trials if there is a definite way to reset */
1192 /* the SPI to it's initial value. */
1193 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, ®)) {
1194 /* Read failed. Try with CRC off. This might happen when module
1195 * is removed but chip isn't reset*/
1197 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
1198 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, ®)) {
1199 /* Reaad failed with both CRC on and off, something went bad */
1200 PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
1204 if (g_spi.crc_off == 0) {
1205 reg &= ~0xc; /* disable crc checking */
1208 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET, reg)) {
1209 PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
1217 * make sure can read back chip id correctly
1219 if (!spi_read_reg(0x1000, &chipid)) {
1220 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1223 /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1225 g_spi.has_thrpt_enh = 1;
1232 static void spi_max_bus_speed(void)
1234 g_spi.spi_max_speed();
1237 static void spi_default_bus_speed(void)
1241 static int spi_read_size(uint32_t *size)
1244 if (g_spi.has_thrpt_enh) {
1245 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, size);
1246 *size = *size & IRQ_DMA_WD_CNT_MASK;
1251 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1253 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1256 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1268 static int spi_read_int(uint32_t *int_status)
1271 if (g_spi.has_thrpt_enh) {
1272 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, int_status);
1277 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1279 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1282 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1293 spi_read_reg(0x1a90, &irq_flags);
1294 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
1296 if (g_spi.nint > 5) {
1297 spi_read_reg(0x1a94, &irq_flags);
1298 tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
1302 uint32_t unkmown_mask;
1304 unkmown_mask = ~((1ul << g_spi.nint) - 1);
1306 if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
1307 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
1312 } while (happended);
1323 static int spi_clear_int_ext(uint32_t val)
1327 if (g_spi.has_thrpt_enh) {
1328 ret = spi_internal_write(0xe844 - WILC_SPI_REG_BASE, val);
1331 flags = val & ((1 << MAX_NUM_INT) - 1);
1336 for (i = 0; i < g_spi.nint; i++) {
1337 /* No matter what you write 1 or 0, it will clear interrupt. */
1339 ret = spi_write_reg(0x10c8 + i * 4, 1);
1345 PRINT_ER("[wilc spi]: Failed spi_write_reg, set reg %x ...\n", 0x10c8 + i * 4);
1348 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1350 PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i);
1359 /* select VMM table 0 */
1360 if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1361 tbl_ctl |= (1 << 0);
1362 /* select VMM table 1 */
1363 if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1364 tbl_ctl |= (1 << 1);
1366 ret = spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);
1368 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1372 if ((val & EN_VMM) == EN_VMM) {
1374 * enable vmm transfer.
1376 ret = spi_write_reg(WILC_VMM_CORE_CTL, 1);
1378 PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1388 static int spi_sync_ext(int nint /* how mant interrupts to enable. */)
1393 if (nint > MAX_NUM_INT) {
1394 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint);
1401 * interrupt pin mux select
1403 ret = spi_read_reg(WILC_PIN_MUX_0, ®);
1405 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1409 ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1411 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1418 ret = spi_read_reg(WILC_INTR_ENABLE, ®);
1420 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1424 for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1425 reg |= (1 << (27 + i));
1427 ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1429 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1433 ret = spi_read_reg(WILC_INTR2_ENABLE, ®);
1435 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE);
1439 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1443 ret = spi_read_reg(WILC_INTR2_ENABLE, ®);
1445 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE);
1452 /********************************************
1454 * Global spi HIF function table
1456 ********************************************/
1457 wilc_hif_func_t hif_spi = {
1473 spi_default_bus_speed,