drivers/staging/wilc1000/wilc_spi.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_spi.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/fs.h>
  13 #include <linux/slab.h>
  14 #include <linux/types.h>
  15 #include <linux/cdev.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/device.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/of_gpio.h>
  20
  21 #include <linux/string.h>
  22 #include "wilc_wlan_if.h"
  23 #include "wilc_wlan.h"
  24 #include "wilc_wfi_netdevice.h"
  25
  26 struct wilc_spi {
  27         int crc_off;
  28         int nint;
  29         int has_thrpt_enh;
  30 };
  31
  32 static struct wilc_spi g_spi;
  33
  34 static int wilc_spi_read(struct wilc *wilc, u32, u8 *, u32);
  35 static int wilc_spi_write(struct wilc *wilc, u32, u8 *, u32);
  36
  37 /********************************************
  38  *
  39  *      Crc7
  40  *
  41  ********************************************/
  42
  43 static const u8 crc7_syndrome_table[256] = {
  44         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  45         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  46         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  47         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  48         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  49         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  50         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  51         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  52         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  53         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  54         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  55         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  56         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  57         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  58         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  59         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  60         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  61         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  62         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  63         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  64         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  65         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  66         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  67         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  68         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  69         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  70         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  71         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  72         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  73         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  74         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  75         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  76 };
  77
  78 static u8 crc7_byte(u8 crc, u8 data)
  79 {
  80         return crc7_syndrome_table[(crc << 1) ^ data];
  81 }
  82
  83 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  84 {
  85         while (len--)
  86                 crc = crc7_byte(crc, *buffer++);
  87         return crc;
  88 }
  89
  90 /********************************************
  91  *
  92  *      Spi protocol Function
  93  *
  94  ********************************************/
  95
  96 #define CMD_DMA_WRITE                           0xc1
  97 #define CMD_DMA_READ                            0xc2
  98 #define CMD_INTERNAL_WRITE              0xc3
  99 #define CMD_INTERNAL_READ               0xc4
 100 #define CMD_TERMINATE                           0xc5
 101 #define CMD_REPEAT                                      0xc6
 102 #define CMD_DMA_EXT_WRITE               0xc7
 103 #define CMD_DMA_EXT_READ                0xc8
 104 #define CMD_SINGLE_WRITE                        0xc9
 105 #define CMD_SINGLE_READ                 0xca
 106 #define CMD_RESET                                               0xcf
 107
 108 #define N_OK                                                            1
 109 #define N_FAIL                                                          0
 110 #define N_RESET                                                 -1
 111 #define N_RETRY                                                 -2
 112
 113 #define DATA_PKT_SZ_256                         256
 114 #define DATA_PKT_SZ_512                 512
 115 #define DATA_PKT_SZ_1K                          1024
 116 #define DATA_PKT_SZ_4K                          (4 * 1024)
 117 #define DATA_PKT_SZ_8K                          (8 * 1024)
 118 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 119
 120 #define USE_SPI_DMA     0
 121
 122 static int wilc_bus_probe(struct spi_device *spi)
 123 {
 124         int ret, gpio;
 125         struct wilc *wilc;
 126
 127         gpio = of_get_gpio(spi->dev.of_node, 0);
 128         if (gpio < 0)
 129                 gpio = GPIO_NUM;
 130
 131         ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
 132         if (ret)
 133                 return ret;
 134
 135         spi_set_drvdata(spi, wilc);
 136         wilc->dev = &spi->dev;
 137
 138         return 0;
 139 }
 140
 141 static int wilc_bus_remove(struct spi_device *spi)
 142 {
 143         wilc_netdev_cleanup(spi_get_drvdata(spi));
 144         return 0;
 145 }
 146
 147 static const struct of_device_id wilc1000_of_match[] = {
 148         { .compatible = "atmel,wilc_spi", },
 149         {}
 150 };
 151 MODULE_DEVICE_TABLE(of, wilc1000_of_match);
 152
 153 static struct spi_driver wilc1000_spi_driver = {
 154         .driver = {
 155                 .name = MODALIAS,
 156                 .of_match_table = wilc1000_of_match,
 157         },
 158         .probe =  wilc_bus_probe,
 159         .remove = wilc_bus_remove,
 160 };
 161 module_spi_driver(wilc1000_spi_driver);
 162 MODULE_LICENSE("GPL");
 163
 164 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 165 {
 166         struct spi_device *spi = to_spi_device(wilc->dev);
 167         int ret;
 168         struct spi_message msg;
 169
 170         if (len > 0 && b) {
 171                 struct spi_transfer tr = {
 172                         .tx_buf = b,
 173                         .len = len,
 174                         .delay_usecs = 0,
 175                 };
 176                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 177
 178                 if (!r_buffer)
 179                         return -ENOMEM;
 180
 181                 tr.rx_buf = r_buffer;
 182                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 183
 184                 memset(&msg, 0, sizeof(msg));
 185                 spi_message_init(&msg);
 186                 msg.spi = spi;
 187                 msg.is_dma_mapped = USE_SPI_DMA;
 188                 spi_message_add_tail(&tr, &msg);
 189
 190                 ret = spi_sync(spi, &msg);
 191                 if (ret < 0)
 192                         dev_err(&spi->dev, "SPI transaction failed\n");
 193
 194                 kfree(r_buffer);
 195         } else {
 196                 dev_err(&spi->dev,
 197                         "can't write data with the following length: %d\n",
 198                         len);
 199                 dev_err(&spi->dev,
 200                         "FAILED due to NULL buffer or ZERO length check the following length: %d\n",
 201                         len);
 202                 ret = -EINVAL;
 203         }
 204
 205         return ret;
 206 }
 207
 208 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 209 {
 210         struct spi_device *spi = to_spi_device(wilc->dev);
 211         int ret;
 212
 213         if (rlen > 0) {
 214                 struct spi_message msg;
 215                 struct spi_transfer tr = {
 216                         .rx_buf = rb,
 217                         .len = rlen,
 218                         .delay_usecs = 0,
 219
 220                 };
 221                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 222
 223                 if (!t_buffer)
 224                         return -ENOMEM;
 225
 226                 tr.tx_buf = t_buffer;
 227
 228                 memset(&msg, 0, sizeof(msg));
 229                 spi_message_init(&msg);
 230                 msg.spi = spi;
 231                 msg.is_dma_mapped = USE_SPI_DMA;
 232                 spi_message_add_tail(&tr, &msg);
 233
 234                 ret = spi_sync(spi, &msg);
 235                 if (ret < 0)
 236                         dev_err(&spi->dev, "SPI transaction failed\n");
 237                 kfree(t_buffer);
 238         } else {
 239                 dev_err(&spi->dev,
 240                         "can't read data with the following length: %u\n",
 241                         rlen);
 242                 ret = -EINVAL;
 243         }
 244
 245         return ret;
 246 }
 247
 248 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 249 {
 250         struct spi_device *spi = to_spi_device(wilc->dev);
 251         int ret;
 252
 253         if (rlen > 0) {
 254                 struct spi_message msg;
 255                 struct spi_transfer tr = {
 256                         .rx_buf = rb,
 257                         .tx_buf = wb,
 258                         .len = rlen,
 259                         .bits_per_word = 8,
 260                         .delay_usecs = 0,
 261
 262                 };
 263
 264                 memset(&msg, 0, sizeof(msg));
 265                 spi_message_init(&msg);
 266                 msg.spi = spi;
 267                 msg.is_dma_mapped = USE_SPI_DMA;
 268
 269                 spi_message_add_tail(&tr, &msg);
 270                 ret = spi_sync(spi, &msg);
 271                 if (ret < 0)
 272                         dev_err(&spi->dev, "SPI transaction failed\n");
 273         } else {
 274                 dev_err(&spi->dev,
 275                         "can't read data with the following length: %u\n",
 276                         rlen);
 277                 ret = -EINVAL;
 278         }
 279
 280         return ret;
 281 }
 282
 283 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 284                             u8 clockless)
 285 {
 286         struct spi_device *spi = to_spi_device(wilc->dev);
 287         u8 wb[32], rb[32];
 288         u8 wix, rix;
 289         u32 len2;
 290         u8 rsp;
 291         int len = 0;
 292         int result = N_OK;
 293
 294         wb[0] = cmd;
 295         switch (cmd) {
 296         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 297                 wb[1] = (u8)(adr >> 16);
 298                 wb[2] = (u8)(adr >> 8);
 299                 wb[3] = (u8)adr;
 300                 len = 5;
 301                 break;
 302
 303         case CMD_INTERNAL_READ:                 /* internal register read */
 304                 wb[1] = (u8)(adr >> 8);
 305                 if (clockless == 1)
 306                         wb[1] |= BIT(7);
 307                 wb[2] = (u8)adr;
 308                 wb[3] = 0x00;
 309                 len = 5;
 310                 break;
 311
 312         case CMD_TERMINATE:                                     /* termination */
 313                 wb[1] = 0x00;
 314                 wb[2] = 0x00;
 315                 wb[3] = 0x00;
 316                 len = 5;
 317                 break;
 318
 319         case CMD_REPEAT:                                                /* repeat */
 320                 wb[1] = 0x00;
 321                 wb[2] = 0x00;
 322                 wb[3] = 0x00;
 323                 len = 5;
 324                 break;
 325
 326         case CMD_RESET:                                                 /* reset */
 327                 wb[1] = 0xff;
 328                 wb[2] = 0xff;
 329                 wb[3] = 0xff;
 330                 len = 5;
 331                 break;
 332
 333         case CMD_DMA_WRITE:                                     /* dma write */
 334         case CMD_DMA_READ:                                      /* dma read */
 335                 wb[1] = (u8)(adr >> 16);
 336                 wb[2] = (u8)(adr >> 8);
 337                 wb[3] = (u8)adr;
 338                 wb[4] = (u8)(sz >> 8);
 339                 wb[5] = (u8)(sz);
 340                 len = 7;
 341                 break;
 342
 343         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 344         case CMD_DMA_EXT_READ:                  /* dma extended read */
 345                 wb[1] = (u8)(adr >> 16);
 346                 wb[2] = (u8)(adr >> 8);
 347                 wb[3] = (u8)adr;
 348                 wb[4] = (u8)(sz >> 16);
 349                 wb[5] = (u8)(sz >> 8);
 350                 wb[6] = (u8)(sz);
 351                 len = 8;
 352                 break;
 353
 354         case CMD_INTERNAL_WRITE:                /* internal register write */
 355                 wb[1] = (u8)(adr >> 8);
 356                 if (clockless == 1)
 357                         wb[1] |= BIT(7);
 358                 wb[2] = (u8)(adr);
 359                 wb[3] = b[3];
 360                 wb[4] = b[2];
 361                 wb[5] = b[1];
 362                 wb[6] = b[0];
 363                 len = 8;
 364                 break;
 365
 366         case CMD_SINGLE_WRITE:                  /* single word write */
 367                 wb[1] = (u8)(adr >> 16);
 368                 wb[2] = (u8)(adr >> 8);
 369                 wb[3] = (u8)(adr);
 370                 wb[4] = b[3];
 371                 wb[5] = b[2];
 372                 wb[6] = b[1];
 373                 wb[7] = b[0];
 374                 len = 9;
 375                 break;
 376
 377         default:
 378                 result = N_FAIL;
 379                 break;
 380         }
 381
 382         if (result != N_OK)
 383                 return result;
 384
 385         if (!g_spi.crc_off)
 386                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 387         else
 388                 len -= 1;
 389
 390 #define NUM_SKIP_BYTES (1)
 391 #define NUM_RSP_BYTES (2)
 392 #define NUM_DATA_HDR_BYTES (1)
 393 #define NUM_DATA_BYTES (4)
 394 #define NUM_CRC_BYTES (2)
 395 #define NUM_DUMMY_BYTES (3)
 396         if ((cmd == CMD_RESET) ||
 397             (cmd == CMD_TERMINATE) ||
 398             (cmd == CMD_REPEAT)) {
 399                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 400         } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 401                 if (!g_spi.crc_off) {
 402                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 403                                       + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
 404                 } else {
 405                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 406                                       + NUM_DUMMY_BYTES);
 407                 }
 408         } else {
 409                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 410         }
 411 #undef NUM_DUMMY_BYTES
 412
 413         if (len2 > ARRAY_SIZE(wb)) {
 414                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 415                          len2, ARRAY_SIZE(wb));
 416                 result = N_FAIL;
 417                 return result;
 418         }
 419         /* zero spi write buffers. */
 420         for (wix = len; wix < len2; wix++)
 421                 wb[wix] = 0;
 422         rix = len;
 423
 424         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 425                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 426                 result = N_FAIL;
 427                 return result;
 428         }
 429
 430         /**
 431          * Command/Control response
 432          **/
 433         if ((cmd == CMD_RESET) ||
 434             (cmd == CMD_TERMINATE) ||
 435             (cmd == CMD_REPEAT)) {
 436                 rix++;         /* skip 1 byte */
 437         }
 438
 439         /* do { */
 440         rsp = rb[rix++];
 441         /*      if(rsp == cmd) break; */
 442         /* } while(&rptr[1] <= &rb[len2]); */
 443
 444         if (rsp != cmd) {
 445                 dev_err(&spi->dev,
 446                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 447                         cmd, rsp);
 448                 result = N_FAIL;
 449                 return result;
 450         }
 451
 452         /**
 453          * State response
 454          **/
 455         rsp = rb[rix++];
 456         if (rsp != 0x00) {
 457                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 458                         rsp);
 459                 result = N_FAIL;
 460                 return result;
 461         }
 462
 463         if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
 464             || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 465                 int retry;
 466                 /* u16 crc1, crc2; */
 467                 u8 crc[2];
 468                 /**
 469                  * Data Respnose header
 470                  **/
 471                 retry = 100;
 472                 do {
 473                         /* ensure there is room in buffer later to read data and crc */
 474                         if (rix < len2) {
 475                                 rsp = rb[rix++];
 476                         } else {
 477                                 retry = 0;
 478                                 break;
 479                         }
 480                         if (((rsp >> 4) & 0xf) == 0xf)
 481                                 break;
 482                 } while (retry--);
 483
 484                 if (retry <= 0) {
 485                         dev_err(&spi->dev,
 486                                 "Error, data read response (%02x)\n", rsp);
 487                         result = N_RESET;
 488                         return result;
 489                 }
 490
 491                 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 492                         /**
 493                          * Read bytes
 494                          **/
 495                         if ((rix + 3) < len2) {
 496                                 b[0] = rb[rix++];
 497                                 b[1] = rb[rix++];
 498                                 b[2] = rb[rix++];
 499                                 b[3] = rb[rix++];
 500                         } else {
 501                                 dev_err(&spi->dev,
 502                                         "buffer overrun when reading data.\n");
 503                                 result = N_FAIL;
 504                                 return result;
 505                         }
 506
 507                         if (!g_spi.crc_off) {
 508                                 /**
 509                                  * Read Crc
 510                                  **/
 511                                 if ((rix + 1) < len2) {
 512                                         crc[0] = rb[rix++];
 513                                         crc[1] = rb[rix++];
 514                                 } else {
 515                                         dev_err(&spi->dev, "buffer overrun when reading crc.\n");
 516                                         result = N_FAIL;
 517                                         return result;
 518                                 }
 519                         }
 520                 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 521                         int ix;
 522
 523                         /* some data may be read in response to dummy bytes. */
 524                         for (ix = 0; (rix < len2) && (ix < sz); )
 525                                 b[ix++] = rb[rix++];
 526
 527                         sz -= ix;
 528
 529                         if (sz > 0) {
 530                                 int nbytes;
 531
 532                                 if (sz <= (DATA_PKT_SZ - ix))
 533                                         nbytes = sz;
 534                                 else
 535                                         nbytes = DATA_PKT_SZ - ix;
 536
 537                                 /**
 538                                  * Read bytes
 539                                  **/
 540                                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 541                                         dev_err(&spi->dev, "Failed data block read, bus error...\n");
 542                                         result = N_FAIL;
 543                                         goto _error_;
 544                                 }
 545
 546                                 /**
 547                                  * Read Crc
 548                                  **/
 549                                 if (!g_spi.crc_off) {
 550                                         if (wilc_spi_rx(wilc, crc, 2)) {
 551                                                 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
 552                                                 result = N_FAIL;
 553                                                 goto _error_;
 554                                         }
 555                                 }
 556
 557
 558                                 ix += nbytes;
 559                                 sz -= nbytes;
 560                         }
 561
 562                         /*  if any data in left unread, then read the rest using normal DMA code.*/
 563                         while (sz > 0) {
 564                                 int nbytes;
 565
 566                                 if (sz <= DATA_PKT_SZ)
 567                                         nbytes = sz;
 568                                 else
 569                                         nbytes = DATA_PKT_SZ;
 570
 571                                 /**
 572                                  * read data response only on the next DMA cycles not
 573                                  * the first DMA since data response header is already
 574                                  * handled above for the first DMA.
 575                                  **/
 576                                 /**
 577                                  * Data Respnose header
 578                                  **/
 579                                 retry = 10;
 580                                 do {
 581                                         if (wilc_spi_rx(wilc, &rsp, 1)) {
 582                                                 dev_err(&spi->dev, "Failed data response read, bus error...\n");
 583                                                 result = N_FAIL;
 584                                                 break;
 585                                         }
 586                                         if (((rsp >> 4) & 0xf) == 0xf)
 587                                                 break;
 588                                 } while (retry--);
 589
 590                                 if (result == N_FAIL)
 591                                         break;
 592
 593
 594                                 /**
 595                                  * Read bytes
 596                                  **/
 597                                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 598                                         dev_err(&spi->dev, "Failed data block read, bus error...\n");
 599                                         result = N_FAIL;
 600                                         break;
 601                                 }
 602
 603                                 /**
 604                                  * Read Crc
 605                                  **/
 606                                 if (!g_spi.crc_off) {
 607                                         if (wilc_spi_rx(wilc, crc, 2)) {
 608                                                 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
 609                                                 result = N_FAIL;
 610                                                 break;
 611                                         }
 612                                 }
 613
 614                                 ix += nbytes;
 615                                 sz -= nbytes;
 616                         }
 617                 }
 618         }
 619 _error_:
 620         return result;
 621 }
 622
 623 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 624 {
 625         struct spi_device *spi = to_spi_device(wilc->dev);
 626         int ix, nbytes;
 627         int result = 1;
 628         u8 cmd, order, crc[2] = {0};
 629         /* u8 rsp; */
 630
 631         /**
 632          *      Data
 633          **/
 634         ix = 0;
 635         do {
 636                 if (sz <= DATA_PKT_SZ)
 637                         nbytes = sz;
 638                 else
 639                         nbytes = DATA_PKT_SZ;
 640
 641                 /**
 642                  *      Write command
 643                  **/
 644                 cmd = 0xf0;
 645                 if (ix == 0) {
 646                         if (sz <= DATA_PKT_SZ)
 647
 648                                 order = 0x3;
 649                         else
 650                                 order = 0x1;
 651                 } else {
 652                         if (sz <= DATA_PKT_SZ)
 653                                 order = 0x3;
 654                         else
 655                                 order = 0x2;
 656                 }
 657                 cmd |= order;
 658                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 659                         dev_err(&spi->dev,
 660                                 "Failed data block cmd write, bus error...\n");
 661                         result = N_FAIL;
 662                         break;
 663                 }
 664
 665                 /**
 666                  *      Write data
 667                  **/
 668                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 669                         dev_err(&spi->dev,
 670                                 "Failed data block write, bus error...\n");
 671                         result = N_FAIL;
 672                         break;
 673                 }
 674
 675                 /**
 676                  *      Write Crc
 677                  **/
 678                 if (!g_spi.crc_off) {
 679                         if (wilc_spi_tx(wilc, crc, 2)) {
 680                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 681                                 result = N_FAIL;
 682                                 break;
 683                         }
 684                 }
 685
 686                 /**
 687                  *      No need to wait for response
 688                  **/
 689                 ix += nbytes;
 690                 sz -= nbytes;
 691         } while (sz);
 692
 693
 694         return result;
 695 }
 696
 697 /********************************************
 698  *
 699  *      Spi Internal Read/Write Function
 700  *
 701  ********************************************/
 702
 703 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 704 {
 705         struct spi_device *spi = to_spi_device(wilc->dev);
 706         int result;
 707
 708         dat = cpu_to_le32(dat);
 709         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 710                                   0);
 711         if (result != N_OK)
 712                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 713
 714         return result;
 715 }
 716
 717 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 718 {
 719         struct spi_device *spi = to_spi_device(wilc->dev);
 720         int result;
 721
 722         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 723                                   0);
 724         if (result != N_OK) {
 725                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 726                 return 0;
 727         }
 728
 729         *data = cpu_to_le32(*data);
 730
 731         return 1;
 732 }
 733
 734 /********************************************
 735  *
 736  *      Spi interfaces
 737  *
 738  ********************************************/
 739
 740 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 741 {
 742         struct spi_device *spi = to_spi_device(wilc->dev);
 743         int result = N_OK;
 744         u8 cmd = CMD_SINGLE_WRITE;
 745         u8 clockless = 0;
 746
 747         data = cpu_to_le32(data);
 748         if (addr < 0x30) {
 749                 /* Clockless register*/
 750                 cmd = CMD_INTERNAL_WRITE;
 751                 clockless = 1;
 752         }
 753
 754         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 755         if (result != N_OK)
 756                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 757
 758         return result;
 759 }
 760
 761 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 762 {
 763         struct spi_device *spi = to_spi_device(wilc->dev);
 764         int result;
 765         u8 cmd = CMD_DMA_EXT_WRITE;
 766
 767         /**
 768          *      has to be greated than 4
 769          **/
 770         if (size <= 4)
 771                 return 0;
 772
 773         result = spi_cmd_complete(wilc, cmd, addr, NULL, size, 0);
 774         if (result != N_OK) {
 775                 dev_err(&spi->dev,
 776                         "Failed cmd, write block (%08x)...\n", addr);
 777                 return 0;
 778         }
 779
 780         /**
 781          *      Data
 782          **/
 783         result = spi_data_write(wilc, buf, size);
 784         if (result != N_OK)
 785                 dev_err(&spi->dev, "Failed block data write...\n");
 786
 787         return 1;
 788 }
 789
 790 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 791 {
 792         struct spi_device *spi = to_spi_device(wilc->dev);
 793         int result = N_OK;
 794         u8 cmd = CMD_SINGLE_READ;
 795         u8 clockless = 0;
 796
 797         if (addr < 0x30) {
 798                 /* dev_err(&spi->dev, "***** read addr %d\n\n", addr); */
 799                 /* Clockless register*/
 800                 cmd = CMD_INTERNAL_READ;
 801                 clockless = 1;
 802         }
 803
 804         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 805         if (result != N_OK) {
 806                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 807                 return 0;
 808         }
 809
 810         *data = cpu_to_le32(*data);
 811
 812         return 1;
 813 }
 814
 815 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 816 {
 817         struct spi_device *spi = to_spi_device(wilc->dev);
 818         u8 cmd = CMD_DMA_EXT_READ;
 819         int result;
 820
 821         if (size <= 4)
 822                 return 0;
 823
 824         result = spi_cmd_complete(wilc, cmd, addr, buf, size, 0);
 825         if (result != N_OK) {
 826                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 827                 return 0;
 828         }
 829
 830         return 1;
 831 }
 832
 833 /********************************************
 834  *
 835  *      Bus interfaces
 836  *
 837  ********************************************/
 838
 839 static int _wilc_spi_deinit(struct wilc *wilc)
 840 {
 841         /**
 842          *      TODO:
 843          **/
 844         return 1;
 845 }
 846
 847 static int wilc_spi_init(struct wilc *wilc, bool resume)
 848 {
 849         struct spi_device *spi = to_spi_device(wilc->dev);
 850         u32 reg;
 851         u32 chipid;
 852
 853         static int isinit;
 854
 855         if (isinit) {
 856
 857                 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 858                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 859                         return 0;
 860                 }
 861                 return 1;
 862         }
 863
 864         memset(&g_spi, 0, sizeof(struct wilc_spi));
 865
 866         /**
 867          *      configure protocol
 868          **/
 869         g_spi.crc_off = 0;
 870
 871         /* TODO: We can remove the CRC trials if there is a definite way to reset */
 872         /* the SPI to it's initial value. */
 873         if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 874                 /* Read failed. Try with CRC off. This might happen when module
 875                  * is removed but chip isn't reset*/
 876                 g_spi.crc_off = 1;
 877                 dev_err(&spi->dev, "Failed internal read protocol with CRC on, retyring with CRC off...\n");
 878                 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 879                         /* Reaad failed with both CRC on and off, something went bad */
 880                         dev_err(&spi->dev,
 881                                 "Failed internal read protocol...\n");
 882                         return 0;
 883                 }
 884         }
 885         if (g_spi.crc_off == 0) {
 886                 reg &= ~0xc;    /* disable crc checking */
 887                 reg &= ~0x70;
 888                 reg |= (0x5 << 4);
 889                 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
 890                         dev_err(&spi->dev, "[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
 891                         return 0;
 892                 }
 893                 g_spi.crc_off = 1;
 894         }
 895
 896
 897         /**
 898          *      make sure can read back chip id correctly
 899          **/
 900         if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 901                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 902                 return 0;
 903         }
 904         /* dev_err(&spi->dev, "chipid (%08x)\n", chipid); */
 905
 906         g_spi.has_thrpt_enh = 1;
 907
 908         isinit = 1;
 909
 910         return 1;
 911 }
 912
 913 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 914 {
 915         struct spi_device *spi = to_spi_device(wilc->dev);
 916         int ret;
 917
 918         if (g_spi.has_thrpt_enh) {
 919                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 920                                         size);
 921                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
 922         } else {
 923                 u32 tmp;
 924                 u32 byte_cnt;
 925
 926                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 927                                         &byte_cnt);
 928                 if (!ret) {
 929                         dev_err(&spi->dev,
 930                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 931                         goto _fail_;
 932                 }
 933                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 934                 *size = tmp;
 935         }
 936
 937
 938
 939 _fail_:
 940         return ret;
 941 }
 942
 943
 944
 945 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 946 {
 947         struct spi_device *spi = to_spi_device(wilc->dev);
 948         int ret;
 949
 950         if (g_spi.has_thrpt_enh) {
 951                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 952                                         int_status);
 953         } else {
 954                 u32 tmp;
 955                 u32 byte_cnt;
 956
 957                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 958                                         &byte_cnt);
 959                 if (!ret) {
 960                         dev_err(&spi->dev,
 961                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 962                         goto _fail_;
 963                 }
 964                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 965
 966                 {
 967                         int happended, j;
 968
 969                         j = 0;
 970                         do {
 971                                 u32 irq_flags;
 972
 973                                 happended = 0;
 974
 975                                 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
 976                                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
 977
 978                                 if (g_spi.nint > 5) {
 979                                         wilc_spi_read_reg(wilc, 0x1a94,
 980                                                           &irq_flags);
 981                                         tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
 982                                 }
 983
 984                                 {
 985                                         u32 unkmown_mask;
 986
 987                                         unkmown_mask = ~((1ul << g_spi.nint) - 1);
 988
 989                                         if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
 990                                                 dev_err(&spi->dev, "Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
 991                                                 happended = 1;
 992                                         }
 993                                 }
 994                                 j++;
 995                         } while (happended);
 996                 }
 997
 998                 *int_status = tmp;
 999
1000         }
1001
1002 _fail_:
1003         return ret;
1004 }
1005
1006 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1007 {
1008         struct spi_device *spi = to_spi_device(wilc->dev);
1009         int ret;
1010
1011         if (g_spi.has_thrpt_enh) {
1012                 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
1013                                          val);
1014         } else {
1015                 u32 flags;
1016
1017                 flags = val & (BIT(MAX_NUM_INT) - 1);
1018                 if (flags) {
1019                         int i;
1020
1021                         ret = 1;
1022                         for (i = 0; i < g_spi.nint; i++) {
1023                                 /* No matter what you write 1 or 0, it will clear interrupt. */
1024                                 if (flags & 1)
1025                                         ret = wilc_spi_write_reg(wilc, 0x10c8 + i * 4, 1);
1026                                 if (!ret)
1027                                         break;
1028                                 flags >>= 1;
1029                         }
1030                         if (!ret) {
1031                                 dev_err(&spi->dev,
1032                                         "Failed wilc_spi_write_reg, set reg %x ...\n",
1033                                         0x10c8 + i * 4);
1034                                 goto _fail_;
1035                         }
1036                         for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1037                                 if (flags & 1)
1038                                         dev_err(&spi->dev,
1039                                                 "Unexpected interrupt cleared %d...\n",
1040                                                 i);
1041                                 flags >>= 1;
1042                         }
1043                 }
1044
1045                 {
1046                         u32 tbl_ctl;
1047
1048                         tbl_ctl = 0;
1049                         /* select VMM table 0 */
1050                         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1051                                 tbl_ctl |= BIT(0);
1052                         /* select VMM table 1 */
1053                         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1054                                 tbl_ctl |= BIT(1);
1055
1056                         ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL,
1057                                                  tbl_ctl);
1058                         if (!ret) {
1059                                 dev_err(&spi->dev,
1060                                         "fail write reg vmm_tbl_ctl...\n");
1061                                 goto _fail_;
1062                         }
1063
1064                         if ((val & EN_VMM) == EN_VMM) {
1065                                 /**
1066                                  *      enable vmm transfer.
1067                                  **/
1068                                 ret = wilc_spi_write_reg(wilc,
1069                                                          WILC_VMM_CORE_CTL, 1);
1070                                 if (!ret) {
1071                                         dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1072                                         goto _fail_;
1073                                 }
1074                         }
1075                 }
1076         }
1077 _fail_:
1078         return ret;
1079 }
1080
1081 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1082 {
1083         struct spi_device *spi = to_spi_device(wilc->dev);
1084         u32 reg;
1085         int ret, i;
1086
1087         if (nint > MAX_NUM_INT) {
1088                 dev_err(&spi->dev, "Too many interupts (%d)...\n", nint);
1089                 return 0;
1090         }
1091
1092         g_spi.nint = nint;
1093
1094         /**
1095          *      interrupt pin mux select
1096          **/
1097         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1098         if (!ret) {
1099                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1100                         WILC_PIN_MUX_0);
1101                 return 0;
1102         }
1103         reg |= BIT(8);
1104         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1105         if (!ret) {
1106                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1107                         WILC_PIN_MUX_0);
1108                 return 0;
1109         }
1110
1111         /**
1112          *      interrupt enable
1113          **/
1114         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1115         if (!ret) {
1116                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1117                         WILC_INTR_ENABLE);
1118                 return 0;
1119         }
1120
1121         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1122                 reg |= (BIT((27 + i)));
1123
1124         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1125         if (!ret) {
1126                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1127                         WILC_INTR_ENABLE);
1128                 return 0;
1129         }
1130         if (nint) {
1131                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1132                 if (!ret) {
1133                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1134                                 WILC_INTR2_ENABLE);
1135                         return 0;
1136                 }
1137
1138                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1139                         reg |= BIT(i);
1140
1141                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1142                 if (!ret) {
1143                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1144                                 WILC_INTR2_ENABLE);
1145                         return 0;
1146                 }
1147         }
1148
1149         return 1;
1150 }
1151 /********************************************
1152  *
1153  *      Global spi HIF function table
1154  *
1155  ********************************************/
1156 const struct wilc_hif_func wilc_hif_spi = {
1157         .hif_init = wilc_spi_init,
1158         .hif_deinit = _wilc_spi_deinit,
1159         .hif_read_reg = wilc_spi_read_reg,
1160         .hif_write_reg = wilc_spi_write_reg,
1161         .hif_block_rx = wilc_spi_read,
1162         .hif_block_tx = wilc_spi_write,
1163         .hif_read_int = wilc_spi_read_int,
1164         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1165         .hif_read_size = wilc_spi_read_size,
1166         .hif_block_tx_ext = wilc_spi_write,
1167         .hif_block_rx_ext = wilc_spi_read,
1168         .hif_sync_ext = wilc_spi_sync_ext,
1169 };