drivers/staging/wilc1000/wilc_wlan.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_wlan.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9
  10 #include "wilc_wlan_if.h"
  11 #include "wilc_wfi_netdevice.h"
  12 #include "wilc_wlan_cfg.h"
  13
  14 /********************************************
  15  *
  16  *      Global
  17  *
  18  ********************************************/
  19 extern wilc_hif_func_t hif_sdio;
  20 extern wilc_hif_func_t hif_spi;
  21 u32 wilc_get_chipid(u8 update);
  22 u16 Set_machw_change_vir_if(bool bValue);
  23
  24
  25
  26 typedef struct {
  27         int quit;
  28
  29         /**
  30          *      input interface functions
  31          **/
  32         wilc_wlan_io_func_t io_func;
  33
  34         /**
  35          *      host interface functions
  36          **/
  37         wilc_hif_func_t hif_func;
  38
  39         /**
  40          *      configuration interface functions
  41          **/
  42         int cfg_frame_in_use;
  43         wilc_cfg_frame_t cfg_frame;
  44         u32 cfg_frame_offset;
  45         int cfg_seq_no;
  46
  47         /**
  48          *      RX buffer
  49          **/
  50         #ifdef MEMORY_STATIC
  51         u8 *rx_buffer;
  52         u32 rx_buffer_offset;
  53         #endif
  54         /**
  55          *      TX buffer
  56          **/
  57         u8 *tx_buffer;
  58         u32 tx_buffer_offset;
  59
  60         /**
  61          *      TX queue
  62          **/
  63
  64         unsigned long txq_spinlock_flags;
  65
  66         struct txq_entry_t *txq_head;
  67         struct txq_entry_t *txq_tail;
  68         int txq_entries;
  69         int txq_exit;
  70
  71         /**
  72          *      RX queue
  73          **/
  74         struct rxq_entry_t *rxq_head;
  75         struct rxq_entry_t *rxq_tail;
  76         int rxq_entries;
  77         int rxq_exit;
  78
  79
  80 } wilc_wlan_dev_t;
  81
  82 static wilc_wlan_dev_t g_wlan;
  83
  84 static inline void chip_allow_sleep(void);
  85 static inline void chip_wakeup(void);
  86 /********************************************
  87  *
  88  *      Debug
  89  *
  90  ********************************************/
  91
  92 static u32 dbgflag = N_INIT | N_ERR | N_INTR | N_TXQ | N_RXQ;
  93
  94 static void wilc_debug(u32 flag, char *fmt, ...)
  95 {
  96         char buf[256];
  97         va_list args;
  98
  99         if (flag & dbgflag) {
 100                 va_start(args, fmt);
 101                 vsprintf(buf, fmt, args);
 102                 va_end(args);
 103
 104                 linux_wlan_dbg(buf);
 105         }
 106 }
 107
 108 static CHIP_PS_STATE_T genuChipPSstate = CHIP_WAKEDUP;
 109
 110 /*acquire_bus() and release_bus() are made static inline functions*/
 111 /*as a temporary workaround to fix a problem of receiving*/
 112 /*unknown interrupt from FW*/
 113 static inline void acquire_bus(BUS_ACQUIRE_T acquire)
 114 {
 115
 116         mutex_lock(&g_linux_wlan->hif_cs);
 117         #ifndef WILC_OPTIMIZE_SLEEP_INT
 118         if (genuChipPSstate != CHIP_WAKEDUP)
 119         #endif
 120         {
 121                 if (acquire == ACQUIRE_AND_WAKEUP)
 122                         chip_wakeup();
 123         }
 124
 125 }
 126 static inline void release_bus(BUS_RELEASE_T release)
 127 {
 128         #ifdef WILC_OPTIMIZE_SLEEP_INT
 129         if (release == RELEASE_ALLOW_SLEEP)
 130                 chip_allow_sleep();
 131         #endif
 132         mutex_unlock(&g_linux_wlan->hif_cs);
 133 }
 134 /********************************************
 135  *
 136  *      Queue
 137  *
 138  ********************************************/
 139
 140 static void wilc_wlan_txq_remove(struct txq_entry_t *tqe)
 141 {
 142
 143         wilc_wlan_dev_t *p = &g_wlan;
 144         if (tqe == p->txq_head) {
 145
 146                 p->txq_head = tqe->next;
 147                 if (p->txq_head)
 148                         p->txq_head->prev = NULL;
 149
 150
 151         } else if (tqe == p->txq_tail)      {
 152                 p->txq_tail = (tqe->prev);
 153                 if (p->txq_tail)
 154                         p->txq_tail->next = NULL;
 155         } else {
 156                 tqe->prev->next = tqe->next;
 157                 tqe->next->prev = tqe->prev;
 158         }
 159         p->txq_entries -= 1;
 160
 161 }
 162
 163 static struct txq_entry_t *wilc_wlan_txq_remove_from_head(void)
 164 {
 165         struct txq_entry_t *tqe;
 166         wilc_wlan_dev_t *p = &g_wlan;
 167         unsigned long flags;
 168
 169         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 170         if (p->txq_head) {
 171                 tqe = p->txq_head;
 172                 p->txq_head = tqe->next;
 173                 if (p->txq_head)
 174                         p->txq_head->prev = NULL;
 175
 176                 p->txq_entries -= 1;
 177
 178
 179
 180
 181         } else {
 182                 tqe = NULL;
 183         }
 184         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 185         return tqe;
 186 }
 187
 188 static void wilc_wlan_txq_add_to_tail(struct txq_entry_t *tqe)
 189 {
 190         wilc_wlan_dev_t *p = &g_wlan;
 191         unsigned long flags;
 192         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 193
 194         if (p->txq_head == NULL) {
 195                 tqe->next = NULL;
 196                 tqe->prev = NULL;
 197                 p->txq_head = tqe;
 198                 p->txq_tail = tqe;
 199         } else {
 200                 tqe->next = NULL;
 201                 tqe->prev = p->txq_tail;
 202                 p->txq_tail->next = tqe;
 203                 p->txq_tail = tqe;
 204         }
 205         p->txq_entries += 1;
 206         PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries);
 207
 208         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 209
 210         /**
 211          *      wake up TX queue
 212          **/
 213         PRINT_D(TX_DBG, "Wake the txq_handling\n");
 214
 215         up(&g_linux_wlan->txq_event);
 216 }
 217
 218 static int wilc_wlan_txq_add_to_head(struct txq_entry_t *tqe)
 219 {
 220         wilc_wlan_dev_t *p = &g_wlan;
 221         unsigned long flags;
 222         if (linux_wlan_lock_timeout(&g_linux_wlan->txq_add_to_head_cs,
 223                                     CFG_PKTS_TIMEOUT))
 224                 return -1;
 225
 226         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 227
 228         if (p->txq_head == NULL) {
 229                 tqe->next = NULL;
 230                 tqe->prev = NULL;
 231                 p->txq_head = tqe;
 232                 p->txq_tail = tqe;
 233         } else {
 234                 tqe->next = p->txq_head;
 235                 tqe->prev = NULL;
 236                 p->txq_head->prev = tqe;
 237                 p->txq_head = tqe;
 238         }
 239         p->txq_entries += 1;
 240         PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries);
 241
 242         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 243         up(&g_linux_wlan->txq_add_to_head_cs);
 244
 245
 246         /**
 247          *      wake up TX queue
 248          **/
 249         up(&g_linux_wlan->txq_event);
 250         PRINT_D(TX_DBG, "Wake up the txq_handler\n");
 251
 252         return 0;
 253
 254 }
 255
 256 u32 Statisitcs_totalAcks = 0, Statisitcs_DroppedAcks = 0;
 257
 258 #ifdef  TCP_ACK_FILTER
 259 struct Ack_session_info;
 260 struct Ack_session_info {
 261         u32 Ack_seq_num;
 262         u32 Bigger_Ack_num;
 263         u16 src_port;
 264         u16 dst_port;
 265         u16 status;
 266 };
 267
 268 typedef struct {
 269         u32 ack_num;
 270         u32 Session_index;
 271         struct txq_entry_t  *txqe;
 272 } Pending_Acks_info_t /*Ack_info_t*/;
 273
 274
 275
 276
 277 struct Ack_session_info *Free_head;
 278 struct Ack_session_info *Alloc_head;
 279
 280 #define NOT_TCP_ACK                     (-1)
 281
 282 #define MAX_TCP_SESSION         25
 283 #define MAX_PENDING_ACKS                256
 284 struct Ack_session_info Acks_keep_track_info[2 * MAX_TCP_SESSION];
 285 Pending_Acks_info_t Pending_Acks_info[MAX_PENDING_ACKS];
 286
 287 u32 PendingAcks_arrBase;
 288 u32 Opened_TCP_session;
 289 u32 Pending_Acks;
 290
 291
 292
 293 static inline int Init_TCP_tracking(void)
 294 {
 295
 296         return 0;
 297
 298 }
 299 static inline int add_TCP_track_session(u32 src_prt, u32 dst_prt, u32 seq)
 300 {
 301         Acks_keep_track_info[Opened_TCP_session].Ack_seq_num = seq;
 302         Acks_keep_track_info[Opened_TCP_session].Bigger_Ack_num = 0;
 303         Acks_keep_track_info[Opened_TCP_session].src_port = src_prt;
 304         Acks_keep_track_info[Opened_TCP_session].dst_port = dst_prt;
 305         Opened_TCP_session++;
 306
 307         PRINT_D(TCP_ENH, "TCP Session %d to Ack %d\n", Opened_TCP_session, seq);
 308         return 0;
 309 }
 310
 311 static inline int Update_TCP_track_session(u32 index, u32 Ack)
 312 {
 313
 314         if (Ack > Acks_keep_track_info[index].Bigger_Ack_num)
 315                 Acks_keep_track_info[index].Bigger_Ack_num = Ack;
 316         return 0;
 317
 318 }
 319 static inline int add_TCP_Pending_Ack(u32 Ack, u32 Session_index, struct txq_entry_t  *txqe)
 320 {
 321         Statisitcs_totalAcks++;
 322         if (Pending_Acks < MAX_PENDING_ACKS) {
 323                 Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].ack_num = Ack;
 324                 Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].txqe = txqe;
 325                 Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].Session_index = Session_index;
 326                 txqe->tcp_PendingAck_index = PendingAcks_arrBase + Pending_Acks;
 327                 Pending_Acks++;
 328
 329         } else {
 330
 331         }
 332         return 0;
 333 }
 334 static inline int remove_TCP_related(void)
 335 {
 336         wilc_wlan_dev_t *p = &g_wlan;
 337         unsigned long flags;
 338
 339         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 340
 341         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 342         return 0;
 343 }
 344
 345 static inline int tcp_process(struct txq_entry_t *tqe)
 346 {
 347         int ret;
 348         u8 *eth_hdr_ptr;
 349         u8 *buffer = tqe->buffer;
 350         unsigned short h_proto;
 351         int i;
 352         wilc_wlan_dev_t *p = &g_wlan;
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 356
 357         eth_hdr_ptr = &buffer[0];
 358         h_proto = ntohs(*((unsigned short *)&eth_hdr_ptr[12]));
 359         if (h_proto == 0x0800) { /* IP */
 360                 u8 *ip_hdr_ptr;
 361                 u8 protocol;
 362
 363                 ip_hdr_ptr = &buffer[ETHERNET_HDR_LEN];
 364                 protocol = ip_hdr_ptr[9];
 365
 366
 367                 if (protocol == 0x06) {
 368                         u8 *tcp_hdr_ptr;
 369                         u32 IHL, Total_Length, Data_offset;
 370
 371                         tcp_hdr_ptr = &ip_hdr_ptr[IP_HDR_LEN];
 372                         IHL = (ip_hdr_ptr[0] & 0xf) << 2;
 373                         Total_Length = (((u32)ip_hdr_ptr[2]) << 8) + ((u32)ip_hdr_ptr[3]);
 374                         Data_offset = (((u32)tcp_hdr_ptr[12] & 0xf0) >> 2);
 375                         if (Total_Length == (IHL + Data_offset)) { /*we want to recognize the clear Acks(packet only carry Ack infos not with data) so data size must be equal zero*/
 376                                 u32 seq_no, Ack_no;
 377
 378                                 seq_no  = (((u32)tcp_hdr_ptr[4]) << 24) + (((u32)tcp_hdr_ptr[5]) << 16) + (((u32)tcp_hdr_ptr[6]) << 8) + ((u32)tcp_hdr_ptr[7]);
 379
 380                                 Ack_no  = (((u32)tcp_hdr_ptr[8]) << 24) + (((u32)tcp_hdr_ptr[9]) << 16) + (((u32)tcp_hdr_ptr[10]) << 8) + ((u32)tcp_hdr_ptr[11]);
 381
 382
 383                                 for (i = 0; i < Opened_TCP_session; i++) {
 384                                         if (Acks_keep_track_info[i].Ack_seq_num == seq_no) {
 385                                                 Update_TCP_track_session(i, Ack_no);
 386                                                 break;
 387                                         }
 388                                 }
 389                                 if (i == Opened_TCP_session)
 390                                         add_TCP_track_session(0, 0, seq_no);
 391
 392                                 add_TCP_Pending_Ack(Ack_no, i, tqe);
 393
 394
 395                         }
 396
 397                 } else {
 398                         ret = 0;
 399                 }
 400         } else {
 401                 ret = 0;
 402         }
 403         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 404         return ret;
 405 }
 406
 407
 408 static int wilc_wlan_txq_filter_dup_tcp_ack(struct net_device *dev)
 409 {
 410         perInterface_wlan_t *nic;
 411         struct wilc *wilc;
 412         u32 i = 0;
 413         u32 Dropped = 0;
 414         wilc_wlan_dev_t *p = &g_wlan;
 415
 416         nic = netdev_priv(dev);
 417         wilc = nic->wilc;
 418
 419         spin_lock_irqsave(&wilc->txq_spinlock, p->txq_spinlock_flags);
 420         for (i = PendingAcks_arrBase; i < (PendingAcks_arrBase + Pending_Acks); i++) {
 421                 if (Pending_Acks_info[i].ack_num < Acks_keep_track_info[Pending_Acks_info[i].Session_index].Bigger_Ack_num) {
 422                         struct txq_entry_t *tqe;
 423
 424                         PRINT_D(TCP_ENH, "DROP ACK: %u\n", Pending_Acks_info[i].ack_num);
 425                         tqe = Pending_Acks_info[i].txqe;
 426                         if (tqe) {
 427                                 wilc_wlan_txq_remove(tqe);
 428                                 Statisitcs_DroppedAcks++;
 429                                 tqe->status = 1;                                /* mark the packet send */
 430                                 if (tqe->tx_complete_func)
 431                                         tqe->tx_complete_func(tqe->priv, tqe->status);
 432                                 kfree(tqe);
 433                                 Dropped++;
 434                         }
 435                 }
 436         }
 437         Pending_Acks = 0;
 438         Opened_TCP_session = 0;
 439
 440         if (PendingAcks_arrBase == 0)
 441                 PendingAcks_arrBase = MAX_TCP_SESSION;
 442         else
 443                 PendingAcks_arrBase = 0;
 444
 445
 446         spin_unlock_irqrestore(&wilc->txq_spinlock, p->txq_spinlock_flags);
 447
 448         while (Dropped > 0) {
 449                 /*consume the semaphore count of the removed packet*/
 450                 linux_wlan_lock_timeout(&wilc->txq_event, 1);
 451                 Dropped--;
 452         }
 453
 454         return 1;
 455 }
 456 #endif
 457
 458 bool EnableTCPAckFilter = false;
 459
 460 void Enable_TCP_ACK_Filter(bool value)
 461 {
 462         EnableTCPAckFilter = value;
 463 }
 464
 465 bool is_TCP_ACK_Filter_Enabled(void)
 466 {
 467         return EnableTCPAckFilter;
 468 }
 469
 470 static int wilc_wlan_txq_add_cfg_pkt(u8 *buffer, u32 buffer_size)
 471 {
 472         wilc_wlan_dev_t *p = &g_wlan;
 473         struct txq_entry_t *tqe;
 474
 475         PRINT_D(TX_DBG, "Adding config packet ...\n");
 476         if (p->quit) {
 477                 PRINT_D(TX_DBG, "Return due to clear function\n");
 478                 up(&g_linux_wlan->cfg_event);
 479                 return 0;
 480         }
 481
 482         tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC);
 483         if (tqe == NULL) {
 484                 PRINT_ER("Failed to allocate memory\n");
 485                 return 0;
 486         }
 487
 488         tqe->type = WILC_CFG_PKT;
 489         tqe->buffer = buffer;
 490         tqe->buffer_size = buffer_size;
 491         tqe->tx_complete_func = NULL;
 492         tqe->priv = NULL;
 493 #ifdef TCP_ACK_FILTER
 494         tqe->tcp_PendingAck_index = NOT_TCP_ACK;
 495 #endif
 496         /**
 497          *      Configuration packet always at the front
 498          **/
 499         PRINT_D(TX_DBG, "Adding the config packet at the Queue tail\n");
 500
 501         if (wilc_wlan_txq_add_to_head(tqe))
 502                 return 0;
 503         return 1;
 504 }
 505
 506 int wilc_wlan_txq_add_net_pkt(void *priv, u8 *buffer, u32 buffer_size,
 507                               wilc_tx_complete_func_t func)
 508 {
 509         wilc_wlan_dev_t *p = &g_wlan;
 510         struct txq_entry_t *tqe;
 511
 512         if (p->quit)
 513                 return 0;
 514
 515         tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC);
 516
 517         if (tqe == NULL)
 518                 return 0;
 519         tqe->type = WILC_NET_PKT;
 520         tqe->buffer = buffer;
 521         tqe->buffer_size = buffer_size;
 522         tqe->tx_complete_func = func;
 523         tqe->priv = priv;
 524
 525         PRINT_D(TX_DBG, "Adding mgmt packet at the Queue tail\n");
 526 #ifdef TCP_ACK_FILTER
 527         tqe->tcp_PendingAck_index = NOT_TCP_ACK;
 528         if (is_TCP_ACK_Filter_Enabled())
 529                 tcp_process(tqe);
 530 #endif
 531         wilc_wlan_txq_add_to_tail(tqe);
 532         /*return number of itemes in the queue*/
 533         return p->txq_entries;
 534 }
 535
 536 int wilc_wlan_txq_add_mgmt_pkt(void *priv, u8 *buffer, u32 buffer_size, wilc_tx_complete_func_t func)
 537 {
 538
 539         wilc_wlan_dev_t *p = &g_wlan;
 540         struct txq_entry_t *tqe;
 541
 542         if (p->quit)
 543                 return 0;
 544
 545         tqe = kmalloc(sizeof(struct txq_entry_t), GFP_KERNEL);
 546
 547         if (tqe == NULL)
 548                 return 0;
 549         tqe->type = WILC_MGMT_PKT;
 550         tqe->buffer = buffer;
 551         tqe->buffer_size = buffer_size;
 552         tqe->tx_complete_func = func;
 553         tqe->priv = priv;
 554 #ifdef TCP_ACK_FILTER
 555         tqe->tcp_PendingAck_index = NOT_TCP_ACK;
 556 #endif
 557         PRINT_D(TX_DBG, "Adding Network packet at the Queue tail\n");
 558         wilc_wlan_txq_add_to_tail(tqe);
 559         return 1;
 560 }
 561
 562 static struct txq_entry_t *wilc_wlan_txq_get_first(void)
 563 {
 564         wilc_wlan_dev_t *p = &g_wlan;
 565         struct txq_entry_t *tqe;
 566         unsigned long flags;
 567
 568         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 569
 570         tqe = p->txq_head;
 571
 572         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 573
 574
 575         return tqe;
 576 }
 577
 578 static struct txq_entry_t *wilc_wlan_txq_get_next(struct txq_entry_t *tqe)
 579 {
 580         unsigned long flags;
 581         spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags);
 582
 583         tqe = tqe->next;
 584         spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags);
 585
 586
 587         return tqe;
 588 }
 589
 590 static int wilc_wlan_rxq_add(struct rxq_entry_t *rqe)
 591 {
 592         wilc_wlan_dev_t *p = &g_wlan;
 593
 594         if (p->quit)
 595                 return 0;
 596
 597         mutex_lock(&g_linux_wlan->rxq_cs);
 598         if (p->rxq_head == NULL) {
 599                 PRINT_D(RX_DBG, "Add to Queue head\n");
 600                 rqe->next = NULL;
 601                 p->rxq_head = rqe;
 602                 p->rxq_tail = rqe;
 603         } else {
 604                 PRINT_D(RX_DBG, "Add to Queue tail\n");
 605                 p->rxq_tail->next = rqe;
 606                 rqe->next = NULL;
 607                 p->rxq_tail = rqe;
 608         }
 609         p->rxq_entries += 1;
 610         PRINT_D(RX_DBG, "Number of queue entries: %d\n", p->rxq_entries);
 611         mutex_unlock(&g_linux_wlan->rxq_cs);
 612         return p->rxq_entries;
 613 }
 614
 615 static struct rxq_entry_t *wilc_wlan_rxq_remove(struct wilc *wilc)
 616 {
 617         wilc_wlan_dev_t *p = &g_wlan;
 618
 619         PRINT_D(RX_DBG, "Getting rxQ element\n");
 620         if (p->rxq_head) {
 621                 struct rxq_entry_t *rqe;
 622
 623                 mutex_lock(&wilc->rxq_cs);
 624                 rqe = p->rxq_head;
 625                 p->rxq_head = p->rxq_head->next;
 626                 p->rxq_entries -= 1;
 627                 PRINT_D(RX_DBG, "RXQ entries decreased\n");
 628                 mutex_unlock(&wilc->rxq_cs);
 629                 return rqe;
 630         }
 631         PRINT_D(RX_DBG, "Nothing to get from Q\n");
 632         return NULL;
 633 }
 634
 635
 636 /********************************************
 637  *
 638  *      Power Save handle functions
 639  *
 640  ********************************************/
 641
 642
 643
 644 #ifdef WILC_OPTIMIZE_SLEEP_INT
 645
 646 static inline void chip_allow_sleep(void)
 647 {
 648         u32 reg = 0;
 649
 650         /* Clear bit 1 */
 651         g_wlan.hif_func.hif_read_reg(0xf0, &reg);
 652
 653         g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0));
 654 }
 655
 656 static inline void chip_wakeup(void)
 657 {
 658         u32 reg, clk_status_reg, trials = 0;
 659         u32 sleep_time;
 660
 661         if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) {
 662                 do {
 663                         g_wlan.hif_func.hif_read_reg(1, &reg);
 664                         /* Set bit 1 */
 665                         g_wlan.hif_func.hif_write_reg(1, reg | BIT(1));
 666
 667                         /* Clear bit 1*/
 668                         g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1));
 669
 670                         do {
 671                                 /* Wait for the chip to stabilize*/
 672                                 usleep_range(2 * 1000, 2 * 1000);
 673                                 /* Make sure chip is awake. This is an extra step that can be removed */
 674                                 /* later to avoid the bus access overhead */
 675                                 if ((wilc_get_chipid(true) == 0))
 676                                         wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n");
 677
 678                         } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0));
 679
 680                 } while (wilc_get_chipid(true) == 0);
 681         } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO)   {
 682                 g_wlan.hif_func.hif_read_reg(0xf0, &reg);
 683                 do {
 684                         /* Set bit 1 */
 685                         g_wlan.hif_func.hif_write_reg(0xf0, reg | BIT(0));
 686
 687                         /* Check the clock status */
 688                         g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg);
 689
 690                         /* in case of clocks off, wait 2ms, and check it again. */
 691                         /* if still off, wait for another 2ms, for a total wait of 6ms. */
 692                         /* If still off, redo the wake up sequence */
 693                         while (((clk_status_reg & 0x1) == 0) && (((++trials) % 3) == 0)) {
 694                                 /* Wait for the chip to stabilize*/
 695                                 usleep_range(2 * 1000, 2 * 1000);
 696
 697                                 /* Make sure chip is awake. This is an extra step that can be removed */
 698                                 /* later to avoid the bus access overhead */
 699                                 g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg);
 700
 701                                 if ((clk_status_reg & 0x1) == 0)
 702                                         wilc_debug(N_ERR, "clocks still OFF. Wake up failed\n");
 703
 704                         }
 705                         /* in case of failure, Reset the wakeup bit to introduce a new edge on the next loop */
 706                         if ((clk_status_reg & 0x1) == 0) {
 707                                 /* Reset bit 0 */
 708                                 g_wlan.hif_func.hif_write_reg(0xf0, reg &
 709                                                               (~BIT(0)));
 710                         }
 711                 } while ((clk_status_reg & 0x1) == 0);
 712         }
 713
 714
 715         if (genuChipPSstate == CHIP_SLEEPING_MANUAL) {
 716                 g_wlan.hif_func.hif_read_reg(0x1C0C, &reg);
 717                 reg &= ~BIT(0);
 718                 g_wlan.hif_func.hif_write_reg(0x1C0C, reg);
 719
 720                 if (wilc_get_chipid(false) >= 0x1002b0) {
 721                         /* Enable PALDO back right after wakeup */
 722                         u32 val32;
 723
 724                         g_wlan.hif_func.hif_read_reg(0x1e1c, &val32);
 725                         val32 |= BIT(6);
 726                         g_wlan.hif_func.hif_write_reg(0x1e1c, val32);
 727
 728                         g_wlan.hif_func.hif_read_reg(0x1e9c, &val32);
 729                         val32 |= BIT(6);
 730                         g_wlan.hif_func.hif_write_reg(0x1e9c, val32);
 731                 }
 732         }
 733         genuChipPSstate = CHIP_WAKEDUP;
 734 }
 735 #else
 736 static inline void chip_wakeup(void)
 737 {
 738         u32 reg, trials = 0;
 739
 740         do {
 741                 if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) {
 742                         g_wlan.hif_func.hif_read_reg(1, &reg);
 743                         /* Make sure bit 1 is 0 before we start. */
 744                         g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1));
 745                         /* Set bit 1 */
 746                         g_wlan.hif_func.hif_write_reg(1, reg | BIT(1));
 747                         /* Clear bit 1*/
 748                         g_wlan.hif_func.hif_write_reg(1, reg  & ~BIT(1));
 749                 } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO)   {
 750                         /* Make sure bit 0 is 0 before we start. */
 751                         g_wlan.hif_func.hif_read_reg(0xf0, &reg);
 752                         g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0));
 753                         /* Set bit 1 */
 754                         g_wlan.hif_func.hif_write_reg(0xf0, reg | BIT(0));
 755                         /* Clear bit 1 */
 756                         g_wlan.hif_func.hif_write_reg(0xf0, reg  & ~BIT(0));
 757                 }
 758
 759                 do {
 760                         /* Wait for the chip to stabilize*/
 761                         mdelay(3);
 762
 763                         /* Make sure chip is awake. This is an extra step that can be removed */
 764                         /* later to avoid the bus access overhead */
 765                         if ((wilc_get_chipid(true) == 0))
 766                                 wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n");
 767
 768                 } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0));
 769
 770         } while (wilc_get_chipid(true) == 0);
 771
 772         if (genuChipPSstate == CHIP_SLEEPING_MANUAL) {
 773                 g_wlan.hif_func.hif_read_reg(0x1C0C, &reg);
 774                 reg &= ~BIT(0);
 775                 g_wlan.hif_func.hif_write_reg(0x1C0C, reg);
 776
 777                 if (wilc_get_chipid(false) >= 0x1002b0) {
 778                         /* Enable PALDO back right after wakeup */
 779                         u32 val32;
 780
 781                         g_wlan.hif_func.hif_read_reg(0x1e1c, &val32);
 782                         val32 |= BIT(6);
 783                         g_wlan.hif_func.hif_write_reg(0x1e1c, val32);
 784
 785                         g_wlan.hif_func.hif_read_reg(0x1e9c, &val32);
 786                         val32 |= BIT(6);
 787                         g_wlan.hif_func.hif_write_reg(0x1e9c, val32);
 788                 }
 789         }
 790         genuChipPSstate = CHIP_WAKEDUP;
 791 }
 792 #endif
 793 void chip_sleep_manually(u32 u32SleepTime)
 794 {
 795         if (genuChipPSstate != CHIP_WAKEDUP) {
 796                 /* chip is already sleeping. Do nothing */
 797                 return;
 798         }
 799         acquire_bus(ACQUIRE_ONLY);
 800
 801 #ifdef WILC_OPTIMIZE_SLEEP_INT
 802         chip_allow_sleep();
 803 #endif
 804
 805         /* Trigger the manual sleep interrupt */
 806         g_wlan.hif_func.hif_write_reg(0x10a8, 1);
 807
 808         genuChipPSstate = CHIP_SLEEPING_MANUAL;
 809         release_bus(RELEASE_ONLY);
 810
 811 }
 812
 813
 814 /********************************************
 815  *
 816  *      Tx, Rx queue handle functions
 817  *
 818  ********************************************/
 819 int wilc_wlan_handle_txq(struct net_device *dev, u32 *pu32TxqCount)
 820 {
 821         wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
 822         int i, entries = 0;
 823         u32 sum;
 824         u32 reg;
 825         u8 *txb = p->tx_buffer;
 826         u32 offset = 0;
 827         int vmm_sz = 0;
 828         struct txq_entry_t *tqe;
 829         int ret = 0;
 830         int counter;
 831         int timeout;
 832         u32 vmm_table[WILC_VMM_TBL_SIZE];
 833         perInterface_wlan_t *nic;
 834         struct wilc *wilc;
 835
 836         nic = netdev_priv(dev);
 837         wilc = nic->wilc;
 838
 839         p->txq_exit = 0;
 840         do {
 841                 if (p->quit)
 842                         break;
 843
 844                 linux_wlan_lock_timeout(&wilc->txq_add_to_head_cs,
 845                                         CFG_PKTS_TIMEOUT);
 846 #ifdef  TCP_ACK_FILTER
 847                 wilc_wlan_txq_filter_dup_tcp_ack(dev);
 848 #endif
 849                 /**
 850                  *      build the vmm list
 851                  **/
 852                 PRINT_D(TX_DBG, "Getting the head of the TxQ\n");
 853                 tqe = wilc_wlan_txq_get_first();
 854                 i = 0;
 855                 sum = 0;
 856                 do {
 857                         if ((tqe != NULL) && (i < (WILC_VMM_TBL_SIZE - 1)) /* reserve last entry to 0 */) {
 858
 859                                 if (tqe->type == WILC_CFG_PKT)
 860                                         vmm_sz = ETH_CONFIG_PKT_HDR_OFFSET;
 861
 862                                 else if (tqe->type == WILC_NET_PKT)
 863                                         vmm_sz = ETH_ETHERNET_HDR_OFFSET;
 864
 865                                 else
 866                                         vmm_sz = HOST_HDR_OFFSET;
 867
 868                                 vmm_sz += tqe->buffer_size;
 869                                 PRINT_D(TX_DBG, "VMM Size before alignment = %d\n", vmm_sz);
 870                                 if (vmm_sz & 0x3) {                                                                                                     /* has to be word aligned */
 871                                         vmm_sz = (vmm_sz + 4) & ~0x3;
 872                                 }
 873                                 if ((sum + vmm_sz) > LINUX_TX_SIZE)
 874                                         break;
 875
 876                                 PRINT_D(TX_DBG, "VMM Size AFTER alignment = %d\n", vmm_sz);
 877                                 vmm_table[i] = vmm_sz / 4;                                                                                /* table take the word size */
 878                                 PRINT_D(TX_DBG, "VMMTable entry size = %d\n", vmm_table[i]);
 879
 880                                 if (tqe->type == WILC_CFG_PKT) {
 881                                         vmm_table[i] |= BIT(10);
 882                                         PRINT_D(TX_DBG, "VMMTable entry changed for CFG packet = %d\n", vmm_table[i]);
 883                                 }
 884 #ifdef BIG_ENDIAN
 885                                 vmm_table[i] = BYTE_SWAP(vmm_table[i]);
 886 #endif
 887
 888                                 i++;
 889                                 sum += vmm_sz;
 890                                 PRINT_D(TX_DBG, "sum = %d\n", sum);
 891                                 tqe = wilc_wlan_txq_get_next(tqe);
 892                         } else {
 893                                 break;
 894                         }
 895                 } while (1);
 896
 897                 if (i == 0) {           /* nothing in the queue */
 898                         PRINT_D(TX_DBG, "Nothing in TX-Q\n");
 899                         break;
 900                 } else {
 901                         PRINT_D(TX_DBG, "Mark the last entry in VMM table - number of previous entries = %d\n", i);
 902                         vmm_table[i] = 0x0;     /* mark the last element to 0 */
 903                 }
 904                 acquire_bus(ACQUIRE_AND_WAKEUP);
 905                 counter = 0;
 906                 do {
 907
 908                         ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, &reg);
 909                         if (!ret) {
 910                                 wilc_debug(N_ERR, "[wilc txq]: fail can't read reg vmm_tbl_entry..\n");
 911                                 break;
 912                         }
 913
 914                         if ((reg & 0x1) == 0) {
 915                                 /**
 916                                  *      write to vmm table
 917                                  **/
 918                                 PRINT_D(TX_DBG, "Writing VMM table ... with Size = %d\n", ((i + 1) * 4));
 919                                 break;
 920                         } else {
 921                                 counter++;
 922                                 if (counter > 200) {
 923                                         counter = 0;
 924                                         PRINT_D(TX_DBG, "Looping in tx ctrl , forcce quit\n");
 925                                         ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, 0);
 926                                         break;
 927                                 }
 928                                 /**
 929                                  *      wait for vmm table is ready
 930                                  **/
 931                                 PRINT_WRN(GENERIC_DBG, "[wilc txq]: warn, vmm table not clear yet, wait...\n");
 932                                 release_bus(RELEASE_ALLOW_SLEEP);
 933                                 usleep_range(3000, 3000);
 934                                 acquire_bus(ACQUIRE_AND_WAKEUP);
 935                         }
 936                 } while (!p->quit);
 937
 938                 if (!ret)
 939                         goto _end_;
 940
 941                 timeout = 200;
 942                 do {
 943
 944                         /**
 945                          * write to vmm table
 946                          **/
 947                         ret = p->hif_func.hif_block_tx(WILC_VMM_TBL_RX_SHADOW_BASE, (u8 *)vmm_table, ((i + 1) * 4));
 948                         if (!ret) {
 949                                 wilc_debug(N_ERR, "ERR block TX of VMM table.\n");
 950                                 break;
 951                         }
 952
 953
 954                         /**
 955                          * interrupt firmware
 956                          **/
 957                         ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x2);
 958                         if (!ret) {
 959                                 wilc_debug(N_ERR, "[wilc txq]: fail can't write reg host_vmm_ctl..\n");
 960                                 break;
 961                         }
 962
 963                         /**
 964                          *      wait for confirm...
 965                          **/
 966
 967                         do {
 968                                 ret = p->hif_func.hif_read_reg(WILC_HOST_VMM_CTL, &reg);
 969                                 if (!ret) {
 970                                         wilc_debug(N_ERR, "[wilc txq]: fail can't read reg host_vmm_ctl..\n");
 971                                         break;
 972                                 }
 973                                 if ((reg >> 2) & 0x1) {
 974                                         /**
 975                                          *      Get the entries
 976                                          **/
 977                                         entries = ((reg >> 3) & 0x3f);
 978                                         break;
 979                                 } else {
 980                                         release_bus(RELEASE_ALLOW_SLEEP);
 981                                         usleep_range(3000, 3000);
 982                                         acquire_bus(ACQUIRE_AND_WAKEUP);
 983                                         PRINT_WRN(GENERIC_DBG, "Can't get VMM entery - reg = %2x\n", reg);
 984                                 }
 985                         } while (--timeout);
 986                         if (timeout <= 0) {
 987                                 ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x0);
 988                                 break;
 989                         }
 990
 991                         if (!ret)
 992                                 break;
 993
 994                         if (entries == 0) {
 995                                 PRINT_WRN(GENERIC_DBG, "[wilc txq]: no more buffer in the chip (reg: %08x), retry later [[ %d, %x ]]\n", reg, i, vmm_table[i - 1]);
 996
 997                                 /* undo the transaction. */
 998                                 ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, &reg);
 999                                 if (!ret) {
1000                                         wilc_debug(N_ERR, "[wilc txq]: fail can't read reg WILC_HOST_TX_CTRL..\n");
1001                                         break;
1002                                 }
1003                                 reg &= ~BIT(0);
1004                                 ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, reg);
1005                                 if (!ret) {
1006                                         wilc_debug(N_ERR, "[wilc txq]: fail can't write reg WILC_HOST_TX_CTRL..\n");
1007                                         break;
1008                                 }
1009                                 break;
1010                         } else {
1011                                 break;
1012                         }
1013                 } while (1);
1014
1015                 if (!ret)
1016                         goto _end_;
1017
1018                 if (entries == 0) {
1019                         ret = WILC_TX_ERR_NO_BUF;
1020                         goto _end_;
1021                 }
1022
1023                 /* since copying data into txb takes some time, then
1024                  * allow the bus lock to be released let the RX task go. */
1025                 release_bus(RELEASE_ALLOW_SLEEP);
1026
1027                 /**
1028                  *      Copy data to the TX buffer
1029                  **/
1030                 offset = 0;
1031                 i = 0;
1032                 do {
1033                         tqe = wilc_wlan_txq_remove_from_head();
1034                         if (tqe != NULL && (vmm_table[i] != 0)) {
1035                                 u32 header, buffer_offset;
1036
1037 #ifdef BIG_ENDIAN
1038                                 vmm_table[i] = BYTE_SWAP(vmm_table[i]);
1039 #endif
1040                                 vmm_sz = (vmm_table[i] & 0x3ff);        /* in word unit */
1041                                 vmm_sz *= 4;
1042                                 header = (tqe->type << 31) | (tqe->buffer_size << 15) | vmm_sz;
1043                                 if (tqe->type == WILC_MGMT_PKT)
1044                                         header |= BIT(30);
1045                                 else
1046                                         header &= ~BIT(30);
1047
1048 #ifdef BIG_ENDIAN
1049                                 header = BYTE_SWAP(header);
1050 #endif
1051                                 memcpy(&txb[offset], &header, 4);
1052                                 if (tqe->type == WILC_CFG_PKT) {
1053                                         buffer_offset = ETH_CONFIG_PKT_HDR_OFFSET;
1054                                 }
1055                                 else if (tqe->type == WILC_NET_PKT) {
1056                                         char *pBSSID = ((struct tx_complete_data *)(tqe->priv))->pBssid;
1057
1058                                         buffer_offset = ETH_ETHERNET_HDR_OFFSET;
1059                                         /* copy the bssid at the sart of the buffer */
1060                                         memcpy(&txb[offset + 4], pBSSID, 6);
1061                                 }
1062                                 else {
1063                                         buffer_offset = HOST_HDR_OFFSET;
1064                                 }
1065
1066                                 memcpy(&txb[offset + buffer_offset], tqe->buffer, tqe->buffer_size);
1067                                 offset += vmm_sz;
1068                                 i++;
1069                                 tqe->status = 1;                                /* mark the packet send */
1070                                 if (tqe->tx_complete_func)
1071                                         tqe->tx_complete_func(tqe->priv, tqe->status);
1072                                 #ifdef TCP_ACK_FILTER
1073                                 if (tqe->tcp_PendingAck_index != NOT_TCP_ACK)
1074                                         Pending_Acks_info[tqe->tcp_PendingAck_index].txqe = NULL;
1075                                 #endif
1076                                 kfree(tqe);
1077                         } else {
1078                                 break;
1079                         }
1080                 } while (--entries);
1081
1082                 /**
1083                  *      lock the bus
1084                  **/
1085                 acquire_bus(ACQUIRE_AND_WAKEUP);
1086
1087                 ret = p->hif_func.hif_clear_int_ext(ENABLE_TX_VMM);
1088                 if (!ret) {
1089                         wilc_debug(N_ERR, "[wilc txq]: fail can't start tx VMM ...\n");
1090                         goto _end_;
1091                 }
1092
1093                 /**
1094                  *      transfer
1095                  **/
1096                 ret = p->hif_func.hif_block_tx_ext(0, txb, offset);
1097                 if (!ret) {
1098                         wilc_debug(N_ERR, "[wilc txq]: fail can't block tx ext...\n");
1099                         goto _end_;
1100                 }
1101
1102 _end_:
1103
1104                 release_bus(RELEASE_ALLOW_SLEEP);
1105                 if (ret != 1)
1106                         break;
1107         } while (0);
1108         up(&wilc->txq_add_to_head_cs);
1109
1110         p->txq_exit = 1;
1111         PRINT_D(TX_DBG, "THREAD: Exiting txq\n");
1112         /* return tx[]q count */
1113         *pu32TxqCount = p->txq_entries;
1114         return ret;
1115 }
1116
1117 static void wilc_wlan_handle_rxq(struct wilc *wilc)
1118 {
1119         wilc_wlan_dev_t *p = &g_wlan;
1120         int offset = 0, size, has_packet = 0;
1121         u8 *buffer;
1122         struct rxq_entry_t *rqe;
1123
1124         p->rxq_exit = 0;
1125
1126
1127
1128
1129         do {
1130                 if (p->quit) {
1131                         PRINT_D(RX_DBG, "exit 1st do-while due to Clean_UP function\n");
1132                         up(&wilc->cfg_event);
1133                         break;
1134                 }
1135                 rqe = wilc_wlan_rxq_remove(wilc);
1136                 if (rqe == NULL) {
1137                         PRINT_D(RX_DBG, "nothing in the queue - exit 1st do-while\n");
1138                         break;
1139                 }
1140                 buffer = rqe->buffer;
1141                 size = rqe->buffer_size;
1142                 PRINT_D(RX_DBG, "rxQ entery Size = %d - Address = %p\n", size, buffer);
1143                 offset = 0;
1144
1145
1146
1147                 do {
1148                         u32 header;
1149                         u32 pkt_len, pkt_offset, tp_len;
1150                         int is_cfg_packet;
1151
1152                         PRINT_D(RX_DBG, "In the 2nd do-while\n");
1153                         memcpy(&header, &buffer[offset], 4);
1154 #ifdef BIG_ENDIAN
1155                         header = BYTE_SWAP(header);
1156 #endif
1157                         PRINT_D(RX_DBG, "Header = %04x - Offset = %d\n", header, offset);
1158
1159
1160
1161                         is_cfg_packet = (header >> 31) & 0x1;
1162                         pkt_offset = (header >> 22) & 0x1ff;
1163                         tp_len = (header >> 11) & 0x7ff;
1164                         pkt_len = header & 0x7ff;
1165
1166                         if (pkt_len == 0 || tp_len == 0) {
1167                                 wilc_debug(N_RXQ, "[wilc rxq]: data corrupt, packet len or tp_len is 0 [%d][%d]\n", pkt_len, tp_len);
1168                                 break;
1169                         }
1170
1171                         #define IS_MANAGMEMENT                          0x100
1172                         #define IS_MANAGMEMENT_CALLBACK                 0x080
1173                         #define IS_MGMT_STATUS_SUCCES                   0x040
1174
1175
1176                         if (pkt_offset & IS_MANAGMEMENT) {
1177                                 /* reset mgmt indicator bit, to use pkt_offeset in furthur calculations */
1178                                 pkt_offset &= ~(IS_MANAGMEMENT | IS_MANAGMEMENT_CALLBACK | IS_MGMT_STATUS_SUCCES);
1179
1180                                 WILC_WFI_mgmt_rx(wilc, &buffer[offset + HOST_HDR_OFFSET], pkt_len);
1181                         }
1182                         else
1183                         {
1184
1185                                 if (!is_cfg_packet) {
1186                                         if (pkt_len > 0) {
1187                                                 frmw_to_linux(&buffer[offset],
1188                                                               pkt_len,
1189                                                               pkt_offset);
1190                                                 has_packet = 1;
1191                                         }
1192                                 } else {
1193                                         wilc_cfg_rsp_t rsp;
1194
1195
1196
1197                                         wilc_wlan_cfg_indicate_rx(&buffer[pkt_offset + offset], pkt_len, &rsp);
1198                                         if (rsp.type == WILC_CFG_RSP) {
1199                                                 /**
1200                                                  *      wake up the waiting task...
1201                                                  **/
1202                                                 PRINT_D(RX_DBG, "p->cfg_seq_no = %d - rsp.seq_no = %d\n", p->cfg_seq_no, rsp.seq_no);
1203                                                 if (p->cfg_seq_no == rsp.seq_no)
1204                                                         up(&wilc->cfg_event);
1205                                         } else if (rsp.type == WILC_CFG_RSP_STATUS) {
1206                                                 /**
1207                                                  *      Call back to indicate status...
1208                                                  **/
1209                                                 linux_wlan_mac_indicate(wilc, WILC_MAC_INDICATE_STATUS);
1210
1211                                         } else if (rsp.type == WILC_CFG_RSP_SCAN) {
1212                                                 linux_wlan_mac_indicate(wilc, WILC_MAC_INDICATE_SCAN);
1213                                         }
1214                                 }
1215                         }
1216                         offset += tp_len;
1217                         if (offset >= size)
1218                                 break;
1219                 } while (1);
1220
1221
1222 #ifndef MEMORY_STATIC
1223                 kfree(buffer);
1224 #endif
1225                 kfree(rqe);
1226
1227                 if (has_packet)
1228                         linux_wlan_rx_complete();
1229
1230         } while (1);
1231
1232         p->rxq_exit = 1;
1233         PRINT_D(RX_DBG, "THREAD: Exiting RX thread\n");
1234 }
1235
1236 /********************************************
1237  *
1238  *      Fast DMA Isr
1239  *
1240  ********************************************/
1241 static void wilc_unknown_isr_ext(void)
1242 {
1243         g_wlan.hif_func.hif_clear_int_ext(0);
1244 }
1245 static void wilc_pllupdate_isr_ext(u32 int_stats)
1246 {
1247
1248         int trials = 10;
1249
1250         g_wlan.hif_func.hif_clear_int_ext(PLL_INT_CLR);
1251
1252         /* Waiting for PLL */
1253         mdelay(WILC_PLL_TO);
1254
1255         /* poll till read a valid data */
1256         while (!(ISWILC1000(wilc_get_chipid(true)) && --trials)) {
1257                 PRINT_D(TX_DBG, "PLL update retrying\n");
1258                 mdelay(1);
1259         }
1260 }
1261
1262 static void wilc_sleeptimer_isr_ext(u32 int_stats1)
1263 {
1264         g_wlan.hif_func.hif_clear_int_ext(SLEEP_INT_CLR);
1265 #ifndef WILC_OPTIMIZE_SLEEP_INT
1266         genuChipPSstate = CHIP_SLEEPING_AUTO;
1267 #endif
1268 }
1269
1270 static void wilc_wlan_handle_isr_ext(struct wilc *wilc, u32 int_status)
1271 {
1272         wilc_wlan_dev_t *p = &g_wlan;
1273 #ifdef MEMORY_STATIC
1274         u32 offset = p->rx_buffer_offset;
1275 #endif
1276         u8 *buffer = NULL;
1277         u32 size;
1278         u32 retries = 0;
1279         int ret = 0;
1280         struct rxq_entry_t *rqe;
1281
1282
1283         /**
1284          *      Get the rx size
1285          **/
1286
1287         size = ((int_status & 0x7fff) << 2);
1288
1289         while (!size && retries < 10) {
1290                 u32 time = 0;
1291                 /*looping more secure*/
1292                 /*zero size make a crashe because the dma will not happen and that will block the firmware*/
1293                 wilc_debug(N_ERR, "RX Size equal zero ... Trying to read it again for %d time\n", time++);
1294                 p->hif_func.hif_read_size(&size);
1295                 size = ((size & 0x7fff) << 2);
1296                 retries++;
1297
1298         }
1299
1300         if (size > 0) {
1301 #ifdef MEMORY_STATIC
1302                 if (LINUX_RX_SIZE - offset < size)
1303                         offset = 0;
1304
1305                 if (p->rx_buffer)
1306                         buffer = &p->rx_buffer[offset];
1307                 else {
1308                         wilc_debug(N_ERR, "[wilc isr]: fail Rx Buffer is NULL...drop the packets (%d)\n", size);
1309                         goto _end_;
1310                 }
1311
1312 #else
1313                 buffer = kmalloc(size, GFP_KERNEL);
1314                 if (buffer == NULL) {
1315                         wilc_debug(N_ERR, "[wilc isr]: fail alloc host memory...drop the packets (%d)\n", size);
1316                         usleep_range(100 * 1000, 100 * 1000);
1317                         goto _end_;
1318                 }
1319 #endif
1320
1321                 /**
1322                  *      clear the chip's interrupt       after getting size some register getting corrupted after clear the interrupt
1323                  **/
1324                 p->hif_func.hif_clear_int_ext(DATA_INT_CLR | ENABLE_RX_VMM);
1325
1326
1327                 /**
1328                  * start transfer
1329                  **/
1330                 ret = p->hif_func.hif_block_rx_ext(0, buffer, size);
1331
1332                 if (!ret) {
1333                         wilc_debug(N_ERR, "[wilc isr]: fail block rx...\n");
1334                         goto _end_;
1335                 }
1336 _end_:
1337
1338
1339                 if (ret) {
1340 #ifdef MEMORY_STATIC
1341                         offset += size;
1342                         p->rx_buffer_offset = offset;
1343 #endif
1344                         /**
1345                          *      add to rx queue
1346                          **/
1347                         rqe = kmalloc(sizeof(struct rxq_entry_t), GFP_KERNEL);
1348                         if (rqe != NULL) {
1349                                 rqe->buffer = buffer;
1350                                 rqe->buffer_size = size;
1351                                 PRINT_D(RX_DBG, "rxq entery Size= %d - Address = %p\n", rqe->buffer_size, rqe->buffer);
1352                                 wilc_wlan_rxq_add(rqe);
1353                         }
1354                 } else {
1355 #ifndef MEMORY_STATIC
1356                         kfree(buffer);
1357 #endif
1358                 }
1359         }
1360         wilc_wlan_handle_rxq(wilc);
1361 }
1362
1363 void wilc_handle_isr(void *wilc)
1364 {
1365         u32 int_status;
1366
1367         acquire_bus(ACQUIRE_AND_WAKEUP);
1368         g_wlan.hif_func.hif_read_int(&int_status);
1369
1370         if (int_status & PLL_INT_EXT)
1371                 wilc_pllupdate_isr_ext(int_status);
1372
1373         if (int_status & DATA_INT_EXT) {
1374                 wilc_wlan_handle_isr_ext(wilc, int_status);
1375         #ifndef WILC_OPTIMIZE_SLEEP_INT
1376                 /* Chip is up and talking*/
1377                 genuChipPSstate = CHIP_WAKEDUP;
1378         #endif
1379         }
1380         if (int_status & SLEEP_INT_EXT)
1381                 wilc_sleeptimer_isr_ext(int_status);
1382
1383         if (!(int_status & (ALL_INT_EXT))) {
1384 #ifdef WILC_SDIO
1385                 PRINT_D(TX_DBG, ">> UNKNOWN_INTERRUPT - 0x%08x\n", int_status);
1386 #endif
1387                 wilc_unknown_isr_ext();
1388         }
1389         release_bus(RELEASE_ALLOW_SLEEP);
1390 }
1391
1392 /********************************************
1393  *
1394  *      Firmware download
1395  *
1396  ********************************************/
1397 int wilc_wlan_firmware_download(const u8 *buffer, u32 buffer_size)
1398 {
1399         wilc_wlan_dev_t *p = &g_wlan;
1400         u32 offset;
1401         u32 addr, size, size2, blksz;
1402         u8 *dma_buffer;
1403         int ret = 0;
1404
1405         blksz = BIT(12);
1406         /* Allocate a DMA coherent  buffer. */
1407
1408         dma_buffer = kmalloc(blksz, GFP_KERNEL);
1409         if (dma_buffer == NULL) {
1410                 /*EIO   5*/
1411                 ret = -5;
1412                 PRINT_ER("Can't allocate buffer for firmware download IO error\n ");
1413                 goto _fail_1;
1414         }
1415
1416         PRINT_D(INIT_DBG, "Downloading firmware size = %d ...\n", buffer_size);
1417         /**
1418          *      load the firmware
1419          **/
1420         offset = 0;
1421         do {
1422                 memcpy(&addr, &buffer[offset], 4);
1423                 memcpy(&size, &buffer[offset + 4], 4);
1424 #ifdef BIG_ENDIAN
1425                 addr = BYTE_SWAP(addr);
1426                 size = BYTE_SWAP(size);
1427 #endif
1428                 acquire_bus(ACQUIRE_ONLY);
1429                 offset += 8;
1430                 while (((int)size) && (offset < buffer_size)) {
1431                         if (size <= blksz)
1432                                 size2 = size;
1433                         else
1434                                 size2 = blksz;
1435                         /* Copy firmware into a DMA coherent buffer */
1436                         memcpy(dma_buffer, &buffer[offset], size2);
1437                         ret = p->hif_func.hif_block_tx(addr, dma_buffer, size2);
1438                         if (!ret)
1439                                 break;
1440
1441                         addr += size2;
1442                         offset += size2;
1443                         size -= size2;
1444                 }
1445                 release_bus(RELEASE_ONLY);
1446
1447                 if (!ret) {
1448                         /*EIO   5*/
1449                         ret = -5;
1450                         PRINT_ER("Can't download firmware IO error\n ");
1451                         goto _fail_;
1452                 }
1453                 PRINT_D(INIT_DBG, "Offset = %d\n", offset);
1454         } while (offset < buffer_size);
1455
1456 _fail_:
1457
1458         kfree(dma_buffer);
1459
1460 _fail_1:
1461
1462         return (ret < 0) ? ret : 0;
1463 }
1464
1465 /********************************************
1466  *
1467  *      Common
1468  *
1469  ********************************************/
1470 int wilc_wlan_start(void)
1471 {
1472         wilc_wlan_dev_t *p = &g_wlan;
1473         u32 reg = 0;
1474         int ret;
1475         u32 chipid;
1476
1477         /**
1478          *      Set the host interface
1479          **/
1480         if (p->io_func.io_type == HIF_SDIO) {
1481                 reg = 0;
1482                 reg |= BIT(3); /* bug 4456 and 4557 */
1483         } else if (p->io_func.io_type == HIF_SPI) {
1484                 reg = 1;
1485         }
1486         acquire_bus(ACQUIRE_ONLY);
1487         ret = p->hif_func.hif_write_reg(WILC_VMM_CORE_CFG, reg);
1488         if (!ret) {
1489                 wilc_debug(N_ERR, "[wilc start]: fail write reg vmm_core_cfg...\n");
1490                 release_bus(RELEASE_ONLY);
1491                 /* EIO  5*/
1492                 ret = -5;
1493                 return ret;
1494         }
1495         reg = 0;
1496 #ifdef WILC_SDIO_IRQ_GPIO
1497         reg |= WILC_HAVE_SDIO_IRQ_GPIO;
1498 #endif
1499
1500 #ifdef WILC_DISABLE_PMU
1501 #else
1502         reg |= WILC_HAVE_USE_PMU;
1503 #endif
1504
1505 #ifdef WILC_SLEEP_CLK_SRC_XO
1506         reg |= WILC_HAVE_SLEEP_CLK_SRC_XO;
1507 #elif defined WILC_SLEEP_CLK_SRC_RTC
1508         reg |= WILC_HAVE_SLEEP_CLK_SRC_RTC;
1509 #endif
1510
1511 #ifdef WILC_EXT_PA_INV_TX_RX
1512         reg |= WILC_HAVE_EXT_PA_INV_TX_RX;
1513 #endif
1514
1515         reg |= WILC_HAVE_LEGACY_RF_SETTINGS;
1516
1517
1518 /*Set oscillator frequency*/
1519 #ifdef XTAL_24
1520         reg |= WILC_HAVE_XTAL_24;
1521 #endif
1522
1523 /*Enable/Disable GPIO configuration for FW logs*/
1524 #ifdef DISABLE_WILC_UART
1525         reg |= WILC_HAVE_DISABLE_WILC_UART;
1526 #endif
1527
1528         ret = p->hif_func.hif_write_reg(WILC_GP_REG_1, reg);
1529         if (!ret) {
1530                 wilc_debug(N_ERR, "[wilc start]: fail write WILC_GP_REG_1 ...\n");
1531                 release_bus(RELEASE_ONLY);
1532                 /* EIO  5*/
1533                 ret = -5;
1534                 return ret;
1535         }
1536
1537         /**
1538          *      Bus related
1539          **/
1540         p->hif_func.hif_sync_ext(NUM_INT_EXT);
1541
1542         ret = p->hif_func.hif_read_reg(0x1000, &chipid);
1543         if (!ret) {
1544                 wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1000 ...\n");
1545                 release_bus(RELEASE_ONLY);
1546                 /* EIO  5*/
1547                 ret = -5;
1548                 return ret;
1549         }
1550
1551         /**
1552          *      Go...
1553          **/
1554
1555
1556         p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1557         if ((reg & BIT(10)) == BIT(10)) {
1558                 reg &= ~BIT(10);
1559                 p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1560                 p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1561         }
1562
1563         reg |= BIT(10);
1564         ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1565         p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1566         release_bus(RELEASE_ONLY);
1567
1568         return (ret < 0) ? ret : 0;
1569 }
1570
1571 void wilc_wlan_global_reset(void)
1572 {
1573
1574         wilc_wlan_dev_t *p = &g_wlan;
1575
1576         acquire_bus(ACQUIRE_AND_WAKEUP);
1577         p->hif_func.hif_write_reg(WILC_GLB_RESET_0, 0x0);
1578         release_bus(RELEASE_ONLY);
1579 }
1580 int wilc_wlan_stop(void)
1581 {
1582         wilc_wlan_dev_t *p = &g_wlan;
1583         u32 reg = 0;
1584         int ret;
1585         u8 timeout = 10;
1586         /**
1587          *      TODO: stop the firmware, need a re-download
1588          **/
1589         acquire_bus(ACQUIRE_AND_WAKEUP);
1590
1591         ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1592         if (!ret) {
1593                 PRINT_ER("Error while reading reg\n");
1594                 release_bus(RELEASE_ALLOW_SLEEP);
1595                 return ret;
1596         }
1597
1598         reg &= ~BIT(10);
1599
1600
1601         ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1602         if (!ret) {
1603                 PRINT_ER("Error while writing reg\n");
1604                 release_bus(RELEASE_ALLOW_SLEEP);
1605                 return ret;
1606         }
1607
1608
1609
1610         do {
1611                 ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1612                 if (!ret) {
1613                         PRINT_ER("Error while reading reg\n");
1614                         release_bus(RELEASE_ALLOW_SLEEP);
1615                         return ret;
1616                 }
1617                 PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout);
1618                 /*Workaround to ensure that the chip is actually reset*/
1619                 if ((reg & BIT(10))) {
1620                         PRINT_D(GENERIC_DBG, "Bit 10 not reset : Retry %d\n", timeout);
1621                         reg &= ~BIT(10);
1622                         ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1623                         timeout--;
1624                 } else {
1625                         PRINT_D(GENERIC_DBG, "Bit 10 reset after : Retry %d\n", timeout);
1626                         ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1627                         if (!ret) {
1628                                 PRINT_ER("Error while reading reg\n");
1629                                 release_bus(RELEASE_ALLOW_SLEEP);
1630                                 return ret;
1631                         }
1632                         PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout);
1633                         break;
1634                 }
1635
1636         } while (timeout);
1637         reg = (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(8) | BIT(9) | BIT(26) |
1638                BIT(29) | BIT(30) | BIT(31));
1639
1640         p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1641         reg = (u32)~BIT(10);
1642
1643         ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1644
1645         release_bus(RELEASE_ALLOW_SLEEP);
1646
1647         return ret;
1648 }
1649
1650 void wilc_wlan_cleanup(struct net_device *dev)
1651 {
1652         wilc_wlan_dev_t *p = &g_wlan;
1653         struct txq_entry_t *tqe;
1654         struct rxq_entry_t *rqe;
1655         u32 reg = 0;
1656         int ret;
1657         perInterface_wlan_t *nic;
1658         struct wilc *wilc;
1659
1660         nic = netdev_priv(dev);
1661         wilc = nic->wilc;
1662
1663         p->quit = 1;
1664         do {
1665                 tqe = wilc_wlan_txq_remove_from_head();
1666                 if (tqe == NULL)
1667                         break;
1668                 if (tqe->tx_complete_func)
1669                         tqe->tx_complete_func(tqe->priv, 0);
1670                 kfree(tqe);
1671         } while (1);
1672
1673         do {
1674                 rqe = wilc_wlan_rxq_remove(wilc);
1675                 if (rqe == NULL)
1676                         break;
1677 #ifndef MEMORY_STATIC
1678                 kfree(rqe->buffer);
1679 #endif
1680                 kfree(rqe);
1681         } while (1);
1682
1683         /**
1684          *      clean up buffer
1685          **/
1686
1687         #ifdef MEMORY_STATIC
1688         kfree(p->rx_buffer);
1689         p->rx_buffer = NULL;
1690         #endif
1691         kfree(p->tx_buffer);
1692
1693         acquire_bus(ACQUIRE_AND_WAKEUP);
1694
1695
1696         ret = p->hif_func.hif_read_reg(WILC_GP_REG_0, &reg);
1697         if (!ret) {
1698                 PRINT_ER("Error while reading reg\n");
1699                 release_bus(RELEASE_ALLOW_SLEEP);
1700         }
1701         PRINT_ER("Writing ABORT reg\n");
1702         ret = p->hif_func.hif_write_reg(WILC_GP_REG_0, (reg | ABORT_INT));
1703         if (!ret) {
1704                 PRINT_ER("Error while writing reg\n");
1705                 release_bus(RELEASE_ALLOW_SLEEP);
1706         }
1707         release_bus(RELEASE_ALLOW_SLEEP);
1708         /**
1709          *      io clean up
1710          **/
1711         p->hif_func.hif_deinit(NULL);
1712
1713 }
1714
1715 static int wilc_wlan_cfg_commit(int type, u32 drvHandler)
1716 {
1717         wilc_wlan_dev_t *p = &g_wlan;
1718         wilc_cfg_frame_t *cfg = &p->cfg_frame;
1719         int total_len = p->cfg_frame_offset + 4 + DRIVER_HANDLER_SIZE;
1720         int seq_no = p->cfg_seq_no % 256;
1721         int driver_handler = (u32)drvHandler;
1722
1723
1724         /**
1725          *      Set up header
1726          **/
1727         if (type == WILC_CFG_SET) {             /* Set */
1728                 cfg->wid_header[0] = 'W';
1729         } else {                                        /* Query */
1730                 cfg->wid_header[0] = 'Q';
1731         }
1732         cfg->wid_header[1] = seq_no;    /* sequence number */
1733         cfg->wid_header[2] = (u8)total_len;
1734         cfg->wid_header[3] = (u8)(total_len >> 8);
1735         cfg->wid_header[4] = (u8)driver_handler;
1736         cfg->wid_header[5] = (u8)(driver_handler >> 8);
1737         cfg->wid_header[6] = (u8)(driver_handler >> 16);
1738         cfg->wid_header[7] = (u8)(driver_handler >> 24);
1739         p->cfg_seq_no = seq_no;
1740
1741         /**
1742          *      Add to TX queue
1743          **/
1744
1745         if (!wilc_wlan_txq_add_cfg_pkt(&cfg->wid_header[0], total_len))
1746                 return -1;
1747
1748         return 0;
1749 }
1750
1751 int wilc_wlan_cfg_set(int start, u32 wid, u8 *buffer, u32 buffer_size,
1752                       int commit, u32 drvHandler)
1753 {
1754         wilc_wlan_dev_t *p = &g_wlan;
1755         u32 offset;
1756         int ret_size;
1757
1758
1759         if (p->cfg_frame_in_use)
1760                 return 0;
1761
1762         if (start)
1763                 p->cfg_frame_offset = 0;
1764
1765         offset = p->cfg_frame_offset;
1766         ret_size = wilc_wlan_cfg_set_wid(p->cfg_frame.frame, offset, (u16)wid,
1767                                          buffer, buffer_size);
1768         offset += ret_size;
1769         p->cfg_frame_offset = offset;
1770
1771         if (commit) {
1772                 PRINT_D(TX_DBG, "[WILC]PACKET Commit with sequence number %d\n", p->cfg_seq_no);
1773                 PRINT_D(RX_DBG, "Processing cfg_set()\n");
1774                 p->cfg_frame_in_use = 1;
1775
1776                 if (wilc_wlan_cfg_commit(WILC_CFG_SET, drvHandler))
1777                         ret_size = 0;
1778
1779                 if (linux_wlan_lock_timeout(&g_linux_wlan->cfg_event,
1780                                             CFG_PKTS_TIMEOUT)) {
1781                         PRINT_D(TX_DBG, "Set Timed Out\n");
1782                         ret_size = 0;
1783                 }
1784                 p->cfg_frame_in_use = 0;
1785                 p->cfg_frame_offset = 0;
1786                 p->cfg_seq_no += 1;
1787
1788         }
1789
1790         return ret_size;
1791 }
1792 int wilc_wlan_cfg_get(int start, u32 wid, int commit, u32 drvHandler)
1793 {
1794         wilc_wlan_dev_t *p = &g_wlan;
1795         u32 offset;
1796         int ret_size;
1797
1798
1799         if (p->cfg_frame_in_use)
1800                 return 0;
1801
1802         if (start)
1803                 p->cfg_frame_offset = 0;
1804
1805         offset = p->cfg_frame_offset;
1806         ret_size = wilc_wlan_cfg_get_wid(p->cfg_frame.frame, offset, (u16)wid);
1807         offset += ret_size;
1808         p->cfg_frame_offset = offset;
1809
1810         if (commit) {
1811                 p->cfg_frame_in_use = 1;
1812
1813                 if (wilc_wlan_cfg_commit(WILC_CFG_QUERY, drvHandler))
1814                         ret_size = 0;
1815
1816
1817                 if (linux_wlan_lock_timeout(&g_linux_wlan->cfg_event,
1818                                             CFG_PKTS_TIMEOUT)) {
1819                         PRINT_D(TX_DBG, "Get Timed Out\n");
1820                         ret_size = 0;
1821                 }
1822                 PRINT_D(GENERIC_DBG, "[WILC]Get Response received\n");
1823                 p->cfg_frame_in_use = 0;
1824                 p->cfg_frame_offset = 0;
1825                 p->cfg_seq_no += 1;
1826         }
1827
1828         return ret_size;
1829 }
1830
1831 int wilc_wlan_cfg_get_val(u32 wid, u8 *buffer, u32 buffer_size)
1832 {
1833         int ret;
1834
1835         ret = wilc_wlan_cfg_get_wid_value((u16)wid, buffer, buffer_size);
1836
1837         return ret;
1838 }
1839
1840 void wilc_bus_set_max_speed(void)
1841 {
1842
1843         /* Increase bus speed to max possible.  */
1844         g_wlan.hif_func.hif_set_max_bus_speed();
1845 }
1846
1847 void wilc_bus_set_default_speed(void)
1848 {
1849
1850         /* Restore bus speed to default.  */
1851         g_wlan.hif_func.hif_set_default_bus_speed();
1852 }
1853 u32 init_chip(void)
1854 {
1855         u32 chipid;
1856         u32 reg, ret = 0;
1857
1858         acquire_bus(ACQUIRE_ONLY);
1859
1860         chipid = wilc_get_chipid(true);
1861
1862
1863
1864         if ((chipid & 0xfff) != 0xa0) {
1865                 /**
1866                  * Avoid booting from boot ROM. Make sure that Drive IRQN [SDIO platform]
1867                  * or SD_DAT3 [SPI platform] to ?1?
1868                  **/
1869                 /* Set cortus reset register to register control. */
1870                 ret = g_wlan.hif_func.hif_read_reg(0x1118, &reg);
1871                 if (!ret) {
1872                         wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1118 ...\n");
1873                         return ret;
1874                 }
1875                 reg |= BIT(0);
1876                 ret = g_wlan.hif_func.hif_write_reg(0x1118, reg);
1877                 if (!ret) {
1878                         wilc_debug(N_ERR, "[wilc start]: fail write reg 0x1118 ...\n");
1879                         return ret;
1880                 }
1881                 /**
1882                  * Write branch intruction to IRAM (0x71 trap) at location 0xFFFF0000
1883                  * (Cortus map) or C0000 (AHB map).
1884                  **/
1885                 ret = g_wlan.hif_func.hif_write_reg(0xc0000, 0x71);
1886                 if (!ret) {
1887                         wilc_debug(N_ERR, "[wilc start]: fail write reg 0xc0000 ...\n");
1888                         return ret;
1889                 }
1890         }
1891
1892         release_bus(RELEASE_ONLY);
1893
1894         return ret;
1895
1896 }
1897
1898 u32 wilc_get_chipid(u8 update)
1899 {
1900         static u32 chipid;
1901         /* SDIO can't read into global variables */
1902         /* Use this variable as a temp, then copy to the global */
1903         u32 tempchipid = 0;
1904         u32 rfrevid;
1905
1906         if (chipid == 0 || update != 0) {
1907                 g_wlan.hif_func.hif_read_reg(0x1000, &tempchipid);
1908                 g_wlan.hif_func.hif_read_reg(0x13f4, &rfrevid);
1909                 if (!ISWILC1000(tempchipid)) {
1910                         chipid = 0;
1911                         goto _fail_;
1912                 }
1913                 if (tempchipid == 0x1002a0) {
1914                         if (rfrevid == 0x1) { /* 1002A0 */
1915                         } else { /* if (rfrevid == 0x2) */   /* 1002A1 */
1916                                 tempchipid = 0x1002a1;
1917                         }
1918                 } else if (tempchipid == 0x1002b0) {
1919                         if (rfrevid == 3) { /* 1002B0 */
1920                         } else if (rfrevid == 4) { /* 1002B1 */
1921                                 tempchipid = 0x1002b1;
1922                         } else { /* if(rfrevid == 5) */   /* 1002B2 */
1923                                 tempchipid = 0x1002b2;
1924                         }
1925                 } else {
1926                 }
1927
1928                 chipid = tempchipid;
1929         }
1930 _fail_:
1931         return chipid;
1932 }
1933
1934 int wilc_wlan_init(wilc_wlan_inp_t *inp)
1935 {
1936
1937         int ret = 0;
1938
1939         PRINT_D(INIT_DBG, "Initializing WILC_Wlan ...\n");
1940
1941         memset((void *)&g_wlan, 0, sizeof(wilc_wlan_dev_t));
1942
1943         /**
1944          *      store the input
1945          **/
1946         memcpy((void *)&g_wlan.io_func, (void *)&inp->io_func, sizeof(wilc_wlan_io_func_t));
1947         /***
1948          *      host interface init
1949          **/
1950         if ((inp->io_func.io_type & 0x1) == HIF_SDIO) {
1951                 if (!hif_sdio.hif_init(inp, wilc_debug)) {
1952                         /* EIO  5 */
1953                         ret = -5;
1954                         goto _fail_;
1955                 }
1956                 memcpy((void *)&g_wlan.hif_func, &hif_sdio, sizeof(wilc_hif_func_t));
1957         } else {
1958                 if ((inp->io_func.io_type & 0x1) == HIF_SPI) {
1959                         /**
1960                          *      TODO:
1961                          **/
1962                         if (!hif_spi.hif_init(inp, wilc_debug)) {
1963                                 /* EIO  5 */
1964                                 ret = -5;
1965                                 goto _fail_;
1966                         }
1967                         memcpy((void *)&g_wlan.hif_func, &hif_spi, sizeof(wilc_hif_func_t));
1968                 } else {
1969                         /* EIO  5 */
1970                         ret = -5;
1971                         goto _fail_;
1972                 }
1973         }
1974
1975         /***
1976          *      mac interface init
1977          **/
1978         if (!wilc_wlan_cfg_init(wilc_debug)) {
1979                 /* ENOBUFS      105 */
1980                 ret = -105;
1981                 goto _fail_;
1982         }
1983
1984         /**
1985          *      alloc tx, rx buffer
1986          **/
1987         if (g_wlan.tx_buffer == NULL)
1988                 g_wlan.tx_buffer = kmalloc(LINUX_TX_SIZE, GFP_KERNEL);
1989         PRINT_D(TX_DBG, "g_wlan.tx_buffer = %p\n", g_wlan.tx_buffer);
1990
1991         if (g_wlan.tx_buffer == NULL) {
1992                 /* ENOBUFS      105 */
1993                 ret = -105;
1994                 PRINT_ER("Can't allocate Tx Buffer");
1995                 goto _fail_;
1996         }
1997
1998 /* rx_buffer is not used unless we activate USE_MEM STATIC which is not applicable, allocating such memory is useless*/
1999 #if defined (MEMORY_STATIC)
2000         if (g_wlan.rx_buffer == NULL)
2001                 g_wlan.rx_buffer = kmalloc(LINUX_RX_SIZE, GFP_KERNEL);
2002         PRINT_D(TX_DBG, "g_wlan.rx_buffer =%p\n", g_wlan.rx_buffer);
2003         if (g_wlan.rx_buffer == NULL) {
2004                 /* ENOBUFS      105 */
2005                 ret = -105;
2006                 PRINT_ER("Can't allocate Rx Buffer");
2007                 goto _fail_;
2008         }
2009 #endif
2010
2011         if (!init_chip()) {
2012                 /* EIO  5 */
2013                 ret = -5;
2014                 goto _fail_;
2015         }
2016 #ifdef  TCP_ACK_FILTER
2017         Init_TCP_tracking();
2018 #endif
2019
2020         return 1;
2021
2022 _fail_:
2023
2024   #ifdef MEMORY_STATIC
2025         kfree(g_wlan.rx_buffer);
2026         g_wlan.rx_buffer = NULL;
2027   #endif
2028         kfree(g_wlan.tx_buffer);
2029         g_wlan.tx_buffer = NULL;
2030
2031         return ret;
2032
2033 }
2034
2035 u16 Set_machw_change_vir_if(bool bValue)
2036 {
2037         u16 ret;
2038         u32 reg;
2039
2040         /*Reset WILC_CHANGING_VIR_IF register to allow adding futrue keys to CE H/W*/
2041         mutex_lock(&g_linux_wlan->hif_cs);
2042         ret = (&g_wlan)->hif_func.hif_read_reg(WILC_CHANGING_VIR_IF, &reg);
2043         if (!ret)
2044                 PRINT_ER("Error while Reading reg WILC_CHANGING_VIR_IF\n");
2045
2046         if (bValue)
2047                 reg |= BIT(31);
2048         else
2049                 reg &= ~BIT(31);
2050
2051         ret = (&g_wlan)->hif_func.hif_write_reg(WILC_CHANGING_VIR_IF, reg);
2052
2053         if (!ret)
2054                 PRINT_ER("Error while writing reg WILC_CHANGING_VIR_IF\n");
2055
2056         mutex_unlock(&g_linux_wlan->hif_cs);
2057
2058         return ret;
2059 }