1 #ifndef __WINBOND_WBHAL_S_H
2 #define __WINBOND_WBHAL_S_H
4 #include <linux/types.h>
5 #include <linux/if_ether.h> /* for ETH_ALEN */
8 #define HAL_LED_SET_MASK 0x001c //20060901 Extend
9 #define HAL_LED_SET_SHIFT 2
12 #define RF_MAXIM_2825 0
13 #define RF_MAXIM_2827 1
14 #define RF_MAXIM_2828 2
15 #define RF_MAXIM_2829 3
16 #define RF_MAXIM_V1 15
17 #define RF_AIROHA_2230 16
18 #define RF_AIROHA_7230 17
19 #define RF_AIROHA_2230S 18 // 20060420 Add this
20 // #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
22 #define RF_WB_242_1 34 // 20060619.5 Add
23 #define RF_DECIDE_BY_INF 255
25 //----------------------------------------------------------------
26 // The follow define connect to upper layer
27 // User must modify for connection between HAL and upper layer
28 //----------------------------------------------------------------
33 /////////////////////////////////////////////////////////////////////////////////////////////////////
34 //================================================================================================
36 //================================================================================================
37 #define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
40 #define SCAN_MAX_CHNL_TIME (50)
42 // For TxL2 Frame typr recognise
43 #define FRAME_TYPE_802_3_DATA 0
44 #define FRAME_TYPE_802_11_MANAGEMENT 1
45 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
46 #define FRAME_TYPE_802_11_CONTROL 3
47 #define FRAME_TYPE_802_11_DATA 4
48 #define FRAME_TYPE_PROMISCUOUS 5
50 // The follow definition is used for convert the frame--------------------
51 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
52 #define DOT_3_TYPE_OFFSET 12
53 #define DOT_11_MAC_HEADER_SIZE 24
54 #define DOT_11_SNAP_SIZE 6
55 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
56 #define DEFAULT_SIFSTIME 10
57 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
58 #define DEFAULT_MSDU_LIFE_TIME 0xffff
60 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
61 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
62 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
65 // Frame Type of Bits (2, 3)---------------------------------------------
66 #define MAC_TYPE_MANAGEMENT 0x00
67 #define MAC_TYPE_CONTROL 0x04
68 #define MAC_TYPE_DATA 0x08
69 #define MASK_FRAGMENT_NUMBER 0x000F
70 #define SEQUENCE_NUMBER_SHIFT 4
72 #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
73 #define HAL_WOL_TYPE_MAGIC_PACKET 0x02
76 #define HAL_KEYTYPE_WEP40 0
77 #define HAL_KEYTYPE_WEP104 1
78 #define HAL_KEYTYPE_TKIP 2 // 128 bit key
79 #define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
88 // Be used for 802.11 mac header
89 typedef struct _MAC_FRAME_CONTROL {
90 u8 mac_frame_info; // this is a combination of the protovl version, type and subtype
99 } MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
101 //-----------------------------------------------------
102 // Normal Key table format
103 //-----------------------------------------------------
104 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
105 #define MAX_KEY_TABLE 24 // 24 entry for storing key data
106 #define GROUP_KEY_START_INDEX 4
107 #define MAPPING_KEY_START_INDEX 8
108 typedef struct _KEY_TABLE
112 u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
119 u32 DW2_RxSequenceCount1;
121 u32 DW3_RxSequenceCount2:16;
124 u32 DW4_TxSequenceCount1;
126 u32 DW5_TxSequenceCount2:16;
129 } KEY_TABLE, *PKEY_TABLE;
131 //--------------------------------------------------------
133 //--------------------------------------------------------
134 #define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
135 //#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
136 #define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
137 //#define FLAG_ERROR_RX_MASK 0x00000c3f
138 //#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
139 //Don't care replay error,
140 //it is handled by S/W
141 #define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
143 #define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
145 typedef struct _R00_DESCRIPTOR
150 #ifdef _BIG_ENDIAN_ //20060926 anson's endian
153 u32 R00_packet_or_buffer_status:1;
154 u32 R00_packet_in_fifo:1;
156 u32 R00_receive_byte_count:12;
157 u32 R00_receive_time_index:16;
162 u32 R00_receive_time_index:16;
163 u32 R00_receive_byte_count:12;
165 u32 R00_packet_in_fifo:1;
166 u32 R00_packet_or_buffer_status:1;
170 } R00_DESCRIPTOR, *PR00_DESCRIPTOR;
172 typedef struct _T00_DESCRIPTOR
177 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
180 u32 T00_first_mpdu:1; // for hardware use
181 u32 T00_last_mpdu:1; // for hardware use
182 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
183 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
184 u32 T00_RESERVED_ID:2;//3 bit ID reserved
185 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
187 u32 T00_header_length:6;
188 u32 T00_frame_length:12;
193 u32 T00_frame_length:12;
194 u32 T00_header_length:6;
196 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
197 u32 T00_RESERVED_ID:2;//3 bit ID reserved
198 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
199 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
200 u32 T00_last_mpdu:1; // for hardware use
201 u32 T00_first_mpdu:1; // for hardware use
205 } T00_DESCRIPTOR, *PT00_DESCRIPTOR;
207 typedef struct _R01_DESCRIPTOR
212 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
221 u32 R01_decryption_method:2;
224 u32 R01_broadcast_frame:1;
225 u32 R01_multicast_frame:1;
226 u32 R01_directed_frame:1;
227 u32 R01_receive_frame_antenna_selection:1;
228 u32 R01_frame_receive_during_atim_window:1;
229 u32 R01_protocol_version_error:1;
230 u32 R01_authentication_frame_icv_error:1;
231 u32 R01_null_key_to_authentication_frame:1;
240 u32 R01_null_key_to_authentication_frame:1;
241 u32 R01_authentication_frame_icv_error:1;
242 u32 R01_protocol_version_error:1;
243 u32 R01_frame_receive_during_atim_window:1;
244 u32 R01_receive_frame_antenna_selection:1;
245 u32 R01_directed_frame:1;
246 u32 R01_multicast_frame:1;
247 u32 R01_broadcast_frame:1;
250 u32 R01_decryption_method:2;
260 } R01_DESCRIPTOR, *PR01_DESCRIPTOR;
262 typedef struct _T01_DESCRIPTOR
267 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
270 u32 T01_rts_cts_duration:16;
271 u32 T01_fall_back_rate:3;
274 u32 T01_modulation_type:1;
275 u32 T01_plcp_header_length:1;
276 u32 T01_transmit_rate:3;
278 u32 T01_add_challenge_text:1;
279 u32 T01_inhibit_crc:1;
280 u32 T01_loop_back_wep_mode:1;
281 u32 T01_retry_abort_ebable:1;
286 u32 T01_retry_abort_ebable:1;
287 u32 T01_loop_back_wep_mode:1;
288 u32 T01_inhibit_crc:1;
289 u32 T01_add_challenge_text:1;
291 u32 T01_transmit_rate:3;
292 u32 T01_plcp_header_length:1;
293 u32 T01_modulation_type:1;
296 u32 T01_fall_back_rate:3;
297 u32 T01_rts_cts_duration:16;
301 } T01_DESCRIPTOR, *PT01_DESCRIPTOR;
303 typedef struct _T02_DESCRIPTOR
308 #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
311 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
312 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
313 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
318 u32 T02_transmit_complete:1;
319 u32 T02_transmit_abort_due_to_TBTT:1;
320 u32 T02_effective_transmission_rate:1;
321 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
322 u32 T02_discard_due_to_null_wep_key:1;
323 u32 T02_RESERVED_1:1;
324 u32 T02_out_of_MaxTxMSDULiftTime:1;
325 u32 T02_transmit_abort:1;
326 u32 T02_transmit_fail:1;
331 u32 T02_transmit_fail:1;
332 u32 T02_transmit_abort:1;
333 u32 T02_out_of_MaxTxMSDULiftTime:1;
334 u32 T02_RESERVED_1:1;
335 u32 T02_discard_due_to_null_wep_key:1;
336 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
337 u32 T02_effective_transmission_rate:1;
338 u32 T02_transmit_abort_due_to_TBTT:1;
339 u32 T02_transmit_complete:1;
344 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
345 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
346 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
350 } T02_DESCRIPTOR, *PT02_DESCRIPTOR;
352 typedef struct _DESCRIPTOR { // Skip length = 8 DWORD
353 // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
355 //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
358 u16 FragmentThreshold;
359 u8 InternalUsed;//Only can be used by operation of descriptor definition
360 u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
362 u8 PreambleMode;// 0: short 1:long
365 u8 EapFix; // For speed up key install
367 // For R00 and T00 ----------------------------------------------
374 // For R01 and T01 ----------------------------------------------
381 // For R02 and T02 ----------------------------------------------
388 // For R03 and T03 ----------------------------------------------
397 u8 buffer_start_index;
398 u16 buffer_total_size;
402 // For storing the buffer
403 u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
404 void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
406 } DESCRIPTOR, *PDESCRIPTOR;
409 #define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
411 #define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
412 #define MAX_RF_PARAMETER 32
414 typedef struct _TXVGA_FOR_50 {
420 //=====================================================================
421 // Device related include
422 //=====================================================================
425 #include "wb35reg_s.h"
426 #include "wb35tx_s.h"
427 #include "wb35rx_s.h"
429 // For Hal using ==================================================================
430 typedef struct _HW_DATA_T
432 // For compatible with 33
434 u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
435 u32 BB54_cal; // The value for Rx calibration comes from EEPROM
438 // For surprise remove
439 u32 SurpriseRemove; // 0: Normal 1: Surprise remove
442 u8 CalOneTime; // 20060630.1
446 // For Fix 1'st DMA bug
448 u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
450 //===============================================
451 // Definition for MAC address
452 //===============================================
453 u8 PermanentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
454 u8 CurrentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
456 //=====================================================================
457 // Definition for 802.11
458 //=====================================================================
459 u8 *bssid_pointer; // Used by hal_get_bssid for return value
460 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
461 u8 ssid[32];// maximum ssid length is 32 byte
468 u16 CapabilityInformation;
473 u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
474 u8 preamble;// 0: short preamble, 1: long preamble
475 u8 slot_time_select;// 9 or 20 value
476 u8 phy_type;// Phy select
478 u32 phy_para[MAX_RF_PARAMETER];
481 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
482 u32 CurrentRadioHw; // 20060825 0:On 1:Off
484 u8 *power_save_point; // Used by hal_get_power_save_mode for return value
486 u8 desired_power_save;
487 u8 dtim;// Is running dtim
488 u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
490 u16 MaxReceiveLifeTime;
491 u16 FragmentThreshold;
492 u16 FragmentThreshold_tmp;
495 u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
496 u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
497 u8 CurrentDefaultKeyIndex;
498 u32 CurrentDefaultKeyLength;
500 //========================================================================
501 // Variable for each module
502 //========================================================================
503 WBUSB WbUsb; // Need WbUsb.h
504 struct wb35_reg reg; // Need Wb35Reg.h
505 WB35TX Wb35Tx; // Need Wb35Tx.h
506 WB35RX Wb35Rx; // Need Wb35Rx.h
508 struct timer_list LEDTimer;// For LED
510 u32 LEDpoint;// For LED
512 u32 dto_tx_retry_count; // LA20040210_DTO kevin
513 u32 dto_tx_frag_count; // LA20040210_DTO kevin
514 u32 rx_ok_count[13]; // index=0: total rx ok
515 //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
516 u32 rx_err_count[13]; // index=0: total rx err
519 u32 tx_TBTT_start_count;
521 u32 tx_WepOn_false_count;
522 u32 tx_Null_key_count;
523 u32 tx_retry_count[8];
525 u8 PowerIndexFromEEPROM; // For 2412MHz
527 u8 IsWaitJoinComplete; // TRUE: set join request
533 u32 IsInitOK; // 0: Driver starting 1: Driver init OK
535 // For Phy calibration
536 s32 iq_rsdl_gain_tx_d2;
537 s32 iq_rsdl_phase_tx_d2;
538 u32 txvga_setting_for_cal; // 20060703.1 Add
540 u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
541 u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
542 TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
549 // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
551 // For Led gray setting
553 // 0: normal control, LED behavior will decide by EEPROM setting
554 // 1: Turn off specific LED
555 // 2: Always on specific LED
556 // 3: slow blinking specific LED
557 // 4: fast blinking specific LED
558 // 5: WPS led control is set. Led0 is Red, Led1 id Green
559 // Led[1] is parameter for WPS LED mode
560 // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
562 u32 LED_LinkOn; //Turn LED on control
563 u32 LED_Scanning; // Let LED in scan process control
564 u32 LED_Blinking; // Temp variable for shining
568 atomic_t SurpriseRemoveCount;
571 u32 time_count;//TICK_TIME_100ms 1 = 100ms
576 // 20060828.1 for avoid AP disconnect
579 } hw_data_t, *phw_data_t;
581 // The mapping of Rx and Tx descriptor field
582 typedef struct _HAL_RATE
608 } HAL_RATE, *PHAL_RATE;