3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/delay.h> /* udelay */
11 #include "vb_setmode.h"
18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
20 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
21 { 2, 13, 9, 64, 0x45},
22 { 2, 12, 9, 32, 0x35},
23 { 2, 12, 8, 16, 0x31},
24 { 2, 11, 8, 8, 0x21} };
26 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
27 { 2, 14, 11, 128, 0x5D},
28 { 2, 14, 10, 64, 0x59},
29 { 2, 13, 11, 64, 0x4D},
30 { 2, 14, 9, 32, 0x55},
31 { 2, 13, 10, 32, 0x49},
32 { 2, 12, 11, 32, 0x3D},
33 { 2, 14, 8, 16, 0x51},
34 { 2, 13, 9, 16, 0x45},
35 { 2, 12, 10, 16, 0x39},
38 { 2, 12, 8, 4, 0x31} };
40 static int XGINew_RAMType;
42 static void DelayUS(unsigned long MicroSeconds)
47 static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
48 struct vb_device_info *pVBInfo)
50 unsigned char data, temp;
52 if (HwDeviceExtension->jChipType < XG20) {
53 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
54 data = *pVBInfo->pSoftSetting & 0x07;
57 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39) & 0x02;
60 data = (XGINew_GetReg1(pVBInfo->P3c4, 0x3A) & 0x02) >> 1;
64 } else if (HwDeviceExtension->jChipType == XG27) {
65 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
66 data = *pVBInfo->pSoftSetting & 0x07;
69 temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
71 if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
76 } else if (HwDeviceExtension->jChipType == XG21) {
77 XGINew_SetRegAND(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
79 XGINew_SetRegOR(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
80 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
82 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */
83 if (temp & 0x01) /* DVI read GPIOH */
87 /* ~HOTPLUG_SUPPORT */
88 XGINew_SetRegOR(pVBInfo->P3d4, 0xB4, 0x02);
91 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97) & 0x01;
100 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
102 XGINew_SetReg1(P3c4, 0x18, 0x01);
103 XGINew_SetReg1(P3c4, 0x19, 0x20);
104 XGINew_SetReg1(P3c4, 0x16, 0x00);
105 XGINew_SetReg1(P3c4, 0x16, 0x80);
107 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
108 DelayUS(3000); /* Delay 67 x 3 Delay15us */
109 XGINew_SetReg1(P3c4, 0x18, 0x00);
110 XGINew_SetReg1(P3c4, 0x19, 0x20);
111 XGINew_SetReg1(P3c4, 0x16, 0x00);
112 XGINew_SetReg1(P3c4, 0x16, 0x80);
116 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
117 XGINew_SetReg1(P3c4, 0x19, 0x01);
118 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[0]);
119 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[1]);
121 XGINew_SetReg1(P3c4, 0x1B, 0x03);
123 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
124 XGINew_SetReg1(P3c4, 0x19, 0x00);
125 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[2]);
126 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[3]);
127 XGINew_SetReg1(P3c4, 0x1B, 0x00);
130 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
131 struct vb_device_info *pVBInfo)
134 XGINew_SetReg1(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
135 XGINew_SetReg1(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
136 XGINew_SetReg1(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
138 XGINew_SetReg1(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
139 XGINew_SetReg1(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
140 XGINew_SetReg1(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
142 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
143 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
144 if (HwDeviceExtension->jChipType == XG42) {
145 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
146 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
147 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
148 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
149 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
150 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
151 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
155 static void XGINew_DDRII_Bootup_XG27(
156 struct xgi_hw_device_info *HwDeviceExtension,
157 unsigned long P3c4, struct vb_device_info *pVBInfo)
159 unsigned long P3d4 = P3c4 + 0x10;
160 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
161 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
163 /* Set Double Frequency */
164 /* XGINew_SetReg1(P3d4, 0x97, 0x11); *//* CR97 */
165 XGINew_SetReg1(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
169 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
170 XGINew_SetReg1(P3c4, 0x19, 0x80); /* Set SR19 */
171 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
173 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
176 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
177 XGINew_SetReg1(P3c4, 0x19, 0xC0); /* Set SR19 */
178 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
180 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
183 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
184 XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
185 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
187 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
190 XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
191 XGINew_SetReg1(P3c4, 0x19, 0x0A); /* Set SR19 */
192 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
194 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
195 XGINew_SetReg1(P3c4, 0x16, 0x80); /* Set SR16 */
198 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B */
200 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* Set SR1B */
202 XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
203 XGINew_SetReg1(P3c4, 0x19, 0x08); /* Set SR19 */
204 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
207 XGINew_SetReg1(P3c4, 0x16, 0x83); /* Set SR16 */
210 XGINew_SetReg1(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
211 XGINew_SetReg1(P3c4, 0x19, 0x46); /* Set SR19 */
212 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
214 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
217 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
218 XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
219 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
221 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
224 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
229 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
230 unsigned long P3c4, struct vb_device_info *pVBInfo)
232 unsigned long P3d4 = P3c4 + 0x10;
234 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
235 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
237 XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
240 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
241 XGINew_SetReg1(P3c4, 0x19, 0x80);
242 XGINew_SetReg1(P3c4, 0x16, 0x05);
243 XGINew_SetReg1(P3c4, 0x16, 0x85);
245 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS3 */
246 XGINew_SetReg1(P3c4, 0x19, 0xC0);
247 XGINew_SetReg1(P3c4, 0x16, 0x05);
248 XGINew_SetReg1(P3c4, 0x16, 0x85);
250 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS1 */
251 XGINew_SetReg1(P3c4, 0x19, 0x40);
252 XGINew_SetReg1(P3c4, 0x16, 0x05);
253 XGINew_SetReg1(P3c4, 0x16, 0x85);
255 /* XGINew_SetReg1(P3c4, 0x18, 0x52); */ /* MRS1 */
256 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
257 XGINew_SetReg1(P3c4, 0x19, 0x02);
258 XGINew_SetReg1(P3c4, 0x16, 0x05);
259 XGINew_SetReg1(P3c4, 0x16, 0x85);
262 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
264 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
267 /* XGINew_SetReg1(P3c4 ,0x18, 0x52); */ /* MRS2 */
268 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
269 XGINew_SetReg1(P3c4, 0x19, 0x00);
270 XGINew_SetReg1(P3c4, 0x16, 0x05);
271 XGINew_SetReg1(P3c4, 0x16, 0x85);
276 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
279 XGINew_SetReg1(P3c4, 0x18, 0x01);
280 XGINew_SetReg1(P3c4, 0x19, 0x40);
281 XGINew_SetReg1(P3c4, 0x16, 0x00);
282 XGINew_SetReg1(P3c4, 0x16, 0x80);
285 XGINew_SetReg1(P3c4, 0x18, 0x00);
286 XGINew_SetReg1(P3c4, 0x19, 0x40);
287 XGINew_SetReg1(P3c4, 0x16, 0x00);
288 XGINew_SetReg1(P3c4, 0x16, 0x80);
290 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
291 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
292 XGINew_SetReg1(P3c4, 0x19, 0x01);
293 XGINew_SetReg1(P3c4, 0x16, 0x03);
294 XGINew_SetReg1(P3c4, 0x16, 0x83);
296 XGINew_SetReg1(P3c4, 0x1B, 0x03);
298 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
299 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
300 XGINew_SetReg1(P3c4, 0x19, 0x00);
301 XGINew_SetReg1(P3c4, 0x16, 0x03);
302 XGINew_SetReg1(P3c4, 0x16, 0x83);
303 XGINew_SetReg1(P3c4, 0x1B, 0x00);
306 static void XGINew_DDR1x_DefaultRegister(
307 struct xgi_hw_device_info *HwDeviceExtension,
308 unsigned long Port, struct vb_device_info *pVBInfo)
310 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
312 if (HwDeviceExtension->jChipType >= XG20) {
313 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
314 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
315 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
316 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
318 XGINew_SetReg1(P3d4, 0x98, 0x01);
319 XGINew_SetReg1(P3d4, 0x9A, 0x02);
321 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
323 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
325 switch (HwDeviceExtension->jChipType) {
328 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
329 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
330 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
333 XGINew_SetReg1(P3d4, 0x82, 0x88);
334 XGINew_SetReg1(P3d4, 0x86, 0x00);
335 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
336 XGINew_SetReg1(P3d4, 0x86, 0x88);
337 XGINew_GetReg1(P3d4, 0x86);
338 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
339 XGINew_SetReg1(P3d4, 0x82, 0x77);
340 XGINew_SetReg1(P3d4, 0x85, 0x00);
341 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
342 XGINew_SetReg1(P3d4, 0x85, 0x88);
343 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
344 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
345 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
349 XGINew_SetReg1(P3d4, 0x97, 0x00);
350 XGINew_SetReg1(P3d4, 0x98, 0x01);
351 XGINew_SetReg1(P3d4, 0x9A, 0x02);
352 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
356 static void XGINew_DDR2_DefaultRegister(
357 struct xgi_hw_device_info *HwDeviceExtension,
358 unsigned long Port, struct vb_device_info *pVBInfo)
360 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
362 /* keep following setting sequence, each setting in the same reg insert idle */
363 XGINew_SetReg1(P3d4, 0x82, 0x77);
364 XGINew_SetReg1(P3d4, 0x86, 0x00);
365 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
366 XGINew_SetReg1(P3d4, 0x86, 0x88);
367 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
368 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
369 XGINew_SetReg1(P3d4, 0x82, 0x77);
370 XGINew_SetReg1(P3d4, 0x85, 0x00);
371 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
372 XGINew_SetReg1(P3d4, 0x85, 0x88);
373 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
374 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
375 if (HwDeviceExtension->jChipType == XG27)
376 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
378 XGINew_SetReg1(P3d4, 0x82, 0xA8); /* CR82 */
380 XGINew_SetReg1(P3d4, 0x98, 0x01);
381 XGINew_SetReg1(P3d4, 0x9A, 0x02);
382 if (HwDeviceExtension->jChipType == XG27)
383 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
385 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
388 static void XGINew_SetDRAMDefaultRegister340(
389 struct xgi_hw_device_info *HwDeviceExtension,
390 unsigned long Port, struct vb_device_info *pVBInfo)
392 unsigned char temp, temp1, temp2, temp3, i, j, k;
394 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
396 XGINew_SetReg1(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
397 XGINew_SetReg1(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
398 XGINew_SetReg1(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
399 XGINew_SetReg1(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
402 for (i = 0; i < 4; i++) {
403 temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */
404 for (j = 0; j < 4; j++) {
405 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
407 XGINew_SetReg1(P3d4, 0x6B, temp2);
408 XGINew_GetReg1(P3d4, 0x6B); /* Insert read command for delay */
415 for (i = 0; i < 4; i++) {
416 temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */
417 for (j = 0; j < 4; j++) {
418 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
420 XGINew_SetReg1(P3d4, 0x6E, temp2);
421 XGINew_GetReg1(P3d4, 0x6E); /* Insert read command for delay */
428 for (k = 0; k < 4; k++) {
429 XGINew_SetRegANDOR(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */
431 for (i = 0; i < 8; i++) {
432 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */
433 for (j = 0; j < 4; j++) {
434 temp1 = (temp >> (2 * j)) & 0x03;
436 XGINew_SetReg1(P3d4, 0x6F, temp2);
437 XGINew_GetReg1(P3d4, 0x6F); /* Insert read command for delay */
445 XGINew_SetReg1(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
446 XGINew_SetReg1(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
449 temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */
450 for (j = 0; j < 4; j++) {
451 temp1 = (temp >> (2 * j)) & 0x03;
453 XGINew_SetReg1(P3d4, 0x89, temp2);
454 XGINew_GetReg1(P3d4, 0x89); /* Insert read command for delay */
459 temp = pVBInfo->CR89[XGINew_RAMType][1];
462 XGINew_SetReg1(P3d4, 0x89, temp2);
464 temp = pVBInfo->CR40[3][XGINew_RAMType];
466 temp2 = (temp >> 4) & 0x07;
468 XGINew_SetReg1(P3d4, 0x45, temp1); /* CR45 */
469 XGINew_SetReg1(P3d4, 0x99, temp2); /* CR99 */
470 XGINew_SetRegOR(P3d4, 0x40, temp3); /* CR40_D[7] */
471 XGINew_SetReg1(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
473 if (HwDeviceExtension->jChipType == XG27)
474 XGINew_SetReg1(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
476 for (j = 0; j <= 6; j++)
477 XGINew_SetReg1(P3d4, (0x90 + j),
478 pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */
480 for (j = 0; j <= 2; j++)
481 XGINew_SetReg1(P3d4, (0xC3 + j),
482 pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */
484 for (j = 0; j < 2; j++)
485 XGINew_SetReg1(P3d4, (0x8A + j),
486 pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */
488 if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42))
489 XGINew_SetReg1(P3d4, 0x8C, 0x87);
491 XGINew_SetReg1(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
493 XGINew_SetReg1(P3d4, 0x83, 0x09); /* CR83 */
494 XGINew_SetReg1(P3d4, 0x87, 0x00); /* CR87 */
495 XGINew_SetReg1(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
496 if (XGINew_RAMType) {
497 /* XGINew_SetReg1(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
498 XGINew_SetReg1(P3c4, 0x17, 0x80); /* SR17 DDRII */
499 if (HwDeviceExtension->jChipType == XG27)
500 XGINew_SetReg1(P3c4, 0x17, 0x02); /* SR17 DDRII */
503 XGINew_SetReg1(P3c4, 0x17, 0x00); /* SR17 DDR */
505 XGINew_SetReg1(P3c4, 0x1A, 0x87); /* SR1A */
507 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
509 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
511 XGINew_SetReg1(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
512 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
514 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
517 static void XGINew_SetDRAMSizingType(int index,
518 unsigned short DRAMTYPE_TABLE[][5],
519 struct vb_device_info *pVBInfo)
523 data = DRAMTYPE_TABLE[index][4];
524 XGINew_SetRegANDOR(pVBInfo->P3c4, 0x13, 0x80, data);
526 /* should delay 50 ns */
529 static unsigned short XGINew_SetDRAMSizeReg(int index,
530 unsigned short DRAMTYPE_TABLE[][5],
531 struct vb_device_info *pVBInfo)
533 unsigned short data = 0, memsize = 0;
535 unsigned char ChannelNo;
537 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
538 data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
546 if (XGINew_ChannelAB == 3)
549 ChannelNo = XGINew_ChannelAB;
551 if (ChannelNo * RankSize <= 256) {
552 while ((RankSize >>= 1) > 0)
557 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
558 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
560 /* data |= XGINew_ChannelAB << 2; */
561 /* data |= (XGINew_DataBusWidth / 64) << 1; */
562 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
565 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
570 static unsigned short XGINew_SetDRAMSize20Reg(int index,
571 unsigned short DRAMTYPE_TABLE[][5],
572 struct vb_device_info *pVBInfo)
574 unsigned short data = 0, memsize = 0;
576 unsigned char ChannelNo;
578 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
579 data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
587 if (XGINew_ChannelAB == 3)
590 ChannelNo = XGINew_ChannelAB;
592 if (ChannelNo * RankSize <= 256) {
593 while ((RankSize >>= 1) > 0)
598 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
599 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
602 /* data |= XGINew_ChannelAB << 2; */
603 /* data |= (XGINew_DataBusWidth / 64) << 1; */
604 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
607 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
612 static int XGINew_ReadWriteRest(unsigned short StopAddr,
613 unsigned short StartAddr, struct vb_device_info *pVBInfo)
616 unsigned long Position = 0;
618 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
620 for (i = StartAddr; i <= StopAddr; i++) {
622 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
625 DelayUS(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
629 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
632 for (i = StartAddr; i <= StopAddr; i++) {
634 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
640 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
644 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
646 if ((data & 0x10) == 0) {
647 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39);
648 data = (data & 0x02) >> 1;
655 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
656 struct vb_device_info *pVBInfo)
660 switch (HwDeviceExtension->jChipType) {
663 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
665 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
667 if (data == 0) { /* Single_32_16 */
669 if ((HwDeviceExtension->ulVideoMemorySize - 1)
672 XGINew_DataBusWidth = 32; /* 32 bits */
673 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
674 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
677 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
680 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
681 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
682 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
685 if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
690 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
691 XGINew_DataBusWidth = 16; /* 16 bits */
692 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
693 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41);
696 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
699 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31);
703 } else { /* Dual_16_8 */
704 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
706 XGINew_DataBusWidth = 16; /* 16 bits */
707 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
708 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
711 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
714 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
715 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
716 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
719 if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
724 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
725 XGINew_DataBusWidth = 8; /* 8 bits */
726 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
727 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
730 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
733 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
740 XGINew_DataBusWidth = 16; /* 16 bits */
741 XGINew_ChannelAB = 1; /* Single channel */
742 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
745 if (XGINew_CheckFrequence(pVBInfo) == 1) {
746 XGINew_DataBusWidth = 32; /* 32 bits */
747 XGINew_ChannelAB = 3; /* Quad Channel */
748 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
749 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
751 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
754 XGINew_ChannelAB = 2; /* Dual channels */
755 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
757 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
760 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x49);
762 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
765 XGINew_ChannelAB = 3;
766 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
767 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
769 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
772 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
774 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
777 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x39);
779 XGINew_DataBusWidth = 64; /* 64 bits */
780 XGINew_ChannelAB = 2; /* Dual channels */
781 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
782 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
784 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
787 XGINew_ChannelAB = 1; /* Single channels */
788 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
790 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
793 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x53);
795 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
798 XGINew_ChannelAB = 2; /* Dual channels */
799 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
800 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
802 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
805 XGINew_ChannelAB = 1; /* Single channels */
806 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
808 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
811 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x43);
818 XG42 SR14 D[3] Reserve
819 D[2] = 1, Dual Channel
822 It's Different from Other XG40 Series.
824 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
825 XGINew_DataBusWidth = 32; /* 32 bits */
826 XGINew_ChannelAB = 2; /* 2 Channel */
827 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
828 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x44);
830 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
833 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
834 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x34);
835 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
838 XGINew_ChannelAB = 1; /* Single Channel */
839 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
840 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x40);
842 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
845 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
846 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30);
849 XGINew_DataBusWidth = 64; /* 64 bits */
850 XGINew_ChannelAB = 1; /* 1 channels */
851 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
852 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
854 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
857 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
858 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
866 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
867 XGINew_DataBusWidth = 32; /* 32 bits */
868 XGINew_ChannelAB = 3;
869 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
870 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
872 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
875 XGINew_ChannelAB = 2; /* 2 channels */
876 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
878 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
881 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
882 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
884 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
885 XGINew_ChannelAB = 3; /* 4 channels */
887 XGINew_ChannelAB = 2; /* 2 channels */
888 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
891 XGINew_DataBusWidth = 64; /* 64 bits */
892 XGINew_ChannelAB = 2; /* 2 channels */
893 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
894 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
896 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
899 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
900 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
907 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
908 struct vb_device_info *pVBInfo)
911 unsigned short memsize, addr;
913 XGINew_SetReg1(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
914 XGINew_SetReg1(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
915 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
917 if (HwDeviceExtension->jChipType >= XG20) {
918 for (i = 0; i < 12; i++) {
919 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
920 memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
924 addr = memsize + (XGINew_ChannelAB - 2) + 20;
925 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
928 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
932 for (i = 0; i < 4; i++) {
933 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
934 memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
939 addr = memsize + (XGINew_ChannelAB - 2) + 20;
940 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
943 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
950 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
951 struct vb_device_info *pVBInfo)
955 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
956 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
958 XGISetModeNew(HwDeviceExtension, 0x2e);
960 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
961 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
962 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
964 /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x1); */
966 /* XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
967 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
968 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
969 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
972 static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
974 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
977 /* Volari customize data area end */
979 if (ChipType == XG21) {
980 pVBInfo->IF_DEF_LVDS = 0;
981 if (pVideoMemory[0x65] & 0x1) {
982 pVBInfo->IF_DEF_LVDS = 1;
983 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
984 j = pVideoMemory[i - 1];
988 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
989 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
990 pVBInfo->XG21_LVDSCapList[k].LVDSHT
991 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
992 pVBInfo->XG21_LVDSCapList[k].LVDSVT
993 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
994 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
995 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
996 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
997 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
998 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
999 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
1000 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1001 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
1002 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1003 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
1004 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1005 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1006 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1007 = pVideoMemory[i + 18];
1008 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1009 = pVideoMemory[i + 19];
1010 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1011 = pVideoMemory[i + 20];
1012 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1013 = pVideoMemory[i + 21];
1014 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1015 = pVideoMemory[i + 22];
1016 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1017 = pVideoMemory[i + 23];
1018 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1019 = pVideoMemory[i + 24];
1023 } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct))));
1025 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1026 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
1027 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1028 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
1029 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1030 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
1031 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1032 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
1033 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1034 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
1035 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1036 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
1037 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1038 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
1039 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1040 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
1041 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1042 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1043 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1044 = pVideoMemory[i + 18];
1045 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1046 = pVideoMemory[i + 19];
1047 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1048 = pVideoMemory[i + 20];
1049 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1050 = pVideoMemory[i + 21];
1051 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1052 = pVideoMemory[i + 22];
1053 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1054 = pVideoMemory[i + 23];
1055 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1056 = pVideoMemory[i + 24];
1062 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1063 struct vb_device_info *pVBInfo)
1065 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1067 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x32);
1069 if (temp & Monitor1Sense)
1070 tempbx |= ActiveCRT1;
1071 if (temp & LCDSense)
1072 tempbx |= ActiveLCD;
1073 if (temp & Monitor2Sense)
1074 tempbx |= ActiveCRT2;
1075 if (temp & TVSense) {
1077 if (temp & AVIDEOSense)
1078 tempbx |= (ActiveAVideo << 8);
1079 if (temp & SVIDEOSense)
1080 tempbx |= (ActiveSVideo << 8);
1081 if (temp & SCARTSense)
1082 tempbx |= (ActiveSCART << 8);
1083 if (temp & HiTVSense)
1084 tempbx |= (ActiveHiTV << 8);
1085 if (temp & YPbPrSense)
1086 tempbx |= (ActiveYPbPr << 8);
1089 tempcx = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
1090 tempcx |= (XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8);
1092 if (tempbx & tempcx) {
1093 CR3CData = XGINew_GetReg1(pVBInfo->P3d4, 0x3c);
1094 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1096 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1101 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1106 XGINew_SetReg1(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1107 XGINew_SetReg1(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1110 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1111 struct vb_device_info *pVBInfo)
1113 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1115 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
1116 temp |= XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8;
1117 temp |= (XGINew_GetReg1(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1119 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1120 if (temp & ActiveCRT2)
1121 tempcl = SetCRT2ToRAMDAC;
1124 if (temp & ActiveLCD) {
1125 tempcl |= SetCRT2ToLCD;
1126 if (temp & DriverMode) {
1127 if (temp & ActiveTV) {
1128 tempch = SetToLCDA | EnableDualEdge;
1129 temp ^= SetCRT2ToLCD;
1131 if ((temp >> 8) & ActiveAVideo)
1132 tempcl |= SetCRT2ToAVIDEO;
1133 if ((temp >> 8) & ActiveSVideo)
1134 tempcl |= SetCRT2ToSVIDEO;
1135 if ((temp >> 8) & ActiveSCART)
1136 tempcl |= SetCRT2ToSCART;
1138 if (pVBInfo->IF_DEF_HiVision == 1) {
1139 if ((temp >> 8) & ActiveHiTV)
1140 tempcl |= SetCRT2ToHiVisionTV;
1143 if (pVBInfo->IF_DEF_YPbPr == 1) {
1144 if ((temp >> 8) & ActiveYPbPr)
1150 if ((temp >> 8) & ActiveAVideo)
1151 tempcl |= SetCRT2ToAVIDEO;
1152 if ((temp >> 8) & ActiveSVideo)
1153 tempcl |= SetCRT2ToSVIDEO;
1154 if ((temp >> 8) & ActiveSCART)
1155 tempcl |= SetCRT2ToSCART;
1157 if (pVBInfo->IF_DEF_HiVision == 1) {
1158 if ((temp >> 8) & ActiveHiTV)
1159 tempcl |= SetCRT2ToHiVisionTV;
1162 if (pVBInfo->IF_DEF_YPbPr == 1) {
1163 if ((temp >> 8) & ActiveYPbPr)
1168 tempcl |= SetSimuScanMode;
1169 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1170 || (temp & ActiveCRT2)))
1171 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1172 if ((temp & ActiveLCD) && (temp & ActiveTV))
1173 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1174 XGINew_SetReg1(pVBInfo->P3d4, 0x30, tempcl);
1176 CR31Data = XGINew_GetReg1(pVBInfo->P3d4, 0x31);
1177 CR31Data &= ~(SetNotSimuMode >> 8);
1178 if (!(temp & ActiveCRT1))
1179 CR31Data |= (SetNotSimuMode >> 8);
1180 CR31Data &= ~(DisableCRT2Display >> 8);
1181 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1182 CR31Data |= (DisableCRT2Display >> 8);
1183 XGINew_SetReg1(pVBInfo->P3d4, 0x31, CR31Data);
1185 CR38Data = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
1186 CR38Data &= ~SetYPbPr;
1188 XGINew_SetReg1(pVBInfo->P3d4, 0x38, CR38Data);
1192 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1193 struct vb_device_info *pVBInfo)
1196 volatile unsigned char *pVideoMemory =
1197 (unsigned char *) pVBInfo->ROMAddr;
1199 pVBInfo->IF_DEF_LVDS = 0;
1202 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1203 pVBInfo->IF_DEF_LVDS = 1;
1204 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1205 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */
1208 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read */
1209 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0xC0;
1210 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1211 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1212 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1213 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */
1214 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x04;
1216 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */
1218 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */
1219 XGINew_SetRegAND(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */
1226 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1227 struct vb_device_info *pVBInfo)
1229 unsigned char Temp, bCR4A;
1231 pVBInfo->IF_DEF_LVDS = 0;
1232 bCR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1233 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read */
1234 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x07;
1235 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, bCR4A);
1238 pVBInfo->IF_DEF_LVDS = 1;
1239 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */
1240 XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x21);
1242 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */
1244 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1248 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1250 unsigned char CR38, CR4A, temp;
1252 CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1253 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */
1254 CR38 = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
1256 if ((CR38 & 0xE0) > 0x80) {
1257 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
1262 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
1267 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1269 unsigned char CR4A, temp;
1271 CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1272 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */
1273 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
1277 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1279 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
1284 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1286 struct vb_device_info VBINF;
1287 struct vb_device_info *pVBInfo = &VBINF;
1288 unsigned char i, temp = 0, temp1;
1289 /* VBIOSVersion[5]; */
1290 volatile unsigned char *pVideoMemory;
1292 /* unsigned long j, k; */
1296 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1298 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1300 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1302 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1304 /* Newdebugcode(0x99); */
1307 /* if (pVBInfo->ROMAddr == 0) */
1310 if (pVBInfo->FBAddr == NULL) {
1311 printk("\n pVBInfo->FBAddr == 0 ");
1315 if (pVBInfo->BaseAddr == 0) {
1316 printk("\npVBInfo->BaseAddr == 0 ");
1321 XGINew_SetReg3((pVBInfo->BaseAddr + 0x12), 0x67); /* 3c2 <- 67 ,ynlai */
1323 pVBInfo->ISXPDOS = 0;
1328 /* VBIOSVersion[4] = 0x0; */
1330 /* 09/07/99 modify by domao */
1332 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1333 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1334 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1335 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1336 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1337 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1338 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1339 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1340 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1341 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1342 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1343 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1344 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1345 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1346 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1347 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1348 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1351 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1352 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
1354 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1357 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1360 XGINew_SetReg1(pVBInfo->P3c4, 0x05, 0x86);
1363 /* GetXG21Sense (GPIO) */
1364 if (HwDeviceExtension->jChipType == XG21)
1365 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1367 if (HwDeviceExtension->jChipType == XG27)
1368 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1372 /* 2.Reset Extended register */
1374 for (i = 0x06; i < 0x20; i++)
1375 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1377 for (i = 0x21; i <= 0x27; i++)
1378 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1380 /* for(i = 0x06; i <= 0x27; i++) */
1381 /* XGINew_SetReg1(pVBInfo->P3c4, i, 0); */
1385 if ((HwDeviceExtension->jChipType >= XG20) || (HwDeviceExtension->jChipType >= XG40)) {
1386 for (i = 0x31; i <= 0x3B; i++)
1387 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1389 for (i = 0x31; i <= 0x3D; i++)
1390 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1394 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1395 XGINew_SetReg1(pVBInfo->P3c4, 0x3B, 0xC0);
1397 /* for (i = 0x30; i <= 0x3F; i++) */
1398 /* XGINew_SetReg1(pVBInfo->P3d4, i, 0); */
1400 for (i = 0x79; i <= 0x7C; i++)
1401 XGINew_SetReg1(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1405 if (HwDeviceExtension->jChipType >= XG20)
1406 XGINew_SetReg1(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1410 if (HwDeviceExtension->jChipType >= XG40)
1411 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1416 /* 4.SetDefExt1Regs begin */
1417 XGINew_SetReg1(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1418 if (HwDeviceExtension->jChipType == XG27) {
1419 XGINew_SetReg1(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1420 XGINew_SetReg1(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1422 XGINew_SetReg1(pVBInfo->P3c4, 0x11, 0x0F);
1423 XGINew_SetReg1(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1424 /* XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0x20); */
1425 XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1426 XGINew_SetReg1(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1427 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1428 XGINew_SetReg1(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1431 /* XGINew_SetReg1(pVBInfo->P3c4, 0x11, SR11); */
1435 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1438 temp1 = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
1440 if (temp1 == 0x02) {
1441 XGINew_SetReg4(0xcf8, 0x80000000);
1442 ChipsetID = XGINew_GetReg3(0x0cfc);
1443 XGINew_SetReg4(0xcf8, 0x8000002C);
1444 VendorID = XGINew_GetReg3(0x0cfc);
1445 VendorID &= 0x0000FFFF;
1446 XGINew_SetReg4(0xcf8, 0x8001002C);
1447 GraphicVendorID = XGINew_GetReg3(0x0cfc);
1448 GraphicVendorID &= 0x0000FFFF;
1450 if (ChipsetID == 0x7301039)
1451 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x09);
1453 ChipsetID &= 0x0000FFFF;
1455 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
1456 if (ChipsetID == 0x1106) {
1457 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
1458 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0D);
1460 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
1462 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
1470 if (HwDeviceExtension->jChipType >= XG40) {
1471 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1472 for (i = 0x47; i <= 0x4C; i++)
1473 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
1475 for (i = 0x70; i <= 0x71; i++)
1476 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
1478 for (i = 0x74; i <= 0x77; i++)
1479 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
1480 /* Set AGP customize registers (in SetDefAGPRegs) End */
1481 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1482 /* XGINew_SetReg4(0xcf8 , 0x80000000); */
1483 /* ChipsetID = XGINew_GetReg3(0x0cfc); */
1484 /* if (ChipsetID == 0x25308086) */
1485 /* XGINew_SetReg1(pVBInfo->P3d4, 0x77, 0xF0); */
1487 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
1492 XGINew_SetReg1(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1498 XGINew_SetReg1(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1499 XGINew_SetReg1(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1500 XGINew_SetReg1(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1503 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1505 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1506 XGINew_SetRegANDOR(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
1507 XGINew_SetReg1(pVBInfo->Part1Port, 0x00, 0x00);
1508 temp1 = (unsigned char) XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
1509 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1511 XGINew_SetReg1(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
1515 XGINew_SetReg1(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1518 XGINew_SetReg1(pVBInfo->P3c4, 0x27, 0x1F);
1520 if ((HwDeviceExtension->jChipType == XG42)
1521 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
1522 XGINew_SetReg1(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
1523 XGINew_SetReg1(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
1525 XGINew_SetReg1(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1526 XGINew_SetReg1(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1528 XGINew_SetReg1(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1532 if (HwDeviceExtension->jChipType >= XG40)
1533 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1535 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1536 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1537 if (pVBInfo->IF_DEF_LVDS == 0) {
1538 XGINew_SetReg1(pVBInfo->Part2Port, 0x00, 0x1C);
1539 XGINew_SetReg1(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
1540 XGINew_SetReg1(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
1541 XGINew_SetReg1(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
1542 XGINew_SetReg1(pVBInfo->Part4Port, 0x0F, 0x3F);
1545 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1554 XGI_SenseCRT1(pVBInfo);
1557 /* XGINew_DetectMonitor(HwDeviceExtension); */
1558 pVBInfo->IF_DEF_CH7007 = 0;
1559 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
1561 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
1565 if (HwDeviceExtension->jChipType == XG21) {
1568 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1569 temp = GetXG21FPBits(pVBInfo);
1570 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x01, temp);
1574 if (HwDeviceExtension->jChipType == XG27) {
1575 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1576 temp = GetXG27FPBits(pVBInfo);
1577 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x03, temp);
1581 if (HwDeviceExtension->jChipType >= XG40) {
1582 if (HwDeviceExtension->jChipType >= XG40)
1583 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1585 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
1588 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1594 /* SetDefExt2Regs begin */
1597 temp = (unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x3A);
1603 *pVBInfo->pSR21 &= 0xEF;
1605 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1607 *pVBInfo->pSR22 &= 0x20;
1608 XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1610 /* base = 0x80000000; */
1611 /* OutPortLong(0xcf8, base); */
1612 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1613 /* if (Temp == 0x1039) { */
1614 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1616 /* XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1619 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1623 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1624 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1628 XGINew_SetReg1(pVBInfo->P3d4, 0x8c, 0x87);
1629 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31);