1 #include <linux/delay.h>
2 #include <linux/vmalloc.h>
7 #include "vb_setmode.h"
9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
29 #define XGIFB_ROM_SIZE 65536
32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
35 unsigned char data, temp;
37 if (HwDeviceExtension->jChipType < XG20) {
38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
43 } else if (HwDeviceExtension->jChipType == XG27) {
44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
51 } else if (HwDeviceExtension->jChipType == XG21) {
52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
56 /* GPIOF 0:DVI 1:DVO */
57 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
59 /* for current XG20 & XG21, GPIOH is floating, driver will
60 * fix DDR temporarily */
62 data &= 0x01; /* 1=DDRII, 0=DDR */
63 /* ~HOTPLUG_SUPPORT */
64 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
67 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
76 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
77 struct vb_device_info *pVBInfo)
79 xgifb_reg_set(P3c4, 0x18, 0x01);
80 xgifb_reg_set(P3c4, 0x19, 0x20);
81 xgifb_reg_set(P3c4, 0x16, 0x00);
82 xgifb_reg_set(P3c4, 0x16, 0x80);
85 xgifb_reg_set(P3c4, 0x18, 0x00);
86 xgifb_reg_set(P3c4, 0x19, 0x20);
87 xgifb_reg_set(P3c4, 0x16, 0x00);
88 xgifb_reg_set(P3c4, 0x16, 0x80);
91 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
92 xgifb_reg_set(P3c4, 0x19, 0x01);
93 xgifb_reg_set(P3c4, 0x16, 0x03);
94 xgifb_reg_set(P3c4, 0x16, 0x83);
96 xgifb_reg_set(P3c4, 0x1B, 0x03);
98 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
99 xgifb_reg_set(P3c4, 0x19, 0x00);
100 xgifb_reg_set(P3c4, 0x16, 0x03);
101 xgifb_reg_set(P3c4, 0x16, 0x83);
102 xgifb_reg_set(P3c4, 0x1B, 0x00);
105 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
107 xgifb_reg_set(pVBInfo->P3c4,
109 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
110 xgifb_reg_set(pVBInfo->P3c4,
112 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
113 xgifb_reg_set(pVBInfo->P3c4,
115 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
117 xgifb_reg_set(pVBInfo->P3c4,
119 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
120 xgifb_reg_set(pVBInfo->P3c4,
122 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
123 xgifb_reg_set(pVBInfo->P3c4,
125 XGI340_ECLKData[pVBInfo->ram_type].SR30);
128 static void XGINew_DDRII_Bootup_XG27(
129 struct xgi_hw_device_info *HwDeviceExtension,
130 unsigned long P3c4, struct vb_device_info *pVBInfo)
132 unsigned long P3d4 = P3c4 + 0x10;
133 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
134 XGINew_SetMemoryClock(pVBInfo);
136 /* Set Double Frequency */
137 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
141 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
142 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
143 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
145 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
148 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
149 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
150 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
152 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
155 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
156 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
157 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
159 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
162 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
163 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
164 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
166 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
167 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
169 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
171 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
173 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
174 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
175 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
178 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
181 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
182 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
183 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
185 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
188 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
189 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
190 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
192 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
195 /* Set SR1B refresh control 000:close; 010:open */
196 xgifb_reg_set(P3c4, 0x1B, 0x04);
201 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
202 unsigned long P3c4, struct vb_device_info *pVBInfo)
204 unsigned long P3d4 = P3c4 + 0x10;
206 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
207 XGINew_SetMemoryClock(pVBInfo);
209 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
212 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
213 xgifb_reg_set(P3c4, 0x19, 0x80);
214 xgifb_reg_set(P3c4, 0x16, 0x05);
215 xgifb_reg_set(P3c4, 0x16, 0x85);
217 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
218 xgifb_reg_set(P3c4, 0x19, 0xC0);
219 xgifb_reg_set(P3c4, 0x16, 0x05);
220 xgifb_reg_set(P3c4, 0x16, 0x85);
222 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
223 xgifb_reg_set(P3c4, 0x19, 0x40);
224 xgifb_reg_set(P3c4, 0x16, 0x05);
225 xgifb_reg_set(P3c4, 0x16, 0x85);
227 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
228 xgifb_reg_set(P3c4, 0x19, 0x02);
229 xgifb_reg_set(P3c4, 0x16, 0x05);
230 xgifb_reg_set(P3c4, 0x16, 0x85);
233 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
235 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
238 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
239 xgifb_reg_set(P3c4, 0x19, 0x00);
240 xgifb_reg_set(P3c4, 0x16, 0x05);
241 xgifb_reg_set(P3c4, 0x16, 0x85);
246 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
247 struct vb_device_info *pVBInfo)
249 xgifb_reg_set(P3c4, 0x18, 0x01);
250 xgifb_reg_set(P3c4, 0x19, 0x40);
251 xgifb_reg_set(P3c4, 0x16, 0x00);
252 xgifb_reg_set(P3c4, 0x16, 0x80);
255 xgifb_reg_set(P3c4, 0x18, 0x00);
256 xgifb_reg_set(P3c4, 0x19, 0x40);
257 xgifb_reg_set(P3c4, 0x16, 0x00);
258 xgifb_reg_set(P3c4, 0x16, 0x80);
260 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
261 xgifb_reg_set(P3c4, 0x19, 0x01);
262 xgifb_reg_set(P3c4, 0x16, 0x03);
263 xgifb_reg_set(P3c4, 0x16, 0x83);
265 xgifb_reg_set(P3c4, 0x1B, 0x03);
267 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
268 xgifb_reg_set(P3c4, 0x19, 0x00);
269 xgifb_reg_set(P3c4, 0x16, 0x03);
270 xgifb_reg_set(P3c4, 0x16, 0x83);
271 xgifb_reg_set(P3c4, 0x1B, 0x00);
274 static void XGINew_DDR1x_DefaultRegister(
275 struct xgi_hw_device_info *HwDeviceExtension,
276 unsigned long Port, struct vb_device_info *pVBInfo)
278 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
280 if (HwDeviceExtension->jChipType >= XG20) {
281 XGINew_SetMemoryClock(pVBInfo);
284 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
287 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
290 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
292 xgifb_reg_set(P3d4, 0x98, 0x01);
293 xgifb_reg_set(P3d4, 0x9A, 0x02);
295 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
297 XGINew_SetMemoryClock(pVBInfo);
299 switch (HwDeviceExtension->jChipType) {
304 pVBInfo->CR40[11][pVBInfo->ram_type]);
308 pVBInfo->CR40[12][pVBInfo->ram_type]);
312 pVBInfo->CR40[13][pVBInfo->ram_type]);
315 xgifb_reg_set(P3d4, 0x82, 0x88);
316 xgifb_reg_set(P3d4, 0x86, 0x00);
317 /* Insert read command for delay */
318 xgifb_reg_get(P3d4, 0x86);
319 xgifb_reg_set(P3d4, 0x86, 0x88);
320 xgifb_reg_get(P3d4, 0x86);
323 pVBInfo->CR40[13][pVBInfo->ram_type]);
324 xgifb_reg_set(P3d4, 0x82, 0x77);
325 xgifb_reg_set(P3d4, 0x85, 0x00);
327 /* Insert read command for delay */
328 xgifb_reg_get(P3d4, 0x85);
329 xgifb_reg_set(P3d4, 0x85, 0x88);
331 /* Insert read command for delay */
332 xgifb_reg_get(P3d4, 0x85);
336 pVBInfo->CR40[12][pVBInfo->ram_type]);
340 pVBInfo->CR40[11][pVBInfo->ram_type]);
344 xgifb_reg_set(P3d4, 0x97, 0x00);
345 xgifb_reg_set(P3d4, 0x98, 0x01);
346 xgifb_reg_set(P3d4, 0x9A, 0x02);
347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
351 static void XGINew_DDR2_DefaultRegister(
352 struct xgi_hw_device_info *HwDeviceExtension,
353 unsigned long Port, struct vb_device_info *pVBInfo)
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
357 /* keep following setting sequence, each setting in
358 * the same reg insert idle */
359 xgifb_reg_set(P3d4, 0x82, 0x77);
360 xgifb_reg_set(P3d4, 0x86, 0x00);
361 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
362 xgifb_reg_set(P3d4, 0x86, 0x88);
363 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
365 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
366 xgifb_reg_set(P3d4, 0x82, 0x77);
367 xgifb_reg_set(P3d4, 0x85, 0x00);
368 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
369 xgifb_reg_set(P3d4, 0x85, 0x88);
370 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
373 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
374 if (HwDeviceExtension->jChipType == XG27)
376 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
378 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
380 xgifb_reg_set(P3d4, 0x98, 0x01);
381 xgifb_reg_set(P3d4, 0x9A, 0x02);
382 if (HwDeviceExtension->jChipType == XG27)
383 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
385 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
388 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
389 u8 shift_factor, u8 mask1, u8 mask2)
392 for (j = 0; j < 4; j++) {
393 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
394 xgifb_reg_set(P3d4, reg, temp2);
395 xgifb_reg_get(P3d4, reg);
401 static void XGINew_SetDRAMDefaultRegister340(
402 struct xgi_hw_device_info *HwDeviceExtension,
403 unsigned long Port, struct vb_device_info *pVBInfo)
405 unsigned char temp, temp1, temp2, temp3, j, k;
407 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
409 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
410 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
411 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
412 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
414 /* CR6B DQS fine tune delay */
416 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
418 /* CR6E DQM fine tune delay */
419 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
422 for (k = 0; k < 4; k++) {
423 /* CR6E_D[1:0] select channel */
424 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
425 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
431 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
434 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
437 /* CR89 terminator type select */
438 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
443 xgifb_reg_set(P3d4, 0x89, temp2);
445 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
447 temp2 = (temp >> 4) & 0x07;
449 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
450 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
451 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
454 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
456 if (HwDeviceExtension->jChipType == XG27)
457 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
459 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
460 xgifb_reg_set(P3d4, (0x90 + j),
461 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
463 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
464 xgifb_reg_set(P3d4, (0xC3 + j),
465 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
467 for (j = 0; j < 2; j++) /* CR8A - CR8B */
468 xgifb_reg_set(P3d4, (0x8A + j),
469 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
471 if (HwDeviceExtension->jChipType == XG42)
472 xgifb_reg_set(P3d4, 0x8C, 0x87);
476 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
478 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
479 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
480 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
481 if (pVBInfo->ram_type) {
482 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
483 if (HwDeviceExtension->jChipType == XG27)
484 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
487 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
489 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
491 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
493 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
495 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
496 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
498 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
502 static unsigned short XGINew_SetDRAMSize20Reg(
503 unsigned short dram_size,
504 struct vb_device_info *pVBInfo)
506 unsigned short data = 0, memsize = 0;
508 unsigned char ChannelNo;
510 RankSize = dram_size * pVBInfo->ram_bus / 8;
511 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
519 if (pVBInfo->ram_channel == 3)
522 ChannelNo = pVBInfo->ram_channel;
524 if (ChannelNo * RankSize <= 256) {
525 while ((RankSize >>= 1) > 0)
530 /* Fix DRAM Sizing Error */
531 xgifb_reg_set(pVBInfo->P3c4,
533 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
540 static int XGINew_ReadWriteRest(unsigned short StopAddr,
541 unsigned short StartAddr, struct vb_device_info *pVBInfo)
544 unsigned long Position = 0;
545 void __iomem *fbaddr = pVBInfo->FBAddr;
547 writel(Position, fbaddr + Position);
549 for (i = StartAddr; i <= StopAddr; i++) {
551 writel(Position, fbaddr + Position);
554 udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
558 if (readl(fbaddr + Position) != Position)
561 for (i = StartAddr; i <= StopAddr; i++) {
563 if (readl(fbaddr + Position) != Position)
569 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
573 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
575 if ((data & 0x10) == 0) {
576 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
577 data = (data & 0x02) >> 1;
584 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
585 struct vb_device_info *pVBInfo)
589 switch (HwDeviceExtension->jChipType) {
592 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
594 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
596 if (data == 0) { /* Single_32_16 */
598 if ((HwDeviceExtension->ulVideoMemorySize - 1)
601 pVBInfo->ram_bus = 32; /* 32 bits */
602 /* 22bit + 2 rank + 32bit */
603 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
604 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
607 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
610 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
612 /* 22bit + 1 rank + 32bit */
613 xgifb_reg_set(pVBInfo->P3c4,
616 xgifb_reg_set(pVBInfo->P3c4,
621 if (XGINew_ReadWriteRest(23,
628 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
630 pVBInfo->ram_bus = 16; /* 16 bits */
631 /* 22bit + 2 rank + 16bit */
632 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
633 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
636 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
639 xgifb_reg_set(pVBInfo->P3c4,
645 } else { /* Dual_16_8 */
646 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
648 pVBInfo->ram_bus = 16; /* 16 bits */
649 /* (0x31:12x8x2) 22bit + 2 rank */
650 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
652 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
655 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
658 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
660 /* (0x31:12x8x2) 22bit + 1 rank */
661 xgifb_reg_set(pVBInfo->P3c4,
665 xgifb_reg_set(pVBInfo->P3c4,
670 if (XGINew_ReadWriteRest(22,
677 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
679 pVBInfo->ram_bus = 8; /* 8 bits */
680 /* (0x31:12x8x2) 22bit + 2 rank */
681 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
683 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
686 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
688 else /* (0x31:12x8x2) 22bit + 1 rank */
689 xgifb_reg_set(pVBInfo->P3c4,
698 pVBInfo->ram_bus = 16; /* 16 bits */
699 pVBInfo->ram_channel = 1; /* Single channel */
700 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
704 XG42 SR14 D[3] Reserve
705 D[2] = 1, Dual Channel
708 It's Different from Other XG40 Series.
710 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
711 pVBInfo->ram_bus = 32; /* 32 bits */
712 pVBInfo->ram_channel = 2; /* 2 Channel */
713 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
714 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
716 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
719 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
720 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
721 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
724 pVBInfo->ram_channel = 1; /* Single Channel */
725 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
726 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
728 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
731 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
732 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
735 pVBInfo->ram_bus = 64; /* 64 bits */
736 pVBInfo->ram_channel = 1; /* 1 channels */
737 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
738 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
740 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
743 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
744 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
752 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
753 pVBInfo->ram_bus = 32; /* 32 bits */
754 pVBInfo->ram_channel = 3;
755 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
756 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
758 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
761 pVBInfo->ram_channel = 2; /* 2 channels */
762 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
764 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
767 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
768 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
770 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
771 pVBInfo->ram_channel = 3; /* 4 channels */
773 pVBInfo->ram_channel = 2; /* 2 channels */
774 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
777 pVBInfo->ram_bus = 64; /* 64 bits */
778 pVBInfo->ram_channel = 2; /* 2 channels */
779 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
780 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
782 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
785 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
786 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
793 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
794 struct vb_device_info *pVBInfo)
797 unsigned short memsize, start_addr;
798 const unsigned short (*dram_table)[2];
800 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
801 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
802 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
804 if (HwDeviceExtension->jChipType >= XG20) {
805 dram_table = XGINew_DDRDRAM_TYPE20;
806 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
809 dram_table = XGINew_DDRDRAM_TYPE340;
810 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
814 for (i = 0; i < size; i++) {
815 /* SetDRAMSizingType */
816 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
817 udelay(15); /* should delay 50 ns */
819 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
824 memsize += (pVBInfo->ram_channel - 2) + 20;
825 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
826 (unsigned long) (1 << memsize))
829 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
835 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
836 struct xgi_hw_device_info *HwDeviceExtension,
837 struct vb_device_info *pVBInfo)
841 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
843 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
845 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
846 /* disable read cache */
847 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
848 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
850 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
851 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
852 /* enable read cache */
853 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
856 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
858 void __iomem *rom_address;
861 rom_address = pci_map_rom(dev, rom_size);
862 if (rom_address == NULL)
865 rom_copy = vzalloc(XGIFB_ROM_SIZE);
866 if (rom_copy == NULL)
869 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
870 memcpy_fromio(rom_copy, rom_address, *rom_size);
873 pci_unmap_rom(dev, rom_address);
877 static bool xgifb_read_vbios(struct pci_dev *pdev)
879 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
883 struct XGI21_LVDSCapStruct *lvds;
887 vbios = xgifb_copy_rom(pdev, &vbios_size);
889 dev_err(&pdev->dev, "Video BIOS not available\n");
892 if (vbios_size <= 0x65)
895 * The user can ignore the LVDS bit in the BIOS and force the display
898 if (!(vbios[0x65] & 0x1) &&
899 (!xgifb_info->display2_force ||
900 xgifb_info->display2 != XGIFB_DISP_LCD)) {
904 if (vbios_size <= 0x317)
906 i = vbios[0x316] | (vbios[0x317] << 8);
907 if (vbios_size <= i - 1)
915 * Read the LVDS table index scratch register set by the BIOS.
917 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
921 lvds = &xgifb_info->lvds_data;
922 if (vbios_size <= i + 24)
924 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
925 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
926 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
927 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
928 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
929 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
930 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
931 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
932 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
933 lvds->VCLKData1 = vbios[i + 18];
934 lvds->VCLKData2 = vbios[i + 19];
935 lvds->PSC_S1 = vbios[i + 20];
936 lvds->PSC_S2 = vbios[i + 21];
937 lvds->PSC_S3 = vbios[i + 22];
938 lvds->PSC_S4 = vbios[i + 23];
939 lvds->PSC_S5 = vbios[i + 24];
943 dev_err(&pdev->dev, "Video BIOS corrupted\n");
948 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
950 unsigned short tempbx = 0, temp, tempcx, CR3CData;
952 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
954 if (temp & Monitor1Sense)
955 tempbx |= ActiveCRT1;
958 if (temp & Monitor2Sense)
959 tempbx |= ActiveCRT2;
960 if (temp & TVSense) {
962 if (temp & AVIDEOSense)
963 tempbx |= (ActiveAVideo << 8);
964 if (temp & SVIDEOSense)
965 tempbx |= (ActiveSVideo << 8);
966 if (temp & SCARTSense)
967 tempbx |= (ActiveSCART << 8);
968 if (temp & HiTVSense)
969 tempbx |= (ActiveHiTV << 8);
970 if (temp & YPbPrSense)
971 tempbx |= (ActiveYPbPr << 8);
974 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
975 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
977 if (tempbx & tempcx) {
978 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
979 if (!(CR3CData & DisplayDeviceFromCMOS))
986 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
987 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
990 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
992 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
994 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
995 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
996 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
998 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
999 if (temp & ActiveCRT2)
1000 tempcl = SetCRT2ToRAMDAC;
1003 if (temp & ActiveLCD) {
1004 tempcl |= SetCRT2ToLCD;
1005 if (temp & DriverMode) {
1006 if (temp & ActiveTV) {
1007 tempch = SetToLCDA | EnableDualEdge;
1008 temp ^= SetCRT2ToLCD;
1010 if ((temp >> 8) & ActiveAVideo)
1011 tempcl |= SetCRT2ToAVIDEO;
1012 if ((temp >> 8) & ActiveSVideo)
1013 tempcl |= SetCRT2ToSVIDEO;
1014 if ((temp >> 8) & ActiveSCART)
1015 tempcl |= SetCRT2ToSCART;
1017 if (pVBInfo->IF_DEF_HiVision == 1) {
1018 if ((temp >> 8) & ActiveHiTV)
1019 tempcl |= SetCRT2ToHiVision;
1022 if (pVBInfo->IF_DEF_YPbPr == 1) {
1023 if ((temp >> 8) & ActiveYPbPr)
1029 if ((temp >> 8) & ActiveAVideo)
1030 tempcl |= SetCRT2ToAVIDEO;
1031 if ((temp >> 8) & ActiveSVideo)
1032 tempcl |= SetCRT2ToSVIDEO;
1033 if ((temp >> 8) & ActiveSCART)
1034 tempcl |= SetCRT2ToSCART;
1036 if (pVBInfo->IF_DEF_HiVision == 1) {
1037 if ((temp >> 8) & ActiveHiTV)
1038 tempcl |= SetCRT2ToHiVision;
1041 if (pVBInfo->IF_DEF_YPbPr == 1) {
1042 if ((temp >> 8) & ActiveYPbPr)
1047 tempcl |= SetSimuScanMode;
1048 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1049 || (temp & ActiveCRT2)))
1050 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1051 if ((temp & ActiveLCD) && (temp & ActiveTV))
1052 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1053 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1055 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1056 CR31Data &= ~(SetNotSimuMode >> 8);
1057 if (!(temp & ActiveCRT1))
1058 CR31Data |= (SetNotSimuMode >> 8);
1059 CR31Data &= ~(DisableCRT2Display >> 8);
1060 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1061 CR31Data |= (DisableCRT2Display >> 8);
1062 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1064 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1065 CR38Data &= ~SetYPbPr;
1067 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1071 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1073 struct vb_device_info *pVBInfo)
1075 unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1077 switch (HwDeviceExtension->ulCRT2LCDType) {
1085 temp = 0; /* overwrite used ulCRT2LCDType */
1087 case LCD_UNKNOWN: /* unknown lcd, do nothing */
1090 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1094 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1095 struct vb_device_info *pVBInfo)
1097 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1100 if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1101 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1103 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1105 /* Enable GPIOA/B read */
1106 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1107 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1108 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1109 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1110 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1111 /* Enable read GPIOF */
1112 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1113 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1114 Temp = 0xA0; /* Only DVO on chip */
1116 Temp = 0x80; /* TMDS on chip */
1117 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1118 /* Disable read GPIOF */
1119 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1124 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1126 unsigned char Temp, bCR4A;
1128 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1129 /* Enable GPIOA/B/C read */
1130 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1131 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1132 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1136 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1137 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1139 /* TMDS/DVO setting */
1140 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1142 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1146 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1148 unsigned char CR38, CR4A, temp;
1150 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1151 /* enable GPIOE read */
1152 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1153 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1155 if ((CR38 & 0xE0) > 0x80) {
1156 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1161 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1166 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1168 unsigned char CR4A, temp;
1170 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1171 /* enable GPIOA/B/C read */
1172 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1173 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1175 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1177 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1182 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1186 flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1187 return flag == 1 || flag == 2;
1190 unsigned char XGIInitNew(struct pci_dev *pdev)
1192 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1193 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1194 struct vb_device_info VBINF;
1195 struct vb_device_info *pVBInfo = &VBINF;
1196 unsigned char i, temp = 0, temp1;
1198 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1200 if (pVBInfo->FBAddr == NULL) {
1201 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1205 XGIRegInit(pVBInfo, xgifb_info->vga_base);
1207 outb(0x67, pVBInfo->P3c2);
1209 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1212 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1214 /* GetXG21Sense (GPIO) */
1215 if (HwDeviceExtension->jChipType == XG21)
1216 XGINew_GetXG21Sense(pdev, pVBInfo);
1218 if (HwDeviceExtension->jChipType == XG27)
1219 XGINew_GetXG27Sense(pVBInfo);
1221 /* Reset Extended register */
1223 for (i = 0x06; i < 0x20; i++)
1224 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1226 for (i = 0x21; i <= 0x27; i++)
1227 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1229 for (i = 0x31; i <= 0x3B; i++)
1230 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1232 /* Auto over driver for XG42 */
1233 if (HwDeviceExtension->jChipType == XG42)
1234 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1236 for (i = 0x79; i <= 0x7C; i++)
1237 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1239 if (HwDeviceExtension->jChipType >= XG20)
1240 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1242 /* SetDefExt1Regs begin */
1243 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1244 if (HwDeviceExtension->jChipType == XG27) {
1245 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1246 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1248 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1249 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1250 /* Frame buffer can read/write SR20 */
1251 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1252 /* H/W request for slow corner chip */
1253 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1254 if (HwDeviceExtension->jChipType == XG27)
1255 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1257 if (HwDeviceExtension->jChipType < XG20) {
1260 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1261 for (i = 0x47; i <= 0x4C; i++)
1262 xgifb_reg_set(pVBInfo->P3d4,
1264 XGI340_AGPReg[i - 0x47]);
1266 for (i = 0x70; i <= 0x71; i++)
1267 xgifb_reg_set(pVBInfo->P3d4,
1269 XGI340_AGPReg[6 + i - 0x70]);
1271 for (i = 0x74; i <= 0x77; i++)
1272 xgifb_reg_set(pVBInfo->P3d4,
1274 XGI340_AGPReg[8 + i - 0x74]);
1276 pci_read_config_dword(pdev, 0x50, &Temp);
1281 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1285 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1286 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1287 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1289 if (HwDeviceExtension->jChipType < XG20) {
1291 XGI_UnLockCRT2(pVBInfo);
1292 /* disable VideoCapture */
1293 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1294 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1295 /* chk if BCLK>=100MHz */
1296 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1298 xgifb_reg_set(pVBInfo->Part1Port,
1299 0x02, XGI330_CRT2Data_1_2);
1301 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1304 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1306 if ((HwDeviceExtension->jChipType == XG42) &&
1307 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1309 xgifb_reg_set(pVBInfo->P3c4,
1311 (XGI330_SR31 & 0x3F) | 0x40);
1312 xgifb_reg_set(pVBInfo->P3c4,
1314 (XGI330_SR32 & 0xFC) | 0x01);
1316 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1317 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1319 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1321 if (HwDeviceExtension->jChipType < XG20) {
1322 if (xgifb_bridge_is_on(pVBInfo)) {
1323 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1324 xgifb_reg_set(pVBInfo->Part4Port,
1325 0x0D, XGI330_CRT2Data_4_D);
1326 xgifb_reg_set(pVBInfo->Part4Port,
1327 0x0E, XGI330_CRT2Data_4_E);
1328 xgifb_reg_set(pVBInfo->Part4Port,
1329 0x10, XGI330_CRT2Data_4_10);
1330 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1331 XGI_LockCRT2(pVBInfo);
1335 XGI_SenseCRT1(pVBInfo);
1337 if (HwDeviceExtension->jChipType == XG21) {
1339 xgifb_reg_and_or(pVBInfo->P3d4,
1342 Monitor1Sense); /* Z9 default has CRT */
1343 temp = GetXG21FPBits(pVBInfo);
1344 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1347 if (HwDeviceExtension->jChipType == XG27) {
1348 xgifb_reg_and_or(pVBInfo->P3d4,
1351 Monitor1Sense); /* Z9 default has CRT */
1352 temp = GetXG27FPBits(pVBInfo);
1353 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1356 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1358 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1362 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1364 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1365 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1367 XGINew_ChkSenseStatus(pVBInfo);
1368 XGINew_SetModeScratch(pVBInfo);
1370 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);