drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h>
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8 #include "vb_init.h"
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  10         { 16, 0x45},
  11         {  8, 0x35},
  12         {  4, 0x31},
  13         {  2, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  16         { 128, 0x5D},
  17         { 64, 0x59},
  18         { 64, 0x4D},
  19         { 32, 0x55},
  20         { 32, 0x49},
  21         { 32, 0x3D},
  22         { 16, 0x51},
  23         { 16, 0x45},
  24         { 16, 0x39},
  25         {  8, 0x41},
  26         {  8, 0x35},
  27         {  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  39                 if (data == 0)
  40                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  41                                    0x02) >> 1;
  42                 return data;
  43         } else if (HwDeviceExtension->jChipType == XG27) {
  44                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  45                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  46                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  47                         data = 0; /* DDR */
  48                 else
  49                         data = 1; /* DDRII */
  50                 return data;
  51         } else if (HwDeviceExtension->jChipType == XG21) {
  52                 /* Independent GPIO control */
  53                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  54                 usleep_range(800, 1800);
  55                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  56                 /* GPIOF 0:DVI 1:DVO */
  57                 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  58                 /* HOTPLUG_SUPPORT */
  59                 /* for current XG20 & XG21, GPIOH is floating, driver will
  60                  * fix DDR temporarily
  61                  */
  62                 /* DVI read GPIOH */
  63                 data &= 0x01; /* 1=DDRII, 0=DDR */
  64                 /* ~HOTPLUG_SUPPORT */
  65                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  66                 return data;
  67         }
  68         data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  69
  70         if (data == 1)
  71                 data++;
  72
  73         return data;
  74 }
  75
  76 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  77                                  struct vb_device_info *pVBInfo)
  78 {
  79         xgifb_reg_set(P3c4, 0x18, 0x01);
  80         xgifb_reg_set(P3c4, 0x19, 0x20);
  81         xgifb_reg_set(P3c4, 0x16, 0x00);
  82         xgifb_reg_set(P3c4, 0x16, 0x80);
  83
  84         usleep_range(3, 1003);
  85         xgifb_reg_set(P3c4, 0x18, 0x00);
  86         xgifb_reg_set(P3c4, 0x19, 0x20);
  87         xgifb_reg_set(P3c4, 0x16, 0x00);
  88         xgifb_reg_set(P3c4, 0x16, 0x80);
  89
  90         usleep_range(60, 1060);
  91         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  92         xgifb_reg_set(P3c4, 0x19, 0x01);
  93         xgifb_reg_set(P3c4, 0x16, 0x03);
  94         xgifb_reg_set(P3c4, 0x16, 0x83);
  95         usleep_range(1, 1001);
  96         xgifb_reg_set(P3c4, 0x1B, 0x03);
  97         usleep_range(500, 1500);
  98         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  99         xgifb_reg_set(P3c4, 0x19, 0x00);
 100         xgifb_reg_set(P3c4, 0x16, 0x03);
 101         xgifb_reg_set(P3c4, 0x16, 0x83);
 102         xgifb_reg_set(P3c4, 0x1B, 0x00);
 103 }
 104
 105 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
 106 {
 107         xgifb_reg_set(pVBInfo->P3c4,
 108                       0x28,
 109                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 110         xgifb_reg_set(pVBInfo->P3c4,
 111                       0x29,
 112                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 113         xgifb_reg_set(pVBInfo->P3c4,
 114                       0x2A,
 115                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 116
 117         xgifb_reg_set(pVBInfo->P3c4,
 118                       0x2E,
 119                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 120         xgifb_reg_set(pVBInfo->P3c4,
 121                       0x2F,
 122                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 123         xgifb_reg_set(pVBInfo->P3c4,
 124                       0x30,
 125                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 126 }
 127
 128 static void XGINew_DDRII_Bootup_XG27(
 129                         struct xgi_hw_device_info *HwDeviceExtension,
 130                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 131 {
 132         unsigned long P3d4 = P3c4 + 0x10;
 133
 134         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 135         XGINew_SetMemoryClock(pVBInfo);
 136
 137         /* Set Double Frequency */
 138         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 139
 140         usleep_range(200, 1200);
 141
 142         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 143         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 144         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 145         usleep_range(15, 1015);
 146         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 147         usleep_range(15, 1015);
 148
 149         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 150         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 151         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 152         usleep_range(15, 1015);
 153         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 154         usleep_range(15, 1015);
 155
 156         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 157         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 158         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 159         usleep_range(30, 1030);
 160         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 161         usleep_range(15, 1015);
 162
 163         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 164         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 165         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 166         usleep_range(30, 1030);
 167         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 168         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 169
 170         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 171         usleep_range(60, 1060);
 172         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 173
 174         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 175         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 176         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 177
 178         usleep_range(30, 1030);
 179         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 180         usleep_range(15, 1015);
 181
 182         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 183         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 184         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 185         usleep_range(30, 1030);
 186         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 187         usleep_range(15, 1015);
 188
 189         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 190         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 191         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 192         usleep_range(30, 1030);
 193         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 194         usleep_range(15, 1015);
 195
 196         /* Set SR1B refresh control 000:close; 010:open */
 197         xgifb_reg_set(P3c4, 0x1B, 0x04);
 198         usleep_range(200, 1200);
 199 }
 200
 201 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 202                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 203 {
 204         unsigned long P3d4 = P3c4 + 0x10;
 205
 206         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 207         XGINew_SetMemoryClock(pVBInfo);
 208
 209         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 210
 211         usleep_range(200, 1200);
 212         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 213         xgifb_reg_set(P3c4, 0x19, 0x80);
 214         xgifb_reg_set(P3c4, 0x16, 0x05);
 215         xgifb_reg_set(P3c4, 0x16, 0x85);
 216
 217         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 218         xgifb_reg_set(P3c4, 0x19, 0xC0);
 219         xgifb_reg_set(P3c4, 0x16, 0x05);
 220         xgifb_reg_set(P3c4, 0x16, 0x85);
 221
 222         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 223         xgifb_reg_set(P3c4, 0x19, 0x40);
 224         xgifb_reg_set(P3c4, 0x16, 0x05);
 225         xgifb_reg_set(P3c4, 0x16, 0x85);
 226
 227         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 228         xgifb_reg_set(P3c4, 0x19, 0x02);
 229         xgifb_reg_set(P3c4, 0x16, 0x05);
 230         xgifb_reg_set(P3c4, 0x16, 0x85);
 231
 232         usleep_range(15, 1015);
 233         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 234         usleep_range(30, 1030);
 235         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 236         usleep_range(100, 1100);
 237
 238         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 239         xgifb_reg_set(P3c4, 0x19, 0x00);
 240         xgifb_reg_set(P3c4, 0x16, 0x05);
 241         xgifb_reg_set(P3c4, 0x16, 0x85);
 242
 243         usleep_range(200, 1200);
 244 }
 245
 246 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 247                                   struct vb_device_info *pVBInfo)
 248 {
 249         xgifb_reg_set(P3c4, 0x18, 0x01);
 250         xgifb_reg_set(P3c4, 0x19, 0x40);
 251         xgifb_reg_set(P3c4, 0x16, 0x00);
 252         xgifb_reg_set(P3c4, 0x16, 0x80);
 253         usleep_range(60, 1060);
 254
 255         xgifb_reg_set(P3c4, 0x18, 0x00);
 256         xgifb_reg_set(P3c4, 0x19, 0x40);
 257         xgifb_reg_set(P3c4, 0x16, 0x00);
 258         xgifb_reg_set(P3c4, 0x16, 0x80);
 259         usleep_range(60, 1060);
 260         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 261         xgifb_reg_set(P3c4, 0x19, 0x01);
 262         xgifb_reg_set(P3c4, 0x16, 0x03);
 263         xgifb_reg_set(P3c4, 0x16, 0x83);
 264         usleep_range(1, 1001);
 265         xgifb_reg_set(P3c4, 0x1B, 0x03);
 266         usleep_range(500, 1500);
 267         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 268         xgifb_reg_set(P3c4, 0x19, 0x00);
 269         xgifb_reg_set(P3c4, 0x16, 0x03);
 270         xgifb_reg_set(P3c4, 0x16, 0x83);
 271         xgifb_reg_set(P3c4, 0x1B, 0x00);
 272 }
 273
 274 static void XGINew_DDR1x_DefaultRegister(
 275                 struct xgi_hw_device_info *HwDeviceExtension,
 276                 unsigned long Port, struct vb_device_info *pVBInfo)
 277 {
 278         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 279
 280         if (HwDeviceExtension->jChipType >= XG20) {
 281                 XGINew_SetMemoryClock(pVBInfo);
 282                 xgifb_reg_set(P3d4,
 283                               0x82,
 284                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 285                 xgifb_reg_set(P3d4,
 286                               0x85,
 287                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 288                 xgifb_reg_set(P3d4,
 289                               0x86,
 290                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 291
 292                 xgifb_reg_set(P3d4, 0x98, 0x01);
 293                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 294
 295                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 296         } else {
 297                 XGINew_SetMemoryClock(pVBInfo);
 298
 299                 switch (HwDeviceExtension->jChipType) {
 300                 case XG42:
 301                         /* CR82 */
 302                         xgifb_reg_set(P3d4,
 303                                       0x82,
 304                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 305                         /* CR85 */
 306                         xgifb_reg_set(P3d4,
 307                                       0x85,
 308                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 309                         /* CR86 */
 310                         xgifb_reg_set(P3d4,
 311                                       0x86,
 312                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 313                         break;
 314                 default:
 315                         xgifb_reg_set(P3d4, 0x82, 0x88);
 316                         xgifb_reg_set(P3d4, 0x86, 0x00);
 317                         /* Insert read command for delay */
 318                         xgifb_reg_get(P3d4, 0x86);
 319                         xgifb_reg_set(P3d4, 0x86, 0x88);
 320                         xgifb_reg_get(P3d4, 0x86);
 321                         xgifb_reg_set(P3d4,
 322                                       0x86,
 323                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 324                         xgifb_reg_set(P3d4, 0x82, 0x77);
 325                         xgifb_reg_set(P3d4, 0x85, 0x00);
 326
 327                         /* Insert read command for delay */
 328                         xgifb_reg_get(P3d4, 0x85);
 329                         xgifb_reg_set(P3d4, 0x85, 0x88);
 330
 331                         /* Insert read command for delay */
 332                         xgifb_reg_get(P3d4, 0x85);
 333                         /* CR85 */
 334                         xgifb_reg_set(P3d4,
 335                                       0x85,
 336                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 337                         /* CR82 */
 338                         xgifb_reg_set(P3d4,
 339                                       0x82,
 340                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 341                         break;
 342                 }
 343
 344                 xgifb_reg_set(P3d4, 0x97, 0x00);
 345                 xgifb_reg_set(P3d4, 0x98, 0x01);
 346                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 347                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 348         }
 349 }
 350
 351 static void XGINew_DDR2_DefaultRegister(
 352                 struct xgi_hw_device_info *HwDeviceExtension,
 353                 unsigned long Port, struct vb_device_info *pVBInfo)
 354 {
 355         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 356
 357         /* keep following setting sequence, each setting in
 358          * the same reg insert idle */
 359         xgifb_reg_set(P3d4, 0x82, 0x77);
 360         xgifb_reg_set(P3d4, 0x86, 0x00);
 361         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 362         xgifb_reg_set(P3d4, 0x86, 0x88);
 363         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 364         /* CR86 */
 365         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 366         xgifb_reg_set(P3d4, 0x82, 0x77);
 367         xgifb_reg_set(P3d4, 0x85, 0x00);
 368         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 369         xgifb_reg_set(P3d4, 0x85, 0x88);
 370         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 371         xgifb_reg_set(P3d4,
 372                       0x85,
 373                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 374         if (HwDeviceExtension->jChipType == XG27)
 375                 /* CR82 */
 376                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 377         else
 378                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 379
 380         xgifb_reg_set(P3d4, 0x98, 0x01);
 381         xgifb_reg_set(P3d4, 0x9A, 0x02);
 382         if (HwDeviceExtension->jChipType == XG27)
 383                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 384         else
 385                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 386 }
 387
 388 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 389         u8 shift_factor, u8 mask1, u8 mask2)
 390 {
 391         u8 j;
 392
 393         for (j = 0; j < 4; j++) {
 394                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 395                 xgifb_reg_set(P3d4, reg, temp2);
 396                 xgifb_reg_get(P3d4, reg);
 397                 temp2 &= mask1;
 398                 temp2 += mask2;
 399         }
 400 }
 401
 402 static void XGINew_SetDRAMDefaultRegister340(
 403                 struct xgi_hw_device_info *HwDeviceExtension,
 404                 unsigned long Port, struct vb_device_info *pVBInfo)
 405 {
 406         unsigned char temp, temp1, temp2, temp3, j, k;
 407
 408         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 409
 410         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 411         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 412         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 413         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 414
 415         /* CR6B DQS fine tune delay */
 416         temp = 0xaa;
 417         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 418
 419         /* CR6E DQM fine tune delay */
 420         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 421
 422         temp3 = 0;
 423         for (k = 0; k < 4; k++) {
 424                 /* CR6E_D[1:0] select channel */
 425                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 426                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 427                 temp3 += 0x01;
 428         }
 429
 430         xgifb_reg_set(P3d4,
 431                       0x80,
 432                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 433         xgifb_reg_set(P3d4,
 434                       0x81,
 435                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 436
 437         temp2 = 0x80;
 438         /* CR89 terminator type select */
 439         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 440
 441         temp = 0;
 442         temp1 = temp & 0x03;
 443         temp2 |= temp1;
 444         xgifb_reg_set(P3d4, 0x89, temp2);
 445
 446         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 447         temp1 = temp & 0x0F;
 448         temp2 = (temp >> 4) & 0x07;
 449         temp3 = temp & 0x80;
 450         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 451         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 452         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 453         xgifb_reg_set(P3d4,
 454                       0x41,
 455                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 456
 457         if (HwDeviceExtension->jChipType == XG27)
 458                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 459
 460         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 461                 xgifb_reg_set(P3d4, (0x90 + j),
 462                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 463
 464         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 465                 xgifb_reg_set(P3d4, (0xC3 + j),
 466                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 467
 468         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 469                 xgifb_reg_set(P3d4, (0x8A + j),
 470                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 471
 472         if (HwDeviceExtension->jChipType == XG42)
 473                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 474
 475         xgifb_reg_set(P3d4,
 476                       0x59,
 477                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 478
 479         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 480         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 481         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 482         if (pVBInfo->ram_type) {
 483                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 484                 if (HwDeviceExtension->jChipType == XG27)
 485                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 486
 487         } else {
 488                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 489         }
 490         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 491
 492         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 493         if (temp == 0) {
 494                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 495         } else {
 496                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 497                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 498         }
 499         xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
 500 }
 501
 502 static unsigned short XGINew_SetDRAMSize20Reg(
 503                 unsigned short dram_size,
 504                 struct vb_device_info *pVBInfo)
 505 {
 506         unsigned short data = 0, memsize = 0;
 507         int RankSize;
 508         unsigned char ChannelNo;
 509
 510         RankSize = dram_size * pVBInfo->ram_bus / 8;
 511         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 512         data &= 0x80;
 513
 514         if (data == 0x80)
 515                 RankSize *= 2;
 516
 517         data = 0;
 518
 519         if (pVBInfo->ram_channel == 3)
 520                 ChannelNo = 4;
 521         else
 522                 ChannelNo = pVBInfo->ram_channel;
 523
 524         if (ChannelNo * RankSize <= 256) {
 525                 while ((RankSize >>= 1) > 0)
 526                         data += 0x10;
 527
 528                 memsize = data >> 4;
 529
 530                 /* Fix DRAM Sizing Error */
 531                 xgifb_reg_set(pVBInfo->P3c4,
 532                               0x14,
 533                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 534                                 (data & 0xF0));
 535                 usleep_range(15, 1015);
 536         }
 537         return memsize;
 538 }
 539
 540 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 541                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 542 {
 543         int i;
 544         unsigned long Position = 0;
 545         void __iomem *fbaddr = pVBInfo->FBAddr;
 546
 547         writel(Position, fbaddr + Position);
 548
 549         for (i = StartAddr; i <= StopAddr; i++) {
 550                 Position = 1 << i;
 551                 writel(Position, fbaddr + Position);
 552         }
 553
 554         usleep_range(500, 1500); /* Fix #1759 Memory Size error in Multi-Adapter. */
 555
 556         Position = 0;
 557
 558         if (readl(fbaddr + Position) != Position)
 559                 return 0;
 560
 561         for (i = StartAddr; i <= StopAddr; i++) {
 562                 Position = 1 << i;
 563                 if (readl(fbaddr + Position) != Position)
 564                         return 0;
 565         }
 566         return 1;
 567 }
 568
 569 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 570 {
 571         unsigned char data;
 572
 573         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 574
 575         if ((data & 0x10) == 0) {
 576                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 577                 data = (data & 0x02) >> 1;
 578                 return data;
 579         }
 580         return data & 0x01;
 581 }
 582
 583 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 584                 struct vb_device_info *pVBInfo)
 585 {
 586         unsigned char data;
 587
 588         switch (HwDeviceExtension->jChipType) {
 589         case XG20:
 590         case XG21:
 591                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 592                 data = data & 0x01;
 593                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 594
 595                 if (data == 0) { /* Single_32_16 */
 596
 597                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 598                                         > 0x1000000) {
 599                                 pVBInfo->ram_bus = 32; /* 32 bits */
 600                                 /* 22bit + 2 rank + 32bit */
 601                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 602                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 603                                 usleep_range(15, 1015);
 604
 605                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 606                                         return;
 607
 608                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 609                                     0x800000) {
 610                                         /* 22bit + 1 rank + 32bit */
 611                                         xgifb_reg_set(pVBInfo->P3c4,
 612                                                       0x13,
 613                                                       0x31);
 614                                         xgifb_reg_set(pVBInfo->P3c4,
 615                                                       0x14,
 616                                                       0x42);
 617                                         usleep_range(15, 1015);
 618
 619                                         if (XGINew_ReadWriteRest(23,
 620                                                                  23,
 621                                                                  pVBInfo) == 1)
 622                                                 return;
 623                                 }
 624                         }
 625
 626                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 627                             0x800000) {
 628                                 pVBInfo->ram_bus = 16; /* 16 bits */
 629                                 /* 22bit + 2 rank + 16bit */
 630                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 631                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 632                                 usleep_range(15, 1015);
 633
 634                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 635                                         return;
 636                                 xgifb_reg_set(pVBInfo->P3c4,
 637                                               0x13,
 638                                               0x31);
 639                                 usleep_range(15, 1015);
 640                         }
 641
 642                 } else { /* Dual_16_8 */
 643                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 644                             0x800000) {
 645                                 pVBInfo->ram_bus = 16; /* 16 bits */
 646                                 /* (0x31:12x8x2) 22bit + 2 rank */
 647                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 648                                 /* 0x41:16Mx16 bit*/
 649                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 650                                 usleep_range(15, 1015);
 651
 652                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 653                                         return;
 654
 655                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 656                                     0x400000) {
 657                                         /* (0x31:12x8x2) 22bit + 1 rank */
 658                                         xgifb_reg_set(pVBInfo->P3c4,
 659                                                       0x13,
 660                                                       0x31);
 661                                         /* 0x31:8Mx16 bit*/
 662                                         xgifb_reg_set(pVBInfo->P3c4,
 663                                                       0x14,
 664                                                       0x31);
 665                                         usleep_range(15, 1015);
 666
 667                                         if (XGINew_ReadWriteRest(22,
 668                                                                  22,
 669                                                                  pVBInfo) == 1)
 670                                                 return;
 671                                 }
 672                         }
 673
 674                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 675                             0x400000) {
 676                                 pVBInfo->ram_bus = 8; /* 8 bits */
 677                                 /* (0x31:12x8x2) 22bit + 2 rank */
 678                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 679                                 /* 0x30:8Mx8 bit*/
 680                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 681                                 usleep_range(15, 1015);
 682
 683                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 684                                         return;
 685
 686                                 /* (0x31:12x8x2) 22bit + 1 rank */
 687                                 xgifb_reg_set(pVBInfo->P3c4,
 688                                               0x13,
 689                                               0x31);
 690                                 usleep_range(15, 1015);
 691                         }
 692                 }
 693                 break;
 694
 695         case XG27:
 696                 pVBInfo->ram_bus = 16; /* 16 bits */
 697                 pVBInfo->ram_channel = 1; /* Single channel */
 698                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 699                 break;
 700         case XG42:
 701                 /*
 702                  XG42 SR14 D[3] Reserve
 703                  D[2] = 1, Dual Channel
 704                  = 0, Single Channel
 705
 706                  It's Different from Other XG40 Series.
 707                  */
 708                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 709                         pVBInfo->ram_bus = 32; /* 32 bits */
 710                         pVBInfo->ram_channel = 2; /* 2 Channel */
 711                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 712                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 713
 714                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 715                                 return;
 716
 717                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 718                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 719                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 720                                 return;
 721
 722                         pVBInfo->ram_channel = 1; /* Single Channel */
 723                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 724                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 725
 726                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 727                                 return;
 728                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 729                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 730                 } else { /* DDR */
 731                         pVBInfo->ram_bus = 64; /* 64 bits */
 732                         pVBInfo->ram_channel = 1; /* 1 channels */
 733                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 734                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 735
 736                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 737                                 return;
 738                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 739                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 740                 }
 741
 742                 break;
 743
 744         default: /* XG40 */
 745
 746                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 747                         pVBInfo->ram_bus = 32; /* 32 bits */
 748                         pVBInfo->ram_channel = 3;
 749                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 750                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 751
 752                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 753                                 return;
 754
 755                         pVBInfo->ram_channel = 2; /* 2 channels */
 756                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 757
 758                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 759                                 return;
 760
 761                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 762                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 763
 764                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 765                                 pVBInfo->ram_channel = 3; /* 4 channels */
 766                         } else {
 767                                 pVBInfo->ram_channel = 2; /* 2 channels */
 768                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 769                         }
 770                 } else { /* DDR */
 771                         pVBInfo->ram_bus = 64; /* 64 bits */
 772                         pVBInfo->ram_channel = 2; /* 2 channels */
 773                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 774                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 775
 776                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 777                                 return;
 778                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 779                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 780                 }
 781                 break;
 782         }
 783 }
 784
 785 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 786                 struct vb_device_info *pVBInfo)
 787 {
 788         u8 i, size;
 789         unsigned short memsize, start_addr;
 790         const unsigned short (*dram_table)[2];
 791
 792         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 793         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 794         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 795
 796         if (HwDeviceExtension->jChipType >= XG20) {
 797                 dram_table = XGINew_DDRDRAM_TYPE20;
 798                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 799                 start_addr = 5;
 800         } else {
 801                 dram_table = XGINew_DDRDRAM_TYPE340;
 802                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 803                 start_addr = 9;
 804         }
 805
 806         for (i = 0; i < size; i++) {
 807                 /* SetDRAMSizingType */
 808                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 809                 usleep_range(50, 1050); /* should delay 50 ns */
 810
 811                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 812
 813                 if (memsize == 0)
 814                         continue;
 815
 816                 memsize += (pVBInfo->ram_channel - 2) + 20;
 817                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 818                         (unsigned long)(1 << memsize))
 819                         continue;
 820
 821                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 822                         return 1;
 823         }
 824         return 0;
 825 }
 826
 827 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 828                 struct xgi_hw_device_info *HwDeviceExtension,
 829                 struct vb_device_info *pVBInfo)
 830 {
 831         unsigned short data;
 832
 833         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 834
 835         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 836
 837         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 838         /* disable read cache */
 839         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
 840         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 841
 842         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 843         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 844         /* enable read cache */
 845         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
 846 }
 847
 848 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
 849 {
 850         void __iomem *rom_address;
 851         u8 *rom_copy;
 852
 853         rom_address = pci_map_rom(dev, rom_size);
 854         if (!rom_address)
 855                 return NULL;
 856
 857         rom_copy = vzalloc(XGIFB_ROM_SIZE);
 858         if (!rom_copy)
 859                 goto done;
 860
 861         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
 862         memcpy_fromio(rom_copy, rom_address, *rom_size);
 863
 864 done:
 865         pci_unmap_rom(dev, rom_address);
 866         return rom_copy;
 867 }
 868
 869 static bool xgifb_read_vbios(struct pci_dev *pdev)
 870 {
 871         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
 872         u8 *vbios;
 873         unsigned long i;
 874         unsigned char j;
 875         struct XGI21_LVDSCapStruct *lvds;
 876         size_t vbios_size;
 877         int entry;
 878
 879         vbios = xgifb_copy_rom(pdev, &vbios_size);
 880         if (!vbios) {
 881                 dev_err(&pdev->dev, "Video BIOS not available\n");
 882                 return false;
 883         }
 884         if (vbios_size <= 0x65)
 885                 goto error;
 886         /*
 887          * The user can ignore the LVDS bit in the BIOS and force the display
 888          * type.
 889          */
 890         if (!(vbios[0x65] & 0x1) &&
 891             (!xgifb_info->display2_force ||
 892              xgifb_info->display2 != XGIFB_DISP_LCD)) {
 893                 vfree(vbios);
 894                 return false;
 895         }
 896         if (vbios_size <= 0x317)
 897                 goto error;
 898         i = vbios[0x316] | (vbios[0x317] << 8);
 899         if (vbios_size <= i - 1)
 900                 goto error;
 901         j = vbios[i - 1];
 902         if (j == 0)
 903                 goto error;
 904         if (j == 0xff)
 905                 j = 1;
 906         /*
 907          * Read the LVDS table index scratch register set by the BIOS.
 908          */
 909         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
 910         if (entry >= j)
 911                 entry = 0;
 912         i += entry * 25;
 913         lvds = &xgifb_info->lvds_data;
 914         if (vbios_size <= i + 24)
 915                 goto error;
 916         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
 917         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
 918         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
 919         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
 920         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
 921         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
 922         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
 923         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
 924         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
 925         lvds->VCLKData1         = vbios[i + 18];
 926         lvds->VCLKData2         = vbios[i + 19];
 927         lvds->PSC_S1            = vbios[i + 20];
 928         lvds->PSC_S2            = vbios[i + 21];
 929         lvds->PSC_S3            = vbios[i + 22];
 930         lvds->PSC_S4            = vbios[i + 23];
 931         lvds->PSC_S5            = vbios[i + 24];
 932         vfree(vbios);
 933         return true;
 934 error:
 935         dev_err(&pdev->dev, "Video BIOS corrupted\n");
 936         vfree(vbios);
 937         return false;
 938 }
 939
 940 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
 941 {
 942         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 943
 944         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 945
 946         if (temp & Monitor1Sense)
 947                 tempbx |= ActiveCRT1;
 948         if (temp & LCDSense)
 949                 tempbx |= ActiveLCD;
 950         if (temp & Monitor2Sense)
 951                 tempbx |= ActiveCRT2;
 952         if (temp & TVSense) {
 953                 tempbx |= ActiveTV;
 954                 if (temp & AVIDEOSense)
 955                         tempbx |= (ActiveAVideo << 8);
 956                 if (temp & SVIDEOSense)
 957                         tempbx |= (ActiveSVideo << 8);
 958                 if (temp & SCARTSense)
 959                         tempbx |= (ActiveSCART << 8);
 960                 if (temp & HiTVSense)
 961                         tempbx |= (ActiveHiTV << 8);
 962                 if (temp & YPbPrSense)
 963                         tempbx |= (ActiveYPbPr << 8);
 964         }
 965
 966         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 967         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
 968
 969         if (tempbx & tempcx) {
 970                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
 971                 if (!(CR3CData & DisplayDeviceFromCMOS))
 972                         tempcx = 0x1FF0;
 973         } else {
 974                 tempcx = 0x1FF0;
 975         }
 976
 977         tempbx &= tempcx;
 978         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
 979         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
 980 }
 981
 982 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
 983 {
 984         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
 985
 986         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 987         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
 988         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
 989
 990         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
 991                 if (temp & ActiveCRT2)
 992                         tempcl = SetCRT2ToRAMDAC;
 993         }
 994
 995         if (temp & ActiveLCD) {
 996                 tempcl |= SetCRT2ToLCD;
 997                 if (temp & DriverMode) {
 998                         if (temp & ActiveTV) {
 999                                 tempch = SetToLCDA | EnableDualEdge;
1000                                 temp ^= SetCRT2ToLCD;
1001
1002                                 if ((temp >> 8) & ActiveAVideo)
1003                                         tempcl |= SetCRT2ToAVIDEO;
1004                                 if ((temp >> 8) & ActiveSVideo)
1005                                         tempcl |= SetCRT2ToSVIDEO;
1006                                 if ((temp >> 8) & ActiveSCART)
1007                                         tempcl |= SetCRT2ToSCART;
1008
1009                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1010                                         if ((temp >> 8) & ActiveHiTV)
1011                                                 tempcl |= SetCRT2ToHiVision;
1012                                 }
1013
1014                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1015                                         if ((temp >> 8) & ActiveYPbPr)
1016                                                 tempch |= SetYPbPr;
1017                                 }
1018                         }
1019                 }
1020         } else {
1021                 if ((temp >> 8) & ActiveAVideo)
1022                         tempcl |= SetCRT2ToAVIDEO;
1023                 if ((temp >> 8) & ActiveSVideo)
1024                         tempcl |= SetCRT2ToSVIDEO;
1025                 if ((temp >> 8) & ActiveSCART)
1026                         tempcl |= SetCRT2ToSCART;
1027
1028                 if (pVBInfo->IF_DEF_HiVision == 1) {
1029                         if ((temp >> 8) & ActiveHiTV)
1030                                 tempcl |= SetCRT2ToHiVision;
1031                 }
1032
1033                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1034                         if ((temp >> 8) & ActiveYPbPr)
1035                                 tempch |= SetYPbPr;
1036                 }
1037         }
1038
1039         tempcl |= SetSimuScanMode;
1040         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1041                         || (temp & ActiveCRT2)))
1042                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1043         if ((temp & ActiveLCD) && (temp & ActiveTV))
1044                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1045         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1046
1047         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1048         CR31Data &= ~(SetNotSimuMode >> 8);
1049         if (!(temp & ActiveCRT1))
1050                 CR31Data |= (SetNotSimuMode >> 8);
1051         CR31Data &= ~(DisableCRT2Display >> 8);
1052         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1053                 CR31Data |= (DisableCRT2Display >> 8);
1054         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1055
1056         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1057         CR38Data &= ~SetYPbPr;
1058         CR38Data |= tempch;
1059         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1060 }
1061
1062 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1063                                                         *HwDeviceExtension,
1064                                       struct vb_device_info *pVBInfo)
1065 {
1066         unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1067
1068         switch (HwDeviceExtension->ulCRT2LCDType) {
1069         case LCD_640x480:
1070         case LCD_1024x600:
1071         case LCD_1152x864:
1072         case LCD_1280x960:
1073         case LCD_1152x768:
1074         case LCD_1920x1440:
1075         case LCD_2048x1536:
1076                 temp = 0; /* overwrite used ulCRT2LCDType */
1077                 break;
1078         case LCD_UNKNOWN: /* unknown lcd, do nothing */
1079                 return 0;
1080         }
1081         xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1082         return 1;
1083 }
1084
1085 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1086                 struct vb_device_info *pVBInfo)
1087 {
1088         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1089         unsigned char Temp;
1090
1091         if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1092                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1093                 /* LVDS on chip */
1094                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1095         } else {
1096                 /* Enable GPIOA/B read  */
1097                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1098                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1099                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1100                         XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1101                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1102                         /* Enable read GPIOF */
1103                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1104                         if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1105                                 Temp = 0xA0; /* Only DVO on chip */
1106                         else
1107                                 Temp = 0x80; /* TMDS on chip */
1108                         xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1109                         /* Disable read GPIOF */
1110                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1111                 }
1112         }
1113 }
1114
1115 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1116 {
1117         unsigned char Temp, bCR4A;
1118
1119         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1120         /* Enable GPIOA/B/C read  */
1121         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1122         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1123         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1124
1125         if (Temp <= 0x02) {
1126                 /* LVDS setting */
1127                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1128                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1129         } else {
1130                 /* TMDS/DVO setting */
1131                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1132         }
1133         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1134 }
1135
1136 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1137 {
1138         unsigned char CR38, CR4A, temp;
1139
1140         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1141         /* enable GPIOE read */
1142         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1143         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1144         temp = 0;
1145         if ((CR38 & 0xE0) > 0x80) {
1146                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1147                 temp &= 0x08;
1148                 temp >>= 3;
1149         }
1150
1151         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1152
1153         return temp;
1154 }
1155
1156 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1157 {
1158         unsigned char CR4A, temp;
1159
1160         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1161         /* enable GPIOA/B/C read */
1162         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1163         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1164         if (temp > 2)
1165                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1166
1167         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1168
1169         return temp;
1170 }
1171
1172 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1173 {
1174         u8 flag;
1175
1176         flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1177         return flag == 1 || flag == 2;
1178 }
1179
1180 unsigned char XGIInitNew(struct pci_dev *pdev)
1181 {
1182         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1183         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1184         struct vb_device_info VBINF;
1185         struct vb_device_info *pVBInfo = &VBINF;
1186         unsigned char i, temp = 0, temp1;
1187
1188         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1189
1190         if (!pVBInfo->FBAddr) {
1191                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1192                 return 0;
1193         }
1194
1195         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1196
1197         outb(0x67, pVBInfo->P3c2);
1198
1199         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1200
1201         /* Openkey */
1202         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1203
1204         /* GetXG21Sense (GPIO) */
1205         if (HwDeviceExtension->jChipType == XG21)
1206                 XGINew_GetXG21Sense(pdev, pVBInfo);
1207
1208         if (HwDeviceExtension->jChipType == XG27)
1209                 XGINew_GetXG27Sense(pVBInfo);
1210
1211         /* Reset Extended register */
1212
1213         for (i = 0x06; i < 0x20; i++)
1214                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1215
1216         for (i = 0x21; i <= 0x27; i++)
1217                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1218
1219         for (i = 0x31; i <= 0x3B; i++)
1220                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1221
1222         /* Auto over driver for XG42 */
1223         if (HwDeviceExtension->jChipType == XG42)
1224                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1225
1226         for (i = 0x79; i <= 0x7C; i++)
1227                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1228
1229         if (HwDeviceExtension->jChipType >= XG20)
1230                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1231
1232         /* SetDefExt1Regs begin */
1233         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1234         if (HwDeviceExtension->jChipType == XG27) {
1235                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1236                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1237         }
1238         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1239         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1240         /* Frame buffer can read/write SR20 */
1241         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1242         /* H/W request for slow corner chip */
1243         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1244         if (HwDeviceExtension->jChipType == XG27)
1245                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1246
1247         if (HwDeviceExtension->jChipType < XG20) {
1248                 u32 Temp;
1249
1250                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1251                 for (i = 0x47; i <= 0x4C; i++)
1252                         xgifb_reg_set(pVBInfo->P3d4,
1253                                       i,
1254                                       XGI340_AGPReg[i - 0x47]);
1255
1256                 for (i = 0x70; i <= 0x71; i++)
1257                         xgifb_reg_set(pVBInfo->P3d4,
1258                                       i,
1259                                       XGI340_AGPReg[6 + i - 0x70]);
1260
1261                 for (i = 0x74; i <= 0x77; i++)
1262                         xgifb_reg_set(pVBInfo->P3d4,
1263                                       i,
1264                                       XGI340_AGPReg[8 + i - 0x74]);
1265
1266                 pci_read_config_dword(pdev, 0x50, &Temp);
1267                 Temp >>= 20;
1268                 Temp &= 0xF;
1269
1270                 if (Temp == 1)
1271                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1272         } /* != XG20 */
1273
1274         /* Set PCI */
1275         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1276         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1277         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1278
1279         if (HwDeviceExtension->jChipType < XG20) {
1280                 /* Set VB */
1281                 XGI_UnLockCRT2(pVBInfo);
1282                 /* disable VideoCapture */
1283                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1284                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1285                 /* chk if BCLK>=100MHz */
1286                 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1287
1288                 xgifb_reg_set(pVBInfo->Part1Port,
1289                               0x02, XGI330_CRT2Data_1_2);
1290
1291                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1292         } /* != XG20 */
1293
1294         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1295
1296         if ((HwDeviceExtension->jChipType == XG42) &&
1297             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1298                 /* Not DDR */
1299                 xgifb_reg_set(pVBInfo->P3c4,
1300                               0x31,
1301                               (XGI330_SR31 & 0x3F) | 0x40);
1302                 xgifb_reg_set(pVBInfo->P3c4,
1303                               0x32,
1304                               (XGI330_SR32 & 0xFC) | 0x01);
1305         } else {
1306                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1307                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1308         }
1309         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1310
1311         if (HwDeviceExtension->jChipType < XG20) {
1312                 if (xgifb_bridge_is_on(pVBInfo)) {
1313                         xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1314                         xgifb_reg_set(pVBInfo->Part4Port,
1315                                       0x0D, XGI330_CRT2Data_4_D);
1316                         xgifb_reg_set(pVBInfo->Part4Port,
1317                                       0x0E, XGI330_CRT2Data_4_E);
1318                         xgifb_reg_set(pVBInfo->Part4Port,
1319                                       0x10, XGI330_CRT2Data_4_10);
1320                         xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1321                         XGI_LockCRT2(pVBInfo);
1322                 }
1323         } /* != XG20 */
1324
1325         XGI_SenseCRT1(pVBInfo);
1326
1327         if (HwDeviceExtension->jChipType == XG21) {
1328                 xgifb_reg_and_or(pVBInfo->P3d4,
1329                                  0x32,
1330                                  ~Monitor1Sense,
1331                                  Monitor1Sense); /* Z9 default has CRT */
1332                 temp = GetXG21FPBits(pVBInfo);
1333                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1334         }
1335         if (HwDeviceExtension->jChipType == XG27) {
1336                 xgifb_reg_and_or(pVBInfo->P3d4,
1337                                  0x32,
1338                                  ~Monitor1Sense,
1339                                  Monitor1Sense); /* Z9 default has CRT */
1340                 temp = GetXG27FPBits(pVBInfo);
1341                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1342         }
1343
1344         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1345
1346         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1347                                          pVBInfo->P3d4,
1348                                          pVBInfo);
1349
1350         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1351
1352         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1353         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1354
1355         XGINew_ChkSenseStatus(pVBInfo);
1356         XGINew_SetModeScratch(pVBInfo);
1357
1358         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1359
1360         return 1;
1361 } /* end of init */