1 #include <linux/delay.h>
2 #include <linux/vmalloc.h>
7 #include "vb_setmode.h"
9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
29 #define XGIFB_ROM_SIZE 65536
32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
35 unsigned char data, temp;
37 if (HwDeviceExtension->jChipType < XG20) {
38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
43 } else if (HwDeviceExtension->jChipType == XG27) {
44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
51 } else if (HwDeviceExtension->jChipType == XG21) {
52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
54 usleep_range(800, 1800);
55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
56 /* GPIOF 0:DVI 1:DVO */
57 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
59 /* for current XG20 & XG21, GPIOH is floating, driver will
63 data &= 0x01; /* 1=DDRII, 0=DDR */
64 /* ~HOTPLUG_SUPPORT */
65 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
68 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
76 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
77 struct vb_device_info *pVBInfo)
79 xgifb_reg_set(P3c4, 0x18, 0x01);
80 xgifb_reg_set(P3c4, 0x19, 0x20);
81 xgifb_reg_set(P3c4, 0x16, 0x00);
82 xgifb_reg_set(P3c4, 0x16, 0x80);
84 usleep_range(3, 1003);
85 xgifb_reg_set(P3c4, 0x18, 0x00);
86 xgifb_reg_set(P3c4, 0x19, 0x20);
87 xgifb_reg_set(P3c4, 0x16, 0x00);
88 xgifb_reg_set(P3c4, 0x16, 0x80);
90 usleep_range(60, 1060);
91 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
92 xgifb_reg_set(P3c4, 0x19, 0x01);
93 xgifb_reg_set(P3c4, 0x16, 0x03);
94 xgifb_reg_set(P3c4, 0x16, 0x83);
95 usleep_range(1, 1001);
96 xgifb_reg_set(P3c4, 0x1B, 0x03);
97 usleep_range(500, 1500);
98 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
99 xgifb_reg_set(P3c4, 0x19, 0x00);
100 xgifb_reg_set(P3c4, 0x16, 0x03);
101 xgifb_reg_set(P3c4, 0x16, 0x83);
102 xgifb_reg_set(P3c4, 0x1B, 0x00);
105 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
107 xgifb_reg_set(pVBInfo->P3c4,
109 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
110 xgifb_reg_set(pVBInfo->P3c4,
112 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
113 xgifb_reg_set(pVBInfo->P3c4,
115 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
117 xgifb_reg_set(pVBInfo->P3c4,
119 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
120 xgifb_reg_set(pVBInfo->P3c4,
122 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
123 xgifb_reg_set(pVBInfo->P3c4,
125 XGI340_ECLKData[pVBInfo->ram_type].SR30);
128 static void XGINew_DDRII_Bootup_XG27(
129 struct xgi_hw_device_info *HwDeviceExtension,
130 unsigned long P3c4, struct vb_device_info *pVBInfo)
132 unsigned long P3d4 = P3c4 + 0x10;
134 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
135 XGINew_SetMemoryClock(pVBInfo);
137 /* Set Double Frequency */
138 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
140 usleep_range(200, 1200);
142 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
143 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
144 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
145 usleep_range(15, 1015);
146 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
147 usleep_range(15, 1015);
149 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
150 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
151 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
152 usleep_range(15, 1015);
153 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
154 usleep_range(15, 1015);
156 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
157 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
158 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
159 usleep_range(30, 1030);
160 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
161 usleep_range(15, 1015);
163 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
164 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
165 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
166 usleep_range(30, 1030);
167 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
168 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
170 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
171 usleep_range(60, 1060);
172 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
174 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
175 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
176 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
178 usleep_range(30, 1030);
179 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
180 usleep_range(15, 1015);
182 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
183 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
184 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
185 usleep_range(30, 1030);
186 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
187 usleep_range(15, 1015);
189 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
190 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
191 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
192 usleep_range(30, 1030);
193 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
194 usleep_range(15, 1015);
196 /* Set SR1B refresh control 000:close; 010:open */
197 xgifb_reg_set(P3c4, 0x1B, 0x04);
198 usleep_range(200, 1200);
201 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
202 unsigned long P3c4, struct vb_device_info *pVBInfo)
204 unsigned long P3d4 = P3c4 + 0x10;
206 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
207 XGINew_SetMemoryClock(pVBInfo);
209 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
211 usleep_range(200, 1200);
212 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
213 xgifb_reg_set(P3c4, 0x19, 0x80);
214 xgifb_reg_set(P3c4, 0x16, 0x05);
215 xgifb_reg_set(P3c4, 0x16, 0x85);
217 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
218 xgifb_reg_set(P3c4, 0x19, 0xC0);
219 xgifb_reg_set(P3c4, 0x16, 0x05);
220 xgifb_reg_set(P3c4, 0x16, 0x85);
222 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
223 xgifb_reg_set(P3c4, 0x19, 0x40);
224 xgifb_reg_set(P3c4, 0x16, 0x05);
225 xgifb_reg_set(P3c4, 0x16, 0x85);
227 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
228 xgifb_reg_set(P3c4, 0x19, 0x02);
229 xgifb_reg_set(P3c4, 0x16, 0x05);
230 xgifb_reg_set(P3c4, 0x16, 0x85);
232 usleep_range(15, 1015);
233 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
234 usleep_range(30, 1030);
235 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
236 usleep_range(100, 1100);
238 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
239 xgifb_reg_set(P3c4, 0x19, 0x00);
240 xgifb_reg_set(P3c4, 0x16, 0x05);
241 xgifb_reg_set(P3c4, 0x16, 0x85);
243 usleep_range(200, 1200);
246 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
247 struct vb_device_info *pVBInfo)
249 xgifb_reg_set(P3c4, 0x18, 0x01);
250 xgifb_reg_set(P3c4, 0x19, 0x40);
251 xgifb_reg_set(P3c4, 0x16, 0x00);
252 xgifb_reg_set(P3c4, 0x16, 0x80);
253 usleep_range(60, 1060);
255 xgifb_reg_set(P3c4, 0x18, 0x00);
256 xgifb_reg_set(P3c4, 0x19, 0x40);
257 xgifb_reg_set(P3c4, 0x16, 0x00);
258 xgifb_reg_set(P3c4, 0x16, 0x80);
259 usleep_range(60, 1060);
260 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
261 xgifb_reg_set(P3c4, 0x19, 0x01);
262 xgifb_reg_set(P3c4, 0x16, 0x03);
263 xgifb_reg_set(P3c4, 0x16, 0x83);
264 usleep_range(1, 1001);
265 xgifb_reg_set(P3c4, 0x1B, 0x03);
266 usleep_range(500, 1500);
267 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
268 xgifb_reg_set(P3c4, 0x19, 0x00);
269 xgifb_reg_set(P3c4, 0x16, 0x03);
270 xgifb_reg_set(P3c4, 0x16, 0x83);
271 xgifb_reg_set(P3c4, 0x1B, 0x00);
274 static void XGINew_DDR1x_DefaultRegister(
275 struct xgi_hw_device_info *HwDeviceExtension,
276 unsigned long Port, struct vb_device_info *pVBInfo)
278 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
280 if (HwDeviceExtension->jChipType >= XG20) {
281 XGINew_SetMemoryClock(pVBInfo);
284 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
287 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
290 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
292 xgifb_reg_set(P3d4, 0x98, 0x01);
293 xgifb_reg_set(P3d4, 0x9A, 0x02);
295 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
297 XGINew_SetMemoryClock(pVBInfo);
299 switch (HwDeviceExtension->jChipType) {
304 pVBInfo->CR40[11][pVBInfo->ram_type]);
308 pVBInfo->CR40[12][pVBInfo->ram_type]);
312 pVBInfo->CR40[13][pVBInfo->ram_type]);
315 xgifb_reg_set(P3d4, 0x82, 0x88);
316 xgifb_reg_set(P3d4, 0x86, 0x00);
317 /* Insert read command for delay */
318 xgifb_reg_get(P3d4, 0x86);
319 xgifb_reg_set(P3d4, 0x86, 0x88);
320 xgifb_reg_get(P3d4, 0x86);
323 pVBInfo->CR40[13][pVBInfo->ram_type]);
324 xgifb_reg_set(P3d4, 0x82, 0x77);
325 xgifb_reg_set(P3d4, 0x85, 0x00);
327 /* Insert read command for delay */
328 xgifb_reg_get(P3d4, 0x85);
329 xgifb_reg_set(P3d4, 0x85, 0x88);
331 /* Insert read command for delay */
332 xgifb_reg_get(P3d4, 0x85);
336 pVBInfo->CR40[12][pVBInfo->ram_type]);
340 pVBInfo->CR40[11][pVBInfo->ram_type]);
344 xgifb_reg_set(P3d4, 0x97, 0x00);
345 xgifb_reg_set(P3d4, 0x98, 0x01);
346 xgifb_reg_set(P3d4, 0x9A, 0x02);
347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
351 static void XGINew_DDR2_DefaultRegister(
352 struct xgi_hw_device_info *HwDeviceExtension,
353 unsigned long Port, struct vb_device_info *pVBInfo)
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
357 /* keep following setting sequence, each setting in
358 * the same reg insert idle */
359 xgifb_reg_set(P3d4, 0x82, 0x77);
360 xgifb_reg_set(P3d4, 0x86, 0x00);
361 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
362 xgifb_reg_set(P3d4, 0x86, 0x88);
363 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
365 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
366 xgifb_reg_set(P3d4, 0x82, 0x77);
367 xgifb_reg_set(P3d4, 0x85, 0x00);
368 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
369 xgifb_reg_set(P3d4, 0x85, 0x88);
370 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
373 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
374 if (HwDeviceExtension->jChipType == XG27)
376 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
378 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
380 xgifb_reg_set(P3d4, 0x98, 0x01);
381 xgifb_reg_set(P3d4, 0x9A, 0x02);
382 if (HwDeviceExtension->jChipType == XG27)
383 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
385 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
388 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
389 u8 shift_factor, u8 mask1, u8 mask2)
393 for (j = 0; j < 4; j++) {
394 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
395 xgifb_reg_set(P3d4, reg, temp2);
396 xgifb_reg_get(P3d4, reg);
402 static void XGINew_SetDRAMDefaultRegister340(
403 struct xgi_hw_device_info *HwDeviceExtension,
404 unsigned long Port, struct vb_device_info *pVBInfo)
406 unsigned char temp, temp1, temp2, temp3, j, k;
408 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
410 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
411 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
412 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
413 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
415 /* CR6B DQS fine tune delay */
417 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
419 /* CR6E DQM fine tune delay */
420 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
423 for (k = 0; k < 4; k++) {
424 /* CR6E_D[1:0] select channel */
425 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
426 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
432 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
435 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
438 /* CR89 terminator type select */
439 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
444 xgifb_reg_set(P3d4, 0x89, temp2);
446 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
448 temp2 = (temp >> 4) & 0x07;
450 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
451 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
452 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
455 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
457 if (HwDeviceExtension->jChipType == XG27)
458 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
460 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
461 xgifb_reg_set(P3d4, (0x90 + j),
462 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
464 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
465 xgifb_reg_set(P3d4, (0xC3 + j),
466 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
468 for (j = 0; j < 2; j++) /* CR8A - CR8B */
469 xgifb_reg_set(P3d4, (0x8A + j),
470 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
472 if (HwDeviceExtension->jChipType == XG42)
473 xgifb_reg_set(P3d4, 0x8C, 0x87);
477 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
479 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
480 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
481 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
482 if (pVBInfo->ram_type) {
483 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
484 if (HwDeviceExtension->jChipType == XG27)
485 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
488 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
490 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
492 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
494 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
496 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
497 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
499 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
502 static unsigned short XGINew_SetDRAMSize20Reg(
503 unsigned short dram_size,
504 struct vb_device_info *pVBInfo)
506 unsigned short data = 0, memsize = 0;
508 unsigned char ChannelNo;
510 RankSize = dram_size * pVBInfo->ram_bus / 8;
511 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
519 if (pVBInfo->ram_channel == 3)
522 ChannelNo = pVBInfo->ram_channel;
524 if (ChannelNo * RankSize <= 256) {
525 while ((RankSize >>= 1) > 0)
530 /* Fix DRAM Sizing Error */
531 xgifb_reg_set(pVBInfo->P3c4,
533 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
535 usleep_range(15, 1015);
540 static int XGINew_ReadWriteRest(unsigned short StopAddr,
541 unsigned short StartAddr, struct vb_device_info *pVBInfo)
544 unsigned long Position = 0;
545 void __iomem *fbaddr = pVBInfo->FBAddr;
547 writel(Position, fbaddr + Position);
549 for (i = StartAddr; i <= StopAddr; i++) {
551 writel(Position, fbaddr + Position);
554 usleep_range(500, 1500); /* Fix #1759 Memory Size error in Multi-Adapter. */
558 if (readl(fbaddr + Position) != Position)
561 for (i = StartAddr; i <= StopAddr; i++) {
563 if (readl(fbaddr + Position) != Position)
569 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
573 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
575 if ((data & 0x10) == 0) {
576 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
577 data = (data & 0x02) >> 1;
583 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
584 struct vb_device_info *pVBInfo)
588 switch (HwDeviceExtension->jChipType) {
591 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
593 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
595 if (data == 0) { /* Single_32_16 */
597 if ((HwDeviceExtension->ulVideoMemorySize - 1)
599 pVBInfo->ram_bus = 32; /* 32 bits */
600 /* 22bit + 2 rank + 32bit */
601 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
602 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
603 usleep_range(15, 1015);
605 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
608 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
610 /* 22bit + 1 rank + 32bit */
611 xgifb_reg_set(pVBInfo->P3c4,
614 xgifb_reg_set(pVBInfo->P3c4,
617 usleep_range(15, 1015);
619 if (XGINew_ReadWriteRest(23,
626 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
628 pVBInfo->ram_bus = 16; /* 16 bits */
629 /* 22bit + 2 rank + 16bit */
630 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
631 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
632 usleep_range(15, 1015);
634 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
636 xgifb_reg_set(pVBInfo->P3c4,
639 usleep_range(15, 1015);
642 } else { /* Dual_16_8 */
643 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
645 pVBInfo->ram_bus = 16; /* 16 bits */
646 /* (0x31:12x8x2) 22bit + 2 rank */
647 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
649 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
650 usleep_range(15, 1015);
652 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
655 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
657 /* (0x31:12x8x2) 22bit + 1 rank */
658 xgifb_reg_set(pVBInfo->P3c4,
662 xgifb_reg_set(pVBInfo->P3c4,
665 usleep_range(15, 1015);
667 if (XGINew_ReadWriteRest(22,
674 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
676 pVBInfo->ram_bus = 8; /* 8 bits */
677 /* (0x31:12x8x2) 22bit + 2 rank */
678 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
680 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
681 usleep_range(15, 1015);
683 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
686 /* (0x31:12x8x2) 22bit + 1 rank */
687 xgifb_reg_set(pVBInfo->P3c4,
690 usleep_range(15, 1015);
696 pVBInfo->ram_bus = 16; /* 16 bits */
697 pVBInfo->ram_channel = 1; /* Single channel */
698 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
702 XG42 SR14 D[3] Reserve
703 D[2] = 1, Dual Channel
706 It's Different from Other XG40 Series.
708 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
709 pVBInfo->ram_bus = 32; /* 32 bits */
710 pVBInfo->ram_channel = 2; /* 2 Channel */
711 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
712 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
714 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
717 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
718 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
719 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
722 pVBInfo->ram_channel = 1; /* Single Channel */
723 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
724 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
726 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
728 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
729 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
731 pVBInfo->ram_bus = 64; /* 64 bits */
732 pVBInfo->ram_channel = 1; /* 1 channels */
733 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
734 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
736 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
738 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
739 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
746 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
747 pVBInfo->ram_bus = 32; /* 32 bits */
748 pVBInfo->ram_channel = 3;
749 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
750 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
752 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
755 pVBInfo->ram_channel = 2; /* 2 channels */
756 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
758 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
761 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
762 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
764 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
765 pVBInfo->ram_channel = 3; /* 4 channels */
767 pVBInfo->ram_channel = 2; /* 2 channels */
768 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
771 pVBInfo->ram_bus = 64; /* 64 bits */
772 pVBInfo->ram_channel = 2; /* 2 channels */
773 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
774 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
776 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
778 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
779 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
785 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
786 struct vb_device_info *pVBInfo)
789 unsigned short memsize, start_addr;
790 const unsigned short (*dram_table)[2];
792 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
793 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
794 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
796 if (HwDeviceExtension->jChipType >= XG20) {
797 dram_table = XGINew_DDRDRAM_TYPE20;
798 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
801 dram_table = XGINew_DDRDRAM_TYPE340;
802 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
806 for (i = 0; i < size; i++) {
807 /* SetDRAMSizingType */
808 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
809 usleep_range(50, 1050); /* should delay 50 ns */
811 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
816 memsize += (pVBInfo->ram_channel - 2) + 20;
817 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
818 (unsigned long)(1 << memsize))
821 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
827 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
828 struct xgi_hw_device_info *HwDeviceExtension,
829 struct vb_device_info *pVBInfo)
833 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
835 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
837 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
838 /* disable read cache */
839 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
840 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
842 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
843 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
844 /* enable read cache */
845 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
848 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
850 void __iomem *rom_address;
853 rom_address = pci_map_rom(dev, rom_size);
857 rom_copy = vzalloc(XGIFB_ROM_SIZE);
861 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
862 memcpy_fromio(rom_copy, rom_address, *rom_size);
865 pci_unmap_rom(dev, rom_address);
869 static bool xgifb_read_vbios(struct pci_dev *pdev)
871 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
875 struct XGI21_LVDSCapStruct *lvds;
879 vbios = xgifb_copy_rom(pdev, &vbios_size);
881 dev_err(&pdev->dev, "Video BIOS not available\n");
884 if (vbios_size <= 0x65)
887 * The user can ignore the LVDS bit in the BIOS and force the display
890 if (!(vbios[0x65] & 0x1) &&
891 (!xgifb_info->display2_force ||
892 xgifb_info->display2 != XGIFB_DISP_LCD)) {
896 if (vbios_size <= 0x317)
898 i = vbios[0x316] | (vbios[0x317] << 8);
899 if (vbios_size <= i - 1)
907 * Read the LVDS table index scratch register set by the BIOS.
909 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
913 lvds = &xgifb_info->lvds_data;
914 if (vbios_size <= i + 24)
916 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
917 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
918 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
919 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
920 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
921 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
922 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
923 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
924 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
925 lvds->VCLKData1 = vbios[i + 18];
926 lvds->VCLKData2 = vbios[i + 19];
927 lvds->PSC_S1 = vbios[i + 20];
928 lvds->PSC_S2 = vbios[i + 21];
929 lvds->PSC_S3 = vbios[i + 22];
930 lvds->PSC_S4 = vbios[i + 23];
931 lvds->PSC_S5 = vbios[i + 24];
935 dev_err(&pdev->dev, "Video BIOS corrupted\n");
940 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
942 unsigned short tempbx = 0, temp, tempcx, CR3CData;
944 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
946 if (temp & Monitor1Sense)
947 tempbx |= ActiveCRT1;
950 if (temp & Monitor2Sense)
951 tempbx |= ActiveCRT2;
952 if (temp & TVSense) {
954 if (temp & AVIDEOSense)
955 tempbx |= (ActiveAVideo << 8);
956 if (temp & SVIDEOSense)
957 tempbx |= (ActiveSVideo << 8);
958 if (temp & SCARTSense)
959 tempbx |= (ActiveSCART << 8);
960 if (temp & HiTVSense)
961 tempbx |= (ActiveHiTV << 8);
962 if (temp & YPbPrSense)
963 tempbx |= (ActiveYPbPr << 8);
966 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
967 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
969 if (tempbx & tempcx) {
970 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
971 if (!(CR3CData & DisplayDeviceFromCMOS))
978 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
979 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
982 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
984 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
986 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
987 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
988 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
990 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
991 if (temp & ActiveCRT2)
992 tempcl = SetCRT2ToRAMDAC;
995 if (temp & ActiveLCD) {
996 tempcl |= SetCRT2ToLCD;
997 if (temp & DriverMode) {
998 if (temp & ActiveTV) {
999 tempch = SetToLCDA | EnableDualEdge;
1000 temp ^= SetCRT2ToLCD;
1002 if ((temp >> 8) & ActiveAVideo)
1003 tempcl |= SetCRT2ToAVIDEO;
1004 if ((temp >> 8) & ActiveSVideo)
1005 tempcl |= SetCRT2ToSVIDEO;
1006 if ((temp >> 8) & ActiveSCART)
1007 tempcl |= SetCRT2ToSCART;
1009 if (pVBInfo->IF_DEF_HiVision == 1) {
1010 if ((temp >> 8) & ActiveHiTV)
1011 tempcl |= SetCRT2ToHiVision;
1014 if (pVBInfo->IF_DEF_YPbPr == 1) {
1015 if ((temp >> 8) & ActiveYPbPr)
1021 if ((temp >> 8) & ActiveAVideo)
1022 tempcl |= SetCRT2ToAVIDEO;
1023 if ((temp >> 8) & ActiveSVideo)
1024 tempcl |= SetCRT2ToSVIDEO;
1025 if ((temp >> 8) & ActiveSCART)
1026 tempcl |= SetCRT2ToSCART;
1028 if (pVBInfo->IF_DEF_HiVision == 1) {
1029 if ((temp >> 8) & ActiveHiTV)
1030 tempcl |= SetCRT2ToHiVision;
1033 if (pVBInfo->IF_DEF_YPbPr == 1) {
1034 if ((temp >> 8) & ActiveYPbPr)
1039 tempcl |= SetSimuScanMode;
1040 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1041 || (temp & ActiveCRT2)))
1042 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1043 if ((temp & ActiveLCD) && (temp & ActiveTV))
1044 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1045 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1047 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1048 CR31Data &= ~(SetNotSimuMode >> 8);
1049 if (!(temp & ActiveCRT1))
1050 CR31Data |= (SetNotSimuMode >> 8);
1051 CR31Data &= ~(DisableCRT2Display >> 8);
1052 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1053 CR31Data |= (DisableCRT2Display >> 8);
1054 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1056 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1057 CR38Data &= ~SetYPbPr;
1059 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1062 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1064 struct vb_device_info *pVBInfo)
1066 unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1068 switch (HwDeviceExtension->ulCRT2LCDType) {
1076 temp = 0; /* overwrite used ulCRT2LCDType */
1078 case LCD_UNKNOWN: /* unknown lcd, do nothing */
1081 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1085 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1086 struct vb_device_info *pVBInfo)
1088 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1091 if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1092 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1094 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1096 /* Enable GPIOA/B read */
1097 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1098 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1099 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1100 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1101 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1102 /* Enable read GPIOF */
1103 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1104 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1105 Temp = 0xA0; /* Only DVO on chip */
1107 Temp = 0x80; /* TMDS on chip */
1108 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1109 /* Disable read GPIOF */
1110 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1115 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1117 unsigned char Temp, bCR4A;
1119 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1120 /* Enable GPIOA/B/C read */
1121 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1122 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1123 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1127 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1128 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1130 /* TMDS/DVO setting */
1131 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1133 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1136 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1138 unsigned char CR38, CR4A, temp;
1140 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1141 /* enable GPIOE read */
1142 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1143 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1145 if ((CR38 & 0xE0) > 0x80) {
1146 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1151 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1156 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1158 unsigned char CR4A, temp;
1160 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1161 /* enable GPIOA/B/C read */
1162 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1163 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1165 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1167 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1172 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1176 flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1177 return flag == 1 || flag == 2;
1180 unsigned char XGIInitNew(struct pci_dev *pdev)
1182 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1183 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1184 struct vb_device_info VBINF;
1185 struct vb_device_info *pVBInfo = &VBINF;
1186 unsigned char i, temp = 0, temp1;
1188 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1190 if (!pVBInfo->FBAddr) {
1191 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1195 XGIRegInit(pVBInfo, xgifb_info->vga_base);
1197 outb(0x67, pVBInfo->P3c2);
1199 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1202 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1204 /* GetXG21Sense (GPIO) */
1205 if (HwDeviceExtension->jChipType == XG21)
1206 XGINew_GetXG21Sense(pdev, pVBInfo);
1208 if (HwDeviceExtension->jChipType == XG27)
1209 XGINew_GetXG27Sense(pVBInfo);
1211 /* Reset Extended register */
1213 for (i = 0x06; i < 0x20; i++)
1214 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1216 for (i = 0x21; i <= 0x27; i++)
1217 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1219 for (i = 0x31; i <= 0x3B; i++)
1220 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1222 /* Auto over driver for XG42 */
1223 if (HwDeviceExtension->jChipType == XG42)
1224 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1226 for (i = 0x79; i <= 0x7C; i++)
1227 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1229 if (HwDeviceExtension->jChipType >= XG20)
1230 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1232 /* SetDefExt1Regs begin */
1233 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1234 if (HwDeviceExtension->jChipType == XG27) {
1235 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1236 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1238 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1239 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1240 /* Frame buffer can read/write SR20 */
1241 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1242 /* H/W request for slow corner chip */
1243 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1244 if (HwDeviceExtension->jChipType == XG27)
1245 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1247 if (HwDeviceExtension->jChipType < XG20) {
1250 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1251 for (i = 0x47; i <= 0x4C; i++)
1252 xgifb_reg_set(pVBInfo->P3d4,
1254 XGI340_AGPReg[i - 0x47]);
1256 for (i = 0x70; i <= 0x71; i++)
1257 xgifb_reg_set(pVBInfo->P3d4,
1259 XGI340_AGPReg[6 + i - 0x70]);
1261 for (i = 0x74; i <= 0x77; i++)
1262 xgifb_reg_set(pVBInfo->P3d4,
1264 XGI340_AGPReg[8 + i - 0x74]);
1266 pci_read_config_dword(pdev, 0x50, &Temp);
1271 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1275 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1276 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1277 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1279 if (HwDeviceExtension->jChipType < XG20) {
1281 XGI_UnLockCRT2(pVBInfo);
1282 /* disable VideoCapture */
1283 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1284 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1285 /* chk if BCLK>=100MHz */
1286 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1288 xgifb_reg_set(pVBInfo->Part1Port,
1289 0x02, XGI330_CRT2Data_1_2);
1291 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1294 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1296 if ((HwDeviceExtension->jChipType == XG42) &&
1297 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1299 xgifb_reg_set(pVBInfo->P3c4,
1301 (XGI330_SR31 & 0x3F) | 0x40);
1302 xgifb_reg_set(pVBInfo->P3c4,
1304 (XGI330_SR32 & 0xFC) | 0x01);
1306 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1307 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1309 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1311 if (HwDeviceExtension->jChipType < XG20) {
1312 if (xgifb_bridge_is_on(pVBInfo)) {
1313 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1314 xgifb_reg_set(pVBInfo->Part4Port,
1315 0x0D, XGI330_CRT2Data_4_D);
1316 xgifb_reg_set(pVBInfo->Part4Port,
1317 0x0E, XGI330_CRT2Data_4_E);
1318 xgifb_reg_set(pVBInfo->Part4Port,
1319 0x10, XGI330_CRT2Data_4_10);
1320 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1321 XGI_LockCRT2(pVBInfo);
1325 XGI_SenseCRT1(pVBInfo);
1327 if (HwDeviceExtension->jChipType == XG21) {
1328 xgifb_reg_and_or(pVBInfo->P3d4,
1331 Monitor1Sense); /* Z9 default has CRT */
1332 temp = GetXG21FPBits(pVBInfo);
1333 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1335 if (HwDeviceExtension->jChipType == XG27) {
1336 xgifb_reg_and_or(pVBInfo->P3d4,
1339 Monitor1Sense); /* Z9 default has CRT */
1340 temp = GetXG27FPBits(pVBInfo);
1341 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1344 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1346 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1350 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1352 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1353 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1355 XGINew_ChkSenseStatus(pVBInfo);
1356 XGINew_SetModeScratch(pVBInfo);
1358 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);