3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/delay.h> /* udelay */
11 #include "vb_setmode.h"
18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
20 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
21 { 2, 13, 9, 64, 0x45},
22 { 2, 12, 9, 32, 0x35},
23 { 2, 12, 8, 16, 0x31},
24 { 2, 11, 8, 8, 0x21} };
26 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
27 { 2, 14, 11, 128, 0x5D},
28 { 2, 14, 10, 64, 0x59},
29 { 2, 13, 11, 64, 0x4D},
30 { 2, 14, 9, 32, 0x55},
31 { 2, 13, 10, 32, 0x49},
32 { 2, 12, 11, 32, 0x3D},
33 { 2, 14, 8, 16, 0x51},
34 { 2, 13, 9, 16, 0x45},
35 { 2, 12, 10, 16, 0x39},
38 { 2, 12, 8, 4, 0x31} };
40 static int XGINew_RAMType;
42 static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
43 struct vb_device_info *pVBInfo)
45 unsigned char data, temp;
47 if (HwDeviceExtension->jChipType < XG20) {
48 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
49 data = *pVBInfo->pSoftSetting & 0x07;
52 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39) & 0x02;
55 data = (XGINew_GetReg1(pVBInfo->P3c4, 0x3A) & 0x02) >> 1;
59 } else if (HwDeviceExtension->jChipType == XG27) {
60 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
61 data = *pVBInfo->pSoftSetting & 0x07;
64 temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
66 if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
71 } else if (HwDeviceExtension->jChipType == XG21) {
72 XGINew_SetRegAND(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
74 XGINew_SetRegOR(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
75 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
77 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */
78 if (temp & 0x01) /* DVI read GPIOH */
82 /* ~HOTPLUG_SUPPORT */
83 XGINew_SetRegOR(pVBInfo->P3d4, 0xB4, 0x02);
86 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97) & 0x01;
95 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
97 XGINew_SetReg1(P3c4, 0x18, 0x01);
98 XGINew_SetReg1(P3c4, 0x19, 0x20);
99 XGINew_SetReg1(P3c4, 0x16, 0x00);
100 XGINew_SetReg1(P3c4, 0x16, 0x80);
102 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
104 XGINew_SetReg1(P3c4, 0x18, 0x00);
105 XGINew_SetReg1(P3c4, 0x19, 0x20);
106 XGINew_SetReg1(P3c4, 0x16, 0x00);
107 XGINew_SetReg1(P3c4, 0x16, 0x80);
111 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
112 XGINew_SetReg1(P3c4, 0x19, 0x01);
113 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[0]);
114 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[1]);
116 XGINew_SetReg1(P3c4, 0x1B, 0x03);
118 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
119 XGINew_SetReg1(P3c4, 0x19, 0x00);
120 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[2]);
121 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[3]);
122 XGINew_SetReg1(P3c4, 0x1B, 0x00);
125 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
126 struct vb_device_info *pVBInfo)
129 XGINew_SetReg1(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
130 XGINew_SetReg1(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
131 XGINew_SetReg1(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
133 XGINew_SetReg1(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
134 XGINew_SetReg1(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
135 XGINew_SetReg1(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
137 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
138 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
139 if (HwDeviceExtension->jChipType == XG42) {
140 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
141 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
142 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
143 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
144 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
145 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
146 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
150 static void XGINew_DDRII_Bootup_XG27(
151 struct xgi_hw_device_info *HwDeviceExtension,
152 unsigned long P3c4, struct vb_device_info *pVBInfo)
154 unsigned long P3d4 = P3c4 + 0x10;
155 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
156 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
158 /* Set Double Frequency */
159 /* XGINew_SetReg1(P3d4, 0x97, 0x11); *//* CR97 */
160 XGINew_SetReg1(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
164 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
165 XGINew_SetReg1(P3c4, 0x19, 0x80); /* Set SR19 */
166 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
168 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
171 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
172 XGINew_SetReg1(P3c4, 0x19, 0xC0); /* Set SR19 */
173 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
175 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
178 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
179 XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
180 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
182 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
185 XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
186 XGINew_SetReg1(P3c4, 0x19, 0x0A); /* Set SR19 */
187 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
189 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
190 XGINew_SetReg1(P3c4, 0x16, 0x80); /* Set SR16 */
193 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B */
195 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* Set SR1B */
197 XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
198 XGINew_SetReg1(P3c4, 0x19, 0x08); /* Set SR19 */
199 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
202 XGINew_SetReg1(P3c4, 0x16, 0x83); /* Set SR16 */
205 XGINew_SetReg1(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
206 XGINew_SetReg1(P3c4, 0x19, 0x46); /* Set SR19 */
207 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
209 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
212 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
213 XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
214 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
216 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
219 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
224 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
225 unsigned long P3c4, struct vb_device_info *pVBInfo)
227 unsigned long P3d4 = P3c4 + 0x10;
229 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
230 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
232 XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
235 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
236 XGINew_SetReg1(P3c4, 0x19, 0x80);
237 XGINew_SetReg1(P3c4, 0x16, 0x05);
238 XGINew_SetReg1(P3c4, 0x16, 0x85);
240 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS3 */
241 XGINew_SetReg1(P3c4, 0x19, 0xC0);
242 XGINew_SetReg1(P3c4, 0x16, 0x05);
243 XGINew_SetReg1(P3c4, 0x16, 0x85);
245 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS1 */
246 XGINew_SetReg1(P3c4, 0x19, 0x40);
247 XGINew_SetReg1(P3c4, 0x16, 0x05);
248 XGINew_SetReg1(P3c4, 0x16, 0x85);
250 /* XGINew_SetReg1(P3c4, 0x18, 0x52); */ /* MRS1 */
251 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
252 XGINew_SetReg1(P3c4, 0x19, 0x02);
253 XGINew_SetReg1(P3c4, 0x16, 0x05);
254 XGINew_SetReg1(P3c4, 0x16, 0x85);
257 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
259 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
262 /* XGINew_SetReg1(P3c4 ,0x18, 0x52); */ /* MRS2 */
263 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
264 XGINew_SetReg1(P3c4, 0x19, 0x00);
265 XGINew_SetReg1(P3c4, 0x16, 0x05);
266 XGINew_SetReg1(P3c4, 0x16, 0x85);
271 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
274 XGINew_SetReg1(P3c4, 0x18, 0x01);
275 XGINew_SetReg1(P3c4, 0x19, 0x40);
276 XGINew_SetReg1(P3c4, 0x16, 0x00);
277 XGINew_SetReg1(P3c4, 0x16, 0x80);
280 XGINew_SetReg1(P3c4, 0x18, 0x00);
281 XGINew_SetReg1(P3c4, 0x19, 0x40);
282 XGINew_SetReg1(P3c4, 0x16, 0x00);
283 XGINew_SetReg1(P3c4, 0x16, 0x80);
285 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
286 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
287 XGINew_SetReg1(P3c4, 0x19, 0x01);
288 XGINew_SetReg1(P3c4, 0x16, 0x03);
289 XGINew_SetReg1(P3c4, 0x16, 0x83);
291 XGINew_SetReg1(P3c4, 0x1B, 0x03);
293 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
294 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
295 XGINew_SetReg1(P3c4, 0x19, 0x00);
296 XGINew_SetReg1(P3c4, 0x16, 0x03);
297 XGINew_SetReg1(P3c4, 0x16, 0x83);
298 XGINew_SetReg1(P3c4, 0x1B, 0x00);
301 static void XGINew_DDR1x_DefaultRegister(
302 struct xgi_hw_device_info *HwDeviceExtension,
303 unsigned long Port, struct vb_device_info *pVBInfo)
305 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
307 if (HwDeviceExtension->jChipType >= XG20) {
308 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
309 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
310 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
311 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
313 XGINew_SetReg1(P3d4, 0x98, 0x01);
314 XGINew_SetReg1(P3d4, 0x9A, 0x02);
316 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
318 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
320 switch (HwDeviceExtension->jChipType) {
323 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
324 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
325 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
328 XGINew_SetReg1(P3d4, 0x82, 0x88);
329 XGINew_SetReg1(P3d4, 0x86, 0x00);
330 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
331 XGINew_SetReg1(P3d4, 0x86, 0x88);
332 XGINew_GetReg1(P3d4, 0x86);
333 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
334 XGINew_SetReg1(P3d4, 0x82, 0x77);
335 XGINew_SetReg1(P3d4, 0x85, 0x00);
336 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
337 XGINew_SetReg1(P3d4, 0x85, 0x88);
338 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
339 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
340 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
344 XGINew_SetReg1(P3d4, 0x97, 0x00);
345 XGINew_SetReg1(P3d4, 0x98, 0x01);
346 XGINew_SetReg1(P3d4, 0x9A, 0x02);
347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
351 static void XGINew_DDR2_DefaultRegister(
352 struct xgi_hw_device_info *HwDeviceExtension,
353 unsigned long Port, struct vb_device_info *pVBInfo)
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
357 /* keep following setting sequence, each setting in the same reg insert idle */
358 XGINew_SetReg1(P3d4, 0x82, 0x77);
359 XGINew_SetReg1(P3d4, 0x86, 0x00);
360 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
361 XGINew_SetReg1(P3d4, 0x86, 0x88);
362 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
363 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
364 XGINew_SetReg1(P3d4, 0x82, 0x77);
365 XGINew_SetReg1(P3d4, 0x85, 0x00);
366 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
367 XGINew_SetReg1(P3d4, 0x85, 0x88);
368 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
369 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
370 if (HwDeviceExtension->jChipType == XG27)
371 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
373 XGINew_SetReg1(P3d4, 0x82, 0xA8); /* CR82 */
375 XGINew_SetReg1(P3d4, 0x98, 0x01);
376 XGINew_SetReg1(P3d4, 0x9A, 0x02);
377 if (HwDeviceExtension->jChipType == XG27)
378 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
380 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
383 static void XGINew_SetDRAMDefaultRegister340(
384 struct xgi_hw_device_info *HwDeviceExtension,
385 unsigned long Port, struct vb_device_info *pVBInfo)
387 unsigned char temp, temp1, temp2, temp3, i, j, k;
389 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
391 XGINew_SetReg1(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
392 XGINew_SetReg1(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
393 XGINew_SetReg1(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
394 XGINew_SetReg1(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
397 for (i = 0; i < 4; i++) {
398 temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */
399 for (j = 0; j < 4; j++) {
400 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
402 XGINew_SetReg1(P3d4, 0x6B, temp2);
403 XGINew_GetReg1(P3d4, 0x6B); /* Insert read command for delay */
410 for (i = 0; i < 4; i++) {
411 temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */
412 for (j = 0; j < 4; j++) {
413 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
415 XGINew_SetReg1(P3d4, 0x6E, temp2);
416 XGINew_GetReg1(P3d4, 0x6E); /* Insert read command for delay */
423 for (k = 0; k < 4; k++) {
424 XGINew_SetRegANDOR(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */
426 for (i = 0; i < 8; i++) {
427 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */
428 for (j = 0; j < 4; j++) {
429 temp1 = (temp >> (2 * j)) & 0x03;
431 XGINew_SetReg1(P3d4, 0x6F, temp2);
432 XGINew_GetReg1(P3d4, 0x6F); /* Insert read command for delay */
440 XGINew_SetReg1(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
441 XGINew_SetReg1(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
444 temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */
445 for (j = 0; j < 4; j++) {
446 temp1 = (temp >> (2 * j)) & 0x03;
448 XGINew_SetReg1(P3d4, 0x89, temp2);
449 XGINew_GetReg1(P3d4, 0x89); /* Insert read command for delay */
454 temp = pVBInfo->CR89[XGINew_RAMType][1];
457 XGINew_SetReg1(P3d4, 0x89, temp2);
459 temp = pVBInfo->CR40[3][XGINew_RAMType];
461 temp2 = (temp >> 4) & 0x07;
463 XGINew_SetReg1(P3d4, 0x45, temp1); /* CR45 */
464 XGINew_SetReg1(P3d4, 0x99, temp2); /* CR99 */
465 XGINew_SetRegOR(P3d4, 0x40, temp3); /* CR40_D[7] */
466 XGINew_SetReg1(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
468 if (HwDeviceExtension->jChipType == XG27)
469 XGINew_SetReg1(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
471 for (j = 0; j <= 6; j++)
472 XGINew_SetReg1(P3d4, (0x90 + j),
473 pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */
475 for (j = 0; j <= 2; j++)
476 XGINew_SetReg1(P3d4, (0xC3 + j),
477 pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */
479 for (j = 0; j < 2; j++)
480 XGINew_SetReg1(P3d4, (0x8A + j),
481 pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */
483 if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42))
484 XGINew_SetReg1(P3d4, 0x8C, 0x87);
486 XGINew_SetReg1(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
488 XGINew_SetReg1(P3d4, 0x83, 0x09); /* CR83 */
489 XGINew_SetReg1(P3d4, 0x87, 0x00); /* CR87 */
490 XGINew_SetReg1(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
491 if (XGINew_RAMType) {
492 /* XGINew_SetReg1(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
493 XGINew_SetReg1(P3c4, 0x17, 0x80); /* SR17 DDRII */
494 if (HwDeviceExtension->jChipType == XG27)
495 XGINew_SetReg1(P3c4, 0x17, 0x02); /* SR17 DDRII */
498 XGINew_SetReg1(P3c4, 0x17, 0x00); /* SR17 DDR */
500 XGINew_SetReg1(P3c4, 0x1A, 0x87); /* SR1A */
502 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
504 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
506 XGINew_SetReg1(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
507 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
509 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
512 static void XGINew_SetDRAMSizingType(int index,
513 unsigned short DRAMTYPE_TABLE[][5],
514 struct vb_device_info *pVBInfo)
518 data = DRAMTYPE_TABLE[index][4];
519 XGINew_SetRegANDOR(pVBInfo->P3c4, 0x13, 0x80, data);
521 /* should delay 50 ns */
524 static unsigned short XGINew_SetDRAMSizeReg(int index,
525 unsigned short DRAMTYPE_TABLE[][5],
526 struct vb_device_info *pVBInfo)
528 unsigned short data = 0, memsize = 0;
530 unsigned char ChannelNo;
532 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
533 data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
541 if (XGINew_ChannelAB == 3)
544 ChannelNo = XGINew_ChannelAB;
546 if (ChannelNo * RankSize <= 256) {
547 while ((RankSize >>= 1) > 0)
552 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
553 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
555 /* data |= XGINew_ChannelAB << 2; */
556 /* data |= (XGINew_DataBusWidth / 64) << 1; */
557 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
560 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
565 static unsigned short XGINew_SetDRAMSize20Reg(int index,
566 unsigned short DRAMTYPE_TABLE[][5],
567 struct vb_device_info *pVBInfo)
569 unsigned short data = 0, memsize = 0;
571 unsigned char ChannelNo;
573 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
574 data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
582 if (XGINew_ChannelAB == 3)
585 ChannelNo = XGINew_ChannelAB;
587 if (ChannelNo * RankSize <= 256) {
588 while ((RankSize >>= 1) > 0)
593 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
594 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
597 /* data |= XGINew_ChannelAB << 2; */
598 /* data |= (XGINew_DataBusWidth / 64) << 1; */
599 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
602 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
607 static int XGINew_ReadWriteRest(unsigned short StopAddr,
608 unsigned short StartAddr, struct vb_device_info *pVBInfo)
611 unsigned long Position = 0;
613 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
615 for (i = StartAddr; i <= StopAddr; i++) {
617 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
620 udelay(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
624 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
627 for (i = StartAddr; i <= StopAddr; i++) {
629 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
635 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
639 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
641 if ((data & 0x10) == 0) {
642 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39);
643 data = (data & 0x02) >> 1;
650 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
651 struct vb_device_info *pVBInfo)
655 switch (HwDeviceExtension->jChipType) {
658 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
660 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
662 if (data == 0) { /* Single_32_16 */
664 if ((HwDeviceExtension->ulVideoMemorySize - 1)
667 XGINew_DataBusWidth = 32; /* 32 bits */
668 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
669 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
672 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
675 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
676 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
677 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
680 if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
685 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
686 XGINew_DataBusWidth = 16; /* 16 bits */
687 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
688 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41);
691 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
694 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31);
698 } else { /* Dual_16_8 */
699 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
701 XGINew_DataBusWidth = 16; /* 16 bits */
702 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
703 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
706 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
709 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
710 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
711 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
714 if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
719 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
720 XGINew_DataBusWidth = 8; /* 8 bits */
721 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
722 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
725 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
728 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
735 XGINew_DataBusWidth = 16; /* 16 bits */
736 XGINew_ChannelAB = 1; /* Single channel */
737 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
740 if (XGINew_CheckFrequence(pVBInfo) == 1) {
741 XGINew_DataBusWidth = 32; /* 32 bits */
742 XGINew_ChannelAB = 3; /* Quad Channel */
743 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
744 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
746 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
749 XGINew_ChannelAB = 2; /* Dual channels */
750 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
752 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
755 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x49);
757 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
760 XGINew_ChannelAB = 3;
761 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
762 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
764 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
767 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
769 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
772 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x39);
774 XGINew_DataBusWidth = 64; /* 64 bits */
775 XGINew_ChannelAB = 2; /* Dual channels */
776 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
777 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
779 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
782 XGINew_ChannelAB = 1; /* Single channels */
783 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
785 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
788 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x53);
790 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
793 XGINew_ChannelAB = 2; /* Dual channels */
794 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
795 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
797 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
800 XGINew_ChannelAB = 1; /* Single channels */
801 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
803 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
806 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x43);
813 XG42 SR14 D[3] Reserve
814 D[2] = 1, Dual Channel
817 It's Different from Other XG40 Series.
819 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
820 XGINew_DataBusWidth = 32; /* 32 bits */
821 XGINew_ChannelAB = 2; /* 2 Channel */
822 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
823 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x44);
825 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
828 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
829 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x34);
830 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
833 XGINew_ChannelAB = 1; /* Single Channel */
834 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
835 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x40);
837 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
840 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
841 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30);
844 XGINew_DataBusWidth = 64; /* 64 bits */
845 XGINew_ChannelAB = 1; /* 1 channels */
846 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
847 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
849 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
852 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
853 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
861 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
862 XGINew_DataBusWidth = 32; /* 32 bits */
863 XGINew_ChannelAB = 3;
864 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
865 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
867 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
870 XGINew_ChannelAB = 2; /* 2 channels */
871 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
873 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
876 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
877 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
879 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
880 XGINew_ChannelAB = 3; /* 4 channels */
882 XGINew_ChannelAB = 2; /* 2 channels */
883 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
886 XGINew_DataBusWidth = 64; /* 64 bits */
887 XGINew_ChannelAB = 2; /* 2 channels */
888 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
889 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
891 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
894 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
895 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
902 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
903 struct vb_device_info *pVBInfo)
906 unsigned short memsize, addr;
908 XGINew_SetReg1(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
909 XGINew_SetReg1(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
910 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
912 if (HwDeviceExtension->jChipType >= XG20) {
913 for (i = 0; i < 12; i++) {
914 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
915 memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
919 addr = memsize + (XGINew_ChannelAB - 2) + 20;
920 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
923 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
927 for (i = 0; i < 4; i++) {
928 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
929 memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
934 addr = memsize + (XGINew_ChannelAB - 2) + 20;
935 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
938 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
945 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
946 struct vb_device_info *pVBInfo)
950 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
951 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
953 XGISetModeNew(HwDeviceExtension, 0x2e);
955 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
956 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
957 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
959 /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x1); */
961 /* XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
962 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
963 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
964 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
967 static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
969 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
972 /* Volari customize data area end */
974 if (ChipType == XG21) {
975 pVBInfo->IF_DEF_LVDS = 0;
976 if (pVideoMemory[0x65] & 0x1) {
977 pVBInfo->IF_DEF_LVDS = 1;
978 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
979 j = pVideoMemory[i - 1];
983 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
984 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
985 pVBInfo->XG21_LVDSCapList[k].LVDSHT
986 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
987 pVBInfo->XG21_LVDSCapList[k].LVDSVT
988 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
989 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
990 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
991 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
992 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
993 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
994 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
995 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
996 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
997 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
998 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
999 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1000 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1001 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1002 = pVideoMemory[i + 18];
1003 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1004 = pVideoMemory[i + 19];
1005 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1006 = pVideoMemory[i + 20];
1007 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1008 = pVideoMemory[i + 21];
1009 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1010 = pVideoMemory[i + 22];
1011 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1012 = pVideoMemory[i + 23];
1013 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1014 = pVideoMemory[i + 24];
1018 } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct))));
1020 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1021 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
1022 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1023 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
1024 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1025 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
1026 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1027 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
1028 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1029 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
1030 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1031 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
1032 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1033 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
1034 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1035 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
1036 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1037 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1038 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1039 = pVideoMemory[i + 18];
1040 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1041 = pVideoMemory[i + 19];
1042 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1043 = pVideoMemory[i + 20];
1044 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1045 = pVideoMemory[i + 21];
1046 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1047 = pVideoMemory[i + 22];
1048 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1049 = pVideoMemory[i + 23];
1050 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1051 = pVideoMemory[i + 24];
1057 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1058 struct vb_device_info *pVBInfo)
1060 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1062 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x32);
1064 if (temp & Monitor1Sense)
1065 tempbx |= ActiveCRT1;
1066 if (temp & LCDSense)
1067 tempbx |= ActiveLCD;
1068 if (temp & Monitor2Sense)
1069 tempbx |= ActiveCRT2;
1070 if (temp & TVSense) {
1072 if (temp & AVIDEOSense)
1073 tempbx |= (ActiveAVideo << 8);
1074 if (temp & SVIDEOSense)
1075 tempbx |= (ActiveSVideo << 8);
1076 if (temp & SCARTSense)
1077 tempbx |= (ActiveSCART << 8);
1078 if (temp & HiTVSense)
1079 tempbx |= (ActiveHiTV << 8);
1080 if (temp & YPbPrSense)
1081 tempbx |= (ActiveYPbPr << 8);
1084 tempcx = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
1085 tempcx |= (XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8);
1087 if (tempbx & tempcx) {
1088 CR3CData = XGINew_GetReg1(pVBInfo->P3d4, 0x3c);
1089 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1091 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1096 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1101 XGINew_SetReg1(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1102 XGINew_SetReg1(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1105 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1106 struct vb_device_info *pVBInfo)
1108 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1110 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
1111 temp |= XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8;
1112 temp |= (XGINew_GetReg1(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1114 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1115 if (temp & ActiveCRT2)
1116 tempcl = SetCRT2ToRAMDAC;
1119 if (temp & ActiveLCD) {
1120 tempcl |= SetCRT2ToLCD;
1121 if (temp & DriverMode) {
1122 if (temp & ActiveTV) {
1123 tempch = SetToLCDA | EnableDualEdge;
1124 temp ^= SetCRT2ToLCD;
1126 if ((temp >> 8) & ActiveAVideo)
1127 tempcl |= SetCRT2ToAVIDEO;
1128 if ((temp >> 8) & ActiveSVideo)
1129 tempcl |= SetCRT2ToSVIDEO;
1130 if ((temp >> 8) & ActiveSCART)
1131 tempcl |= SetCRT2ToSCART;
1133 if (pVBInfo->IF_DEF_HiVision == 1) {
1134 if ((temp >> 8) & ActiveHiTV)
1135 tempcl |= SetCRT2ToHiVisionTV;
1138 if (pVBInfo->IF_DEF_YPbPr == 1) {
1139 if ((temp >> 8) & ActiveYPbPr)
1145 if ((temp >> 8) & ActiveAVideo)
1146 tempcl |= SetCRT2ToAVIDEO;
1147 if ((temp >> 8) & ActiveSVideo)
1148 tempcl |= SetCRT2ToSVIDEO;
1149 if ((temp >> 8) & ActiveSCART)
1150 tempcl |= SetCRT2ToSCART;
1152 if (pVBInfo->IF_DEF_HiVision == 1) {
1153 if ((temp >> 8) & ActiveHiTV)
1154 tempcl |= SetCRT2ToHiVisionTV;
1157 if (pVBInfo->IF_DEF_YPbPr == 1) {
1158 if ((temp >> 8) & ActiveYPbPr)
1163 tempcl |= SetSimuScanMode;
1164 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1165 || (temp & ActiveCRT2)))
1166 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1167 if ((temp & ActiveLCD) && (temp & ActiveTV))
1168 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1169 XGINew_SetReg1(pVBInfo->P3d4, 0x30, tempcl);
1171 CR31Data = XGINew_GetReg1(pVBInfo->P3d4, 0x31);
1172 CR31Data &= ~(SetNotSimuMode >> 8);
1173 if (!(temp & ActiveCRT1))
1174 CR31Data |= (SetNotSimuMode >> 8);
1175 CR31Data &= ~(DisableCRT2Display >> 8);
1176 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1177 CR31Data |= (DisableCRT2Display >> 8);
1178 XGINew_SetReg1(pVBInfo->P3d4, 0x31, CR31Data);
1180 CR38Data = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
1181 CR38Data &= ~SetYPbPr;
1183 XGINew_SetReg1(pVBInfo->P3d4, 0x38, CR38Data);
1187 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1188 struct vb_device_info *pVBInfo)
1191 volatile unsigned char *pVideoMemory =
1192 (unsigned char *) pVBInfo->ROMAddr;
1194 pVBInfo->IF_DEF_LVDS = 0;
1197 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1198 pVBInfo->IF_DEF_LVDS = 1;
1199 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1200 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */
1203 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read */
1204 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0xC0;
1205 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1206 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1207 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1208 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */
1209 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x04;
1211 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */
1213 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */
1214 XGINew_SetRegAND(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */
1221 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1222 struct vb_device_info *pVBInfo)
1224 unsigned char Temp, bCR4A;
1226 pVBInfo->IF_DEF_LVDS = 0;
1227 bCR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1228 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read */
1229 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x07;
1230 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, bCR4A);
1233 pVBInfo->IF_DEF_LVDS = 1;
1234 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */
1235 XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x21);
1237 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */
1239 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1243 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1245 unsigned char CR38, CR4A, temp;
1247 CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1248 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */
1249 CR38 = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
1251 if ((CR38 & 0xE0) > 0x80) {
1252 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
1257 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
1262 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1264 unsigned char CR4A, temp;
1266 CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1267 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */
1268 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
1272 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1274 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
1279 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1281 struct vb_device_info VBINF;
1282 struct vb_device_info *pVBInfo = &VBINF;
1283 unsigned char i, temp = 0, temp1;
1284 /* VBIOSVersion[5]; */
1285 volatile unsigned char *pVideoMemory;
1287 /* unsigned long j, k; */
1291 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1293 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1295 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1297 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1299 /* Newdebugcode(0x99); */
1302 /* if (pVBInfo->ROMAddr == 0) */
1305 if (pVBInfo->FBAddr == NULL) {
1306 printk("\n pVBInfo->FBAddr == 0 ");
1310 if (pVBInfo->BaseAddr == 0) {
1311 printk("\npVBInfo->BaseAddr == 0 ");
1316 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1318 pVBInfo->ISXPDOS = 0;
1323 /* VBIOSVersion[4] = 0x0; */
1325 /* 09/07/99 modify by domao */
1327 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1328 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1329 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1330 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1331 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1332 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1333 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1334 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1335 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1336 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1337 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1338 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1339 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1340 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1341 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1342 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1343 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1346 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1347 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
1349 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1352 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1355 XGINew_SetReg1(pVBInfo->P3c4, 0x05, 0x86);
1358 /* GetXG21Sense (GPIO) */
1359 if (HwDeviceExtension->jChipType == XG21)
1360 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1362 if (HwDeviceExtension->jChipType == XG27)
1363 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1367 /* 2.Reset Extended register */
1369 for (i = 0x06; i < 0x20; i++)
1370 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1372 for (i = 0x21; i <= 0x27; i++)
1373 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1375 /* for(i = 0x06; i <= 0x27; i++) */
1376 /* XGINew_SetReg1(pVBInfo->P3c4, i, 0); */
1380 for (i = 0x31; i <= 0x3B; i++)
1381 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1384 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1385 XGINew_SetReg1(pVBInfo->P3c4, 0x3B, 0xC0);
1387 /* for (i = 0x30; i <= 0x3F; i++) */
1388 /* XGINew_SetReg1(pVBInfo->P3d4, i, 0); */
1390 for (i = 0x79; i <= 0x7C; i++)
1391 XGINew_SetReg1(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1395 if (HwDeviceExtension->jChipType >= XG20)
1396 XGINew_SetReg1(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1400 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1405 /* 4.SetDefExt1Regs begin */
1406 XGINew_SetReg1(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1407 if (HwDeviceExtension->jChipType == XG27) {
1408 XGINew_SetReg1(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1409 XGINew_SetReg1(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1411 XGINew_SetReg1(pVBInfo->P3c4, 0x11, 0x0F);
1412 XGINew_SetReg1(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1413 /* XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0x20); */
1414 XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1415 XGINew_SetReg1(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1416 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1417 XGINew_SetReg1(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1420 /* XGINew_SetReg1(pVBInfo->P3c4, 0x11, SR11); */
1424 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1427 temp1 = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
1429 if (temp1 == 0x02) {
1430 XGINew_SetReg4(0xcf8, 0x80000000);
1431 ChipsetID = inl(0x0cfc);
1432 XGINew_SetReg4(0xcf8, 0x8000002C);
1433 VendorID = inl(0x0cfc);
1434 VendorID &= 0x0000FFFF;
1435 XGINew_SetReg4(0xcf8, 0x8001002C);
1436 GraphicVendorID = inl(0x0cfc);
1437 GraphicVendorID &= 0x0000FFFF;
1439 if (ChipsetID == 0x7301039)
1440 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x09);
1442 ChipsetID &= 0x0000FFFF;
1444 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
1445 if (ChipsetID == 0x1106) {
1446 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
1447 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0D);
1449 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
1451 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
1459 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1460 for (i = 0x47; i <= 0x4C; i++)
1461 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
1463 for (i = 0x70; i <= 0x71; i++)
1464 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
1466 for (i = 0x74; i <= 0x77; i++)
1467 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
1468 /* Set AGP customize registers (in SetDefAGPRegs) End */
1469 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1470 /* XGINew_SetReg4(0xcf8 , 0x80000000); */
1471 /* ChipsetID = inl(0x0cfc); */
1472 /* if (ChipsetID == 0x25308086) */
1473 /* XGINew_SetReg1(pVBInfo->P3d4, 0x77, 0xF0); */
1475 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
1480 XGINew_SetReg1(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1485 XGINew_SetReg1(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1486 XGINew_SetReg1(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1487 XGINew_SetReg1(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1490 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1492 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1493 XGINew_SetRegANDOR(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
1494 XGINew_SetReg1(pVBInfo->Part1Port, 0x00, 0x00);
1495 temp1 = (unsigned char) XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
1496 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1498 XGINew_SetReg1(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
1502 XGINew_SetReg1(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1505 XGINew_SetReg1(pVBInfo->P3c4, 0x27, 0x1F);
1507 if ((HwDeviceExtension->jChipType == XG42)
1508 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
1509 XGINew_SetReg1(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
1510 XGINew_SetReg1(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
1512 XGINew_SetReg1(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1513 XGINew_SetReg1(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1515 XGINew_SetReg1(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1519 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1521 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1522 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1523 if (pVBInfo->IF_DEF_LVDS == 0) {
1524 XGINew_SetReg1(pVBInfo->Part2Port, 0x00, 0x1C);
1525 XGINew_SetReg1(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
1526 XGINew_SetReg1(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
1527 XGINew_SetReg1(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
1528 XGINew_SetReg1(pVBInfo->Part4Port, 0x0F, 0x3F);
1531 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1540 XGI_SenseCRT1(pVBInfo);
1543 /* XGINew_DetectMonitor(HwDeviceExtension); */
1544 pVBInfo->IF_DEF_CH7007 = 0;
1545 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
1547 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
1551 if (HwDeviceExtension->jChipType == XG21) {
1554 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1555 temp = GetXG21FPBits(pVBInfo);
1556 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x01, temp);
1560 if (HwDeviceExtension->jChipType == XG27) {
1561 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1562 temp = GetXG27FPBits(pVBInfo);
1563 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x03, temp);
1567 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1569 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
1572 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1577 /* SetDefExt2Regs begin */
1580 temp = (unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x3A);
1586 *pVBInfo->pSR21 &= 0xEF;
1588 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1590 *pVBInfo->pSR22 &= 0x20;
1591 XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1593 /* base = 0x80000000; */
1594 /* OutPortLong(0xcf8, base); */
1595 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1596 /* if (Temp == 0x1039) { */
1597 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1599 /* XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1602 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1606 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1607 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1611 XGINew_SetReg1(pVBInfo->P3d4, 0x8c, 0x87);
1612 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31);