4 #include <linux/version.h>
5 #include <linux/types.h>
6 #include <linux/delay.h> /* udelay */
10 #include "vb_struct.h"
12 #include "vb_setmode.h"
22 UCHAR XGINew_ChannelAB,XGINew_DataBusWidth;
24 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
25 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44},
26 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40},
27 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32},
28 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30},
29 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28},
30 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24},
31 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10},
32 {0x09,0x08,0x01,0x01,0x00}};
34 USHORT XGINew_SDRDRAM_TYPE[13][5]=
51 USHORT XGINew_DDRDRAM_TYPE[4][5]=
58 USHORT XGINew_DDRDRAM_TYPE340[4][5]=
65 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
81 void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
82 void XGINew_SetDRAMSize_310(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
83 void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO );
84 void XGINew_SetDRAMModeRegister(PVB_DEVICE_INFO );
85 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension );
86 void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG, PVB_DEVICE_INFO );
87 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo);
88 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension) ;
90 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO );
91 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO) ;
92 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO) ;
93 int XGINew_SDRSizing(PVB_DEVICE_INFO);
94 int XGINew_DDRSizing( PVB_DEVICE_INFO );
95 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
96 int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
97 ULONG UNIROM; /* UNIROM */
98 BOOLEAN ChkLFB( PVB_DEVICE_INFO );
99 void XGINew_Delay15us(ULONG);
100 void SetPowerConsume (PXGI_HW_DEVICE_INFO HwDeviceExtension,ULONG XGI_P3d4Port);
101 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo);
102 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo);
103 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension );
104 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension );
105 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
106 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
107 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
108 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo);
109 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
110 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo);
112 void DelayUS(ULONG MicroSeconds)
114 udelay(MicroSeconds);
118 /* --------------------------------------------------------------------- */
119 /* Function : XGIInitNew */
123 /* --------------------------------------------------------------------- */
124 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension )
127 VB_DEVICE_INFO VBINF;
128 PVB_DEVICE_INFO pVBInfo = &VBINF;
129 UCHAR i , temp = 0 , temp1 ;
130 // VBIOSVersion[ 5 ] ;
131 PUCHAR volatile pVideoMemory;
139 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
141 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
143 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
145 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr;
148 // Newdebugcode( 0x99 ) ;
151 /* if ( pVBInfo->ROMAddr == 0 ) */
152 /* return( FALSE ) ; */
154 if ( pVBInfo->FBAddr == 0 )
156 printk("\n pVBInfo->FBAddr == 0 ");
160 if ( pVBInfo->BaseAddr == 0 )
162 printk("\npVBInfo->BaseAddr == 0 ");
167 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
169 pVBInfo->ISXPDOS = 0 ;
172 if ( !HwDeviceExtension->bIntegratedMMEnabled )
174 return( FALSE ) ; /* alan */
178 // XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ;
180 // VBIOSVersion[ 4 ] = 0x0 ;
182 /* 09/07/99 modify by domao */
184 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
185 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
186 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
187 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
188 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
189 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
190 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
191 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
192 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
193 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
194 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
195 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
196 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
197 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
198 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
199 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
200 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
203 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
204 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
206 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
209 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
212 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
215 /* GetXG21Sense (GPIO) */
216 if ( HwDeviceExtension->jChipType == XG21 )
218 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
220 if ( HwDeviceExtension->jChipType == XG27 )
222 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
226 /* 2.Reset Extended register */
228 for( i = 0x06 ; i < 0x20 ; i++ )
229 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
231 for( i = 0x21 ; i <= 0x27 ; i++ )
232 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
234 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
235 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
239 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
241 for( i = 0x31 ; i <= 0x3B ; i++ )
242 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
246 for( i = 0x31 ; i <= 0x3D ; i++ )
247 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
251 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
252 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
254 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
255 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
257 for( i = 0x79 ; i <= 0x7C ; i++ )
258 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
262 if ( HwDeviceExtension->jChipType >= XG20 )
263 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
267 if ( HwDeviceExtension->jChipType >= XG40 )
268 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
270 if ( HwDeviceExtension->jChipType < XG40 )
271 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
275 /* 4.SetDefExt1Regs begin */
276 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
277 if ( HwDeviceExtension->jChipType == XG27 )
279 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
280 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
282 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
283 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
284 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
285 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
286 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
287 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
288 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
291 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
295 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
297 // /* Set AGP Rate */
298 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
300 // if ( temp1 == 0x02 )
302 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
303 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
304 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
305 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
306 // VendorID &= 0x0000FFFF ;
307 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
308 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
309 // GraphicVendorID &= 0x0000FFFF;
311 // if ( ChipsetID == 0x7301039 )
312 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
314 // ChipsetID &= 0x0000FFFF ;
316 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
318 // if ( ChipsetID == 0x1106 )
320 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
321 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
323 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
326 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
332 if ( HwDeviceExtension->jChipType >= XG40 )
334 /* Set AGP customize registers (in SetDefAGPRegs) Start */
335 for( i = 0x47 ; i <= 0x4C ; i++ )
336 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
338 for( i = 0x70 ; i <= 0x71 ; i++ )
339 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
341 for( i = 0x74 ; i <= 0x77 ; i++ )
342 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
343 /* Set AGP customize registers (in SetDefAGPRegs) End */
344 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
345 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
346 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
347 // if ( ChipsetID == 0x25308086 )
348 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
350 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
355 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
359 if ( HwDeviceExtension->jChipType < XG40 )
360 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
364 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
365 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
366 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
369 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
372 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
373 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
374 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
375 temp1 = ( UCHAR )XGINew_GetReg1( pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
376 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ;
379 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
383 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
387 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
389 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
391 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
392 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
396 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
397 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
399 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
403 if ( HwDeviceExtension->jChipType >= XG40 )
404 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
406 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
408 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
410 if ( pVBInfo->IF_DEF_LVDS == 0 )
412 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
413 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
414 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
415 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
416 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
419 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
424 if ( HwDeviceExtension->jChipType < XG40 )
425 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
428 if ( HwDeviceExtension->bSkipSense == FALSE )
432 XGI_SenseCRT1(pVBInfo) ;
435 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
436 pVBInfo->IF_DEF_CH7007 = 0;
437 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
440 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
444 if ( HwDeviceExtension->jChipType == XG21 )
448 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
449 temp = GetXG21FPBits( pVBInfo ) ;
450 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
454 if ( HwDeviceExtension->jChipType == XG27 )
456 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
457 temp = GetXG27FPBits( pVBInfo ) ;
458 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
463 if ( HwDeviceExtension->jChipType >= XG40 )
465 if ( HwDeviceExtension->jChipType >= XG40 )
467 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
470 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
472 if ( HwDeviceExtension->bSkipDramSizing == TRUE )
474 pSR = HwDeviceExtension->pSR ;
477 while( pSR->jIdx != 0xFF )
479 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
483 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
484 } /* SkipDramSizing */
488 if ( HwDeviceExtension->jChipType == XG20 )
490 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
491 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
492 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ;
499 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
509 /* SetDefExt2Regs begin */
512 temp =( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) ;
518 *pVBInfo->pSR21 &= 0xEF ;
520 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
522 *pVBInfo->pSR22 &= 0x20 ;
523 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
526 // base = 0x80000000 ;
527 // OutPortLong( 0xcf8 , base ) ;
528 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
529 // if ( Temp == 0x1039 )
531 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , ( UCHAR )( ( *pVBInfo->pSR22 ) & 0xFE ) ) ;
535 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
538 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
543 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
544 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
549 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
550 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
560 /* ============== alan ====================== */
562 /* --------------------------------------------------------------------- */
563 /* Function : XGINew_GetXG20DRAMType */
567 /* --------------------------------------------------------------------- */
568 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
572 if ( HwDeviceExtension->jChipType < XG20 )
574 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
576 data = *pVBInfo->pSoftSetting & 0x07 ;
581 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
584 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
589 else if ( HwDeviceExtension->jChipType == XG27 )
591 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
593 data = *pVBInfo->pSoftSetting & 0x07 ;
596 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
598 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
604 else if ( HwDeviceExtension->jChipType == XG21 )
606 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
608 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
609 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
611 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
612 if ( temp & 0x01 ) /* DVI read GPIOH */
617 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
622 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
632 /* --------------------------------------------------------------------- */
633 /* Function : XGINew_Get310DRAMType */
637 /* --------------------------------------------------------------------- */
638 UCHAR XGINew_Get310DRAMType(PVB_DEVICE_INFO pVBInfo)
642 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
645 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
646 data = *pVBInfo->pSoftSetting & 0x03 ;
648 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
655 /* --------------------------------------------------------------------- */
656 /* Function : XGINew_Delay15us */
660 /* --------------------------------------------------------------------- */
662 void XGINew_Delay15us(ULONG ulMicrsoSec)
668 /* --------------------------------------------------------------------- */
669 /* Function : XGINew_SDR_MRS */
673 /* --------------------------------------------------------------------- */
674 void XGINew_SDR_MRS( PVB_DEVICE_INFO pVBInfo )
678 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
679 data &= 0x3F ; /* SR16 D7=0,D6=0 */
680 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
681 /* XGINew_Delay15us( 0x100 ) ; */
682 data |= 0x80 ; /* SR16 D7=1,D6=0 */
683 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
684 /* XGINew_Delay15us( 0x100 ) ; */
688 /* --------------------------------------------------------------------- */
689 /* Function : XGINew_DDR1x_MRS_340 */
693 /* --------------------------------------------------------------------- */
694 void XGINew_DDR1x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
696 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
697 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
698 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
699 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
701 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
703 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
704 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
705 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
706 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
707 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
711 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
712 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
713 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
714 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
716 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
718 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
719 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
720 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
721 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
722 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
726 /* --------------------------------------------------------------------- */
727 /* Function : XGINew_DDR2x_MRS_340 */
731 /* --------------------------------------------------------------------- */
732 void XGINew_DDR2x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
734 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
735 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
736 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
737 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
739 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
740 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
741 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
742 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
743 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
745 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
747 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
748 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
749 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
750 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
751 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
752 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
755 /* --------------------------------------------------------------------- */
756 /* Function : XGINew_DDRII_Bootup_XG27 */
760 /* --------------------------------------------------------------------- */
761 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
763 ULONG P3d4 = P3c4 + 0x10 ;
764 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
765 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
767 /* Set Double Frequency */
768 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
769 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
773 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
774 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
775 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
777 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
780 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
781 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
782 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
784 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
787 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
788 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
789 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
791 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
794 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
795 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
796 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
798 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
799 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
800 /* DelayUS( 15 ) ; */
802 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
804 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
806 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
807 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
808 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
811 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
814 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
815 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
816 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
818 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
821 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
822 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
823 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
825 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
828 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
833 /* --------------------------------------------------------------------- */
834 /* Function : XGINew_DDR2_MRS_XG20 */
838 /* --------------------------------------------------------------------- */
839 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
841 ULONG P3d4 = P3c4 + 0x10 ;
843 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
844 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
846 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
849 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
850 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
851 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
852 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
854 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
855 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
856 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
857 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
859 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
860 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
861 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
862 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
864 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
865 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
866 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
867 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
868 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
871 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
873 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
876 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
877 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
878 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
879 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
880 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
885 /* --------------------------------------------------------------------- */
886 /* Function : XGINew_DDR2_MRS_XG20 */
890 /* --------------------------------------------------------------------- */
891 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
893 ULONG P3d4 = P3c4 + 0x10 ;
895 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
896 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
898 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
900 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
901 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
903 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
904 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
905 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
907 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
908 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
910 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
911 DelayUS( 15 ) ; ////06/11/22 XG27 A0
912 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
915 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
916 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
918 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
919 DelayUS( 15 ) ; ////06/11/22 XG27 A0
920 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
922 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
923 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
925 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
926 DelayUS( 15 ) ; ////06/11/23 XG27 A0
927 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
929 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
930 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
932 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
935 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
936 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
938 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
940 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
942 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
943 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
945 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
947 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
949 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
950 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
952 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
954 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
956 DelayUS( 15 ) ; ////Start Auto-PreCharge
957 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
959 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
963 /* --------------------------------------------------------------------- */
964 /* Function : XGINew_DDR1x_DefaultRegister */
968 /* --------------------------------------------------------------------- */
969 void XGINew_DDR1x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
974 if ( HwDeviceExtension->jChipType >= XG20 )
976 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
977 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
978 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
979 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
981 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
982 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
984 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
988 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
990 switch( HwDeviceExtension->jChipType )
994 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
995 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
996 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
999 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1000 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1001 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1002 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1003 XGINew_GetReg1( P3d4 , 0x86 ) ;
1004 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1005 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1006 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1007 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1008 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1009 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1010 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1011 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1015 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1016 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1017 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1018 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1023 /* --------------------------------------------------------------------- */
1024 /* Function : XGINew_DDR2x_DefaultRegister */
1028 /* --------------------------------------------------------------------- */
1029 void XGINew_DDR2x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port ,PVB_DEVICE_INFO pVBInfo)
1032 P3c4 = Port - 0x10 ;
1034 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1036 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1037 switch( HwDeviceExtension->jChipType )
1041 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1042 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1043 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1046 /* keep following setting sequence, each setting in the same reg insert idle */
1047 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1048 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1049 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1050 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1051 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1052 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1053 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1054 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1055 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1056 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1057 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1059 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1060 if ( HwDeviceExtension->jChipType == XG42 )
1062 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1066 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1068 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1070 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1074 /* --------------------------------------------------------------------- */
1075 /* Function : XGINew_DDR2_DefaultRegister */
1079 /* --------------------------------------------------------------------- */
1080 void XGINew_DDR2_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG Port , PVB_DEVICE_INFO pVBInfo)
1083 P3c4 = Port - 0x10 ;
1085 /* keep following setting sequence, each setting in the same reg insert idle */
1086 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1087 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1088 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1089 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1090 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1091 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1092 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1093 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1094 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1095 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1096 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1097 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1098 if ( HwDeviceExtension->jChipType == XG27 )
1099 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1101 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1103 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1104 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1105 if ( HwDeviceExtension->jChipType == XG27 )
1106 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1108 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1112 /* --------------------------------------------------------------------- */
1113 /* Function : XGINew_SetDRAMDefaultRegister340 */
1117 /* --------------------------------------------------------------------- */
1118 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1120 UCHAR temp , temp1 , temp2 , temp3 ,
1124 P3c4 = Port - 0x10 ;
1126 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1127 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1128 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1129 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1132 for( i = 0 ; i < 4 ; i++ )
1134 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1135 for( j = 0 ; j < 4 ; j++ )
1137 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1139 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1140 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1147 for( i = 0 ; i < 4 ; i++ )
1149 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1150 for( j = 0 ; j < 4 ; j++ )
1152 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1154 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1155 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1162 for( k = 0 ; k < 4 ; k++ )
1164 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1166 for( i = 0 ; i < 8 ; i++ )
1168 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1169 for( j = 0 ; j < 4 ; j++ )
1171 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1173 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1174 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1182 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1183 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1186 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1187 for( j = 0 ; j < 4 ; j++ )
1189 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1191 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1192 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1197 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1198 temp1 = temp & 0x03 ;
1200 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1202 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1203 temp1 = temp & 0x0F ;
1204 temp2 = ( temp >> 4 ) & 0x07 ;
1205 temp3 = temp & 0x80 ;
1206 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1207 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1208 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1209 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1211 if ( HwDeviceExtension->jChipType == XG27 )
1212 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1214 for( j = 0 ; j <= 6 ; j++ )
1215 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1217 for( j = 0 ; j <= 2 ; j++ )
1218 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1220 for( j = 0 ; j < 2 ; j++ )
1221 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1223 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1224 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1226 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1228 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1229 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1230 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1231 if ( XGINew_RAMType )
1233 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1234 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1235 if ( HwDeviceExtension->jChipType == XG27 )
1236 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1240 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1241 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1243 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1245 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1248 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1249 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1251 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1255 /* --------------------------------------------------------------------- */
1256 /* Function : XGINew_DDR_MRS */
1260 /* --------------------------------------------------------------------- */
1261 void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo)
1265 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
1267 /* SR16 <- 1F,DF,2F,AF */
1268 /* yriver modified SR16 <- 0F,DF,0F,AF */
1269 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1270 data = pVideoMemory[ 0xFB ] ;
1271 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1274 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1276 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1278 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1280 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1282 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1284 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1286 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1288 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1293 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1295 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1301 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1306 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1307 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1313 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1319 /* check if read cache pointer is correct */
1323 /* --------------------------------------------------------------------- */
1324 /* Function : XGINew_VerifyMclk */
1328 /* --------------------------------------------------------------------- */
1329 void XGINew_VerifyMclk( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1331 PUCHAR pVideoMemory = pVBInfo->FBAddr ;
1333 USHORT Temp , SR21 ;
1335 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1336 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1338 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1340 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1342 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1343 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1344 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1346 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1347 Temp |= 0x01 ; /* MCLK reset */
1350 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1351 Temp &= 0xFE ; /* MCLK normal operation */
1353 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1355 pVideoMemory[ 16 + j ] = j ;
1356 if ( pVideoMemory[ 16 + j ] == j )
1358 pVideoMemory[ j ] = j ;
1369 /* --------------------------------------------------------------------- */
1370 /* Function : XGINew_SetDRAMSize_340 */
1374 /* --------------------------------------------------------------------- */
1375 void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1379 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1380 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1382 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1385 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1386 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1387 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1389 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1391 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1392 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1393 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1394 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1399 /* --------------------------------------------------------------------- */
1404 /* --------------------------------------------------------------------- */
1405 void XGINew_SetDRAMSize_310( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1408 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1409 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1411 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1414 #ifdef XGI302 /* alan,should change value */
1415 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1416 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1417 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1420 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1422 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1423 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1425 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1427 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1429 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1432 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , ( USHORT )( data | 0x0F ) ) ; /* assume lowest speed DRAM */
1434 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1435 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1436 XGINew_CheckBusWidth_310( pVBInfo) ;
1437 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1441 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1443 XGINew_SDRSizing( pVBInfo ) ;
1447 XGINew_DDRSizing( pVBInfo) ;
1453 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , pVBInfo->SR15[ 1 ][ XGINew_RAMType ] ) ; /* restore SR16 */
1455 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1456 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1457 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1462 /* --------------------------------------------------------------------- */
1463 /* Function : XGINew_SetDRAMModeRegister340 */
1467 /* --------------------------------------------------------------------- */
1469 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension )
1472 VB_DEVICE_INFO VBINF;
1473 PVB_DEVICE_INFO pVBInfo = &VBINF;
1474 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1475 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1476 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
1477 pVBInfo->ISXPDOS = 0 ;
1479 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1480 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1481 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1482 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1483 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1484 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1485 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1486 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1487 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1488 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1489 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1490 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1491 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1492 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1493 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1494 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1495 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1496 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1497 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1499 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1501 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1503 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1505 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1507 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1509 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1512 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1514 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1517 /* --------------------------------------------------------------------- */
1518 /* Function : XGINew_SetDRAMModeRegister */
1522 /* --------------------------------------------------------------------- */
1523 void XGINew_SetDRAMModeRegister( PVB_DEVICE_INFO pVBInfo)
1525 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1527 XGINew_SDR_MRS(pVBInfo ) ;
1531 /* SR16 <- 0F,CF,0F,8F */
1532 XGINew_DDR_MRS( pVBInfo ) ;
1537 /* --------------------------------------------------------------------- */
1538 /* Function : XGINew_DisableRefresh */
1542 /* --------------------------------------------------------------------- */
1543 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1548 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1550 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1555 /* --------------------------------------------------------------------- */
1556 /* Function : XGINew_EnableRefresh */
1560 /* --------------------------------------------------------------------- */
1561 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1564 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1570 /* --------------------------------------------------------------------- */
1571 /* Function : XGINew_DisableChannelInterleaving */
1575 /* --------------------------------------------------------------------- */
1576 void XGINew_DisableChannelInterleaving( int index , USHORT XGINew_DDRDRAM_TYPE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1580 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1583 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1600 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1604 /* --------------------------------------------------------------------- */
1605 /* Function : XGINew_SetDRAMSizingType */
1609 /* --------------------------------------------------------------------- */
1610 void XGINew_SetDRAMSizingType( int index , USHORT DRAMTYPE_TABLE[][ 5 ] ,PVB_DEVICE_INFO pVBInfo)
1614 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1615 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1617 /* should delay 50 ns */
1621 /* --------------------------------------------------------------------- */
1622 /* Function : XGINew_CheckBusWidth_310 */
1626 /* --------------------------------------------------------------------- */
1627 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO pVBInfo)
1630 PULONG volatile pVideoMemory ;
1632 pVideoMemory = (PULONG) pVBInfo->FBAddr;
1634 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1636 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1637 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1639 XGINew_SDR_MRS( pVBInfo ) ;
1641 XGINew_ChannelAB = 0 ;
1642 XGINew_DataBusWidth = 128 ;
1643 pVideoMemory[ 0 ] = 0x01234567L ;
1644 pVideoMemory[ 1 ] = 0x456789ABL ;
1645 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1646 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1647 pVideoMemory[ 4 ] = 0x55555555L ;
1648 pVideoMemory[ 5 ] = 0x55555555L ;
1649 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1650 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1652 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1655 XGINew_DataBusWidth = 64 ;
1656 XGINew_ChannelAB = 0 ;
1657 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1658 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( data & 0xFD ) ) ;
1661 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1664 XGINew_DataBusWidth = 64 ;
1665 XGINew_ChannelAB = 1 ;
1666 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1667 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( ( data & 0xFD ) | 0x01 ) ) ;
1674 /* DDR Dual channel */
1675 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1676 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1678 XGINew_DDR_MRS( pVBInfo ) ;
1680 XGINew_ChannelAB = 0 ;
1681 XGINew_DataBusWidth = 64 ;
1682 pVideoMemory[ 0 ] = 0x01234567L ;
1683 pVideoMemory[ 1 ] = 0x456789ABL ;
1684 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1685 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1686 pVideoMemory[ 4 ] = 0x55555555L ;
1687 pVideoMemory[ 5 ] = 0x55555555L ;
1688 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1689 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1691 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1693 if ( pVideoMemory[ 0 ] == 0x01234567L )
1695 /* Channel A 64bit */
1701 if ( pVideoMemory[ 0 ] == 0x01234567L )
1703 /* Channel A 32bit */
1704 XGINew_DataBusWidth = 32 ;
1705 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1710 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1711 XGINew_DDR_MRS( pVBInfo);
1713 XGINew_ChannelAB = 1 ;
1714 XGINew_DataBusWidth = 64 ;
1715 pVideoMemory[ 0 ] = 0x01234567L ;
1716 pVideoMemory[ 1 ] = 0x456789ABL ;
1717 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1718 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1719 pVideoMemory[ 4 ] = 0x55555555L ;
1720 pVideoMemory[ 5 ] = 0x55555555L ;
1721 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1722 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1724 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1727 if ( pVideoMemory[ 0 ] == 0x01234567L )
1729 /* Channel B 64bit */
1739 if ( pVideoMemory[ 0 ] == 0x01234567L )
1742 XGINew_DataBusWidth = 32 ;
1743 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1754 /* --------------------------------------------------------------------- */
1755 /* Function : XGINew_SetRank */
1759 /* --------------------------------------------------------------------- */
1760 int XGINew_SetRank( int index , UCHAR RankNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1765 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1768 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1770 if ( ( RankNo * RankSize ) <= 128 )
1774 while( ( RankSize >>= 1 ) > 0 )
1778 data |= ( RankNo - 1 ) << 2 ;
1779 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1780 data |= XGINew_ChannelAB ;
1781 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1783 XGINew_SDR_MRS( pVBInfo ) ;
1791 /* --------------------------------------------------------------------- */
1792 /* Function : XGINew_SetDDRChannel */
1796 /* --------------------------------------------------------------------- */
1797 int XGINew_SetDDRChannel( int index , UCHAR ChannelNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1802 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1803 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1804 if ( ChannelNo * RankSize <= 128 )
1807 while( ( RankSize >>= 1 ) > 0 )
1812 if ( ChannelNo == 2 )
1815 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1816 data |= XGINew_ChannelAB ;
1817 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1819 XGINew_DDR_MRS( pVBInfo ) ;
1827 /* --------------------------------------------------------------------- */
1828 /* Function : XGINew_CheckColumn */
1832 /* --------------------------------------------------------------------- */
1833 int XGINew_CheckColumn( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1836 ULONG Increment , Position ;
1838 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1839 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1841 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1843 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1844 Position += Increment ;
1848 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1850 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1851 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1853 Position += Increment ;
1859 /* --------------------------------------------------------------------- */
1860 /* Function : XGINew_CheckBanks */
1864 /* --------------------------------------------------------------------- */
1865 int XGINew_CheckBanks( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1868 ULONG Increment , Position ;
1870 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1872 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1874 /* pVBInfo->FBAddr[ Position ] = Position ; */
1875 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1876 Position += Increment ;
1879 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1881 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1882 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1884 Position += Increment ;
1890 /* --------------------------------------------------------------------- */
1891 /* Function : XGINew_CheckRank */
1895 /* --------------------------------------------------------------------- */
1896 int XGINew_CheckRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1899 ULONG Increment , Position ;
1901 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1902 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1904 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1906 /* pVBInfo->FBAddr[ Position ] = Position ; */
1907 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */
1908 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1909 Position += Increment ;
1912 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1914 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1915 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */
1916 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1918 Position += Increment ;
1924 /* --------------------------------------------------------------------- */
1925 /* Function : XGINew_CheckDDRRank */
1929 /* --------------------------------------------------------------------- */
1930 int XGINew_CheckDDRRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1932 ULONG Increment , Position ;
1935 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1936 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1938 Increment += Increment / 2 ;
1941 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ;
1942 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ;
1943 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ;
1944 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ;
1945 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ;
1946 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ;
1948 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB )
1951 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 )
1954 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1957 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1958 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1960 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1966 /* --------------------------------------------------------------------- */
1967 /* Function : XGINew_CheckRanks */
1971 /* --------------------------------------------------------------------- */
1972 int XGINew_CheckRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1976 for( r = RankNo ; r >= 1 ; r-- )
1978 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
1982 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
1985 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
1992 /* --------------------------------------------------------------------- */
1993 /* Function : XGINew_CheckDDRRanks */
1997 /* --------------------------------------------------------------------- */
1998 int XGINew_CheckDDRRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2002 for( r = RankNo ; r >= 1 ; r-- )
2004 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2008 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2011 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2018 /* --------------------------------------------------------------------- */
2023 /* --------------------------------------------------------------------- */
2024 int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo)
2029 for( i = 0 ; i < 13 ; i++ )
2031 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2033 for( j = 2 ; j > 0 ; j-- )
2035 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) )
2039 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2048 /* --------------------------------------------------------------------- */
2049 /* Function : XGINew_SetDRAMSizeReg */
2053 /* --------------------------------------------------------------------- */
2054 USHORT XGINew_SetDRAMSizeReg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2056 USHORT data = 0 , memsize = 0 ;
2060 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2061 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2069 if( XGINew_ChannelAB == 3 )
2072 ChannelNo = XGINew_ChannelAB ;
2074 if ( ChannelNo * RankSize <= 256 )
2076 while( ( RankSize >>= 1 ) > 0 )
2081 memsize = data >> 4 ;
2083 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2084 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2086 /* data |= XGINew_ChannelAB << 2 ; */
2087 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2088 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2091 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2097 /* --------------------------------------------------------------------- */
2098 /* Function : XGINew_SetDRAMSize20Reg */
2102 /* --------------------------------------------------------------------- */
2103 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2105 USHORT data = 0 , memsize = 0 ;
2109 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2110 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2118 if( XGINew_ChannelAB == 3 )
2121 ChannelNo = XGINew_ChannelAB ;
2123 if ( ChannelNo * RankSize <= 256 )
2125 while( ( RankSize >>= 1 ) > 0 )
2130 memsize = data >> 4 ;
2132 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2133 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2136 /* data |= XGINew_ChannelAB << 2 ; */
2137 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2138 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2141 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2147 /* --------------------------------------------------------------------- */
2148 /* Function : XGINew_ReadWriteRest */
2152 /* --------------------------------------------------------------------- */
2153 int XGINew_ReadWriteRest( USHORT StopAddr , USHORT StartAddr, PVB_DEVICE_INFO pVBInfo)
2156 ULONG Position = 0 ;
2158 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2160 for( i = StartAddr ; i <= StopAddr ; i++ )
2163 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2166 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2170 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2173 for( i = StartAddr ; i <= StopAddr ; i++ )
2176 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2183 /* --------------------------------------------------------------------- */
2184 /* Function : XGINew_CheckFrequence */
2188 /* --------------------------------------------------------------------- */
2189 UCHAR XGINew_CheckFrequence( PVB_DEVICE_INFO pVBInfo )
2193 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2195 if ( ( data & 0x10 ) == 0 )
2197 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2198 data = ( data & 0x02 ) >> 1 ;
2202 return( data & 0x01 ) ;
2206 /* --------------------------------------------------------------------- */
2207 /* Function : XGINew_CheckChannel */
2211 /* --------------------------------------------------------------------- */
2212 void XGINew_CheckChannel( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2216 switch( HwDeviceExtension->jChipType )
2220 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2222 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2224 if ( data == 0 ) /* Single_32_16 */
2227 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2230 XGINew_DataBusWidth = 32 ; /* 32 bits */
2231 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2232 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2235 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2238 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2240 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2241 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2244 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2249 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2251 XGINew_DataBusWidth = 16 ; /* 16 bits */
2252 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2253 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2256 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2259 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2264 else /* Dual_16_8 */
2266 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2269 XGINew_DataBusWidth = 16 ; /* 16 bits */
2270 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2271 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2274 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2277 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2279 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2280 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2283 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2289 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2291 XGINew_DataBusWidth = 8 ; /* 8 bits */
2292 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2293 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2296 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2299 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2306 XGINew_DataBusWidth = 16 ; /* 16 bits */
2307 XGINew_ChannelAB = 1 ; /* Single channel */
2308 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2311 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2313 XGINew_DataBusWidth = 32 ; /* 32 bits */
2314 XGINew_ChannelAB = 3 ; /* Quad Channel */
2315 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2316 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2318 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2321 XGINew_ChannelAB = 2 ; /* Dual channels */
2322 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2324 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2329 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2332 XGINew_ChannelAB = 3 ;
2333 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2336 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2339 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2341 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2344 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2348 XGINew_DataBusWidth = 64 ; /* 64 bits */
2349 XGINew_ChannelAB = 2 ; /* Dual channels */
2350 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2351 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2353 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2356 XGINew_ChannelAB = 1 ; /* Single channels */
2357 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2359 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2362 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2364 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2367 XGINew_ChannelAB = 2 ; /* Dual channels */
2368 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2371 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2374 XGINew_ChannelAB = 1 ; /* Single channels */
2375 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2377 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2380 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2387 XG42 SR14 D[3] Reserve
2388 D[2] = 1, Dual Channel
2391 It's Different from Other XG40 Series.
2393 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2395 XGINew_DataBusWidth = 32 ; /* 32 bits */
2396 XGINew_ChannelAB = 2 ; /* 2 Channel */
2397 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2398 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2400 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2403 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2404 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2405 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2408 XGINew_ChannelAB = 1 ; /* Single Channel */
2409 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2410 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2412 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2416 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2417 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2422 XGINew_DataBusWidth = 64 ; /* 64 bits */
2423 XGINew_ChannelAB = 1 ; /* 1 channels */
2424 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2425 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2427 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2431 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2432 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2440 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2442 XGINew_DataBusWidth = 32 ; /* 32 bits */
2443 XGINew_ChannelAB = 3 ;
2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2445 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2447 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2450 XGINew_ChannelAB = 2 ; /* 2 channels */
2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2453 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2456 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2457 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2459 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2460 XGINew_ChannelAB = 3 ; /* 4 channels */
2463 XGINew_ChannelAB = 2 ; /* 2 channels */
2464 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2469 XGINew_DataBusWidth = 64 ; /* 64 bits */
2470 XGINew_ChannelAB = 2 ; /* 2 channels */
2471 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2472 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2474 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2478 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2479 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2487 /* --------------------------------------------------------------------- */
2488 /* Function : XGINew_DDRSizing340 */
2492 /* --------------------------------------------------------------------- */
2493 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2496 USHORT memsize , addr ;
2498 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2499 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2500 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2503 if ( HwDeviceExtension->jChipType >= XG20 )
2505 for( i = 0 ; i < 12 ; i++ )
2507 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2508 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2512 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2513 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2516 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2522 for( i = 0 ; i < 4 ; i++ )
2524 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2525 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2530 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2531 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2534 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2542 /* --------------------------------------------------------------------- */
2543 /* Function : XGINew_DDRSizing */
2547 /* --------------------------------------------------------------------- */
2548 int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo)
2553 for( i = 0 ; i < 4 ; i++ )
2555 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2556 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2557 for( j = 2 ; j > 0 ; j-- )
2559 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2560 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2564 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2572 /* --------------------------------------------------------------------- */
2573 /* Function : XGINew_SetMemoryClock */
2577 /* --------------------------------------------------------------------- */
2578 void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2582 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2583 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2584 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2588 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2589 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2590 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2592 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2593 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2594 if ( HwDeviceExtension->jChipType == XG42 )
2596 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2597 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2598 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2600 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2606 /* --------------------------------------------------------------------- */
2607 /* Function : ChkLFB */
2611 /* --------------------------------------------------------------------- */
2612 BOOLEAN ChkLFB( PVB_DEVICE_INFO pVBInfo )
2614 if ( LFBDRAMTrap & XGINew_GetReg1( pVBInfo->P3d4 , 0x78 ) )
2621 /* --------------------------------------------------------------------- */
2622 /* input : dx ,valid value : CR or second chip's CR */
2624 /* SetPowerConsume : */
2625 /* Description: reduce 40/43 power consumption in first chip or */
2626 /* in second chip, assume CR A1 D[6]="1" in this case */
2628 /* --------------------------------------------------------------------- */
2629 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG XGI_P3d4Port )
2634 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2635 if ((lTemp&0xFF)==0)
2637 /* set CR58 D[5]=0 D[3]=0 */
2638 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2639 bTemp = (UCHAR) XGINew_GetReg1( XGI_P3d4Port , 0xCB ) ;
2644 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2648 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2657 void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2660 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
2661 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2662 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2663 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
2664 pVBInfo->ISXPDOS = 0 ;
2666 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2667 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2668 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2669 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2670 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2671 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2672 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2673 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2674 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2675 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2676 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2677 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2678 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2679 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2680 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2681 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2682 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2683 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2684 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2686 switch(HwDeviceExtension->jChipType)
2694 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2700 /* --------------------------------------------------------------------- */
2701 /* Function : ReadVBIOSTablData */
2705 /* --------------------------------------------------------------------- */
2706 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo)
2708 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
2713 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */
2718 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2720 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ;
2721 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ;
2722 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ;
2723 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2728 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2730 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ;
2731 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ;
2732 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ;
2733 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2737 /* Volari customize data area start */
2738 /* if ( ChipType == XG40 ) */
2739 if ( ChipType >= XG40 )
2742 for( jj = 0x00 ; jj < 0x03 ; jj++ )
2744 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */
2745 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2746 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2747 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2748 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2749 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2750 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2751 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2756 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */
2757 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2758 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2759 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2760 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2761 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2762 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2763 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2765 *pVBInfo->pSR07 = pVideoMemory[ 0x74 ] ;
2766 *pVBInfo->pSR1F = pVideoMemory[ 0x75 ] ;
2767 *pVBInfo->pSR21 = pVideoMemory[ 0x76 ] ;
2768 *pVBInfo->pSR22 = pVideoMemory[ 0x77 ] ;
2769 *pVBInfo->pSR23 = pVideoMemory[ 0x78 ] ;
2770 *pVBInfo->pSR24 = pVideoMemory[ 0x79 ] ;
2771 pVBInfo->SR25[ 0 ] = pVideoMemory[ 0x7A ] ;
2772 *pVBInfo->pSR31 = pVideoMemory[ 0x7B ] ;
2773 *pVBInfo->pSR32 = pVideoMemory[ 0x7C ] ;
2774 *pVBInfo->pSR33 = pVideoMemory[ 0x7D ] ;
2777 for( jj = 0 ; jj < 3 ; jj++ )
2779 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ;
2780 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2781 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2782 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2783 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2784 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2785 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2786 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2791 for( j = 3 ; j < 24 ; j++ )
2793 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ;
2794 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2795 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2796 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2797 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2798 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2799 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2800 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2804 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ;
2806 for( j = 0 ; j < 8 ; j++ )
2808 for( k = 0 ; k < 4 ; k++ )
2809 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2812 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ;
2814 for( j = 0 ; j < 8 ; j++ )
2816 for( k = 0 ; k < 4 ; k++ )
2817 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2820 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ;
2821 for( j = 0 ; j < 8 ; j++ )
2823 for( k = 0 ; k < 32 ; k++ )
2824 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ;
2827 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ;
2829 for( j = 0 ; j < 8 ; j++ )
2831 for( k = 0 ; k < 2 ; k++ )
2832 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ;
2835 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ;
2836 for( j = 0 ; j < 12 ; j++ )
2837 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ;
2839 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ;
2840 for( j = 0 ; j < 4 ; j++ )
2841 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ;
2843 if ( ChipType == XG21 )
2845 if (pVideoMemory[ 0x67 ] & 0x80)
2847 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2849 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2851 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ;
2852 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ;
2853 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ;
2854 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ;
2858 if ( ChipType == XG27 )
2861 for( i = 0 ; i <= 0xB ; i++,jj++ )
2862 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ;
2863 for( i = 0x0 ; i <= 0x1 ; i++,jj++ )
2864 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ;
2866 *pVBInfo->pSR40 = pVideoMemory[ jj ] ;
2868 *pVBInfo->pSR41 = pVideoMemory[ jj ] ;
2870 if (pVideoMemory[ 0x67 ] & 0x80)
2872 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2874 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2877 *pVBInfo->pCR2E = pVideoMemory[ jj ] ;
2878 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ;
2879 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ;
2880 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ;
2885 *pVBInfo->pCRCF = pVideoMemory[ 0x1CA ] ;
2886 *pVBInfo->pXGINew_DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ;
2887 *pVBInfo->pXGINew_I2CDefinition = pVideoMemory[ 0x1D1 ] ;
2888 if ( ChipType >= XG20 )
2890 *pVBInfo->pXGINew_CR97 = pVideoMemory[ 0x1D2 ] ;
2891 if ( ChipType == XG27 )
2893 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ;
2894 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ;
2900 /* Volari customize data area end */
2902 if ( ChipType == XG21 )
2904 pVBInfo->IF_DEF_LVDS = 0 ;
2905 if (pVideoMemory[ 0x65 ] & 0x1)
2907 pVBInfo->IF_DEF_LVDS = 1 ;
2908 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2909 j = pVideoMemory[ i-1 ] ;
2915 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2916 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2917 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2918 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2919 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2920 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2921 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2922 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2923 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2924 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2925 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2926 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2927 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2928 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2929 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2930 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2934 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) );
2938 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2939 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2940 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2941 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2942 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2943 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2944 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2945 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2946 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2947 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2948 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2949 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2950 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2951 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2952 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2953 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2959 /* --------------------------------------------------------------------- */
2960 /* Function : XGINew_DDR1x_MRS_XG20 */
2964 /* --------------------------------------------------------------------- */
2965 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
2968 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
2969 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2970 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2971 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2974 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
2975 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2976 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2977 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2979 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2980 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2981 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
2982 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2983 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2985 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
2987 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2988 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2989 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
2990 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2991 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2992 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
2995 /* --------------------------------------------------------------------- */
2996 /* Function : XGINew_SetDRAMModeRegister_XG20 */
3000 /* --------------------------------------------------------------------- */
3001 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3003 VB_DEVICE_INFO VBINF;
3004 PVB_DEVICE_INFO pVBInfo = &VBINF;
3005 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3006 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3007 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3008 pVBInfo->ISXPDOS = 0 ;
3010 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3011 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3012 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3013 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3014 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3015 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3016 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3017 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3018 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3019 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3020 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3021 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3022 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3023 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3024 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3025 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3026 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3028 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3030 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3032 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3033 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3035 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3037 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3040 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3042 VB_DEVICE_INFO VBINF;
3043 PVB_DEVICE_INFO pVBInfo = &VBINF;
3044 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3045 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3046 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3047 pVBInfo->ISXPDOS = 0 ;
3049 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3050 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3051 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3052 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3053 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3054 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3055 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3056 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3057 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3058 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3059 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3060 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3061 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3062 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3063 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3064 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3065 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3067 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3069 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3071 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3072 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3074 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3075 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3077 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3078 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
3082 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3086 VB_DEVICE_INFO VBINF;
3087 PVB_DEVICE_INFO pVBInfo = &VBINF;
3088 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3089 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3090 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
3091 pVBInfo->ISXPDOS = 0 ;
3093 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3094 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3095 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3096 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3097 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3098 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3099 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3100 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3101 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3102 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3103 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3104 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3105 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3106 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3107 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3108 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3109 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3111 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3113 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3115 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3116 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3118 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3120 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3123 /* -------------------------------------------------------- */
3124 /* Function : XGINew_ChkSenseStatus */
3128 /* -------------------------------------------------------- */
3129 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
3131 USHORT tempbx=0 , temp , tempcx , CR3CData;
3133 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
3135 if ( temp & Monitor1Sense )
3136 tempbx |= ActiveCRT1 ;
3137 if ( temp & LCDSense )
3138 tempbx |= ActiveLCD ;
3139 if ( temp & Monitor2Sense )
3140 tempbx |= ActiveCRT2 ;
3141 if ( temp & TVSense )
3143 tempbx |= ActiveTV ;
3144 if ( temp & AVIDEOSense )
3145 tempbx |= ( ActiveAVideo << 8 );
3146 if ( temp & SVIDEOSense )
3147 tempbx |= ( ActiveSVideo << 8 );
3148 if ( temp & SCARTSense )
3149 tempbx |= ( ActiveSCART << 8 );
3150 if ( temp & HiTVSense )
3151 tempbx |= ( ActiveHiTV << 8 );
3152 if ( temp & YPbPrSense )
3153 tempbx |= ( ActiveYPbPr << 8 );
3156 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3157 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3159 if ( tempbx & tempcx )
3161 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3162 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3165 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3174 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3181 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3182 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3184 /* -------------------------------------------------------- */
3185 /* Function : XGINew_SetModeScratch */
3189 /* -------------------------------------------------------- */
3190 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo )
3192 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3194 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3195 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3196 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3198 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3200 if ( temp & ActiveCRT2 )
3201 tempcl = SetCRT2ToRAMDAC ;
3204 if ( temp & ActiveLCD )
3206 tempcl |= SetCRT2ToLCD ;
3207 if ( temp & DriverMode )
3209 if ( temp & ActiveTV )
3211 tempch = SetToLCDA | EnableDualEdge ;
3212 temp ^= SetCRT2ToLCD ;
3214 if ( ( temp >> 8 ) & ActiveAVideo )
3215 tempcl |= SetCRT2ToAVIDEO ;
3216 if ( ( temp >> 8 ) & ActiveSVideo )
3217 tempcl |= SetCRT2ToSVIDEO ;
3218 if ( ( temp >> 8 ) & ActiveSCART )
3219 tempcl |= SetCRT2ToSCART ;
3221 if ( pVBInfo->IF_DEF_HiVision == 1 )
3223 if ( ( temp >> 8 ) & ActiveHiTV )
3224 tempcl |= SetCRT2ToHiVisionTV ;
3227 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3229 if ( ( temp >> 8 ) & ActiveYPbPr )
3230 tempch |= SetYPbPr ;
3237 if ( ( temp >> 8 ) & ActiveAVideo )
3238 tempcl |= SetCRT2ToAVIDEO ;
3239 if ( ( temp >> 8 ) & ActiveSVideo )
3240 tempcl |= SetCRT2ToSVIDEO ;
3241 if ( ( temp >> 8 ) & ActiveSCART )
3242 tempcl |= SetCRT2ToSCART ;
3244 if ( pVBInfo->IF_DEF_HiVision == 1 )
3246 if ( ( temp >> 8 ) & ActiveHiTV )
3247 tempcl |= SetCRT2ToHiVisionTV ;
3250 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3252 if ( ( temp >> 8 ) & ActiveYPbPr )
3253 tempch |= SetYPbPr ;
3258 tempcl |= SetSimuScanMode ;
3259 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3260 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3261 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3262 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3263 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3265 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3266 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3267 if ( !( temp & ActiveCRT1 ) )
3268 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3269 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3270 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3271 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3272 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3274 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3275 CR38Data &= ~SetYPbPr ;
3276 CR38Data |= tempch ;
3277 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3281 /* -------------------------------------------------------- */
3282 /* Function : XGINew_GetXG21Sense */
3286 /* -------------------------------------------------------- */
3287 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3290 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
3292 pVBInfo->IF_DEF_LVDS = 0 ;
3295 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3297 pVBInfo->IF_DEF_LVDS = 1 ;
3298 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3299 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3304 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3305 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3307 { /* DVI & DVO GPIOA/B pull high */
3308 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3309 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3310 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3311 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3313 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3315 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3316 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3323 /* -------------------------------------------------------- */
3324 /* Function : XGINew_GetXG27Sense */
3328 /* -------------------------------------------------------- */
3329 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3333 pVBInfo->IF_DEF_LVDS = 0 ;
3334 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3335 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3336 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3337 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3341 pVBInfo->IF_DEF_LVDS = 1 ;
3342 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3343 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3347 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3349 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3353 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo)
3355 UCHAR CR38,CR4A,temp;
3357 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3358 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3359 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3361 if ( ( CR38 & 0xE0 ) > 0x80 )
3363 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3368 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3373 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo)
3377 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3378 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3379 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3386 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3388 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;