drivers/staging/xgifb/vb_init.c

   1 #include "vgatypes.h"
   2
   3 #include <linux/version.h>
   4 #include <linux/types.h>
   5 #include <linux/delay.h> /* udelay */
   6 #include "XGIfb.h"
   7
   8 #include "vb_def.h"
   9 #include "vb_struct.h"
  10 #include "vb_util.h"
  11 #include "vb_setmode.h"
  12 #include "vb_init.h"
  13 #include "vb_ext.h"
  14
  15
  16 #include <asm/io.h>
  17
  18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
  19
  20 unsigned short XGINew_DRAMType[17][5] = {
  21         {0x0C, 0x0A, 0x02, 0x40, 0x39}, {0x0D, 0x0A, 0x01, 0x40, 0x48},
  22         {0x0C, 0x09, 0x02, 0x20, 0x35}, {0x0D, 0x09, 0x01, 0x20, 0x44},
  23         {0x0C, 0x08, 0x02, 0x10, 0x31}, {0x0D, 0x08, 0x01, 0x10, 0x40},
  24         {0x0C, 0x0A, 0x01, 0x20, 0x34}, {0x0C, 0x09, 0x01, 0x08, 0x32},
  25         {0x0B, 0x08, 0x02, 0x08, 0x21}, {0x0C, 0x08, 0x01, 0x08, 0x30},
  26         {0x0A, 0x08, 0x02, 0x04, 0x11}, {0x0B, 0x0A, 0x01, 0x10, 0x28},
  27         {0x09, 0x08, 0x02, 0x02, 0x01}, {0x0B, 0x09, 0x01, 0x08, 0x24},
  28         {0x0B, 0x08, 0x01, 0x04, 0x20}, {0x0A, 0x08, 0x01, 0x02, 0x10},
  29         {0x09, 0x08, 0x01, 0x01, 0x00} };
  30
  31 static unsigned short XGINew_SDRDRAM_TYPE[13][5] = {
  32         { 2, 12, 9, 64, 0x35},
  33         { 1, 13, 9, 64, 0x44},
  34         { 2, 12, 8, 32, 0x31},
  35         { 2, 11, 9, 32, 0x25},
  36         { 1, 12, 9, 32, 0x34},
  37         { 1, 13, 8, 32, 0x40},
  38         { 2, 11, 8, 16, 0x21},
  39         { 1, 12, 8, 16, 0x30},
  40         { 1, 11, 9, 16, 0x24},
  41         { 1, 11, 8,  8, 0x20},
  42         { 2,  9, 8,  4, 0x01},
  43         { 1, 10, 8,  4, 0x10},
  44         { 1,  9, 8,  2, 0x00} };
  45
  46 static unsigned short XGINew_DDRDRAM_TYPE[4][5] = {
  47         { 2, 12, 9, 64, 0x35},
  48         { 2, 12, 8, 32, 0x31},
  49         { 2, 11, 8, 16, 0x21},
  50         { 2,  9, 8,  4, 0x01} };
  51
  52 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  53         { 2, 13, 9, 64, 0x45},
  54         { 2, 12, 9, 32, 0x35},
  55         { 2, 12, 8, 16, 0x31},
  56         { 2, 11, 8,  8, 0x21} };
  57
  58 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  59         { 2, 14, 11, 128, 0x5D},
  60         { 2, 14, 10, 64, 0x59},
  61         { 2, 13, 11, 64, 0x4D},
  62         { 2, 14,  9, 32, 0x55},
  63         { 2, 13, 10, 32, 0x49},
  64         { 2, 12, 11, 32, 0x3D},
  65         { 2, 14,  8, 16, 0x51},
  66         { 2, 13,  9, 16, 0x45},
  67         { 2, 12, 10, 16, 0x39},
  68         { 2, 13,  8,  8, 0x41},
  69         { 2, 12,  9,  8, 0x35},
  70         { 2, 12,  8,  4, 0x31} };
  71
  72 void     XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *);
  73 void     XGINew_SetDRAMSize_310(struct xgi_hw_device_info *, struct vb_device_info *);
  74 void     XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
  75 void     XGINew_SetDRAMModeRegister(struct vb_device_info *);
  76 void     XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension);
  77 void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
  78                                       unsigned long, struct vb_device_info *);
  79 unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  80                                      struct vb_device_info *pVBInfo);
  81 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension);
  82
  83 int      XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *);
  84 void     XGINew_DisableRefresh(struct xgi_hw_device_info *, struct vb_device_info *) ;
  85 void     XGINew_CheckBusWidth_310(struct vb_device_info *) ;
  86 int      XGINew_SDRSizing(struct vb_device_info *);
  87 int      XGINew_DDRSizing(struct vb_device_info *);
  88 void     XGINew_EnableRefresh(struct xgi_hw_device_info *, struct vb_device_info *);
  89 static int      XGINew_RAMType;         /*int      ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
  90 #if 0
  91 static unsigned long     UNIROM;
  92 #endif
  93 unsigned char  ChkLFB(struct vb_device_info *);
  94 void     XGINew_Delay15us(unsigned long);
  95 void     SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
  96                          unsigned long XGI_P3d4Port);
  97 void     ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
  98 void     XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
  99 void     XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension);
 100 void     XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension);
 101 void     XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
 102 void     XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
 103 void     XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
 104 unsigned char    GetXG21FPBits(struct vb_device_info *pVBInfo);
 105 void     XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
 106 unsigned char    GetXG27FPBits(struct vb_device_info *pVBInfo);
 107
 108 static void DelayUS(unsigned long MicroSeconds)
 109 {
 110         udelay(MicroSeconds);
 111 }
 112
 113 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
 114 {
 115         struct vb_device_info VBINF;
 116         struct vb_device_info *pVBInfo = &VBINF;
 117         unsigned char i, temp = 0, temp1;
 118         /* VBIOSVersion[5]; */
 119         volatile unsigned char *pVideoMemory;
 120
 121         /* unsigned long j, k; */
 122
 123         unsigned long Temp;
 124
 125         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
 126
 127         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 128
 129         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
 130
 131         pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
 132
 133         /* Newdebugcode(0x99); */
 134
 135
 136         /* if (pVBInfo->ROMAddr == 0) */
 137         /* return(0); */
 138
 139         if (pVBInfo->FBAddr == NULL) {
 140                 printk("\n pVBInfo->FBAddr == 0 ");
 141                 return 0;
 142         }
 143         printk("1");
 144         if (pVBInfo->BaseAddr == 0) {
 145                 printk("\npVBInfo->BaseAddr == 0 ");
 146                 return 0;
 147         }
 148         printk("2");
 149
 150         XGINew_SetReg3((pVBInfo->BaseAddr + 0x12), 0x67); /* 3c2 <- 67 ,ynlai */
 151
 152         pVBInfo->ISXPDOS = 0;
 153         printk("3");
 154
 155         if (!HwDeviceExtension->bIntegratedMMEnabled)
 156                 return 0; /* alan */
 157
 158         printk("4");
 159
 160         /* VBIOSVersion[4] = 0x0; */
 161
 162         /* 09/07/99 modify by domao */
 163
 164         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
 165         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
 166         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
 167         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
 168         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
 169         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
 170         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
 171         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
 172         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
 173         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
 174         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
 175         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
 176         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
 177         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
 178         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
 179         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
 180         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
 181         printk("5");
 182
 183         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
 184                 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
 185
 186         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
 187
 188         /* ReadVBIOSData */
 189         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
 190
 191         /* 1.Openkey */
 192         XGINew_SetReg1(pVBInfo->P3c4, 0x05, 0x86);
 193         printk("6");
 194
 195         /* GetXG21Sense (GPIO) */
 196         if (HwDeviceExtension->jChipType == XG21)
 197                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
 198
 199         if (HwDeviceExtension->jChipType == XG27)
 200                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
 201
 202         printk("7");
 203
 204         /* 2.Reset Extended register */
 205
 206         for (i = 0x06; i < 0x20; i++)
 207                 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
 208
 209         for (i = 0x21; i <= 0x27; i++)
 210                 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
 211
 212         /* for(i = 0x06; i <= 0x27; i++) */
 213         /* XGINew_SetReg1(pVBInfo->P3c4, i, 0); */
 214
 215         printk("8");
 216
 217         if ((HwDeviceExtension->jChipType >= XG20) || (HwDeviceExtension->jChipType >= XG40)) {
 218                 for (i = 0x31; i <= 0x3B; i++)
 219                         XGINew_SetReg1(pVBInfo->P3c4, i, 0);
 220         } else {
 221                 for (i = 0x31; i <= 0x3D; i++)
 222                         XGINew_SetReg1(pVBInfo->P3c4, i, 0);
 223         }
 224         printk("9");
 225
 226         if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
 227                 XGINew_SetReg1(pVBInfo->P3c4, 0x3B, 0xC0);
 228
 229         /* for (i = 0x30; i <= 0x3F; i++) */
 230         /* XGINew_SetReg1(pVBInfo->P3d4, i, 0); */
 231
 232         for (i = 0x79; i <= 0x7C; i++)
 233                 XGINew_SetReg1(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
 234
 235         printk("10");
 236
 237         if (HwDeviceExtension->jChipType >= XG20)
 238                 XGINew_SetReg1(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
 239
 240         /* 3.SetMemoryClock
 241
 242          if (HwDeviceExtension->jChipType >= XG40)
 243          XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 244
 245          if (HwDeviceExtension->jChipType < XG40)
 246          XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);  */
 247
 248         printk("11");
 249
 250         /* 4.SetDefExt1Regs begin */
 251         XGINew_SetReg1(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
 252         if (HwDeviceExtension->jChipType == XG27) {
 253                 XGINew_SetReg1(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
 254                 XGINew_SetReg1(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
 255         }
 256         XGINew_SetReg1(pVBInfo->P3c4, 0x11, 0x0F);
 257         XGINew_SetReg1(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
 258         /* XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0x20); */
 259         XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
 260         XGINew_SetReg1(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
 261         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
 262                 XGINew_SetReg1(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
 263
 264         /* SR11 = 0x0F; */
 265         /* XGINew_SetReg1(pVBInfo->P3c4, 0x11, SR11); */
 266
 267         printk("12");
 268
 269         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
 270                 /* Set AGP Rate */
 271                 /*
 272                 temp1 = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
 273                 temp1 &= 0x02;
 274                 if (temp1 == 0x02) {
 275                         XGINew_SetReg4(0xcf8, 0x80000000);
 276                         ChipsetID = XGINew_GetReg3(0x0cfc);
 277                         XGINew_SetReg4(0xcf8, 0x8000002C);
 278                         VendorID = XGINew_GetReg3(0x0cfc);
 279                         VendorID &= 0x0000FFFF;
 280                         XGINew_SetReg4(0xcf8, 0x8001002C);
 281                         GraphicVendorID = XGINew_GetReg3(0x0cfc);
 282                         GraphicVendorID &= 0x0000FFFF;
 283
 284                         if (ChipsetID == 0x7301039)
 285                                 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x09);
 286
 287                         ChipsetID &= 0x0000FFFF;
 288
 289                         if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
 290                                 if (ChipsetID == 0x1106) {
 291                                         if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
 292                                                 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0D);
 293                                         else
 294                                                 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
 295                                 } else {
 296                                         XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
 297                                 }
 298                         }
 299                 }
 300                 */
 301
 302                 printk("13");
 303
 304                 if (HwDeviceExtension->jChipType >= XG40) {
 305                         /* Set AGP customize registers (in SetDefAGPRegs) Start */
 306                         for (i = 0x47; i <= 0x4C; i++)
 307                                 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
 308
 309                         for (i = 0x70; i <= 0x71; i++)
 310                                 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
 311
 312                         for (i = 0x74; i <= 0x77; i++)
 313                                 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
 314                         /* Set AGP customize registers (in SetDefAGPRegs) End */
 315                         /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
 316                         /*        XGINew_SetReg4(0xcf8 , 0x80000000); */
 317                         /*        ChipsetID = XGINew_GetReg3(0x0cfc); */
 318                         /*        if (ChipsetID == 0x25308086) */
 319                         /*            XGINew_SetReg1(pVBInfo->P3d4, 0x77, 0xF0); */
 320
 321                         HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
 322                         Temp >>= 20;
 323                         Temp &= 0xF;
 324
 325                         if (Temp == 1)
 326                                 XGINew_SetReg1(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
 327                 }
 328                 printk("14");
 329
 330                 if (HwDeviceExtension->jChipType < XG40)
 331                         XGINew_SetReg1(pVBInfo->P3d4, 0x49, pVBInfo->CR49[0]);
 332         } /* != XG20 */
 333
 334         /* Set PCI */
 335         XGINew_SetReg1(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
 336         XGINew_SetReg1(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
 337         XGINew_SetReg1(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
 338         printk("15");
 339
 340         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
 341                 /* Set VB */
 342                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
 343                 XGINew_SetRegANDOR(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
 344                 XGINew_SetReg1(pVBInfo->Part1Port, 0x00, 0x00);
 345                 temp1 = (unsigned char) XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
 346                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
 347
 348                 XGINew_SetReg1(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
 349
 350                 printk("16");
 351
 352                 XGINew_SetReg1(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
 353         } /* != XG20 */
 354
 355         XGINew_SetReg1(pVBInfo->P3c4, 0x27, 0x1F);
 356
 357         if ((HwDeviceExtension->jChipType == XG42)
 358                         && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
 359                 XGINew_SetReg1(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
 360                 XGINew_SetReg1(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
 361         } else {
 362                 XGINew_SetReg1(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
 363                 XGINew_SetReg1(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
 364         }
 365         XGINew_SetReg1(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
 366         printk("17");
 367
 368         /*
 369          if (HwDeviceExtension->jChipType >= XG40)
 370          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
 371
 372         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
 373                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
 374                         if (pVBInfo->IF_DEF_LVDS == 0) {
 375                                 XGINew_SetReg1(pVBInfo->Part2Port, 0x00, 0x1C);
 376                                 XGINew_SetReg1(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
 377                                 XGINew_SetReg1(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
 378                                 XGINew_SetReg1(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
 379                                 XGINew_SetReg1(pVBInfo->Part4Port, 0x0F, 0x3F);
 380                         }
 381
 382                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
 383                 }
 384         } /* != XG20 */
 385         printk("18");
 386
 387         if (HwDeviceExtension->jChipType < XG40)
 388                 XGINew_SetReg1(pVBInfo->P3d4, 0x83, 0x00);
 389         printk("181");
 390
 391         if (HwDeviceExtension->bSkipSense == 0) {
 392                 printk("182");
 393
 394                 XGI_SenseCRT1(pVBInfo);
 395
 396                 printk("183");
 397                 /* XGINew_DetectMonitor(HwDeviceExtension); */
 398                 pVBInfo->IF_DEF_CH7007 = 0;
 399                 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
 400                         printk("184");
 401                         XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
 402                         printk("185");
 403
 404                 }
 405                 if (HwDeviceExtension->jChipType == XG21) {
 406                         printk("186");
 407
 408                         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
 409                         temp = GetXG21FPBits(pVBInfo);
 410                         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x01, temp);
 411                         printk("187");
 412
 413                 }
 414                 if (HwDeviceExtension->jChipType == XG27) {
 415                         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
 416                         temp = GetXG27FPBits(pVBInfo);
 417                         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x03, temp);
 418                 }
 419         }
 420         printk("19");
 421
 422         if (HwDeviceExtension->jChipType >= XG40) {
 423                 if (HwDeviceExtension->jChipType >= XG40)
 424                         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 425
 426                 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
 427
 428                 printk("20");
 429                 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
 430                 printk("21");
 431         } /* XG40 */
 432
 433         printk("22");
 434
 435         /* SetDefExt2Regs begin */
 436         /*
 437         AGP = 1;
 438         temp = (unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x3A);
 439         temp &= 0x30;
 440         if (temp == 0x30)
 441                 AGP = 0;
 442
 443         if (AGP == 0)
 444                 *pVBInfo->pSR21 &= 0xEF;
 445
 446         XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
 447         if (AGP == 1)
 448                 *pVBInfo->pSR22 &= 0x20;
 449         XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
 450         */
 451         /* base = 0x80000000; */
 452         /* OutPortLong(0xcf8, base); */
 453         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
 454         /* if (Temp == 0x1039) { */
 455         XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
 456         /* } else { */
 457         /*      XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
 458         /* } */
 459
 460         XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
 461
 462         printk("23");
 463
 464         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
 465         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
 466
 467         printk("24");
 468
 469         XGINew_SetReg1(pVBInfo->P3d4, 0x8c, 0x87);
 470         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31);
 471         printk("25");
 472
 473         return 1;
 474 } /* end of init */
 475
 476 /* ============== alan ====================== */
 477
 478 unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
 479                                         struct vb_device_info *pVBInfo)
 480 {
 481         unsigned char data, temp;
 482
 483         if (HwDeviceExtension->jChipType < XG20) {
 484                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
 485                         data = *pVBInfo->pSoftSetting & 0x07;
 486                         return data;
 487                 } else {
 488                         data = XGINew_GetReg1(pVBInfo->P3c4, 0x39) & 0x02;
 489
 490                         if (data == 0)
 491                                 data = (XGINew_GetReg1(pVBInfo->P3c4, 0x3A) & 0x02) >> 1;
 492
 493                         return data;
 494                 }
 495         } else if (HwDeviceExtension->jChipType == XG27) {
 496                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
 497                         data = *pVBInfo->pSoftSetting & 0x07;
 498                         return data;
 499                 }
 500                 temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
 501
 502                 if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
 503                         data = 0; /* DDR */
 504                 else
 505                         data = 1; /* DDRII */
 506                 return data;
 507         } else if (HwDeviceExtension->jChipType == XG21) {
 508                 XGINew_SetRegAND(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
 509                 DelayUS(800);
 510                 XGINew_SetRegOR(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
 511                 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
 512                 /* HOTPLUG_SUPPORT */
 513                 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */
 514                 if (temp & 0x01) /* DVI read GPIOH */
 515                         data = 1; /* DDRII */
 516                 else
 517                         data = 0; /* DDR */
 518                 /* ~HOTPLUG_SUPPORT */
 519                 XGINew_SetRegOR(pVBInfo->P3d4, 0xB4, 0x02);
 520                 return data;
 521         } else {
 522                 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97) & 0x01;
 523
 524                 if (data == 1)
 525                         data++;
 526
 527                 return data;
 528         }
 529 }
 530
 531 static unsigned char XGINew_Get310DRAMType(struct vb_device_info *pVBInfo)
 532 {
 533         unsigned char data;
 534
 535         /* index = XGINew_GetReg1(pVBInfo->P3c4, 0x1A); */
 536         /* index &= 07; */
 537
 538         if (*pVBInfo->pSoftSetting & SoftDRAMType)
 539                 data = *pVBInfo->pSoftSetting & 0x03;
 540         else
 541                 data = XGINew_GetReg1(pVBInfo->P3c4, 0x3a) & 0x03;
 542
 543         return data;
 544 }
 545
 546 /*
 547 void XGINew_Delay15us(unsigned long ulMicrsoSec)
 548 {
 549 }
 550 */
 551
 552 static void XGINew_SDR_MRS(struct vb_device_info *pVBInfo)
 553 {
 554         unsigned short data;
 555
 556         data = XGINew_GetReg1(pVBInfo->P3c4, 0x16);
 557         data &= 0x3F; /* SR16 D7=0,D6=0 */
 558         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data); /* enable mode register set(MRS) low */
 559         /* XGINew_Delay15us(0x100); */
 560         data |= 0x80; /* SR16 D7=1,D6=0 */
 561         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data); /* enable mode register set(MRS) high */
 562         /* XGINew_Delay15us(0x100); */
 563 }
 564
 565 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
 566 {
 567         XGINew_SetReg1(P3c4, 0x18, 0x01);
 568         XGINew_SetReg1(P3c4, 0x19, 0x20);
 569         XGINew_SetReg1(P3c4, 0x16, 0x00);
 570         XGINew_SetReg1(P3c4, 0x16, 0x80);
 571
 572         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
 573                 DelayUS(3000); /* Delay 67 x 3 Delay15us */
 574                 XGINew_SetReg1(P3c4, 0x18, 0x00);
 575                 XGINew_SetReg1(P3c4, 0x19, 0x20);
 576                 XGINew_SetReg1(P3c4, 0x16, 0x00);
 577                 XGINew_SetReg1(P3c4, 0x16, 0x80);
 578         }
 579
 580         DelayUS(60);
 581         XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 582         XGINew_SetReg1(P3c4, 0x19, 0x01);
 583         XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[0]);
 584         XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[1]);
 585         DelayUS(1000);
 586         XGINew_SetReg1(P3c4, 0x1B, 0x03);
 587         DelayUS(500);
 588         XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 589         XGINew_SetReg1(P3c4, 0x19, 0x00);
 590         XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[2]);
 591         XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[3]);
 592         XGINew_SetReg1(P3c4, 0x1B, 0x00);
 593 }
 594
 595 static void XGINew_DDR2x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
 596 {
 597         XGINew_SetReg1(P3c4, 0x18, 0x00);
 598         XGINew_SetReg1(P3c4, 0x19, 0x20);
 599         XGINew_SetReg1(P3c4, 0x16, 0x00);
 600         XGINew_SetReg1(P3c4, 0x16, 0x80);
 601         DelayUS(60);
 602         XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 603         /* XGINew_SetReg1(P3c4 ,0x18 ,0x31); */
 604         XGINew_SetReg1(P3c4, 0x19, 0x01);
 605         XGINew_SetReg1(P3c4, 0x16, 0x05);
 606         XGINew_SetReg1(P3c4, 0x16, 0x85);
 607         DelayUS(1000);
 608         XGINew_SetReg1(P3c4, 0x1B, 0x03);
 609         DelayUS(500);
 610         /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
 611         XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 612         XGINew_SetReg1(P3c4, 0x19, 0x00);
 613         XGINew_SetReg1(P3c4, 0x16, 0x05);
 614         XGINew_SetReg1(P3c4, 0x16, 0x85);
 615         XGINew_SetReg1(P3c4, 0x1B, 0x00);
 616 }
 617
 618 static void XGINew_DDRII_Bootup_XG27(
 619                         struct xgi_hw_device_info *HwDeviceExtension,
 620                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 621 {
 622         unsigned long P3d4 = P3c4 + 0x10;
 623         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 624         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 625
 626         /* Set Double Frequency */
 627         /* XGINew_SetReg1(P3d4, 0x97, 0x11); *//* CR97 */
 628         XGINew_SetReg1(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 629
 630         DelayUS(200);
 631
 632         XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 633         XGINew_SetReg1(P3c4, 0x19, 0x80); /* Set SR19 */
 634         XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
 635         DelayUS(15);
 636         XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
 637         DelayUS(15);
 638
 639         XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 640         XGINew_SetReg1(P3c4, 0x19, 0xC0); /* Set SR19 */
 641         XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
 642         DelayUS(15);
 643         XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
 644         DelayUS(15);
 645
 646         XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 647         XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
 648         XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
 649         DelayUS(30);
 650         XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
 651         DelayUS(15);
 652
 653         XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 654         XGINew_SetReg1(P3c4, 0x19, 0x0A); /* Set SR19 */
 655         XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
 656         DelayUS(30);
 657         XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
 658         XGINew_SetReg1(P3c4, 0x16, 0x80); /* Set SR16 */
 659         /* DelayUS(15); */
 660
 661         XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B */
 662         DelayUS(60);
 663         XGINew_SetReg1(P3c4, 0x1B, 0x00); /* Set SR1B */
 664
 665         XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 666         XGINew_SetReg1(P3c4, 0x19, 0x08); /* Set SR19 */
 667         XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
 668
 669         DelayUS(30);
 670         XGINew_SetReg1(P3c4, 0x16, 0x83); /* Set SR16 */
 671         DelayUS(15);
 672
 673         XGINew_SetReg1(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 674         XGINew_SetReg1(P3c4, 0x19, 0x46); /* Set SR19 */
 675         XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
 676         DelayUS(30);
 677         XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
 678         DelayUS(15);
 679
 680         XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 681         XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
 682         XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
 683         DelayUS(30);
 684         XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
 685         DelayUS(15);
 686
 687         XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
 688         DelayUS(200);
 689
 690 }
 691
 692 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 693                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 694 {
 695         unsigned long P3d4 = P3c4 + 0x10;
 696
 697         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 698         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 699
 700         XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
 701
 702         DelayUS(200);
 703         XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
 704         XGINew_SetReg1(P3c4, 0x19, 0x80);
 705         XGINew_SetReg1(P3c4, 0x16, 0x05);
 706         XGINew_SetReg1(P3c4, 0x16, 0x85);
 707
 708         XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS3 */
 709         XGINew_SetReg1(P3c4, 0x19, 0xC0);
 710         XGINew_SetReg1(P3c4, 0x16, 0x05);
 711         XGINew_SetReg1(P3c4, 0x16, 0x85);
 712
 713         XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS1 */
 714         XGINew_SetReg1(P3c4, 0x19, 0x40);
 715         XGINew_SetReg1(P3c4, 0x16, 0x05);
 716         XGINew_SetReg1(P3c4, 0x16, 0x85);
 717
 718         /* XGINew_SetReg1(P3c4, 0x18, 0x52); */ /* MRS1 */
 719         XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
 720         XGINew_SetReg1(P3c4, 0x19, 0x02);
 721         XGINew_SetReg1(P3c4, 0x16, 0x05);
 722         XGINew_SetReg1(P3c4, 0x16, 0x85);
 723
 724         DelayUS(15);
 725         XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
 726         DelayUS(30);
 727         XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
 728         DelayUS(100);
 729
 730         /* XGINew_SetReg1(P3c4 ,0x18, 0x52); */ /* MRS2 */
 731         XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
 732         XGINew_SetReg1(P3c4, 0x19, 0x00);
 733         XGINew_SetReg1(P3c4, 0x16, 0x05);
 734         XGINew_SetReg1(P3c4, 0x16, 0x85);
 735
 736         DelayUS(200);
 737 }
 738
 739 #if 0
 740 static void XGINew_DDR2_MRS_XG27(struct xgi_hw_device_info *HwDeviceExtension,
 741                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 742 {
 743         unsigned long P3d4 = P3c4 + 0x10;
 744
 745         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 746         XGINew_SetMemoryClock(HwDeviceExtension , pVBInfo);
 747
 748         XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
 749         DelayUS(200);
 750         XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
 751         XGINew_SetReg1(P3c4, 0x19, 0x80);
 752
 753         XGINew_SetReg1(P3c4, 0x16, 0x10);
 754         DelayUS(15); /* 06/11/23 XG27 A0 for CKE enable */
 755         XGINew_SetReg1(P3c4, 0x16, 0x90);
 756
 757         XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS3 */
 758         XGINew_SetReg1(P3c4, 0x19, 0xC0);
 759
 760         XGINew_SetReg1(P3c4, 0x16, 0x00);
 761         DelayUS(15); /* 06/11/22 XG27 A0 */
 762         XGINew_SetReg1(P3c4, 0x16, 0x80);
 763
 764         XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS1 */
 765         XGINew_SetReg1(P3c4, 0x19, 0x40);
 766
 767         XGINew_SetReg1(P3c4, 0x16, 0x00);
 768         DelayUS(15); /* 06/11/22 XG27 A0 */
 769         XGINew_SetReg1(P3c4, 0x16, 0x80);
 770
 771         XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
 772         XGINew_SetReg1(P3c4, 0x19, 0x06); /* [Billy]06/11/22 DLL Reset for XG27 Hynix DRAM */
 773
 774         XGINew_SetReg1(P3c4, 0x16, 0x00);
 775         DelayUS(15); /* 06/11/23 XG27 A0 */
 776         XGINew_SetReg1(P3c4, 0x16, 0x80);
 777
 778         DelayUS(30); /* 06/11/23 XG27 A0 Start Auto-PreCharge */
 779         XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
 780         DelayUS(60);
 781         XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
 782
 783         XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
 784         XGINew_SetReg1(P3c4, 0x19, 0x04); /* DLL without Reset for XG27 Hynix DRAM */
 785
 786         XGINew_SetReg1(P3c4, 0x16, 0x00);
 787         DelayUS(30);
 788         XGINew_SetReg1(P3c4, 0x16, 0x80);
 789
 790         XGINew_SetReg1(P3c4, 0x18, 0x80); /* XG27 OCD ON */
 791         XGINew_SetReg1(P3c4, 0x19, 0x46);
 792
 793         XGINew_SetReg1(P3c4, 0x16, 0x00);
 794         DelayUS(30);
 795         XGINew_SetReg1(P3c4, 0x16, 0x80);
 796
 797         XGINew_SetReg1(P3c4, 0x18, 0x00);
 798         XGINew_SetReg1(P3c4, 0x19, 0x40);
 799
 800         XGINew_SetReg1(P3c4, 0x16, 0x00);
 801         DelayUS(30);
 802         XGINew_SetReg1(P3c4, 0x16, 0x80);
 803
 804         DelayUS(15); /* Start Auto-PreCharge */
 805         XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
 806         DelayUS(200);
 807         XGINew_SetReg1(P3c4, 0x1B, 0x03); /* SR1B */
 808
 809 }
 810 #endif
 811
 812 static void XGINew_DDR1x_DefaultRegister(
 813                 struct xgi_hw_device_info *HwDeviceExtension,
 814                 unsigned long Port, struct vb_device_info *pVBInfo)
 815 {
 816         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 817
 818         if (HwDeviceExtension->jChipType >= XG20) {
 819                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 820                 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 821                 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 822                 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
 823
 824                 XGINew_SetReg1(P3d4, 0x98, 0x01);
 825                 XGINew_SetReg1(P3d4, 0x9A, 0x02);
 826
 827                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 828         } else {
 829                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 830
 831                 switch (HwDeviceExtension->jChipType) {
 832                 case XG41:
 833                 case XG42:
 834                         XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 835                         XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 836                         XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
 837                         break;
 838                 default:
 839                         XGINew_SetReg1(P3d4, 0x82, 0x88);
 840                         XGINew_SetReg1(P3d4, 0x86, 0x00);
 841                         XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
 842                         XGINew_SetReg1(P3d4, 0x86, 0x88);
 843                         XGINew_GetReg1(P3d4, 0x86);
 844                         XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
 845                         XGINew_SetReg1(P3d4, 0x82, 0x77);
 846                         XGINew_SetReg1(P3d4, 0x85, 0x00);
 847                         XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
 848                         XGINew_SetReg1(P3d4, 0x85, 0x88);
 849                         XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
 850                         XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 851                         XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 852                         break;
 853                 }
 854
 855                 XGINew_SetReg1(P3d4, 0x97, 0x00);
 856                 XGINew_SetReg1(P3d4, 0x98, 0x01);
 857                 XGINew_SetReg1(P3d4, 0x9A, 0x02);
 858                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 859         }
 860 }
 861
 862 #if 0
 863
 864 static void XGINew_DDR2x_DefaultRegister(
 865                 struct xgi_hw_device_info *HwDeviceExtension,
 866                 unsigned long Port, struct vb_device_info *pVBInfo)
 867 {
 868         unsigned long P3d4 = Port ,
 869         P3c4 = Port - 0x10;
 870
 871         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 872
 873         /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
 874         switch (HwDeviceExtension->jChipType) {
 875         case XG41:
 876         case XG42:
 877                 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 878                 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 879                 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
 880                 break;
 881         default:
 882                 /* keep following setting sequence, each setting in the same reg insert idle */
 883                 XGINew_SetReg1(P3d4, 0x82, 0x88);
 884                 XGINew_SetReg1(P3d4, 0x86, 0x00);
 885                 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
 886                 XGINew_SetReg1(P3d4, 0x86, 0x88);
 887                 XGINew_SetReg1(P3d4, 0x82, 0x77);
 888                 XGINew_SetReg1(P3d4, 0x85, 0x00);
 889                 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
 890                 XGINew_SetReg1(P3d4, 0x85, 0x88);
 891                 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
 892                 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 893                 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 894         }
 895         XGINew_SetReg1(P3d4, 0x97, 0x11);
 896         if (HwDeviceExtension->jChipType == XG42)
 897                 XGINew_SetReg1(P3d4, 0x98, 0x01);
 898         else
 899                 XGINew_SetReg1(P3d4, 0x98, 0x03);
 900
 901         XGINew_SetReg1(P3d4, 0x9A, 0x02);
 902
 903         XGINew_DDR2x_MRS_340(P3c4, pVBInfo);
 904 }
 905 #endif
 906
 907 static void XGINew_DDR2_DefaultRegister(
 908                 struct xgi_hw_device_info *HwDeviceExtension,
 909                 unsigned long Port, struct vb_device_info *pVBInfo)
 910 {
 911         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 912
 913         /* keep following setting sequence, each setting in the same reg insert idle */
 914         XGINew_SetReg1(P3d4, 0x82, 0x77);
 915         XGINew_SetReg1(P3d4, 0x86, 0x00);
 916         XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
 917         XGINew_SetReg1(P3d4, 0x86, 0x88);
 918         XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
 919         XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
 920         XGINew_SetReg1(P3d4, 0x82, 0x77);
 921         XGINew_SetReg1(P3d4, 0x85, 0x00);
 922         XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
 923         XGINew_SetReg1(P3d4, 0x85, 0x88);
 924         XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
 925         XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 926         if (HwDeviceExtension->jChipType == XG27)
 927                 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 928         else
 929                 XGINew_SetReg1(P3d4, 0x82, 0xA8); /* CR82 */
 930
 931         XGINew_SetReg1(P3d4, 0x98, 0x01);
 932         XGINew_SetReg1(P3d4, 0x9A, 0x02);
 933         if (HwDeviceExtension->jChipType == XG27)
 934                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 935         else
 936                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 937 }
 938
 939 void XGINew_SetDRAMDefaultRegister340(
 940                 struct xgi_hw_device_info *HwDeviceExtension,
 941                 unsigned long Port, struct vb_device_info *pVBInfo)
 942 {
 943         unsigned char temp, temp1, temp2, temp3, i, j, k;
 944
 945         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 946
 947         XGINew_SetReg1(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
 948         XGINew_SetReg1(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
 949         XGINew_SetReg1(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
 950         XGINew_SetReg1(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
 951
 952         temp2 = 0;
 953         for (i = 0; i < 4; i++) {
 954                 temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */
 955                 for (j = 0; j < 4; j++) {
 956                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 957                         temp2 |= temp1;
 958                         XGINew_SetReg1(P3d4, 0x6B, temp2);
 959                         XGINew_GetReg1(P3d4, 0x6B); /* Insert read command for delay */
 960                         temp2 &= 0xF0;
 961                         temp2 += 0x10;
 962                 }
 963         }
 964
 965         temp2 = 0;
 966         for (i = 0; i < 4; i++) {
 967                 temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */
 968                 for (j = 0; j < 4; j++) {
 969                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 970                         temp2 |= temp1;
 971                         XGINew_SetReg1(P3d4, 0x6E, temp2);
 972                         XGINew_GetReg1(P3d4, 0x6E); /* Insert read command for delay */
 973                         temp2 &= 0xF0;
 974                         temp2 += 0x10;
 975                 }
 976         }
 977
 978         temp3 = 0;
 979         for (k = 0; k < 4; k++) {
 980                 XGINew_SetRegANDOR(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */
 981                 temp2 = 0;
 982                 for (i = 0; i < 8; i++) {
 983                         temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */
 984                         for (j = 0; j < 4; j++) {
 985                                 temp1 = (temp >> (2 * j)) & 0x03;
 986                                 temp2 |= temp1;
 987                                 XGINew_SetReg1(P3d4, 0x6F, temp2);
 988                                 XGINew_GetReg1(P3d4, 0x6F); /* Insert read command for delay */
 989                                 temp2 &= 0xF8;
 990                                 temp2 += 0x08;
 991                         }
 992                 }
 993                 temp3 += 0x01;
 994         }
 995
 996         XGINew_SetReg1(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
 997         XGINew_SetReg1(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
 998
 999         temp2 = 0x80;
1000         temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */
1001         for (j = 0; j < 4; j++) {
1002                 temp1 = (temp >> (2 * j)) & 0x03;
1003                 temp2 |= temp1;
1004                 XGINew_SetReg1(P3d4, 0x89, temp2);
1005                 XGINew_GetReg1(P3d4, 0x89); /* Insert read command for delay */
1006                 temp2 &= 0xF0;
1007                 temp2 += 0x10;
1008         }
1009
1010         temp = pVBInfo->CR89[XGINew_RAMType][1];
1011         temp1 = temp & 0x03;
1012         temp2 |= temp1;
1013         XGINew_SetReg1(P3d4, 0x89, temp2);
1014
1015         temp = pVBInfo->CR40[3][XGINew_RAMType];
1016         temp1 = temp & 0x0F;
1017         temp2 = (temp >> 4) & 0x07;
1018         temp3 = temp & 0x80;
1019         XGINew_SetReg1(P3d4, 0x45, temp1); /* CR45 */
1020         XGINew_SetReg1(P3d4, 0x99, temp2); /* CR99 */
1021         XGINew_SetRegOR(P3d4, 0x40, temp3); /* CR40_D[7] */
1022         XGINew_SetReg1(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
1023
1024         if (HwDeviceExtension->jChipType == XG27)
1025                 XGINew_SetReg1(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
1026
1027         for (j = 0; j <= 6; j++)
1028                 XGINew_SetReg1(P3d4, (0x90 + j),
1029                                 pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */
1030
1031         for (j = 0; j <= 2; j++)
1032                 XGINew_SetReg1(P3d4, (0xC3 + j),
1033                                 pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */
1034
1035         for (j = 0; j < 2; j++)
1036                 XGINew_SetReg1(P3d4, (0x8A + j),
1037                                 pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */
1038
1039         if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42))
1040                 XGINew_SetReg1(P3d4, 0x8C, 0x87);
1041
1042         XGINew_SetReg1(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
1043
1044         XGINew_SetReg1(P3d4, 0x83, 0x09); /* CR83 */
1045         XGINew_SetReg1(P3d4, 0x87, 0x00); /* CR87 */
1046         XGINew_SetReg1(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
1047         if (XGINew_RAMType) {
1048                 /* XGINew_SetReg1(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
1049                 XGINew_SetReg1(P3c4, 0x17, 0x80); /* SR17 DDRII */
1050                 if (HwDeviceExtension->jChipType == XG27)
1051                         XGINew_SetReg1(P3c4, 0x17, 0x02); /* SR17 DDRII */
1052
1053         } else {
1054                 XGINew_SetReg1(P3c4, 0x17, 0x00); /* SR17 DDR */
1055         }
1056         XGINew_SetReg1(P3c4, 0x1A, 0x87); /* SR1A */
1057
1058         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1059         if (temp == 0) {
1060                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
1061         } else {
1062                 XGINew_SetReg1(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
1063                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
1064         }
1065         XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
1066 }
1067
1068 static void XGINew_DDR_MRS(struct vb_device_info *pVBInfo)
1069 {
1070         unsigned short data;
1071
1072         volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1073
1074         /* SR16 <- 1F,DF,2F,AF */
1075         /* yriver modified SR16 <- 0F,DF,0F,AF */
1076         /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1077         data = pVideoMemory[0xFB];
1078         /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x16); */
1079
1080         data &= 0x0F;
1081         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1082         data |= 0xC0;
1083         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1084         data &= 0x0F;
1085         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1086         data |= 0x80;
1087         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1088         data &= 0x0F;
1089         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1090         data |= 0xD0;
1091         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1092         data &= 0x0F;
1093         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1094         data |= 0xA0;
1095         XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1096         /*
1097         else {
1098                 data &= 0x0F;
1099                 data |= 0x10;
1100                 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1101
1102                 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) {
1103                         data &= 0x0F;
1104                 }
1105
1106                 data |= 0xC0;
1107                 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1108
1109                 data &= 0x0F;
1110                 data |= 0x20;
1111                 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1112                 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) {
1113                         data &= 0x0F;
1114                 }
1115
1116                 data |= 0x80;
1117                 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1118         }
1119         */
1120 }
1121
1122 /* check if read cache pointer is correct */
1123
1124 static void XGINew_VerifyMclk(struct xgi_hw_device_info *HwDeviceExtension,
1125                 struct vb_device_info *pVBInfo)
1126 {
1127         unsigned char *pVideoMemory = pVBInfo->FBAddr;
1128         unsigned char i, j;
1129         unsigned short Temp, SR21;
1130
1131         pVideoMemory[0] = 0xaa; /* alan */
1132         pVideoMemory[16] = 0x55; /* note: PCI read cache is off */
1133
1134         if ((pVideoMemory[0] != 0xaa) || (pVideoMemory[16] != 0x55)) {
1135                 for (i = 0, j = 16; i < 2; i++, j += 16) {
1136                         SR21 = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1137                         Temp = SR21 & 0xFB; /* disable PCI post write buffer empty gating */
1138                         XGINew_SetReg1(pVBInfo->P3c4, 0x21, Temp);
1139
1140                         Temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3C);
1141                         Temp |= 0x01; /* MCLK reset */
1142
1143                         Temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3C);
1144                         Temp &= 0xFE; /* MCLK normal operation */
1145
1146                         XGINew_SetReg1(pVBInfo->P3c4, 0x21, SR21);
1147
1148                         pVideoMemory[16 + j] = j;
1149                         if (pVideoMemory[16 + j] == j) {
1150                                 pVideoMemory[j] = j;
1151                                 break;
1152                         }
1153                 }
1154         }
1155 }
1156
1157 void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1158                 struct vb_device_info *pVBInfo)
1159 {
1160         unsigned short data;
1161
1162         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1163         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1164
1165         XGISetModeNew(HwDeviceExtension, 0x2e);
1166
1167         data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1168         XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
1169         XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1170
1171         /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x1); */
1172         /* data |= 0x20 ; */
1173         /* XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1174         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1175         data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1176         XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
1177 }
1178
1179 void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *HwDeviceExtension,
1180                 struct vb_device_info *pVBInfo)
1181 {
1182         unsigned short data;
1183         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase, pVBInfo->FBAddr
1184                         = HwDeviceExtension->pjVideoMemoryAddress;
1185 #ifdef XGI301
1186         /* XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x40); */
1187 #endif
1188
1189 #ifdef XGI302   /* alan,should change value */
1190         XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x4D);
1191         XGINew_SetReg1(pVBInfo->P3d4, 0x31, 0xc0);
1192         XGINew_SetReg1(pVBInfo->P3d4, 0x34, 0x3F);
1193 #endif
1194
1195         XGISetModeNew(HwDeviceExtension, 0x2e);
1196
1197         data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1198         XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
1199
1200         data = XGINew_GetReg1(pVBInfo->P3c4, 0x1);
1201         data |= 0x20;
1202         XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); /* Turn OFF Display */
1203
1204         data = XGINew_GetReg1(pVBInfo->P3c4, 0x16);
1205
1206         XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short) (data | 0x0F)); /* assume lowest speed DRAM */
1207
1208         XGINew_SetDRAMModeRegister(pVBInfo);
1209         XGINew_DisableRefresh(HwDeviceExtension, pVBInfo);
1210         XGINew_CheckBusWidth_310(pVBInfo);
1211         XGINew_VerifyMclk(HwDeviceExtension, pVBInfo); /* alan 2000/7/3 */
1212
1213         if (XGINew_Get310DRAMType(pVBInfo) < 2)
1214                 XGINew_SDRSizing(pVBInfo);
1215         else
1216                 XGINew_DDRSizing(pVBInfo);
1217
1218         XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */
1219
1220         XGINew_EnableRefresh(HwDeviceExtension, pVBInfo);
1221         data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1222         XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
1223 }
1224
1225 void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension)
1226 {
1227         unsigned char data;
1228         struct vb_device_info VBINF;
1229         struct vb_device_info *pVBInfo = &VBINF;
1230         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1231         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1232         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1233         pVBInfo->ISXPDOS = 0;
1234
1235         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1236         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1237         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1238         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1239         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1240         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1241         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1242         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1243         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1244         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1245         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1246         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1247         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1248         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1249         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1250         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1251         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1252         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1253                 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
1254
1255         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1256
1257         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1258
1259         if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0) {
1260                 data = (XGINew_GetReg1(pVBInfo->P3c4, 0x39) & 0x02) >> 1;
1261                 if (data == 0x01)
1262                         XGINew_DDR2x_MRS_340(pVBInfo->P3c4, pVBInfo);
1263                 else
1264                         XGINew_DDR1x_MRS_340(pVBInfo->P3c4, pVBInfo);
1265         } else {
1266                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1267         }
1268         XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03);
1269 }
1270
1271 void XGINew_SetDRAMModeRegister(struct vb_device_info *pVBInfo)
1272 {
1273         if (XGINew_Get310DRAMType(pVBInfo) < 2) {
1274                 XGINew_SDR_MRS(pVBInfo);
1275         } else {
1276                 /* SR16 <- 0F,CF,0F,8F */
1277                 XGINew_DDR_MRS(pVBInfo);
1278         }
1279 }
1280
1281 void XGINew_DisableRefresh(struct xgi_hw_device_info *HwDeviceExtension,
1282                 struct vb_device_info *pVBInfo)
1283 {
1284         unsigned short data;
1285
1286         data = XGINew_GetReg1(pVBInfo->P3c4, 0x1B);
1287         data &= 0xF8;
1288         XGINew_SetReg1(pVBInfo->P3c4, 0x1B, data);
1289
1290 }
1291
1292 void XGINew_EnableRefresh(struct xgi_hw_device_info *HwDeviceExtension,
1293                 struct vb_device_info *pVBInfo)
1294 {
1295
1296         XGINew_SetReg1(pVBInfo->P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
1297
1298 }
1299
1300 static void XGINew_DisableChannelInterleaving(int index,
1301                 unsigned short XGINew_DDRDRAM_TYPE[][5],
1302                 struct vb_device_info *pVBInfo)
1303 {
1304         unsigned short data;
1305
1306         data = XGINew_GetReg1(pVBInfo->P3c4, 0x15);
1307         data &= 0x1F;
1308
1309         switch (XGINew_DDRDRAM_TYPE[index][3]) {
1310         case 64:
1311                 data |= 0;
1312                 break;
1313         case 32:
1314                 data |= 0x20;
1315                 break;
1316         case 16:
1317                 data |= 0x40;
1318                 break;
1319         case 4:
1320                 data |= 0x60;
1321                 break;
1322         default:
1323                 break;
1324         }
1325         XGINew_SetReg1(pVBInfo->P3c4, 0x15, data);
1326 }
1327
1328 static void XGINew_SetDRAMSizingType(int index,
1329                 unsigned short DRAMTYPE_TABLE[][5],
1330                 struct vb_device_info *pVBInfo)
1331 {
1332         unsigned short data;
1333
1334         data = DRAMTYPE_TABLE[index][4];
1335         XGINew_SetRegANDOR(pVBInfo->P3c4, 0x13, 0x80, data);
1336         DelayUS(15);
1337         /* should delay 50 ns */
1338 }
1339
1340 void XGINew_CheckBusWidth_310(struct vb_device_info *pVBInfo)
1341 {
1342         unsigned short data;
1343         volatile unsigned long *pVideoMemory;
1344
1345         pVideoMemory = (unsigned long *) pVBInfo->FBAddr;
1346
1347         if (XGINew_Get310DRAMType(pVBInfo) < 2) {
1348                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x00);
1349                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x12);
1350                 /* should delay */
1351                 XGINew_SDR_MRS(pVBInfo);
1352
1353                 XGINew_ChannelAB = 0;
1354                 XGINew_DataBusWidth = 128;
1355                 pVideoMemory[0] = 0x01234567L;
1356                 pVideoMemory[1] = 0x456789ABL;
1357                 pVideoMemory[2] = 0x89ABCDEFL;
1358                 pVideoMemory[3] = 0xCDEF0123L;
1359                 pVideoMemory[4] = 0x55555555L;
1360                 pVideoMemory[5] = 0x55555555L;
1361                 pVideoMemory[6] = 0xFFFFFFFFL;
1362                 pVideoMemory[7] = 0xFFFFFFFFL;
1363
1364                 if ((pVideoMemory[3] != 0xCDEF0123L) || (pVideoMemory[2]
1365                                 != 0x89ABCDEFL)) {
1366                         /* ChannelA64Bit */
1367                         XGINew_DataBusWidth = 64;
1368                         XGINew_ChannelAB = 0;
1369                         data = XGINew_GetReg1(pVBInfo->P3c4, 0x14);
1370                         XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1371                                         (unsigned short) (data & 0xFD));
1372                 }
1373
1374                 if ((pVideoMemory[1] != 0x456789ABL) || (pVideoMemory[0]
1375                                 != 0x01234567L)) {
1376                         /* ChannelB64Bit */
1377                         XGINew_DataBusWidth = 64;
1378                         XGINew_ChannelAB = 1;
1379                         data = XGINew_GetReg1(pVBInfo->P3c4, 0x14);
1380                         XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1381                                         (unsigned short) ((data & 0xFD) | 0x01));
1382                 }
1383
1384                 return;
1385         } else {
1386                 /* DDR Dual channel */
1387                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x00);
1388                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x02); /* Channel A, 64bit */
1389                 /* should delay */
1390                 XGINew_DDR_MRS(pVBInfo);
1391
1392                 XGINew_ChannelAB = 0;
1393                 XGINew_DataBusWidth = 64;
1394                 pVideoMemory[0] = 0x01234567L;
1395                 pVideoMemory[1] = 0x456789ABL;
1396                 pVideoMemory[2] = 0x89ABCDEFL;
1397                 pVideoMemory[3] = 0xCDEF0123L;
1398                 pVideoMemory[4] = 0x55555555L;
1399                 pVideoMemory[5] = 0x55555555L;
1400                 pVideoMemory[6] = 0xAAAAAAAAL;
1401                 pVideoMemory[7] = 0xAAAAAAAAL;
1402
1403                 if (pVideoMemory[1] == 0x456789ABL) {
1404                         if (pVideoMemory[0] == 0x01234567L) {
1405                                 /* Channel A 64bit */
1406                                 return;
1407                         }
1408                 } else {
1409                         if (pVideoMemory[0] == 0x01234567L) {
1410                                 /* Channel A 32bit */
1411                                 XGINew_DataBusWidth = 32;
1412                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x00);
1413                                 return;
1414                         }
1415                 }
1416
1417                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x03); /* Channel B, 64bit */
1418                 XGINew_DDR_MRS(pVBInfo);
1419
1420                 XGINew_ChannelAB = 1;
1421                 XGINew_DataBusWidth = 64;
1422                 pVideoMemory[0] = 0x01234567L;
1423                 pVideoMemory[1] = 0x456789ABL;
1424                 pVideoMemory[2] = 0x89ABCDEFL;
1425                 pVideoMemory[3] = 0xCDEF0123L;
1426                 pVideoMemory[4] = 0x55555555L;
1427                 pVideoMemory[5] = 0x55555555L;
1428                 pVideoMemory[6] = 0xAAAAAAAAL;
1429                 pVideoMemory[7] = 0xAAAAAAAAL;
1430
1431                 if (pVideoMemory[1] == 0x456789ABL) {
1432                         /* Channel B 64 */
1433                         if (pVideoMemory[0] == 0x01234567L) {
1434                                 /* Channel B 64bit */
1435                                 return;
1436                         } else {
1437                                 /* error */
1438                         }
1439                 } else {
1440                         if (pVideoMemory[0] == 0x01234567L) {
1441                                 /* Channel B 32 */
1442                                 XGINew_DataBusWidth = 32;
1443                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x01);
1444                         } else {
1445                                 /* error */
1446                         }
1447                 }
1448         }
1449 }
1450
1451 static int XGINew_SetRank(int index, unsigned char RankNo,
1452                 unsigned char XGINew_ChannelAB,
1453                 unsigned short DRAMTYPE_TABLE[][5],
1454                 struct vb_device_info *pVBInfo)
1455 {
1456         unsigned short data;
1457         int RankSize;
1458
1459         if ((RankNo == 2) && (DRAMTYPE_TABLE[index][0] == 2))
1460                 return 0;
1461
1462         RankSize = DRAMTYPE_TABLE[index][3] / 2 * XGINew_DataBusWidth / 32;
1463
1464         if ((RankNo * RankSize) <= 128) {
1465                 data = 0;
1466
1467                 while ((RankSize >>= 1) > 0)
1468                         data += 0x10;
1469
1470                 data |= (RankNo - 1) << 2;
1471                 data |= (XGINew_DataBusWidth / 64) & 2;
1472                 data |= XGINew_ChannelAB;
1473                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, data);
1474                 /* should delay */
1475                 XGINew_SDR_MRS(pVBInfo);
1476                 return 1;
1477         } else {
1478                 return 0;
1479         }
1480 }
1481
1482 static int XGINew_SetDDRChannel(int index, unsigned char ChannelNo,
1483                 unsigned char XGINew_ChannelAB,
1484                 unsigned short DRAMTYPE_TABLE[][5],
1485                 struct vb_device_info *pVBInfo)
1486 {
1487         unsigned short data;
1488         int RankSize;
1489
1490         RankSize = DRAMTYPE_TABLE[index][3] / 2 * XGINew_DataBusWidth / 32;
1491         /* RankSize = DRAMTYPE_TABLE[index][3]; */
1492         if (ChannelNo * RankSize <= 128) {
1493                 data = 0;
1494                 while ((RankSize >>= 1) > 0)
1495                         data += 0x10;
1496
1497                 if (ChannelNo == 2)
1498                         data |= 0x0C;
1499
1500                 data |= (XGINew_DataBusWidth / 32) & 2;
1501                 data |= XGINew_ChannelAB;
1502                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, data);
1503                 /* should delay */
1504                 XGINew_DDR_MRS(pVBInfo);
1505                 return 1;
1506         } else {
1507                 return 0;
1508         }
1509 }
1510
1511 static int XGINew_CheckColumn(int index, unsigned short DRAMTYPE_TABLE[][5],
1512                 struct vb_device_info *pVBInfo)
1513 {
1514         int i;
1515         unsigned long Increment, Position;
1516
1517         /* Increment = 1 << (DRAMTYPE_TABLE[index][2] + XGINew_DataBusWidth / 64 + 1); */
1518         Increment = 1 << (10 + XGINew_DataBusWidth / 64);
1519
1520         for (i = 0, Position = 0; i < 2; i++) {
1521                 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1522                 Position += Increment;
1523         }
1524
1525         for (i = 0, Position = 0; i < 2; i++) {
1526                 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1527                 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1528                         return 0;
1529                 Position += Increment;
1530         }
1531         return 1;
1532 }
1533
1534 static int XGINew_CheckBanks(int index, unsigned short DRAMTYPE_TABLE[][5],
1535                 struct vb_device_info *pVBInfo)
1536 {
1537         int i;
1538         unsigned long Increment, Position;
1539
1540         Increment = 1 << (DRAMTYPE_TABLE[index][2] + XGINew_DataBusWidth / 64 + 2);
1541
1542         for (i = 0, Position = 0; i < 4; i++) {
1543                 /* pVBInfo->FBAddr[Position] = Position; */
1544                 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1545                 Position += Increment;
1546         }
1547
1548         for (i = 0, Position = 0; i < 4; i++) {
1549                 /* if (pVBInfo->FBAddr[Position] != Position) */
1550                 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1551                         return 0;
1552                 Position += Increment;
1553         }
1554         return 1;
1555 }
1556
1557 static int XGINew_CheckRank(int RankNo, int index,
1558                 unsigned short DRAMTYPE_TABLE[][5],
1559                 struct vb_device_info *pVBInfo)
1560 {
1561         int i;
1562         unsigned long Increment, Position;
1563
1564         Increment = 1 << (DRAMTYPE_TABLE[index][2] + DRAMTYPE_TABLE[index][1]
1565                         + DRAMTYPE_TABLE[index][0] + XGINew_DataBusWidth / 64
1566                         + RankNo);
1567
1568         for (i = 0, Position = 0; i < 2; i++) {
1569                 /* pVBInfo->FBAddr[Position] = Position; */
1570                 /* *((unsigned long *)(pVBInfo->FBAddr)) = Position; */
1571                 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1572                 Position += Increment;
1573         }
1574
1575         for (i = 0, Position = 0; i < 2; i++) {
1576                 /* if (pVBInfo->FBAddr[Position] != Position) */
1577                 /* if ((*(unsigned long *)(pVBInfo->FBAddr)) != Position) */
1578                 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1579                         return 0;
1580                 Position += Increment;
1581         }
1582         return 1;
1583 }
1584
1585 static int XGINew_CheckDDRRank(int RankNo, int index,
1586                 unsigned short DRAMTYPE_TABLE[][5],
1587                 struct vb_device_info *pVBInfo)
1588 {
1589         unsigned long Increment, Position;
1590         unsigned short data;
1591
1592         Increment = 1 << (DRAMTYPE_TABLE[index][2] + DRAMTYPE_TABLE[index][1]
1593                         + DRAMTYPE_TABLE[index][0] + XGINew_DataBusWidth / 64
1594                         + RankNo);
1595
1596         Increment += Increment / 2;
1597
1598         Position = 0;
1599         *((unsigned long *) (pVBInfo->FBAddr + Position + 0)) = 0x01234567;
1600         *((unsigned long *) (pVBInfo->FBAddr + Position + 1)) = 0x456789AB;
1601         *((unsigned long *) (pVBInfo->FBAddr + Position + 2)) = 0x55555555;
1602         *((unsigned long *) (pVBInfo->FBAddr + Position + 3)) = 0x55555555;
1603         *((unsigned long *) (pVBInfo->FBAddr + Position + 4)) = 0xAAAAAAAA;
1604         *((unsigned long *) (pVBInfo->FBAddr + Position + 5)) = 0xAAAAAAAA;
1605
1606         if ((*(unsigned long *) (pVBInfo->FBAddr + 1)) == 0x456789AB)
1607                 return 1;
1608
1609         if ((*(unsigned long *) (pVBInfo->FBAddr + 0)) == 0x01234567)
1610                 return 0;
1611
1612         data = XGINew_GetReg1(pVBInfo->P3c4, 0x14);
1613         data &= 0xF3;
1614         data |= 0x0E;
1615         XGINew_SetReg1(pVBInfo->P3c4, 0x14, data);
1616         data = XGINew_GetReg1(pVBInfo->P3c4, 0x15);
1617         data += 0x20;
1618         XGINew_SetReg1(pVBInfo->P3c4, 0x15, data);
1619
1620         return 1;
1621 }
1622
1623 static int XGINew_CheckRanks(int RankNo, int index,
1624                 unsigned short DRAMTYPE_TABLE[][5],
1625                 struct vb_device_info *pVBInfo)
1626 {
1627         int r;
1628
1629         for (r = RankNo; r >= 1; r--) {
1630                 if (!XGINew_CheckRank(r, index, DRAMTYPE_TABLE, pVBInfo))
1631                         return 0;
1632         }
1633
1634         if (!XGINew_CheckBanks(index, DRAMTYPE_TABLE, pVBInfo))
1635                 return 0;
1636
1637         if (!XGINew_CheckColumn(index, DRAMTYPE_TABLE, pVBInfo))
1638                 return 0;
1639
1640         return 1;
1641 }
1642
1643 static int XGINew_CheckDDRRanks(int RankNo, int index,
1644                 unsigned short DRAMTYPE_TABLE[][5],
1645                 struct vb_device_info *pVBInfo)
1646 {
1647         int r;
1648
1649         for (r = RankNo; r >= 1; r--) {
1650                 if (!XGINew_CheckDDRRank(r, index, DRAMTYPE_TABLE, pVBInfo))
1651                         return 0;
1652         }
1653
1654         if (!XGINew_CheckBanks(index, DRAMTYPE_TABLE, pVBInfo))
1655                 return 0;
1656
1657         if (!XGINew_CheckColumn(index, DRAMTYPE_TABLE, pVBInfo))
1658                 return 0;
1659
1660         return 1;
1661 }
1662
1663 int XGINew_SDRSizing(struct vb_device_info *pVBInfo)
1664 {
1665         int i;
1666         unsigned char j;
1667
1668         for (i = 0; i < 13; i++) {
1669                 XGINew_SetDRAMSizingType(i, XGINew_SDRDRAM_TYPE, pVBInfo);
1670
1671                 for (j = 2; j > 0; j--) {
1672                         if (!XGINew_SetRank(i, (unsigned char) j, XGINew_ChannelAB, XGINew_SDRDRAM_TYPE, pVBInfo)) {
1673                                 continue;
1674                         } else {
1675                                 if (XGINew_CheckRanks(j, i, XGINew_SDRDRAM_TYPE, pVBInfo))
1676                                         return 1;
1677                         }
1678                 }
1679         }
1680         return 0;
1681 }
1682
1683 static unsigned short XGINew_SetDRAMSizeReg(int index,
1684                 unsigned short DRAMTYPE_TABLE[][5],
1685                 struct vb_device_info *pVBInfo)
1686 {
1687         unsigned short data = 0, memsize = 0;
1688         int RankSize;
1689         unsigned char ChannelNo;
1690
1691         RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
1692         data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
1693         data &= 0x80;
1694
1695         if (data == 0x80)
1696                 RankSize *= 2;
1697
1698         data = 0;
1699
1700         if (XGINew_ChannelAB == 3)
1701                 ChannelNo = 4;
1702         else
1703                 ChannelNo = XGINew_ChannelAB;
1704
1705         if (ChannelNo * RankSize <= 256) {
1706                 while ((RankSize >>= 1) > 0)
1707                         data += 0x10;
1708
1709                 memsize = data >> 4;
1710
1711                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
1712                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
1713
1714                 /* data |= XGINew_ChannelAB << 2; */
1715                 /* data |= (XGINew_DataBusWidth / 64) << 1; */
1716                 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
1717
1718                 /* should delay */
1719                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
1720         }
1721         return memsize;
1722 }
1723
1724 static unsigned short XGINew_SetDRAMSize20Reg(int index,
1725                 unsigned short DRAMTYPE_TABLE[][5],
1726                 struct vb_device_info *pVBInfo)
1727 {
1728         unsigned short data = 0, memsize = 0;
1729         int RankSize;
1730         unsigned char ChannelNo;
1731
1732         RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
1733         data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
1734         data &= 0x80;
1735
1736         if (data == 0x80)
1737                 RankSize *= 2;
1738
1739         data = 0;
1740
1741         if (XGINew_ChannelAB == 3)
1742                 ChannelNo = 4;
1743         else
1744                 ChannelNo = XGINew_ChannelAB;
1745
1746         if (ChannelNo * RankSize <= 256) {
1747                 while ((RankSize >>= 1) > 0)
1748                         data += 0x10;
1749
1750                 memsize = data >> 4;
1751
1752                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
1753                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
1754                 DelayUS(15);
1755
1756                 /* data |= XGINew_ChannelAB << 2; */
1757                 /* data |= (XGINew_DataBusWidth / 64) << 1; */
1758                 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
1759
1760                 /* should delay */
1761                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
1762         }
1763         return memsize;
1764 }
1765
1766 static int XGINew_ReadWriteRest(unsigned short StopAddr,
1767                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
1768 {
1769         int i;
1770         unsigned long Position = 0;
1771
1772         *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1773
1774         for (i = StartAddr; i <= StopAddr; i++) {
1775                 Position = 1 << i;
1776                 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1777         }
1778
1779         DelayUS(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
1780
1781         Position = 0;
1782
1783         if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1784                 return 0;
1785
1786         for (i = StartAddr; i <= StopAddr; i++) {
1787                 Position = 1 << i;
1788                 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1789                         return 0;
1790         }
1791         return 1;
1792 }
1793
1794 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
1795 {
1796         unsigned char data;
1797
1798         data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
1799
1800         if ((data & 0x10) == 0) {
1801                 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39);
1802                 data = (data & 0x02) >> 1;
1803                 return data;
1804         } else {
1805                 return data & 0x01;
1806         }
1807 }
1808
1809 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
1810                 struct vb_device_info *pVBInfo)
1811 {
1812         unsigned char data;
1813
1814         switch (HwDeviceExtension->jChipType) {
1815         case XG20:
1816         case XG21:
1817                 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
1818                 data = data & 0x01;
1819                 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
1820
1821                 if (data == 0) { /* Single_32_16 */
1822
1823                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
1824                                         > 0x1000000) {
1825
1826                                 XGINew_DataBusWidth = 32; /* 32 bits */
1827                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
1828                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
1829                                 DelayUS(15);
1830
1831                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1832                                         return;
1833
1834                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
1835                                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
1836                                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
1837                                         DelayUS(15);
1838
1839                                         if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
1840                                                 return;
1841                                 }
1842                         }
1843
1844                         if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
1845                                 XGINew_DataBusWidth = 16; /* 16 bits */
1846                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
1847                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41);
1848                                 DelayUS(15);
1849
1850                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1851                                         return;
1852                                 else
1853                                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31);
1854                                 DelayUS(15);
1855                         }
1856
1857                 } else { /* Dual_16_8 */
1858                         if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
1859
1860                                 XGINew_DataBusWidth = 16; /* 16 bits */
1861                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
1862                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
1863                                 DelayUS(15);
1864
1865                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1866                                         return;
1867
1868                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
1869                                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
1870                                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
1871                                         DelayUS(15);
1872
1873                                         if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
1874                                                 return;
1875                                 }
1876                         }
1877
1878                         if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
1879                                 XGINew_DataBusWidth = 8; /* 8 bits */
1880                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
1881                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
1882                                 DelayUS(15);
1883
1884                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
1885                                         return;
1886                                 else
1887                                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
1888                                 DelayUS(15);
1889                         }
1890                 }
1891                 break;
1892
1893         case XG27:
1894                 XGINew_DataBusWidth = 16; /* 16 bits */
1895                 XGINew_ChannelAB = 1; /* Single channel */
1896                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
1897                 break;
1898         case XG41:
1899                 if (XGINew_CheckFrequence(pVBInfo) == 1) {
1900                         XGINew_DataBusWidth = 32; /* 32 bits */
1901                         XGINew_ChannelAB = 3; /* Quad Channel */
1902                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1903                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
1904
1905                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
1906                                 return;
1907
1908                         XGINew_ChannelAB = 2; /* Dual channels */
1909                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
1910
1911                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1912                                 return;
1913
1914                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x49);
1915
1916                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1917                                 return;
1918
1919                         XGINew_ChannelAB = 3;
1920                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1921                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
1922
1923                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1924                                 return;
1925
1926                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
1927
1928                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
1929                                 return;
1930                         else
1931                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x39);
1932                 } else { /* DDR */
1933                         XGINew_DataBusWidth = 64; /* 64 bits */
1934                         XGINew_ChannelAB = 2; /* Dual channels */
1935                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1936                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
1937
1938                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
1939                                 return;
1940
1941                         XGINew_ChannelAB = 1; /* Single channels */
1942                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
1943
1944                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1945                                 return;
1946
1947                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x53);
1948
1949                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1950                                 return;
1951
1952                         XGINew_ChannelAB = 2; /* Dual channels */
1953                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1954                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
1955
1956                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1957                                 return;
1958
1959                         XGINew_ChannelAB = 1; /* Single channels */
1960                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
1961
1962                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
1963                                 return;
1964                         else
1965                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x43);
1966                 }
1967
1968                 break;
1969
1970         case XG42:
1971                 /*
1972                  XG42 SR14 D[3] Reserve
1973                  D[2] = 1, Dual Channel
1974                  = 0, Single Channel
1975
1976                  It's Different from Other XG40 Series.
1977                  */
1978                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
1979                         XGINew_DataBusWidth = 32; /* 32 bits */
1980                         XGINew_ChannelAB = 2; /* 2 Channel */
1981                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1982                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x44);
1983
1984                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1985                                 return;
1986
1987                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1988                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x34);
1989                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1990                                 return;
1991
1992                         XGINew_ChannelAB = 1; /* Single Channel */
1993                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1994                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x40);
1995
1996                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1997                                 return;
1998                         else {
1999                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
2000                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30);
2001                         }
2002                 } else { /* DDR */
2003                         XGINew_DataBusWidth = 64; /* 64 bits */
2004                         XGINew_ChannelAB = 1; /* 1 channels */
2005                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
2006                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
2007
2008                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
2009                                 return;
2010                         else {
2011                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
2012                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
2013                         }
2014                 }
2015
2016                 break;
2017
2018         default: /* XG40 */
2019
2020                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
2021                         XGINew_DataBusWidth = 32; /* 32 bits */
2022                         XGINew_ChannelAB = 3;
2023                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
2024                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
2025
2026                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
2027                                 return;
2028
2029                         XGINew_ChannelAB = 2; /* 2 channels */
2030                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
2031
2032                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
2033                                 return;
2034
2035                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
2036                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
2037
2038                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
2039                                 XGINew_ChannelAB = 3; /* 4 channels */
2040                         } else {
2041                                 XGINew_ChannelAB = 2; /* 2 channels */
2042                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
2043                         }
2044                 } else { /* DDR */
2045                         XGINew_DataBusWidth = 64; /* 64 bits */
2046                         XGINew_ChannelAB = 2; /* 2 channels */
2047                         XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
2048                         XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
2049
2050                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
2051                                 return;
2052                         } else {
2053                                 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
2054                                 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
2055                         }
2056                 }
2057                 break;
2058         }
2059 }
2060
2061 int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
2062                 struct vb_device_info *pVBInfo)
2063 {
2064         int i;
2065         unsigned short memsize, addr;
2066
2067         XGINew_SetReg1(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
2068         XGINew_SetReg1(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
2069         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
2070
2071         if (HwDeviceExtension->jChipType >= XG20) {
2072                 for (i = 0; i < 12; i++) {
2073                         XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
2074                         memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
2075                         if (memsize == 0)
2076                                 continue;
2077
2078                         addr = memsize + (XGINew_ChannelAB - 2) + 20;
2079                         if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
2080                                 continue;
2081
2082                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
2083                                 return 1;
2084                 }
2085         } else {
2086                 for (i = 0; i < 4; i++) {
2087                         XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
2088                         memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
2089
2090                         if (memsize == 0)
2091                                 continue;
2092
2093                         addr = memsize + (XGINew_ChannelAB - 2) + 20;
2094                         if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
2095                                 continue;
2096
2097                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
2098                                 return 1;
2099                 }
2100         }
2101         return 0;
2102 }
2103
2104 int XGINew_DDRSizing(struct vb_device_info *pVBInfo)
2105 {
2106         int i;
2107         unsigned char j;
2108
2109         for (i = 0; i < 4; i++) {
2110                 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE, pVBInfo);
2111                 XGINew_DisableChannelInterleaving(i, XGINew_DDRDRAM_TYPE, pVBInfo);
2112                 for (j = 2; j > 0; j--) {
2113                         XGINew_SetDDRChannel(i, j, XGINew_ChannelAB, XGINew_DDRDRAM_TYPE, pVBInfo);
2114                         if (!XGINew_SetRank(i, (unsigned char) j, XGINew_ChannelAB, XGINew_DDRDRAM_TYPE, pVBInfo)) {
2115                                 continue;
2116                         } else {
2117                                 if (XGINew_CheckDDRRanks(j, i, XGINew_DDRDRAM_TYPE, pVBInfo))
2118                                         return 1;
2119                         }
2120                 }
2121         }
2122         return 0;
2123 }
2124
2125 void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
2126                 struct vb_device_info *pVBInfo)
2127 {
2128
2129         XGINew_SetReg1(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
2130         XGINew_SetReg1(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
2131         XGINew_SetReg1(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
2132
2133         XGINew_SetReg1(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
2134         XGINew_SetReg1(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
2135         XGINew_SetReg1(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
2136
2137         /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2138         /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2139         if (HwDeviceExtension->jChipType == XG42) {
2140                 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
2141                                 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
2142                                 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
2143                                                 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
2144                                         || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
2145                                                 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
2146                         XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
2147         }
2148 }
2149
2150 unsigned char ChkLFB(struct vb_device_info *pVBInfo)
2151 {
2152         if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4, 0x78))
2153                 return 1;
2154         else
2155                 return 0;
2156 }
2157
2158 /* --------------------------------------------------------------------- */
2159 /* input : dx ,valid value : CR or second chip's CR */
2160 /*  */
2161 /* SetPowerConsume : */
2162 /* Description: reduce 40/43 power consumption in first chip or */
2163 /* in second chip, assume CR A1 D[6]="1" in this case */
2164 /* output : none */
2165 /* --------------------------------------------------------------------- */
2166 void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
2167                 unsigned long XGI_P3d4Port)
2168 {
2169         unsigned long lTemp;
2170         unsigned char bTemp;
2171
2172         HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x08, 0, &lTemp); /* Get */
2173         if ((lTemp & 0xFF) == 0) {
2174                 /* set CR58 D[5]=0 D[3]=0 */
2175                 XGINew_SetRegAND(XGI_P3d4Port, 0x58, 0xD7);
2176                 bTemp = (unsigned char) XGINew_GetReg1(XGI_P3d4Port, 0xCB);
2177                 if (bTemp & 0x20) {
2178                         if (!(bTemp & 0x10))
2179                                 XGINew_SetRegANDOR(XGI_P3d4Port, 0x58, 0xD7, 0x20); /* CR58 D[5]=1 D[3]=0 */
2180                         else
2181                                 XGINew_SetRegANDOR(XGI_P3d4Port, 0x58, 0xD7, 0x08); /* CR58 D[5]=0 D[3]=1 */
2182
2183                 }
2184
2185         }
2186 }
2187
2188 #if 0
2189 static void XGINew_InitVBIOSData(struct xgi_hw_device_info *HwDeviceExtension,
2190                 struct vb_device_info *pVBInfo)
2191 {
2192
2193         /* unsigned long ROMAddr = (unsigned long) HwDeviceExtension->pjVirtualRomBase; */
2194         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2195         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2196         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
2197         pVBInfo->ISXPDOS = 0;
2198
2199         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2200         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2201         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2202         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2203         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2204         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2205         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2206         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2207         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2208         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2209         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2210         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2211         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2212         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2213         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2214         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2215         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2216         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
2217         XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
2218
2219         switch (HwDeviceExtension->jChipType) {
2220         case XG40:
2221         case XG41:
2222         case XG42:
2223         case XG20:
2224         case XG21:
2225         default:
2226                 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
2227                 return;
2228         }
2229
2230 }
2231 #endif
2232
2233 void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
2234 {
2235         volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
2236         unsigned long i;
2237         unsigned char j, k;
2238         /* Volari customize data area end */
2239
2240         if (ChipType == XG21) {
2241                 pVBInfo->IF_DEF_LVDS = 0;
2242                 if (pVideoMemory[0x65] & 0x1) {
2243                         pVBInfo->IF_DEF_LVDS = 1;
2244                         i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
2245                         j = pVideoMemory[i - 1];
2246                         if (j != 0xff) {
2247                                 k = 0;
2248                                 do {
2249                                         pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
2250                                                 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
2251                                         pVBInfo->XG21_LVDSCapList[k].LVDSHT
2252                                                 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
2253                                         pVBInfo->XG21_LVDSCapList[k].LVDSVT
2254                                                 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
2255                                         pVBInfo->XG21_LVDSCapList[k].LVDSHDE
2256                                                 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
2257                                         pVBInfo->XG21_LVDSCapList[k].LVDSVDE
2258                                                 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
2259                                         pVBInfo->XG21_LVDSCapList[k].LVDSHFP
2260                                                 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
2261                                         pVBInfo->XG21_LVDSCapList[k].LVDSVFP
2262                                                 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
2263                                         pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
2264                                                 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
2265                                         pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
2266                                                 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
2267                                         pVBInfo->XG21_LVDSCapList[k].VCLKData1
2268                                                 = pVideoMemory[i + 18];
2269                                         pVBInfo->XG21_LVDSCapList[k].VCLKData2
2270                                                 = pVideoMemory[i + 19];
2271                                         pVBInfo->XG21_LVDSCapList[k].PSC_S1
2272                                                 = pVideoMemory[i + 20];
2273                                         pVBInfo->XG21_LVDSCapList[k].PSC_S2
2274                                                 = pVideoMemory[i + 21];
2275                                         pVBInfo->XG21_LVDSCapList[k].PSC_S3
2276                                                 = pVideoMemory[i + 22];
2277                                         pVBInfo->XG21_LVDSCapList[k].PSC_S4
2278                                                 = pVideoMemory[i + 23];
2279                                         pVBInfo->XG21_LVDSCapList[k].PSC_S5
2280                                                 = pVideoMemory[i + 24];
2281                                         i += 25;
2282                                         j--;
2283                                         k++;
2284                                 } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct))));
2285                         } else {
2286                                 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
2287                                                 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
2288                                 pVBInfo->XG21_LVDSCapList[0].LVDSHT
2289                                                 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
2290                                 pVBInfo->XG21_LVDSCapList[0].LVDSVT
2291                                                 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
2292                                 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
2293                                                 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
2294                                 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
2295                                                 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
2296                                 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
2297                                                 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
2298                                 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
2299                                                 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
2300                                 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
2301                                                 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
2302                                 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
2303                                                 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
2304                                 pVBInfo->XG21_LVDSCapList[0].VCLKData1
2305                                                 = pVideoMemory[i + 18];
2306                                 pVBInfo->XG21_LVDSCapList[0].VCLKData2
2307                                                 = pVideoMemory[i + 19];
2308                                 pVBInfo->XG21_LVDSCapList[0].PSC_S1
2309                                                 = pVideoMemory[i + 20];
2310                                 pVBInfo->XG21_LVDSCapList[0].PSC_S2
2311                                                 = pVideoMemory[i + 21];
2312                                 pVBInfo->XG21_LVDSCapList[0].PSC_S3
2313                                                 = pVideoMemory[i + 22];
2314                                 pVBInfo->XG21_LVDSCapList[0].PSC_S4
2315                                                 = pVideoMemory[i + 23];
2316                                 pVBInfo->XG21_LVDSCapList[0].PSC_S5
2317                                                 = pVideoMemory[i + 24];
2318                         }
2319                 }
2320         }
2321 }
2322
2323 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
2324 {
2325
2326         XGINew_SetReg1(P3c4, 0x18, 0x01);
2327         XGINew_SetReg1(P3c4, 0x19, 0x40);
2328         XGINew_SetReg1(P3c4, 0x16, 0x00);
2329         XGINew_SetReg1(P3c4, 0x16, 0x80);
2330         DelayUS(60);
2331
2332         XGINew_SetReg1(P3c4, 0x18, 0x00);
2333         XGINew_SetReg1(P3c4, 0x19, 0x40);
2334         XGINew_SetReg1(P3c4, 0x16, 0x00);
2335         XGINew_SetReg1(P3c4, 0x16, 0x80);
2336         DelayUS(60);
2337         XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
2338         /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
2339         XGINew_SetReg1(P3c4, 0x19, 0x01);
2340         XGINew_SetReg1(P3c4, 0x16, 0x03);
2341         XGINew_SetReg1(P3c4, 0x16, 0x83);
2342         DelayUS(1000);
2343         XGINew_SetReg1(P3c4, 0x1B, 0x03);
2344         DelayUS(500);
2345         /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
2346         XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
2347         XGINew_SetReg1(P3c4, 0x19, 0x00);
2348         XGINew_SetReg1(P3c4, 0x16, 0x03);
2349         XGINew_SetReg1(P3c4, 0x16, 0x83);
2350         XGINew_SetReg1(P3c4, 0x1B, 0x00);
2351 }
2352
2353 void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension)
2354 {
2355         struct vb_device_info VBINF;
2356         struct vb_device_info *pVBInfo = &VBINF;
2357         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2358         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2359         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
2360         pVBInfo->ISXPDOS = 0;
2361
2362         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2363         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2364         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2365         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2366         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2367         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2368         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2369         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2370         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2371         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2372         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2373         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2374         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2375         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2376         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2377         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2378         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2379
2380         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
2381
2382         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
2383
2384         if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0)
2385                 XGINew_DDR1x_MRS_XG20(pVBInfo->P3c4, pVBInfo);
2386         else
2387                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
2388
2389         XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03);
2390 }
2391
2392 void XGINew_SetDRAMModeRegister_XG27(
2393                 struct xgi_hw_device_info *HwDeviceExtension)
2394 {
2395         struct vb_device_info VBINF;
2396         struct vb_device_info *pVBInfo = &VBINF;
2397         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2398         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2399         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
2400         pVBInfo->ISXPDOS = 0;
2401
2402         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2403         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2404         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2405         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2406         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2407         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2408         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2409         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2410         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2411         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2412         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2413         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2414         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2415         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2416         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2417         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2418         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2419
2420         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
2421
2422         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
2423
2424         if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0)
2425                 XGINew_DDR1x_MRS_XG20(pVBInfo->P3c4, pVBInfo);
2426         else
2427                 /* XGINew_DDR2_MRS_XG27(HwDeviceExtension, pVBInfo->P3c4, pVBInfo); */
2428                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
2429
2430         /* XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03); */
2431         XGINew_SetReg1(pVBInfo->P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
2432
2433 }
2434
2435 /*
2436 void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension)
2437 {
2438         unsigned char data;
2439         struct vb_device_info VBINF;
2440         struct vb_device_info *pVBInfo = &VBINF;
2441         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2442         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2443         pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress;
2444         pVBInfo->ISXPDOS = 0;
2445
2446         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2447         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2448         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2449         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2450         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2451         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2452         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2453         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2454         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2455         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2456         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2457         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2458         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2459         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2460         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2461         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2462         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2463
2464         InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2465
2466         ReadVBIOSTablData(HwDeviceExtension->jChipType , pVBInfo);
2467
2468         if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0)
2469                 XGINew_DDR1x_MRS_XG20(pVBInfo->P3c4, pVBInfo);
2470         else
2471                 XGINew_DDR2_MRS_XG27(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
2472
2473         XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03);
2474 }
2475 */
2476
2477 void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
2478                 struct vb_device_info *pVBInfo)
2479 {
2480         unsigned short tempbx = 0, temp, tempcx, CR3CData;
2481
2482         temp = XGINew_GetReg1(pVBInfo->P3d4, 0x32);
2483
2484         if (temp & Monitor1Sense)
2485                 tempbx |= ActiveCRT1;
2486         if (temp & LCDSense)
2487                 tempbx |= ActiveLCD;
2488         if (temp & Monitor2Sense)
2489                 tempbx |= ActiveCRT2;
2490         if (temp & TVSense) {
2491                 tempbx |= ActiveTV;
2492                 if (temp & AVIDEOSense)
2493                         tempbx |= (ActiveAVideo << 8);
2494                 if (temp & SVIDEOSense)
2495                         tempbx |= (ActiveSVideo << 8);
2496                 if (temp & SCARTSense)
2497                         tempbx |= (ActiveSCART << 8);
2498                 if (temp & HiTVSense)
2499                         tempbx |= (ActiveHiTV << 8);
2500                 if (temp & YPbPrSense)
2501                         tempbx |= (ActiveYPbPr << 8);
2502         }
2503
2504         tempcx = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
2505         tempcx |= (XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8);
2506
2507         if (tempbx & tempcx) {
2508                 CR3CData = XGINew_GetReg1(pVBInfo->P3d4, 0x3c);
2509                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
2510                         tempcx = 0x1FF0;
2511                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
2512                                 tempbx = 0x1FF0;
2513                 }
2514         } else {
2515                 tempcx = 0x1FF0;
2516                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
2517                         tempbx = 0x1FF0;
2518         }
2519
2520         tempbx &= tempcx;
2521         XGINew_SetReg1(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
2522         XGINew_SetReg1(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
2523 }
2524
2525 void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
2526                 struct vb_device_info *pVBInfo)
2527 {
2528         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
2529
2530         temp = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
2531         temp |= XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8;
2532         temp |= (XGINew_GetReg1(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
2533
2534         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
2535                 if (temp & ActiveCRT2)
2536                         tempcl = SetCRT2ToRAMDAC;
2537         }
2538
2539         if (temp & ActiveLCD) {
2540                 tempcl |= SetCRT2ToLCD;
2541                 if (temp & DriverMode) {
2542                         if (temp & ActiveTV) {
2543                                 tempch = SetToLCDA | EnableDualEdge;
2544                                 temp ^= SetCRT2ToLCD;
2545
2546                                 if ((temp >> 8) & ActiveAVideo)
2547                                         tempcl |= SetCRT2ToAVIDEO;
2548                                 if ((temp >> 8) & ActiveSVideo)
2549                                         tempcl |= SetCRT2ToSVIDEO;
2550                                 if ((temp >> 8) & ActiveSCART)
2551                                         tempcl |= SetCRT2ToSCART;
2552
2553                                 if (pVBInfo->IF_DEF_HiVision == 1) {
2554                                         if ((temp >> 8) & ActiveHiTV)
2555                                                 tempcl |= SetCRT2ToHiVisionTV;
2556                                 }
2557
2558                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
2559                                         if ((temp >> 8) & ActiveYPbPr)
2560                                                 tempch |= SetYPbPr;
2561                                 }
2562                         }
2563                 }
2564         } else {
2565                 if ((temp >> 8) & ActiveAVideo)
2566                         tempcl |= SetCRT2ToAVIDEO;
2567                 if ((temp >> 8) & ActiveSVideo)
2568                         tempcl |= SetCRT2ToSVIDEO;
2569                 if ((temp >> 8) & ActiveSCART)
2570                         tempcl |= SetCRT2ToSCART;
2571
2572                 if (pVBInfo->IF_DEF_HiVision == 1) {
2573                         if ((temp >> 8) & ActiveHiTV)
2574                                 tempcl |= SetCRT2ToHiVisionTV;
2575                 }
2576
2577                 if (pVBInfo->IF_DEF_YPbPr == 1) {
2578                         if ((temp >> 8) & ActiveYPbPr)
2579                                 tempch |= SetYPbPr;
2580                 }
2581         }
2582
2583         tempcl |= SetSimuScanMode;
2584         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
2585                         || (temp & ActiveCRT2)))
2586                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
2587         if ((temp & ActiveLCD) && (temp & ActiveTV))
2588                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
2589         XGINew_SetReg1(pVBInfo->P3d4, 0x30, tempcl);
2590
2591         CR31Data = XGINew_GetReg1(pVBInfo->P3d4, 0x31);
2592         CR31Data &= ~(SetNotSimuMode >> 8);
2593         if (!(temp & ActiveCRT1))
2594                 CR31Data |= (SetNotSimuMode >> 8);
2595         CR31Data &= ~(DisableCRT2Display >> 8);
2596         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
2597                 CR31Data |= (DisableCRT2Display >> 8);
2598         XGINew_SetReg1(pVBInfo->P3d4, 0x31, CR31Data);
2599
2600         CR38Data = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
2601         CR38Data &= ~SetYPbPr;
2602         CR38Data |= tempch;
2603         XGINew_SetReg1(pVBInfo->P3d4, 0x38, CR38Data);
2604
2605 }
2606
2607 void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
2608                 struct vb_device_info *pVBInfo)
2609 {
2610         unsigned char Temp;
2611         volatile unsigned char *pVideoMemory =
2612                         (unsigned char *) pVBInfo->ROMAddr;
2613
2614         pVBInfo->IF_DEF_LVDS = 0;
2615
2616 #if 1
2617         if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
2618                 pVBInfo->IF_DEF_LVDS = 1;
2619                 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
2620                 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */
2621         } else {
2622 #endif
2623                 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read  */
2624                 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0xC0;
2625                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
2626                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
2627                         XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
2628                         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */
2629                         Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x04;
2630                         if (!Temp)
2631                                 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */
2632                         else
2633                                 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */
2634                         XGINew_SetRegAND(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */
2635                 }
2636 #if 1
2637         }
2638 #endif
2639 }
2640
2641 void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
2642                 struct vb_device_info *pVBInfo)
2643 {
2644         unsigned char Temp, bCR4A;
2645
2646         pVBInfo->IF_DEF_LVDS = 0;
2647         bCR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
2648         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read  */
2649         Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x07;
2650         XGINew_SetReg1(pVBInfo->P3d4, 0x4A, bCR4A);
2651
2652         if (Temp <= 0x02) {
2653                 pVBInfo->IF_DEF_LVDS = 1;
2654                 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */
2655                 XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x21);
2656         } else {
2657                 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */
2658         }
2659         XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
2660
2661 }
2662
2663 unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
2664 {
2665         unsigned char CR38, CR4A, temp;
2666
2667         CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
2668         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */
2669         CR38 = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
2670         temp = 0;
2671         if ((CR38 & 0xE0) > 0x80) {
2672                 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
2673                 temp &= 0x08;
2674                 temp >>= 3;
2675         }
2676
2677         XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
2678
2679         return temp;
2680 }
2681
2682 unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
2683 {
2684         unsigned char CR4A, temp;
2685
2686         CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
2687         XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */
2688         temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
2689         if (temp <= 2)
2690                 temp &= 0x03;
2691         else
2692                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
2693
2694         XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
2695
2696         return temp;
2697 }
2698