4 #include <linux/version.h>
5 #include <linux/types.h>
6 #include <linux/delay.h> /* udelay */
10 #include "vb_struct.h"
12 #include "vb_setmode.h"
22 UCHAR XGINew_ChannelAB,XGINew_DataBusWidth;
24 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
25 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44},
26 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40},
27 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32},
28 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30},
29 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28},
30 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24},
31 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10},
32 {0x09,0x08,0x01,0x01,0x00}};
34 USHORT XGINew_SDRDRAM_TYPE[13][5]=
51 USHORT XGINew_DDRDRAM_TYPE[4][5]=
58 USHORT XGINew_DDRDRAM_TYPE340[4][5]=
65 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
81 void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
82 void XGINew_SetDRAMSize_310(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
83 void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO );
84 void XGINew_SetDRAMModeRegister(PVB_DEVICE_INFO );
85 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension );
86 void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG, PVB_DEVICE_INFO );
87 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo);
88 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension) ;
90 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO );
91 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO) ;
92 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO) ;
93 int XGINew_SDRSizing(PVB_DEVICE_INFO);
94 int XGINew_DDRSizing( PVB_DEVICE_INFO );
95 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
96 int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
97 ULONG UNIROM; /* UNIROM */
98 BOOLEAN ChkLFB( PVB_DEVICE_INFO );
99 void XGINew_Delay15us(ULONG);
100 void SetPowerConsume (PXGI_HW_DEVICE_INFO HwDeviceExtension,ULONG XGI_P3d4Port);
101 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo);
102 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo);
103 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension );
104 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension );
105 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
106 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
107 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
108 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo);
109 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
110 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo);
112 void DelayUS(ULONG MicroSeconds)
114 udelay(MicroSeconds);
118 /* --------------------------------------------------------------------- */
119 /* Function : XGIInitNew */
123 /* --------------------------------------------------------------------- */
124 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension )
127 VB_DEVICE_INFO VBINF;
128 PVB_DEVICE_INFO pVBInfo = &VBINF;
129 UCHAR i , temp = 0 , temp1 ;
130 // VBIOSVersion[ 5 ] ;
131 PUCHAR volatile pVideoMemory;
139 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
141 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
143 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
145 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr;
148 // Newdebugcode( 0x99 ) ;
151 /* if ( pVBInfo->ROMAddr == 0 ) */
152 /* return( FALSE ) ; */
154 if ( pVBInfo->FBAddr == 0 )
156 printk("\n pVBInfo->FBAddr == 0 ");
160 if ( pVBInfo->BaseAddr == 0 )
162 printk("\npVBInfo->BaseAddr == 0 ");
167 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
169 pVBInfo->ISXPDOS = 0 ;
172 if ( !HwDeviceExtension->bIntegratedMMEnabled )
174 return( FALSE ) ; /* alan */
178 // VBIOSVersion[ 4 ] = 0x0 ;
180 /* 09/07/99 modify by domao */
182 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
183 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
184 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
185 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
186 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
187 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
188 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
189 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
190 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
191 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
192 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
193 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
194 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
195 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
196 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
197 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
198 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
201 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
202 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
204 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
207 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
210 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
213 /* GetXG21Sense (GPIO) */
214 if ( HwDeviceExtension->jChipType == XG21 )
216 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
218 if ( HwDeviceExtension->jChipType == XG27 )
220 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
224 /* 2.Reset Extended register */
226 for( i = 0x06 ; i < 0x20 ; i++ )
227 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
229 for( i = 0x21 ; i <= 0x27 ; i++ )
230 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
232 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
233 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
237 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
239 for( i = 0x31 ; i <= 0x3B ; i++ )
240 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
244 for( i = 0x31 ; i <= 0x3D ; i++ )
245 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
249 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
250 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
252 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
253 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
255 for( i = 0x79 ; i <= 0x7C ; i++ )
256 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
260 if ( HwDeviceExtension->jChipType >= XG20 )
261 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
265 if ( HwDeviceExtension->jChipType >= XG40 )
266 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
268 if ( HwDeviceExtension->jChipType < XG40 )
269 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
273 /* 4.SetDefExt1Regs begin */
274 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
275 if ( HwDeviceExtension->jChipType == XG27 )
277 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
278 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
280 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
281 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
282 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
283 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
284 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
285 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
286 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
289 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
293 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
295 // /* Set AGP Rate */
296 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
298 // if ( temp1 == 0x02 )
300 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
301 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
302 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
303 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
304 // VendorID &= 0x0000FFFF ;
305 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
306 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
307 // GraphicVendorID &= 0x0000FFFF;
309 // if ( ChipsetID == 0x7301039 )
310 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
312 // ChipsetID &= 0x0000FFFF ;
314 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
316 // if ( ChipsetID == 0x1106 )
318 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
319 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
321 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
324 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
330 if ( HwDeviceExtension->jChipType >= XG40 )
332 /* Set AGP customize registers (in SetDefAGPRegs) Start */
333 for( i = 0x47 ; i <= 0x4C ; i++ )
334 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
336 for( i = 0x70 ; i <= 0x71 ; i++ )
337 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
339 for( i = 0x74 ; i <= 0x77 ; i++ )
340 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
341 /* Set AGP customize registers (in SetDefAGPRegs) End */
342 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
343 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
344 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
345 // if ( ChipsetID == 0x25308086 )
346 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
348 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
353 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
357 if ( HwDeviceExtension->jChipType < XG40 )
358 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
362 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
363 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
364 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
367 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
370 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
371 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
372 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
373 temp1 = ( UCHAR )XGINew_GetReg1( pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
374 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ;
377 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
381 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
385 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
387 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
389 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
390 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
394 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
395 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
397 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
401 if ( HwDeviceExtension->jChipType >= XG40 )
402 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
404 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
406 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
408 if ( pVBInfo->IF_DEF_LVDS == 0 )
410 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
411 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
412 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
413 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
414 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
417 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
422 if ( HwDeviceExtension->jChipType < XG40 )
423 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
426 if ( HwDeviceExtension->bSkipSense == FALSE )
430 XGI_SenseCRT1(pVBInfo) ;
433 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
434 pVBInfo->IF_DEF_CH7007 = 0;
435 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
438 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
442 if ( HwDeviceExtension->jChipType == XG21 )
446 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
447 temp = GetXG21FPBits( pVBInfo ) ;
448 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
452 if ( HwDeviceExtension->jChipType == XG27 )
454 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
455 temp = GetXG27FPBits( pVBInfo ) ;
456 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
461 if ( HwDeviceExtension->jChipType >= XG40 )
463 if ( HwDeviceExtension->jChipType >= XG40 )
465 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
468 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
470 if ( HwDeviceExtension->bSkipDramSizing == TRUE )
472 pSR = HwDeviceExtension->pSR ;
475 while( pSR->jIdx != 0xFF )
477 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
481 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
482 } /* SkipDramSizing */
486 if ( HwDeviceExtension->jChipType == XG20 )
488 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
489 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
490 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ;
497 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
507 /* SetDefExt2Regs begin */
510 temp =( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) ;
516 *pVBInfo->pSR21 &= 0xEF ;
518 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
520 *pVBInfo->pSR22 &= 0x20 ;
521 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
524 // base = 0x80000000 ;
525 // OutPortLong( 0xcf8 , base ) ;
526 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
527 // if ( Temp == 0x1039 )
529 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , ( UCHAR )( ( *pVBInfo->pSR22 ) & 0xFE ) ) ;
533 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
536 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
541 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
542 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
547 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
548 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
558 /* ============== alan ====================== */
560 /* --------------------------------------------------------------------- */
561 /* Function : XGINew_GetXG20DRAMType */
565 /* --------------------------------------------------------------------- */
566 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
570 if ( HwDeviceExtension->jChipType < XG20 )
572 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
574 data = *pVBInfo->pSoftSetting & 0x07 ;
579 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
582 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
587 else if ( HwDeviceExtension->jChipType == XG27 )
589 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
591 data = *pVBInfo->pSoftSetting & 0x07 ;
594 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
596 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
602 else if ( HwDeviceExtension->jChipType == XG21 )
604 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
606 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
607 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
609 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
610 if ( temp & 0x01 ) /* DVI read GPIOH */
615 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
620 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
630 /* --------------------------------------------------------------------- */
631 /* Function : XGINew_Get310DRAMType */
635 /* --------------------------------------------------------------------- */
636 UCHAR XGINew_Get310DRAMType(PVB_DEVICE_INFO pVBInfo)
640 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
643 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
644 data = *pVBInfo->pSoftSetting & 0x03 ;
646 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
653 /* --------------------------------------------------------------------- */
654 /* Function : XGINew_Delay15us */
658 /* --------------------------------------------------------------------- */
660 void XGINew_Delay15us(ULONG ulMicrsoSec)
666 /* --------------------------------------------------------------------- */
667 /* Function : XGINew_SDR_MRS */
671 /* --------------------------------------------------------------------- */
672 void XGINew_SDR_MRS( PVB_DEVICE_INFO pVBInfo )
676 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
677 data &= 0x3F ; /* SR16 D7=0,D6=0 */
678 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
679 /* XGINew_Delay15us( 0x100 ) ; */
680 data |= 0x80 ; /* SR16 D7=1,D6=0 */
681 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
682 /* XGINew_Delay15us( 0x100 ) ; */
686 /* --------------------------------------------------------------------- */
687 /* Function : XGINew_DDR1x_MRS_340 */
691 /* --------------------------------------------------------------------- */
692 void XGINew_DDR1x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
694 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
695 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
696 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
697 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
699 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
701 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
702 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
703 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
704 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
705 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
709 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
710 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
711 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
712 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
714 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
716 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
717 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
718 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
719 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
720 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
724 /* --------------------------------------------------------------------- */
725 /* Function : XGINew_DDR2x_MRS_340 */
729 /* --------------------------------------------------------------------- */
730 void XGINew_DDR2x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
732 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
733 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
734 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
735 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
737 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
738 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
739 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
740 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
741 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
743 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
745 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
746 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
747 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
748 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
749 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
750 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
753 /* --------------------------------------------------------------------- */
754 /* Function : XGINew_DDRII_Bootup_XG27 */
758 /* --------------------------------------------------------------------- */
759 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
761 ULONG P3d4 = P3c4 + 0x10 ;
762 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
763 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
765 /* Set Double Frequency */
766 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
767 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
771 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
772 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
773 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
775 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
778 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
779 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
780 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
782 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
785 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
786 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
787 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
789 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
792 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
793 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
794 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
796 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
797 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
798 /* DelayUS( 15 ) ; */
800 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
802 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
804 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
805 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
806 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
809 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
812 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
813 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
814 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
816 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
819 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
820 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
821 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
823 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
826 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
831 /* --------------------------------------------------------------------- */
832 /* Function : XGINew_DDR2_MRS_XG20 */
836 /* --------------------------------------------------------------------- */
837 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
839 ULONG P3d4 = P3c4 + 0x10 ;
841 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
842 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
844 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
847 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
848 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
849 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
850 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
852 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
853 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
854 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
855 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
857 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
858 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
859 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
860 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
862 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
863 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
864 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
865 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
866 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
869 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
871 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
874 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
875 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
876 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
877 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
878 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
883 /* --------------------------------------------------------------------- */
884 /* Function : XGINew_DDR2_MRS_XG20 */
888 /* --------------------------------------------------------------------- */
889 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
891 ULONG P3d4 = P3c4 + 0x10 ;
893 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
894 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
896 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
898 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
899 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
901 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
902 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
903 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
905 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
906 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
908 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
909 DelayUS( 15 ) ; ////06/11/22 XG27 A0
910 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
913 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
914 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
916 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
917 DelayUS( 15 ) ; ////06/11/22 XG27 A0
918 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
920 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
921 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
923 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
924 DelayUS( 15 ) ; ////06/11/23 XG27 A0
925 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
927 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
928 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
930 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
933 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
934 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
936 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
938 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
940 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
941 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
943 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
945 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
947 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
948 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
950 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
952 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
954 DelayUS( 15 ) ; ////Start Auto-PreCharge
955 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
957 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
961 /* --------------------------------------------------------------------- */
962 /* Function : XGINew_DDR1x_DefaultRegister */
966 /* --------------------------------------------------------------------- */
967 void XGINew_DDR1x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
972 if ( HwDeviceExtension->jChipType >= XG20 )
974 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
975 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
976 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
977 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
979 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
980 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
982 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
986 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
988 switch( HwDeviceExtension->jChipType )
992 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
993 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
994 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
997 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
998 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
999 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1000 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1001 XGINew_GetReg1( P3d4 , 0x86 ) ;
1002 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1003 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1004 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1005 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1006 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1007 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1008 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1009 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1013 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1014 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1015 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1016 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1021 /* --------------------------------------------------------------------- */
1022 /* Function : XGINew_DDR2x_DefaultRegister */
1026 /* --------------------------------------------------------------------- */
1027 void XGINew_DDR2x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port ,PVB_DEVICE_INFO pVBInfo)
1030 P3c4 = Port - 0x10 ;
1032 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1034 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1035 switch( HwDeviceExtension->jChipType )
1039 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1040 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1041 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1044 /* keep following setting sequence, each setting in the same reg insert idle */
1045 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1046 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1047 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1048 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1049 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1050 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1051 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1052 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1053 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1054 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1055 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1057 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1058 if ( HwDeviceExtension->jChipType == XG42 )
1060 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1064 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1066 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1068 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1072 /* --------------------------------------------------------------------- */
1073 /* Function : XGINew_DDR2_DefaultRegister */
1077 /* --------------------------------------------------------------------- */
1078 void XGINew_DDR2_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG Port , PVB_DEVICE_INFO pVBInfo)
1081 P3c4 = Port - 0x10 ;
1083 /* keep following setting sequence, each setting in the same reg insert idle */
1084 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1085 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1086 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1087 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1088 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1089 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1090 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1091 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1092 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1093 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1094 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1095 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1096 if ( HwDeviceExtension->jChipType == XG27 )
1097 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1099 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1101 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1102 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1103 if ( HwDeviceExtension->jChipType == XG27 )
1104 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1106 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1110 /* --------------------------------------------------------------------- */
1111 /* Function : XGINew_SetDRAMDefaultRegister340 */
1115 /* --------------------------------------------------------------------- */
1116 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1118 UCHAR temp , temp1 , temp2 , temp3 ,
1122 P3c4 = Port - 0x10 ;
1124 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1125 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1126 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1127 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1130 for( i = 0 ; i < 4 ; i++ )
1132 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1133 for( j = 0 ; j < 4 ; j++ )
1135 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1137 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1138 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1145 for( i = 0 ; i < 4 ; i++ )
1147 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1148 for( j = 0 ; j < 4 ; j++ )
1150 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1152 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1153 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1160 for( k = 0 ; k < 4 ; k++ )
1162 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1164 for( i = 0 ; i < 8 ; i++ )
1166 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1167 for( j = 0 ; j < 4 ; j++ )
1169 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1171 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1172 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1180 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1181 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1184 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1185 for( j = 0 ; j < 4 ; j++ )
1187 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1189 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1190 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1195 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1196 temp1 = temp & 0x03 ;
1198 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1200 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1201 temp1 = temp & 0x0F ;
1202 temp2 = ( temp >> 4 ) & 0x07 ;
1203 temp3 = temp & 0x80 ;
1204 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1205 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1206 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1207 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1209 if ( HwDeviceExtension->jChipType == XG27 )
1210 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1212 for( j = 0 ; j <= 6 ; j++ )
1213 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1215 for( j = 0 ; j <= 2 ; j++ )
1216 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1218 for( j = 0 ; j < 2 ; j++ )
1219 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1221 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1222 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1224 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1226 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1227 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1228 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1229 if ( XGINew_RAMType )
1231 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1232 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1233 if ( HwDeviceExtension->jChipType == XG27 )
1234 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1238 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1239 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1241 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1243 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1246 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1247 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1249 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1253 /* --------------------------------------------------------------------- */
1254 /* Function : XGINew_DDR_MRS */
1258 /* --------------------------------------------------------------------- */
1259 void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo)
1263 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
1265 /* SR16 <- 1F,DF,2F,AF */
1266 /* yriver modified SR16 <- 0F,DF,0F,AF */
1267 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1268 data = pVideoMemory[ 0xFB ] ;
1269 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1272 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1274 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1276 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1278 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1280 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1282 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1284 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1286 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1291 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1293 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1299 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1304 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1305 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1311 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1317 /* check if read cache pointer is correct */
1321 /* --------------------------------------------------------------------- */
1322 /* Function : XGINew_VerifyMclk */
1326 /* --------------------------------------------------------------------- */
1327 void XGINew_VerifyMclk( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1329 PUCHAR pVideoMemory = pVBInfo->FBAddr ;
1331 USHORT Temp , SR21 ;
1333 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1334 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1336 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1338 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1340 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1341 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1342 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1344 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1345 Temp |= 0x01 ; /* MCLK reset */
1348 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1349 Temp &= 0xFE ; /* MCLK normal operation */
1351 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1353 pVideoMemory[ 16 + j ] = j ;
1354 if ( pVideoMemory[ 16 + j ] == j )
1356 pVideoMemory[ j ] = j ;
1367 /* --------------------------------------------------------------------- */
1368 /* Function : XGINew_SetDRAMSize_340 */
1372 /* --------------------------------------------------------------------- */
1373 void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1377 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1378 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1380 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1383 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1384 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1385 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1387 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1389 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1390 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1391 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1392 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1397 /* --------------------------------------------------------------------- */
1402 /* --------------------------------------------------------------------- */
1403 void XGINew_SetDRAMSize_310( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1406 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1407 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1409 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1412 #ifdef XGI302 /* alan,should change value */
1413 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1414 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1415 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1418 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1420 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1421 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1423 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1425 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1427 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1430 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , ( USHORT )( data | 0x0F ) ) ; /* assume lowest speed DRAM */
1432 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1433 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1434 XGINew_CheckBusWidth_310( pVBInfo) ;
1435 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1439 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1441 XGINew_SDRSizing( pVBInfo ) ;
1445 XGINew_DDRSizing( pVBInfo) ;
1451 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , pVBInfo->SR15[ 1 ][ XGINew_RAMType ] ) ; /* restore SR16 */
1453 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1454 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1455 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1460 /* --------------------------------------------------------------------- */
1461 /* Function : XGINew_SetDRAMModeRegister340 */
1465 /* --------------------------------------------------------------------- */
1467 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension )
1470 VB_DEVICE_INFO VBINF;
1471 PVB_DEVICE_INFO pVBInfo = &VBINF;
1472 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1473 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1474 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
1475 pVBInfo->ISXPDOS = 0 ;
1477 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1478 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1479 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1480 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1481 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1482 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1483 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1484 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1485 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1486 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1487 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1488 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1489 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1490 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1491 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1492 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1493 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1494 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1495 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1497 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1499 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1501 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1503 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1505 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1507 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1510 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1512 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1515 /* --------------------------------------------------------------------- */
1516 /* Function : XGINew_SetDRAMModeRegister */
1520 /* --------------------------------------------------------------------- */
1521 void XGINew_SetDRAMModeRegister( PVB_DEVICE_INFO pVBInfo)
1523 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1525 XGINew_SDR_MRS(pVBInfo ) ;
1529 /* SR16 <- 0F,CF,0F,8F */
1530 XGINew_DDR_MRS( pVBInfo ) ;
1535 /* --------------------------------------------------------------------- */
1536 /* Function : XGINew_DisableRefresh */
1540 /* --------------------------------------------------------------------- */
1541 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1546 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1548 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1553 /* --------------------------------------------------------------------- */
1554 /* Function : XGINew_EnableRefresh */
1558 /* --------------------------------------------------------------------- */
1559 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1562 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1568 /* --------------------------------------------------------------------- */
1569 /* Function : XGINew_DisableChannelInterleaving */
1573 /* --------------------------------------------------------------------- */
1574 void XGINew_DisableChannelInterleaving( int index , USHORT XGINew_DDRDRAM_TYPE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1578 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1581 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1598 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1602 /* --------------------------------------------------------------------- */
1603 /* Function : XGINew_SetDRAMSizingType */
1607 /* --------------------------------------------------------------------- */
1608 void XGINew_SetDRAMSizingType( int index , USHORT DRAMTYPE_TABLE[][ 5 ] ,PVB_DEVICE_INFO pVBInfo)
1612 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1613 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1615 /* should delay 50 ns */
1619 /* --------------------------------------------------------------------- */
1620 /* Function : XGINew_CheckBusWidth_310 */
1624 /* --------------------------------------------------------------------- */
1625 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO pVBInfo)
1628 PULONG volatile pVideoMemory ;
1630 pVideoMemory = (PULONG) pVBInfo->FBAddr;
1632 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1634 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1635 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1637 XGINew_SDR_MRS( pVBInfo ) ;
1639 XGINew_ChannelAB = 0 ;
1640 XGINew_DataBusWidth = 128 ;
1641 pVideoMemory[ 0 ] = 0x01234567L ;
1642 pVideoMemory[ 1 ] = 0x456789ABL ;
1643 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1644 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1645 pVideoMemory[ 4 ] = 0x55555555L ;
1646 pVideoMemory[ 5 ] = 0x55555555L ;
1647 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1648 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1650 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1653 XGINew_DataBusWidth = 64 ;
1654 XGINew_ChannelAB = 0 ;
1655 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1656 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( data & 0xFD ) ) ;
1659 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1662 XGINew_DataBusWidth = 64 ;
1663 XGINew_ChannelAB = 1 ;
1664 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1665 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( ( data & 0xFD ) | 0x01 ) ) ;
1672 /* DDR Dual channel */
1673 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1674 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1676 XGINew_DDR_MRS( pVBInfo ) ;
1678 XGINew_ChannelAB = 0 ;
1679 XGINew_DataBusWidth = 64 ;
1680 pVideoMemory[ 0 ] = 0x01234567L ;
1681 pVideoMemory[ 1 ] = 0x456789ABL ;
1682 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1683 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1684 pVideoMemory[ 4 ] = 0x55555555L ;
1685 pVideoMemory[ 5 ] = 0x55555555L ;
1686 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1687 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1689 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1691 if ( pVideoMemory[ 0 ] == 0x01234567L )
1693 /* Channel A 64bit */
1699 if ( pVideoMemory[ 0 ] == 0x01234567L )
1701 /* Channel A 32bit */
1702 XGINew_DataBusWidth = 32 ;
1703 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1708 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1709 XGINew_DDR_MRS( pVBInfo);
1711 XGINew_ChannelAB = 1 ;
1712 XGINew_DataBusWidth = 64 ;
1713 pVideoMemory[ 0 ] = 0x01234567L ;
1714 pVideoMemory[ 1 ] = 0x456789ABL ;
1715 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1716 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1717 pVideoMemory[ 4 ] = 0x55555555L ;
1718 pVideoMemory[ 5 ] = 0x55555555L ;
1719 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1720 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1722 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1725 if ( pVideoMemory[ 0 ] == 0x01234567L )
1727 /* Channel B 64bit */
1737 if ( pVideoMemory[ 0 ] == 0x01234567L )
1740 XGINew_DataBusWidth = 32 ;
1741 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1752 /* --------------------------------------------------------------------- */
1753 /* Function : XGINew_SetRank */
1757 /* --------------------------------------------------------------------- */
1758 int XGINew_SetRank( int index , UCHAR RankNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1763 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1766 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1768 if ( ( RankNo * RankSize ) <= 128 )
1772 while( ( RankSize >>= 1 ) > 0 )
1776 data |= ( RankNo - 1 ) << 2 ;
1777 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1778 data |= XGINew_ChannelAB ;
1779 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1781 XGINew_SDR_MRS( pVBInfo ) ;
1789 /* --------------------------------------------------------------------- */
1790 /* Function : XGINew_SetDDRChannel */
1794 /* --------------------------------------------------------------------- */
1795 int XGINew_SetDDRChannel( int index , UCHAR ChannelNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1800 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1801 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1802 if ( ChannelNo * RankSize <= 128 )
1805 while( ( RankSize >>= 1 ) > 0 )
1810 if ( ChannelNo == 2 )
1813 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1814 data |= XGINew_ChannelAB ;
1815 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1817 XGINew_DDR_MRS( pVBInfo ) ;
1825 /* --------------------------------------------------------------------- */
1826 /* Function : XGINew_CheckColumn */
1830 /* --------------------------------------------------------------------- */
1831 int XGINew_CheckColumn( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1834 ULONG Increment , Position ;
1836 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1837 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1839 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1841 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1842 Position += Increment ;
1846 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1848 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1849 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1851 Position += Increment ;
1857 /* --------------------------------------------------------------------- */
1858 /* Function : XGINew_CheckBanks */
1862 /* --------------------------------------------------------------------- */
1863 int XGINew_CheckBanks( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1866 ULONG Increment , Position ;
1868 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1870 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1872 /* pVBInfo->FBAddr[ Position ] = Position ; */
1873 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1874 Position += Increment ;
1877 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1879 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1880 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1882 Position += Increment ;
1888 /* --------------------------------------------------------------------- */
1889 /* Function : XGINew_CheckRank */
1893 /* --------------------------------------------------------------------- */
1894 int XGINew_CheckRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1897 ULONG Increment , Position ;
1899 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1900 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1902 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1904 /* pVBInfo->FBAddr[ Position ] = Position ; */
1905 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */
1906 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1907 Position += Increment ;
1910 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1912 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1913 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */
1914 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1916 Position += Increment ;
1922 /* --------------------------------------------------------------------- */
1923 /* Function : XGINew_CheckDDRRank */
1927 /* --------------------------------------------------------------------- */
1928 int XGINew_CheckDDRRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1930 ULONG Increment , Position ;
1933 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1934 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1936 Increment += Increment / 2 ;
1939 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ;
1940 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ;
1941 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ;
1942 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ;
1943 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ;
1944 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ;
1946 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB )
1949 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 )
1952 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1955 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1956 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1958 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1964 /* --------------------------------------------------------------------- */
1965 /* Function : XGINew_CheckRanks */
1969 /* --------------------------------------------------------------------- */
1970 int XGINew_CheckRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1974 for( r = RankNo ; r >= 1 ; r-- )
1976 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
1980 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
1983 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
1990 /* --------------------------------------------------------------------- */
1991 /* Function : XGINew_CheckDDRRanks */
1995 /* --------------------------------------------------------------------- */
1996 int XGINew_CheckDDRRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2000 for( r = RankNo ; r >= 1 ; r-- )
2002 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2006 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2009 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2016 /* --------------------------------------------------------------------- */
2021 /* --------------------------------------------------------------------- */
2022 int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo)
2027 for( i = 0 ; i < 13 ; i++ )
2029 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2031 for( j = 2 ; j > 0 ; j-- )
2033 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) )
2037 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2046 /* --------------------------------------------------------------------- */
2047 /* Function : XGINew_SetDRAMSizeReg */
2051 /* --------------------------------------------------------------------- */
2052 USHORT XGINew_SetDRAMSizeReg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2054 USHORT data = 0 , memsize = 0 ;
2058 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2059 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2067 if( XGINew_ChannelAB == 3 )
2070 ChannelNo = XGINew_ChannelAB ;
2072 if ( ChannelNo * RankSize <= 256 )
2074 while( ( RankSize >>= 1 ) > 0 )
2079 memsize = data >> 4 ;
2081 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2082 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2084 /* data |= XGINew_ChannelAB << 2 ; */
2085 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2086 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2089 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2095 /* --------------------------------------------------------------------- */
2096 /* Function : XGINew_SetDRAMSize20Reg */
2100 /* --------------------------------------------------------------------- */
2101 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2103 USHORT data = 0 , memsize = 0 ;
2107 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2108 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2116 if( XGINew_ChannelAB == 3 )
2119 ChannelNo = XGINew_ChannelAB ;
2121 if ( ChannelNo * RankSize <= 256 )
2123 while( ( RankSize >>= 1 ) > 0 )
2128 memsize = data >> 4 ;
2130 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2131 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2134 /* data |= XGINew_ChannelAB << 2 ; */
2135 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2136 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2139 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2145 /* --------------------------------------------------------------------- */
2146 /* Function : XGINew_ReadWriteRest */
2150 /* --------------------------------------------------------------------- */
2151 int XGINew_ReadWriteRest( USHORT StopAddr , USHORT StartAddr, PVB_DEVICE_INFO pVBInfo)
2154 ULONG Position = 0 ;
2156 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2158 for( i = StartAddr ; i <= StopAddr ; i++ )
2161 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2164 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2168 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2171 for( i = StartAddr ; i <= StopAddr ; i++ )
2174 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2181 /* --------------------------------------------------------------------- */
2182 /* Function : XGINew_CheckFrequence */
2186 /* --------------------------------------------------------------------- */
2187 UCHAR XGINew_CheckFrequence( PVB_DEVICE_INFO pVBInfo )
2191 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2193 if ( ( data & 0x10 ) == 0 )
2195 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2196 data = ( data & 0x02 ) >> 1 ;
2200 return( data & 0x01 ) ;
2204 /* --------------------------------------------------------------------- */
2205 /* Function : XGINew_CheckChannel */
2209 /* --------------------------------------------------------------------- */
2210 void XGINew_CheckChannel( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2214 switch( HwDeviceExtension->jChipType )
2218 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2220 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2222 if ( data == 0 ) /* Single_32_16 */
2225 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2228 XGINew_DataBusWidth = 32 ; /* 32 bits */
2229 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2230 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2233 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2236 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2238 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2239 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2242 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2247 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2249 XGINew_DataBusWidth = 16 ; /* 16 bits */
2250 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2251 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2254 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2257 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2262 else /* Dual_16_8 */
2264 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2267 XGINew_DataBusWidth = 16 ; /* 16 bits */
2268 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2269 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2272 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2275 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2277 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2281 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2287 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2289 XGINew_DataBusWidth = 8 ; /* 8 bits */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2291 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2294 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2297 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2304 XGINew_DataBusWidth = 16 ; /* 16 bits */
2305 XGINew_ChannelAB = 1 ; /* Single channel */
2306 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2309 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2311 XGINew_DataBusWidth = 32 ; /* 32 bits */
2312 XGINew_ChannelAB = 3 ; /* Quad Channel */
2313 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2314 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2316 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2319 XGINew_ChannelAB = 2 ; /* Dual channels */
2320 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2322 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2325 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2327 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2330 XGINew_ChannelAB = 3 ;
2331 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2332 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2334 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2337 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2339 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2342 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2346 XGINew_DataBusWidth = 64 ; /* 64 bits */
2347 XGINew_ChannelAB = 2 ; /* Dual channels */
2348 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2349 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2351 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2354 XGINew_ChannelAB = 1 ; /* Single channels */
2355 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2357 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2360 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2362 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2365 XGINew_ChannelAB = 2 ; /* Dual channels */
2366 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2367 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2369 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2372 XGINew_ChannelAB = 1 ; /* Single channels */
2373 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2375 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2378 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2385 XG42 SR14 D[3] Reserve
2386 D[2] = 1, Dual Channel
2389 It's Different from Other XG40 Series.
2391 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2393 XGINew_DataBusWidth = 32 ; /* 32 bits */
2394 XGINew_ChannelAB = 2 ; /* 2 Channel */
2395 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2396 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2398 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2401 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2402 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2403 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2406 XGINew_ChannelAB = 1 ; /* Single Channel */
2407 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2408 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2410 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2414 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2415 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2420 XGINew_DataBusWidth = 64 ; /* 64 bits */
2421 XGINew_ChannelAB = 1 ; /* 1 channels */
2422 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2423 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2425 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2429 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2430 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2438 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2440 XGINew_DataBusWidth = 32 ; /* 32 bits */
2441 XGINew_ChannelAB = 3 ;
2442 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2443 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2445 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2448 XGINew_ChannelAB = 2 ; /* 2 channels */
2449 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2451 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2454 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2455 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2457 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2458 XGINew_ChannelAB = 3 ; /* 4 channels */
2461 XGINew_ChannelAB = 2 ; /* 2 channels */
2462 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2467 XGINew_DataBusWidth = 64 ; /* 64 bits */
2468 XGINew_ChannelAB = 2 ; /* 2 channels */
2469 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2472 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2476 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2477 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2485 /* --------------------------------------------------------------------- */
2486 /* Function : XGINew_DDRSizing340 */
2490 /* --------------------------------------------------------------------- */
2491 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2494 USHORT memsize , addr ;
2496 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2497 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2498 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2501 if ( HwDeviceExtension->jChipType >= XG20 )
2503 for( i = 0 ; i < 12 ; i++ )
2505 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2506 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2510 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2511 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2514 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2520 for( i = 0 ; i < 4 ; i++ )
2522 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2523 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2528 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2529 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2532 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2540 /* --------------------------------------------------------------------- */
2541 /* Function : XGINew_DDRSizing */
2545 /* --------------------------------------------------------------------- */
2546 int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo)
2551 for( i = 0 ; i < 4 ; i++ )
2553 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2554 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2555 for( j = 2 ; j > 0 ; j-- )
2557 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2558 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2562 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2570 /* --------------------------------------------------------------------- */
2571 /* Function : XGINew_SetMemoryClock */
2575 /* --------------------------------------------------------------------- */
2576 void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2580 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2581 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2582 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2586 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2587 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2588 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2590 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2591 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2592 if ( HwDeviceExtension->jChipType == XG42 )
2594 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2595 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2596 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2598 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2604 /* --------------------------------------------------------------------- */
2605 /* Function : ChkLFB */
2609 /* --------------------------------------------------------------------- */
2610 BOOLEAN ChkLFB( PVB_DEVICE_INFO pVBInfo )
2612 if ( LFBDRAMTrap & XGINew_GetReg1( pVBInfo->P3d4 , 0x78 ) )
2619 /* --------------------------------------------------------------------- */
2620 /* input : dx ,valid value : CR or second chip's CR */
2622 /* SetPowerConsume : */
2623 /* Description: reduce 40/43 power consumption in first chip or */
2624 /* in second chip, assume CR A1 D[6]="1" in this case */
2626 /* --------------------------------------------------------------------- */
2627 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG XGI_P3d4Port )
2632 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2633 if ((lTemp&0xFF)==0)
2635 /* set CR58 D[5]=0 D[3]=0 */
2636 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2637 bTemp = (UCHAR) XGINew_GetReg1( XGI_P3d4Port , 0xCB ) ;
2642 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2646 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2655 void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2658 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
2659 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2660 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2661 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
2662 pVBInfo->ISXPDOS = 0 ;
2664 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2665 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2666 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2667 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2668 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2669 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2670 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2671 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2672 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2673 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2674 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2675 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2676 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2677 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2678 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2679 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2680 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2681 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2682 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2684 switch(HwDeviceExtension->jChipType)
2692 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2698 /* --------------------------------------------------------------------- */
2699 /* Function : ReadVBIOSTablData */
2703 /* --------------------------------------------------------------------- */
2704 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo)
2706 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
2711 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */
2716 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2718 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ;
2719 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ;
2720 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ;
2721 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2726 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2728 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ;
2729 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ;
2730 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ;
2731 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2735 /* Volari customize data area start */
2736 /* if ( ChipType == XG40 ) */
2737 if ( ChipType >= XG40 )
2740 for( jj = 0x00 ; jj < 0x03 ; jj++ )
2742 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */
2743 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2744 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2745 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2746 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2747 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2748 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2749 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2754 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */
2755 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2756 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2757 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2758 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2759 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2760 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2761 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2763 *pVBInfo->pSR07 = pVideoMemory[ 0x74 ] ;
2764 *pVBInfo->pSR1F = pVideoMemory[ 0x75 ] ;
2765 *pVBInfo->pSR21 = pVideoMemory[ 0x76 ] ;
2766 *pVBInfo->pSR22 = pVideoMemory[ 0x77 ] ;
2767 *pVBInfo->pSR23 = pVideoMemory[ 0x78 ] ;
2768 *pVBInfo->pSR24 = pVideoMemory[ 0x79 ] ;
2769 pVBInfo->SR25[ 0 ] = pVideoMemory[ 0x7A ] ;
2770 *pVBInfo->pSR31 = pVideoMemory[ 0x7B ] ;
2771 *pVBInfo->pSR32 = pVideoMemory[ 0x7C ] ;
2772 *pVBInfo->pSR33 = pVideoMemory[ 0x7D ] ;
2775 for( jj = 0 ; jj < 3 ; jj++ )
2777 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ;
2778 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2779 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2780 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2781 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2782 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2783 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2784 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2789 for( j = 3 ; j < 24 ; j++ )
2791 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ;
2792 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2793 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2794 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2795 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2796 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2797 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2798 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2802 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ;
2804 for( j = 0 ; j < 8 ; j++ )
2806 for( k = 0 ; k < 4 ; k++ )
2807 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2810 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ;
2812 for( j = 0 ; j < 8 ; j++ )
2814 for( k = 0 ; k < 4 ; k++ )
2815 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2818 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ;
2819 for( j = 0 ; j < 8 ; j++ )
2821 for( k = 0 ; k < 32 ; k++ )
2822 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ;
2825 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ;
2827 for( j = 0 ; j < 8 ; j++ )
2829 for( k = 0 ; k < 2 ; k++ )
2830 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ;
2833 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ;
2834 for( j = 0 ; j < 12 ; j++ )
2835 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ;
2837 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ;
2838 for( j = 0 ; j < 4 ; j++ )
2839 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ;
2841 if ( ChipType == XG21 )
2843 if (pVideoMemory[ 0x67 ] & 0x80)
2845 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2847 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2849 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ;
2850 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ;
2851 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ;
2852 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ;
2856 if ( ChipType == XG27 )
2859 for( i = 0 ; i <= 0xB ; i++,jj++ )
2860 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ;
2861 for( i = 0x0 ; i <= 0x1 ; i++,jj++ )
2862 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ;
2864 *pVBInfo->pSR40 = pVideoMemory[ jj ] ;
2866 *pVBInfo->pSR41 = pVideoMemory[ jj ] ;
2868 if (pVideoMemory[ 0x67 ] & 0x80)
2870 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2872 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2875 *pVBInfo->pCR2E = pVideoMemory[ jj ] ;
2876 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ;
2877 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ;
2878 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ;
2883 *pVBInfo->pCRCF = pVideoMemory[ 0x1CA ] ;
2884 *pVBInfo->pXGINew_DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ;
2885 *pVBInfo->pXGINew_I2CDefinition = pVideoMemory[ 0x1D1 ] ;
2886 if ( ChipType >= XG20 )
2888 *pVBInfo->pXGINew_CR97 = pVideoMemory[ 0x1D2 ] ;
2889 if ( ChipType == XG27 )
2891 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ;
2892 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ;
2898 /* Volari customize data area end */
2900 if ( ChipType == XG21 )
2902 pVBInfo->IF_DEF_LVDS = 0 ;
2903 if (pVideoMemory[ 0x65 ] & 0x1)
2905 pVBInfo->IF_DEF_LVDS = 1 ;
2906 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2907 j = pVideoMemory[ i-1 ] ;
2913 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2914 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2915 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2916 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2917 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2918 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2919 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2920 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2921 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2922 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2923 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2924 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2925 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2926 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2927 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2928 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2932 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) );
2936 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2937 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2938 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2939 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2940 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2941 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2942 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2943 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2944 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2945 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2946 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2947 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2948 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2949 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2950 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2951 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2957 /* --------------------------------------------------------------------- */
2958 /* Function : XGINew_DDR1x_MRS_XG20 */
2962 /* --------------------------------------------------------------------- */
2963 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
2966 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
2967 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2968 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2969 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2972 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
2973 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2974 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2975 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2977 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2978 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2979 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
2980 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2981 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2983 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
2985 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2986 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2987 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
2988 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2989 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2990 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
2993 /* --------------------------------------------------------------------- */
2994 /* Function : XGINew_SetDRAMModeRegister_XG20 */
2998 /* --------------------------------------------------------------------- */
2999 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3001 VB_DEVICE_INFO VBINF;
3002 PVB_DEVICE_INFO pVBInfo = &VBINF;
3003 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3004 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3005 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3006 pVBInfo->ISXPDOS = 0 ;
3008 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3009 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3010 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3011 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3012 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3013 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3014 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3015 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3016 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3017 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3018 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3019 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3020 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3021 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3022 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3023 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3024 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3026 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3028 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3030 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3031 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3033 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3035 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3038 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3040 VB_DEVICE_INFO VBINF;
3041 PVB_DEVICE_INFO pVBInfo = &VBINF;
3042 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3043 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3044 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3045 pVBInfo->ISXPDOS = 0 ;
3047 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3048 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3049 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3050 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3051 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3052 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3053 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3054 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3055 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3056 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3057 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3058 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3059 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3060 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3061 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3062 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3063 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3065 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3067 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3069 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3070 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3072 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3073 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3075 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3076 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
3080 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3084 VB_DEVICE_INFO VBINF;
3085 PVB_DEVICE_INFO pVBInfo = &VBINF;
3086 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3087 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3088 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
3089 pVBInfo->ISXPDOS = 0 ;
3091 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3092 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3093 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3094 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3095 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3096 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3097 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3098 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3099 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3100 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3101 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3102 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3103 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3104 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3105 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3106 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3107 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3109 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3111 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3113 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3114 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3116 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3118 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3121 /* -------------------------------------------------------- */
3122 /* Function : XGINew_ChkSenseStatus */
3126 /* -------------------------------------------------------- */
3127 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
3129 USHORT tempbx=0 , temp , tempcx , CR3CData;
3131 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
3133 if ( temp & Monitor1Sense )
3134 tempbx |= ActiveCRT1 ;
3135 if ( temp & LCDSense )
3136 tempbx |= ActiveLCD ;
3137 if ( temp & Monitor2Sense )
3138 tempbx |= ActiveCRT2 ;
3139 if ( temp & TVSense )
3141 tempbx |= ActiveTV ;
3142 if ( temp & AVIDEOSense )
3143 tempbx |= ( ActiveAVideo << 8 );
3144 if ( temp & SVIDEOSense )
3145 tempbx |= ( ActiveSVideo << 8 );
3146 if ( temp & SCARTSense )
3147 tempbx |= ( ActiveSCART << 8 );
3148 if ( temp & HiTVSense )
3149 tempbx |= ( ActiveHiTV << 8 );
3150 if ( temp & YPbPrSense )
3151 tempbx |= ( ActiveYPbPr << 8 );
3154 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3155 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3157 if ( tempbx & tempcx )
3159 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3160 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3163 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3172 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3179 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3180 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3182 /* -------------------------------------------------------- */
3183 /* Function : XGINew_SetModeScratch */
3187 /* -------------------------------------------------------- */
3188 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo )
3190 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3192 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3193 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3194 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3196 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3198 if ( temp & ActiveCRT2 )
3199 tempcl = SetCRT2ToRAMDAC ;
3202 if ( temp & ActiveLCD )
3204 tempcl |= SetCRT2ToLCD ;
3205 if ( temp & DriverMode )
3207 if ( temp & ActiveTV )
3209 tempch = SetToLCDA | EnableDualEdge ;
3210 temp ^= SetCRT2ToLCD ;
3212 if ( ( temp >> 8 ) & ActiveAVideo )
3213 tempcl |= SetCRT2ToAVIDEO ;
3214 if ( ( temp >> 8 ) & ActiveSVideo )
3215 tempcl |= SetCRT2ToSVIDEO ;
3216 if ( ( temp >> 8 ) & ActiveSCART )
3217 tempcl |= SetCRT2ToSCART ;
3219 if ( pVBInfo->IF_DEF_HiVision == 1 )
3221 if ( ( temp >> 8 ) & ActiveHiTV )
3222 tempcl |= SetCRT2ToHiVisionTV ;
3225 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3227 if ( ( temp >> 8 ) & ActiveYPbPr )
3228 tempch |= SetYPbPr ;
3235 if ( ( temp >> 8 ) & ActiveAVideo )
3236 tempcl |= SetCRT2ToAVIDEO ;
3237 if ( ( temp >> 8 ) & ActiveSVideo )
3238 tempcl |= SetCRT2ToSVIDEO ;
3239 if ( ( temp >> 8 ) & ActiveSCART )
3240 tempcl |= SetCRT2ToSCART ;
3242 if ( pVBInfo->IF_DEF_HiVision == 1 )
3244 if ( ( temp >> 8 ) & ActiveHiTV )
3245 tempcl |= SetCRT2ToHiVisionTV ;
3248 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3250 if ( ( temp >> 8 ) & ActiveYPbPr )
3251 tempch |= SetYPbPr ;
3256 tempcl |= SetSimuScanMode ;
3257 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3258 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3259 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3260 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3261 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3263 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3264 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3265 if ( !( temp & ActiveCRT1 ) )
3266 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3267 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3268 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3269 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3270 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3272 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3273 CR38Data &= ~SetYPbPr ;
3274 CR38Data |= tempch ;
3275 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3279 /* -------------------------------------------------------- */
3280 /* Function : XGINew_GetXG21Sense */
3284 /* -------------------------------------------------------- */
3285 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3288 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
3290 pVBInfo->IF_DEF_LVDS = 0 ;
3293 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3295 pVBInfo->IF_DEF_LVDS = 1 ;
3296 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3297 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3302 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3303 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3305 { /* DVI & DVO GPIOA/B pull high */
3306 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3307 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3308 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3309 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3311 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3313 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3314 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3321 /* -------------------------------------------------------- */
3322 /* Function : XGINew_GetXG27Sense */
3326 /* -------------------------------------------------------- */
3327 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3331 pVBInfo->IF_DEF_LVDS = 0 ;
3332 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3333 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3334 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3335 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3339 pVBInfo->IF_DEF_LVDS = 1 ;
3340 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3341 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3345 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3347 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3351 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo)
3353 UCHAR CR38,CR4A,temp;
3355 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3356 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3357 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3359 if ( ( CR38 & 0xE0 ) > 0x80 )
3361 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3366 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3371 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo)
3375 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3376 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3377 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3384 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3386 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;