1 #include <linux/delay.h>
2 #include <linux/vmalloc.h>
7 #include "vb_setmode.h"
9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
29 #define XGIFB_ROM_SIZE 65536
32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
35 unsigned char data, temp;
37 if (HwDeviceExtension->jChipType < XG20) {
38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
43 } else if (HwDeviceExtension->jChipType == XG27) {
44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
51 } else if (HwDeviceExtension->jChipType == XG21) {
52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
54 usleep_range(800, 1800);
55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
56 /* GPIOF 0:DVI 1:DVO */
57 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
59 /* for current XG20 & XG21, GPIOH is floating, driver will
63 data &= 0x01; /* 1=DDRII, 0=DDR */
64 /* ~HOTPLUG_SUPPORT */
65 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
68 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
76 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
77 struct vb_device_info *pVBInfo)
79 xgifb_reg_set(P3c4, 0x18, 0x01);
80 xgifb_reg_set(P3c4, 0x19, 0x20);
81 xgifb_reg_set(P3c4, 0x16, 0x00);
82 xgifb_reg_set(P3c4, 0x16, 0x80);
84 usleep_range(3, 1003);
85 xgifb_reg_set(P3c4, 0x18, 0x00);
86 xgifb_reg_set(P3c4, 0x19, 0x20);
87 xgifb_reg_set(P3c4, 0x16, 0x00);
88 xgifb_reg_set(P3c4, 0x16, 0x80);
90 usleep_range(60, 1060);
91 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
92 xgifb_reg_set(P3c4, 0x19, 0x01);
93 xgifb_reg_set(P3c4, 0x16, 0x03);
94 xgifb_reg_set(P3c4, 0x16, 0x83);
95 usleep_range(1, 1001);
96 xgifb_reg_set(P3c4, 0x1B, 0x03);
97 usleep_range(500, 1500);
98 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
99 xgifb_reg_set(P3c4, 0x19, 0x00);
100 xgifb_reg_set(P3c4, 0x16, 0x03);
101 xgifb_reg_set(P3c4, 0x16, 0x83);
102 xgifb_reg_set(P3c4, 0x1B, 0x00);
105 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
107 xgifb_reg_set(pVBInfo->P3c4,
109 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
110 xgifb_reg_set(pVBInfo->P3c4,
112 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
113 xgifb_reg_set(pVBInfo->P3c4,
115 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
117 xgifb_reg_set(pVBInfo->P3c4,
119 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
120 xgifb_reg_set(pVBInfo->P3c4,
122 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
123 xgifb_reg_set(pVBInfo->P3c4,
125 XGI340_ECLKData[pVBInfo->ram_type].SR30);
128 static void XGINew_DDRII_Bootup_XG27(
129 struct xgi_hw_device_info *HwDeviceExtension,
130 unsigned long P3c4, struct vb_device_info *pVBInfo)
132 unsigned long P3d4 = P3c4 + 0x10;
134 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
135 XGINew_SetMemoryClock(pVBInfo);
137 /* Set Double Frequency */
138 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
140 usleep_range(200, 1200);
142 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
143 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
144 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
145 usleep_range(15, 1015);
146 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
147 usleep_range(15, 1015);
149 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
150 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
151 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
152 usleep_range(15, 1015);
153 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
154 usleep_range(15, 1015);
156 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
157 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
158 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
159 usleep_range(30, 1030);
160 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
161 usleep_range(15, 1015);
163 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
164 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
165 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
166 usleep_range(30, 1030);
167 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
168 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
170 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
171 usleep_range(60, 1060);
172 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
174 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
175 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
176 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
178 usleep_range(30, 1030);
179 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
180 usleep_range(15, 1015);
182 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
183 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
184 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
185 usleep_range(30, 1030);
186 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
187 usleep_range(15, 1015);
189 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
190 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
191 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
192 usleep_range(30, 1030);
193 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
194 usleep_range(15, 1015);
196 /* Set SR1B refresh control 000:close; 010:open */
197 xgifb_reg_set(P3c4, 0x1B, 0x04);
198 usleep_range(200, 1200);
201 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
202 unsigned long P3c4, struct vb_device_info *pVBInfo)
204 unsigned long P3d4 = P3c4 + 0x10;
206 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
207 XGINew_SetMemoryClock(pVBInfo);
209 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
211 usleep_range(200, 1200);
212 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
213 xgifb_reg_set(P3c4, 0x19, 0x80);
214 xgifb_reg_set(P3c4, 0x16, 0x05);
215 xgifb_reg_set(P3c4, 0x16, 0x85);
217 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
218 xgifb_reg_set(P3c4, 0x19, 0xC0);
219 xgifb_reg_set(P3c4, 0x16, 0x05);
220 xgifb_reg_set(P3c4, 0x16, 0x85);
222 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
223 xgifb_reg_set(P3c4, 0x19, 0x40);
224 xgifb_reg_set(P3c4, 0x16, 0x05);
225 xgifb_reg_set(P3c4, 0x16, 0x85);
227 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
228 xgifb_reg_set(P3c4, 0x19, 0x02);
229 xgifb_reg_set(P3c4, 0x16, 0x05);
230 xgifb_reg_set(P3c4, 0x16, 0x85);
232 usleep_range(15, 1015);
233 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
234 usleep_range(30, 1030);
235 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
236 usleep_range(100, 1100);
238 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
239 xgifb_reg_set(P3c4, 0x19, 0x00);
240 xgifb_reg_set(P3c4, 0x16, 0x05);
241 xgifb_reg_set(P3c4, 0x16, 0x85);
243 usleep_range(200, 1200);
246 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
247 struct vb_device_info *pVBInfo)
249 xgifb_reg_set(P3c4, 0x18, 0x01);
250 xgifb_reg_set(P3c4, 0x19, 0x40);
251 xgifb_reg_set(P3c4, 0x16, 0x00);
252 xgifb_reg_set(P3c4, 0x16, 0x80);
253 usleep_range(60, 1060);
255 xgifb_reg_set(P3c4, 0x18, 0x00);
256 xgifb_reg_set(P3c4, 0x19, 0x40);
257 xgifb_reg_set(P3c4, 0x16, 0x00);
258 xgifb_reg_set(P3c4, 0x16, 0x80);
259 usleep_range(60, 1060);
260 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
261 xgifb_reg_set(P3c4, 0x19, 0x01);
262 xgifb_reg_set(P3c4, 0x16, 0x03);
263 xgifb_reg_set(P3c4, 0x16, 0x83);
264 usleep_range(1, 1001);
265 xgifb_reg_set(P3c4, 0x1B, 0x03);
266 usleep_range(500, 1500);
267 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
268 xgifb_reg_set(P3c4, 0x19, 0x00);
269 xgifb_reg_set(P3c4, 0x16, 0x03);
270 xgifb_reg_set(P3c4, 0x16, 0x83);
271 xgifb_reg_set(P3c4, 0x1B, 0x00);
274 static void XGINew_DDR1x_DefaultRegister(
275 struct xgi_hw_device_info *HwDeviceExtension,
276 unsigned long Port, struct vb_device_info *pVBInfo)
278 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
280 if (HwDeviceExtension->jChipType >= XG20) {
281 XGINew_SetMemoryClock(pVBInfo);
284 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
287 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
290 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
292 xgifb_reg_set(P3d4, 0x98, 0x01);
293 xgifb_reg_set(P3d4, 0x9A, 0x02);
295 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
297 XGINew_SetMemoryClock(pVBInfo);
299 switch (HwDeviceExtension->jChipType) {
304 pVBInfo->CR40[11][pVBInfo->ram_type]);
308 pVBInfo->CR40[12][pVBInfo->ram_type]);
312 pVBInfo->CR40[13][pVBInfo->ram_type]);
315 xgifb_reg_set(P3d4, 0x82, 0x88);
316 xgifb_reg_set(P3d4, 0x86, 0x00);
317 /* Insert read command for delay */
318 xgifb_reg_get(P3d4, 0x86);
319 xgifb_reg_set(P3d4, 0x86, 0x88);
320 xgifb_reg_get(P3d4, 0x86);
323 pVBInfo->CR40[13][pVBInfo->ram_type]);
324 xgifb_reg_set(P3d4, 0x82, 0x77);
325 xgifb_reg_set(P3d4, 0x85, 0x00);
327 /* Insert read command for delay */
328 xgifb_reg_get(P3d4, 0x85);
329 xgifb_reg_set(P3d4, 0x85, 0x88);
331 /* Insert read command for delay */
332 xgifb_reg_get(P3d4, 0x85);
336 pVBInfo->CR40[12][pVBInfo->ram_type]);
340 pVBInfo->CR40[11][pVBInfo->ram_type]);
344 xgifb_reg_set(P3d4, 0x97, 0x00);
345 xgifb_reg_set(P3d4, 0x98, 0x01);
346 xgifb_reg_set(P3d4, 0x9A, 0x02);
347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
351 static void XGINew_DDR2_DefaultRegister(
352 struct xgi_hw_device_info *HwDeviceExtension,
353 unsigned long Port, struct vb_device_info *pVBInfo)
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
357 /* keep following setting sequence, each setting in
358 * the same reg insert idle
360 xgifb_reg_set(P3d4, 0x82, 0x77);
361 xgifb_reg_set(P3d4, 0x86, 0x00);
362 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
363 xgifb_reg_set(P3d4, 0x86, 0x88);
364 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
366 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
367 xgifb_reg_set(P3d4, 0x82, 0x77);
368 xgifb_reg_set(P3d4, 0x85, 0x00);
369 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
370 xgifb_reg_set(P3d4, 0x85, 0x88);
371 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
374 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
375 if (HwDeviceExtension->jChipType == XG27)
377 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
379 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
381 xgifb_reg_set(P3d4, 0x98, 0x01);
382 xgifb_reg_set(P3d4, 0x9A, 0x02);
383 if (HwDeviceExtension->jChipType == XG27)
384 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
386 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
389 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
390 u8 shift_factor, u8 mask1, u8 mask2)
394 for (j = 0; j < 4; j++) {
395 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
396 xgifb_reg_set(P3d4, reg, temp2);
397 xgifb_reg_get(P3d4, reg);
403 static void XGINew_SetDRAMDefaultRegister340(
404 struct xgi_hw_device_info *HwDeviceExtension,
405 unsigned long Port, struct vb_device_info *pVBInfo)
407 unsigned char temp, temp1, temp2, temp3, j, k;
409 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
411 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
412 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
413 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
414 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
416 /* CR6B DQS fine tune delay */
418 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
420 /* CR6E DQM fine tune delay */
421 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
424 for (k = 0; k < 4; k++) {
425 /* CR6E_D[1:0] select channel */
426 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
427 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
433 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
436 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
439 /* CR89 terminator type select */
440 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
445 xgifb_reg_set(P3d4, 0x89, temp2);
447 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
449 temp2 = (temp >> 4) & 0x07;
451 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
452 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
453 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
456 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
458 if (HwDeviceExtension->jChipType == XG27)
459 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
461 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
462 xgifb_reg_set(P3d4, (0x90 + j),
463 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
465 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
466 xgifb_reg_set(P3d4, (0xC3 + j),
467 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
469 for (j = 0; j < 2; j++) /* CR8A - CR8B */
470 xgifb_reg_set(P3d4, (0x8A + j),
471 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
473 if (HwDeviceExtension->jChipType == XG42)
474 xgifb_reg_set(P3d4, 0x8C, 0x87);
478 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
480 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
481 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
482 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
483 if (pVBInfo->ram_type) {
484 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
485 if (HwDeviceExtension->jChipType == XG27)
486 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
489 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
491 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
493 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
495 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
497 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
498 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
500 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
503 static unsigned short XGINew_SetDRAMSize20Reg(
504 unsigned short dram_size,
505 struct vb_device_info *pVBInfo)
507 unsigned short data = 0, memsize = 0;
509 unsigned char ChannelNo;
511 RankSize = dram_size * pVBInfo->ram_bus / 8;
512 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
520 if (pVBInfo->ram_channel == 3)
523 ChannelNo = pVBInfo->ram_channel;
525 if (ChannelNo * RankSize <= 256) {
526 while ((RankSize >>= 1) > 0)
531 /* Fix DRAM Sizing Error */
532 xgifb_reg_set(pVBInfo->P3c4,
534 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
536 usleep_range(15, 1015);
541 static int XGINew_ReadWriteRest(unsigned short StopAddr,
542 unsigned short StartAddr, struct vb_device_info *pVBInfo)
545 unsigned long Position = 0;
546 void __iomem *fbaddr = pVBInfo->FBAddr;
548 writel(Position, fbaddr + Position);
550 for (i = StartAddr; i <= StopAddr; i++) {
552 writel(Position, fbaddr + Position);
555 /* Fix #1759 Memory Size error in Multi-Adapter. */
556 usleep_range(500, 1500);
560 if (readl(fbaddr + Position) != Position)
563 for (i = StartAddr; i <= StopAddr; i++) {
565 if (readl(fbaddr + Position) != Position)
571 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
575 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
577 if ((data & 0x10) == 0) {
578 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
579 data = (data & 0x02) >> 1;
585 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
586 struct vb_device_info *pVBInfo)
590 switch (HwDeviceExtension->jChipType) {
593 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
595 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
597 if (data == 0) { /* Single_32_16 */
599 if ((HwDeviceExtension->ulVideoMemorySize - 1)
601 pVBInfo->ram_bus = 32; /* 32 bits */
602 /* 22bit + 2 rank + 32bit */
603 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
604 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
605 usleep_range(15, 1015);
607 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
610 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
612 /* 22bit + 1 rank + 32bit */
613 xgifb_reg_set(pVBInfo->P3c4,
616 xgifb_reg_set(pVBInfo->P3c4,
619 usleep_range(15, 1015);
621 if (XGINew_ReadWriteRest(23,
628 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
630 pVBInfo->ram_bus = 16; /* 16 bits */
631 /* 22bit + 2 rank + 16bit */
632 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
633 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
634 usleep_range(15, 1015);
636 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
638 xgifb_reg_set(pVBInfo->P3c4,
641 usleep_range(15, 1015);
644 } else { /* Dual_16_8 */
645 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
647 pVBInfo->ram_bus = 16; /* 16 bits */
648 /* (0x31:12x8x2) 22bit + 2 rank */
649 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
651 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
652 usleep_range(15, 1015);
654 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
657 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
659 /* (0x31:12x8x2) 22bit + 1 rank */
660 xgifb_reg_set(pVBInfo->P3c4,
664 xgifb_reg_set(pVBInfo->P3c4,
667 usleep_range(15, 1015);
669 if (XGINew_ReadWriteRest(22,
676 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
678 pVBInfo->ram_bus = 8; /* 8 bits */
679 /* (0x31:12x8x2) 22bit + 2 rank */
680 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
682 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
683 usleep_range(15, 1015);
685 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
688 /* (0x31:12x8x2) 22bit + 1 rank */
689 xgifb_reg_set(pVBInfo->P3c4,
692 usleep_range(15, 1015);
698 pVBInfo->ram_bus = 16; /* 16 bits */
699 pVBInfo->ram_channel = 1; /* Single channel */
700 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
704 * XG42 SR14 D[3] Reserve
705 * D[2] = 1, Dual Channel
706 * = 0, Single Channel
708 * It's Different from Other XG40 Series.
710 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
711 pVBInfo->ram_bus = 32; /* 32 bits */
712 pVBInfo->ram_channel = 2; /* 2 Channel */
713 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
714 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
716 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
719 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
720 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
721 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
724 pVBInfo->ram_channel = 1; /* Single Channel */
725 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
726 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
728 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
730 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
731 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
733 pVBInfo->ram_bus = 64; /* 64 bits */
734 pVBInfo->ram_channel = 1; /* 1 channels */
735 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
736 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
738 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
740 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
741 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
748 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
749 pVBInfo->ram_bus = 32; /* 32 bits */
750 pVBInfo->ram_channel = 3;
751 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
752 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
754 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
757 pVBInfo->ram_channel = 2; /* 2 channels */
758 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
760 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
763 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
764 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
766 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
767 pVBInfo->ram_channel = 3; /* 4 channels */
769 pVBInfo->ram_channel = 2; /* 2 channels */
770 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
773 pVBInfo->ram_bus = 64; /* 64 bits */
774 pVBInfo->ram_channel = 2; /* 2 channels */
775 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
776 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
778 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
780 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
781 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
787 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
788 struct vb_device_info *pVBInfo)
791 unsigned short memsize, start_addr;
792 const unsigned short (*dram_table)[2];
794 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
795 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
796 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
798 if (HwDeviceExtension->jChipType >= XG20) {
799 dram_table = XGINew_DDRDRAM_TYPE20;
800 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
803 dram_table = XGINew_DDRDRAM_TYPE340;
804 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
808 for (i = 0; i < size; i++) {
809 /* SetDRAMSizingType */
810 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
811 usleep_range(50, 1050); /* should delay 50 ns */
813 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
818 memsize += (pVBInfo->ram_channel - 2) + 20;
819 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
820 (unsigned long)(1 << memsize))
823 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
829 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
830 struct xgi_hw_device_info *HwDeviceExtension,
831 struct vb_device_info *pVBInfo)
835 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
837 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
839 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
840 /* disable read cache */
841 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
842 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
844 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
845 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
846 /* enable read cache */
847 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
850 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
852 void __iomem *rom_address;
855 rom_address = pci_map_rom(dev, rom_size);
859 rom_copy = vzalloc(XGIFB_ROM_SIZE);
863 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
864 memcpy_fromio(rom_copy, rom_address, *rom_size);
867 pci_unmap_rom(dev, rom_address);
871 static bool xgifb_read_vbios(struct pci_dev *pdev)
873 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
877 struct XGI21_LVDSCapStruct *lvds;
881 vbios = xgifb_copy_rom(pdev, &vbios_size);
883 dev_err(&pdev->dev, "Video BIOS not available\n");
886 if (vbios_size <= 0x65)
889 * The user can ignore the LVDS bit in the BIOS and force the display
892 if (!(vbios[0x65] & 0x1) &&
893 (!xgifb_info->display2_force ||
894 xgifb_info->display2 != XGIFB_DISP_LCD)) {
898 if (vbios_size <= 0x317)
900 i = vbios[0x316] | (vbios[0x317] << 8);
901 if (vbios_size <= i - 1)
909 * Read the LVDS table index scratch register set by the BIOS.
911 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
915 lvds = &xgifb_info->lvds_data;
916 if (vbios_size <= i + 24)
918 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
919 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
920 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
921 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
922 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
923 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
924 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
925 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
926 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
927 lvds->VCLKData1 = vbios[i + 18];
928 lvds->VCLKData2 = vbios[i + 19];
929 lvds->PSC_S1 = vbios[i + 20];
930 lvds->PSC_S2 = vbios[i + 21];
931 lvds->PSC_S3 = vbios[i + 22];
932 lvds->PSC_S4 = vbios[i + 23];
933 lvds->PSC_S5 = vbios[i + 24];
937 dev_err(&pdev->dev, "Video BIOS corrupted\n");
942 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
944 unsigned short tempbx = 0, temp, tempcx, CR3CData;
946 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
948 if (temp & Monitor1Sense)
949 tempbx |= ActiveCRT1;
952 if (temp & Monitor2Sense)
953 tempbx |= ActiveCRT2;
954 if (temp & TVSense) {
956 if (temp & AVIDEOSense)
957 tempbx |= (ActiveAVideo << 8);
958 if (temp & SVIDEOSense)
959 tempbx |= (ActiveSVideo << 8);
960 if (temp & SCARTSense)
961 tempbx |= (ActiveSCART << 8);
962 if (temp & HiTVSense)
963 tempbx |= (ActiveHiTV << 8);
964 if (temp & YPbPrSense)
965 tempbx |= (ActiveYPbPr << 8);
968 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
969 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
971 if (tempbx & tempcx) {
972 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
973 if (!(CR3CData & DisplayDeviceFromCMOS))
980 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
981 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
984 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
986 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
988 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
989 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
990 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
992 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
993 if (temp & ActiveCRT2)
994 tempcl = SetCRT2ToRAMDAC;
997 if (temp & ActiveLCD) {
998 tempcl |= SetCRT2ToLCD;
999 if (temp & DriverMode) {
1000 if (temp & ActiveTV) {
1001 tempch = SetToLCDA | EnableDualEdge;
1002 temp ^= SetCRT2ToLCD;
1004 if ((temp >> 8) & ActiveAVideo)
1005 tempcl |= SetCRT2ToAVIDEO;
1006 if ((temp >> 8) & ActiveSVideo)
1007 tempcl |= SetCRT2ToSVIDEO;
1008 if ((temp >> 8) & ActiveSCART)
1009 tempcl |= SetCRT2ToSCART;
1011 if (pVBInfo->IF_DEF_HiVision == 1) {
1012 if ((temp >> 8) & ActiveHiTV)
1013 tempcl |= SetCRT2ToHiVision;
1016 if (pVBInfo->IF_DEF_YPbPr == 1) {
1017 if ((temp >> 8) & ActiveYPbPr)
1023 if ((temp >> 8) & ActiveAVideo)
1024 tempcl |= SetCRT2ToAVIDEO;
1025 if ((temp >> 8) & ActiveSVideo)
1026 tempcl |= SetCRT2ToSVIDEO;
1027 if ((temp >> 8) & ActiveSCART)
1028 tempcl |= SetCRT2ToSCART;
1030 if (pVBInfo->IF_DEF_HiVision == 1) {
1031 if ((temp >> 8) & ActiveHiTV)
1032 tempcl |= SetCRT2ToHiVision;
1035 if (pVBInfo->IF_DEF_YPbPr == 1) {
1036 if ((temp >> 8) & ActiveYPbPr)
1041 tempcl |= SetSimuScanMode;
1042 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1043 || (temp & ActiveCRT2)))
1044 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1045 if ((temp & ActiveLCD) && (temp & ActiveTV))
1046 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1047 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1049 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1050 CR31Data &= ~(SetNotSimuMode >> 8);
1051 if (!(temp & ActiveCRT1))
1052 CR31Data |= (SetNotSimuMode >> 8);
1053 CR31Data &= ~(DisableCRT2Display >> 8);
1054 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1055 CR31Data |= (DisableCRT2Display >> 8);
1056 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1058 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1059 CR38Data &= ~SetYPbPr;
1061 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1064 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1066 struct vb_device_info *pVBInfo)
1068 unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1070 switch (HwDeviceExtension->ulCRT2LCDType) {
1078 temp = 0; /* overwrite used ulCRT2LCDType */
1080 case LCD_UNKNOWN: /* unknown lcd, do nothing */
1083 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1087 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1088 struct vb_device_info *pVBInfo)
1090 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1093 if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1094 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1096 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1098 /* Enable GPIOA/B read */
1099 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1100 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1101 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1102 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1103 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1104 /* Enable read GPIOF */
1105 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1106 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1107 Temp = 0xA0; /* Only DVO on chip */
1109 Temp = 0x80; /* TMDS on chip */
1110 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1111 /* Disable read GPIOF */
1112 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1117 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1119 unsigned char Temp, bCR4A;
1121 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1122 /* Enable GPIOA/B/C read */
1123 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1124 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1125 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1129 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1130 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1132 /* TMDS/DVO setting */
1133 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1135 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1138 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1140 unsigned char CR38, CR4A, temp;
1142 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1143 /* enable GPIOE read */
1144 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1145 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1147 if ((CR38 & 0xE0) > 0x80) {
1148 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1153 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1158 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1160 unsigned char CR4A, temp;
1162 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1163 /* enable GPIOA/B/C read */
1164 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1165 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1167 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1169 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1174 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1178 flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1179 return flag == 1 || flag == 2;
1182 unsigned char XGIInitNew(struct pci_dev *pdev)
1184 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1185 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1186 struct vb_device_info VBINF;
1187 struct vb_device_info *pVBInfo = &VBINF;
1188 unsigned char i, temp = 0, temp1;
1190 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1192 if (!pVBInfo->FBAddr) {
1193 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1197 XGIRegInit(pVBInfo, xgifb_info->vga_base);
1199 outb(0x67, pVBInfo->P3c2);
1201 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1204 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1206 /* GetXG21Sense (GPIO) */
1207 if (HwDeviceExtension->jChipType == XG21)
1208 XGINew_GetXG21Sense(pdev, pVBInfo);
1210 if (HwDeviceExtension->jChipType == XG27)
1211 XGINew_GetXG27Sense(pVBInfo);
1213 /* Reset Extended register */
1215 for (i = 0x06; i < 0x20; i++)
1216 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1218 for (i = 0x21; i <= 0x27; i++)
1219 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1221 for (i = 0x31; i <= 0x3B; i++)
1222 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1224 /* Auto over driver for XG42 */
1225 if (HwDeviceExtension->jChipType == XG42)
1226 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1228 for (i = 0x79; i <= 0x7C; i++)
1229 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1231 if (HwDeviceExtension->jChipType >= XG20)
1232 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1234 /* SetDefExt1Regs begin */
1235 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1236 if (HwDeviceExtension->jChipType == XG27) {
1237 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1238 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1240 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1241 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1242 /* Frame buffer can read/write SR20 */
1243 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1244 /* H/W request for slow corner chip */
1245 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1246 if (HwDeviceExtension->jChipType == XG27)
1247 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1249 if (HwDeviceExtension->jChipType < XG20) {
1252 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1253 for (i = 0x47; i <= 0x4C; i++)
1254 xgifb_reg_set(pVBInfo->P3d4,
1256 XGI340_AGPReg[i - 0x47]);
1258 for (i = 0x70; i <= 0x71; i++)
1259 xgifb_reg_set(pVBInfo->P3d4,
1261 XGI340_AGPReg[6 + i - 0x70]);
1263 for (i = 0x74; i <= 0x77; i++)
1264 xgifb_reg_set(pVBInfo->P3d4,
1266 XGI340_AGPReg[8 + i - 0x74]);
1268 pci_read_config_dword(pdev, 0x50, &Temp);
1273 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1277 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1278 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1279 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1281 if (HwDeviceExtension->jChipType < XG20) {
1283 XGI_UnLockCRT2(pVBInfo);
1284 /* disable VideoCapture */
1285 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1286 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1287 /* chk if BCLK>=100MHz */
1288 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1290 xgifb_reg_set(pVBInfo->Part1Port,
1291 0x02, XGI330_CRT2Data_1_2);
1293 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1296 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1298 if ((HwDeviceExtension->jChipType == XG42) &&
1299 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1301 xgifb_reg_set(pVBInfo->P3c4,
1303 (XGI330_SR31 & 0x3F) | 0x40);
1304 xgifb_reg_set(pVBInfo->P3c4,
1306 (XGI330_SR32 & 0xFC) | 0x01);
1308 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1309 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1311 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1313 if (HwDeviceExtension->jChipType < XG20) {
1314 if (xgifb_bridge_is_on(pVBInfo)) {
1315 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1316 xgifb_reg_set(pVBInfo->Part4Port,
1317 0x0D, XGI330_CRT2Data_4_D);
1318 xgifb_reg_set(pVBInfo->Part4Port,
1319 0x0E, XGI330_CRT2Data_4_E);
1320 xgifb_reg_set(pVBInfo->Part4Port,
1321 0x10, XGI330_CRT2Data_4_10);
1322 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1323 XGI_LockCRT2(pVBInfo);
1327 XGI_SenseCRT1(pVBInfo);
1329 if (HwDeviceExtension->jChipType == XG21) {
1330 xgifb_reg_and_or(pVBInfo->P3d4,
1333 Monitor1Sense); /* Z9 default has CRT */
1334 temp = GetXG21FPBits(pVBInfo);
1335 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1337 if (HwDeviceExtension->jChipType == XG27) {
1338 xgifb_reg_and_or(pVBInfo->P3d4,
1341 Monitor1Sense); /* Z9 default has CRT */
1342 temp = GetXG27FPBits(pVBInfo);
1343 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1346 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1348 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1352 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1354 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1355 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1357 XGINew_ChkSenseStatus(pVBInfo);
1358 XGINew_SetModeScratch(pVBInfo);
1360 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);