6 #include <linux/version.h>
7 #include <linux/types.h>
8 #include <linux/delay.h> /* udelay */
10 /*#if LINUX_VERSxION_CODE >= KERNEL_VERSION(2,5,0)
11 #include <video/XGIfb.h>
13 #include <linux/XGIfb.h>
29 #include "vb_struct.h"
31 #include "vb_setmode.h"
37 #include "xf86PciInfo.h"
44 #include <linux/types.h>
50 UCHAR XGINew_ChannelAB,XGINew_DataBusWidth;
52 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
53 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44},
54 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40},
55 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32},
56 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30},
57 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28},
58 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24},
59 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10},
60 {0x09,0x08,0x01,0x01,0x00}};
62 USHORT XGINew_SDRDRAM_TYPE[13][5]=
79 USHORT XGINew_DDRDRAM_TYPE[4][5]=
86 USHORT XGINew_DDRDRAM_TYPE340[4][5]=
93 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
109 void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
110 void XGINew_SetDRAMSize_310(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
111 void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO );
112 void XGINew_SetDRAMModeRegister(PVB_DEVICE_INFO );
113 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension );
114 void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG, PVB_DEVICE_INFO );
115 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo);
116 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension) ;
118 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO );
119 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO) ;
120 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO) ;
121 int XGINew_SDRSizing(PVB_DEVICE_INFO);
122 int XGINew_DDRSizing( PVB_DEVICE_INFO );
123 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
124 int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
125 ULONG UNIROM; /* UNIROM */
126 BOOLEAN ChkLFB( PVB_DEVICE_INFO );
127 void XGINew_Delay15us(ULONG);
128 void SetPowerConsume (PXGI_HW_DEVICE_INFO HwDeviceExtension,ULONG XGI_P3d4Port);
129 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo);
130 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo);
131 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension );
132 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension );
133 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
134 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
135 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
136 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo);
137 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
138 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo);
141 /* [Billy] 2007/05/20 For CH7007 */
142 extern UCHAR CH7007TVReg_UNTSC[][8],CH7007TVReg_ONTSC[][8],CH7007TVReg_UPAL[][8],CH7007TVReg_OPAL[][8];
143 extern UCHAR XGI7007_CHTVVCLKUNTSC[],XGI7007_CHTVVCLKONTSC[],XGI7007_CHTVVCLKUPAL[],XGI7007_CHTVVCLKOPAL[];
147 void DelayUS(ULONG MicroSeconds)
149 udelay(MicroSeconds);
153 /* --------------------------------------------------------------------- */
154 /* Function : XGIInitNew */
158 /* --------------------------------------------------------------------- */
159 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension )
162 VB_DEVICE_INFO VBINF;
163 PVB_DEVICE_INFO pVBInfo = &VBINF;
164 UCHAR i , temp = 0 , temp1 ;
165 // VBIOSVersion[ 5 ] ;
166 PUCHAR volatile pVideoMemory;
174 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
176 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
178 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
180 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr;
183 // Newdebugcode( 0x99 ) ;
186 /* if ( pVBInfo->ROMAddr == 0 ) */
187 /* return( FALSE ) ; */
189 if ( pVBInfo->FBAddr == 0 )
191 printk("\n pVBInfo->FBAddr == 0 ");
195 if ( pVBInfo->BaseAddr == 0 )
197 printk("\npVBInfo->BaseAddr == 0 ");
202 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
204 pVBInfo->ISXPDOS = 0 ;
207 if ( !HwDeviceExtension->bIntegratedMMEnabled )
209 return( FALSE ) ; /* alan */
213 // XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ;
215 // VBIOSVersion[ 4 ] = 0x0 ;
217 /* 09/07/99 modify by domao */
219 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
220 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
221 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
222 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
223 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
224 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
225 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
226 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
227 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
228 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
229 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
230 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
231 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
232 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
233 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
234 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
235 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
238 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
239 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
241 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
244 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
247 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
250 /* GetXG21Sense (GPIO) */
251 if ( HwDeviceExtension->jChipType == XG21 )
253 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
255 if ( HwDeviceExtension->jChipType == XG27 )
257 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
261 /* 2.Reset Extended register */
263 for( i = 0x06 ; i < 0x20 ; i++ )
264 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
266 for( i = 0x21 ; i <= 0x27 ; i++ )
267 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
269 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
270 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
274 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
276 for( i = 0x31 ; i <= 0x3B ; i++ )
277 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
281 for( i = 0x31 ; i <= 0x3D ; i++ )
282 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
286 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
287 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
289 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
290 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
292 for( i = 0x79 ; i <= 0x7C ; i++ )
293 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
297 if ( HwDeviceExtension->jChipType >= XG20 )
298 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
302 if ( HwDeviceExtension->jChipType >= XG40 )
303 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
305 if ( HwDeviceExtension->jChipType < XG40 )
306 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
310 /* 4.SetDefExt1Regs begin */
311 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
312 if ( HwDeviceExtension->jChipType == XG27 )
314 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
315 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
317 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
318 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
319 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
320 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
321 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
322 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
323 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
326 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
330 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
332 // /* Set AGP Rate */
333 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
335 // if ( temp1 == 0x02 )
337 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
338 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
339 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
340 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
341 // VendorID &= 0x0000FFFF ;
342 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
343 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
344 // GraphicVendorID &= 0x0000FFFF;
346 // if ( ChipsetID == 0x7301039 )
347 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
349 // ChipsetID &= 0x0000FFFF ;
351 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
353 // if ( ChipsetID == 0x1106 )
355 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
356 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
358 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
361 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
367 if ( HwDeviceExtension->jChipType >= XG40 )
369 /* Set AGP customize registers (in SetDefAGPRegs) Start */
370 for( i = 0x47 ; i <= 0x4C ; i++ )
371 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
373 for( i = 0x70 ; i <= 0x71 ; i++ )
374 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
376 for( i = 0x74 ; i <= 0x77 ; i++ )
377 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
378 /* Set AGP customize registers (in SetDefAGPRegs) End */
379 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
380 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
381 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
382 // if ( ChipsetID == 0x25308086 )
383 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
385 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
390 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
394 if ( HwDeviceExtension->jChipType < XG40 )
395 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
399 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
400 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
401 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
404 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
407 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
408 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
409 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
410 temp1 = ( UCHAR )XGINew_GetReg1( pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
411 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ;
414 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
418 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
422 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
424 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
426 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
427 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
431 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
432 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
434 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
438 if ( HwDeviceExtension->jChipType >= XG40 )
439 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
441 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
443 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
445 if ( pVBInfo->IF_DEF_LVDS == 0 )
447 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
448 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
449 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
450 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
451 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
454 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
459 if ( HwDeviceExtension->jChipType < XG40 )
460 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
463 if ( HwDeviceExtension->bSkipSense == FALSE )
467 XGI_SenseCRT1(pVBInfo) ;
470 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
471 pVBInfo->IF_DEF_CH7007 = 0;
472 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
475 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
479 if ( HwDeviceExtension->jChipType == XG21 )
483 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
484 temp = GetXG21FPBits( pVBInfo ) ;
485 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
489 if ( HwDeviceExtension->jChipType == XG27 )
491 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
492 temp = GetXG27FPBits( pVBInfo ) ;
493 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
498 if ( HwDeviceExtension->jChipType >= XG40 )
500 if ( HwDeviceExtension->jChipType >= XG40 )
502 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
505 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
507 if ( HwDeviceExtension->bSkipDramSizing == TRUE )
509 pSR = HwDeviceExtension->pSR ;
512 while( pSR->jIdx != 0xFF )
514 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
518 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
519 } /* SkipDramSizing */
523 if ( HwDeviceExtension->jChipType == XG20 )
525 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
526 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
527 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ;
534 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
544 /* SetDefExt2Regs begin */
547 temp =( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) ;
553 *pVBInfo->pSR21 &= 0xEF ;
555 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
557 *pVBInfo->pSR22 &= 0x20 ;
558 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
561 // base = 0x80000000 ;
562 // OutPortLong( 0xcf8 , base ) ;
563 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
564 // if ( Temp == 0x1039 )
566 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , ( UCHAR )( ( *pVBInfo->pSR22 ) & 0xFE ) ) ;
570 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
573 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
578 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
579 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
584 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
585 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
595 /* ============== alan ====================== */
597 /* --------------------------------------------------------------------- */
598 /* Function : XGINew_GetXG20DRAMType */
602 /* --------------------------------------------------------------------- */
603 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
607 if ( HwDeviceExtension->jChipType < XG20 )
609 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
611 data = *pVBInfo->pSoftSetting & 0x07 ;
616 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
619 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
624 else if ( HwDeviceExtension->jChipType == XG27 )
626 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
628 data = *pVBInfo->pSoftSetting & 0x07 ;
631 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
633 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
639 else if ( HwDeviceExtension->jChipType == XG21 )
641 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
643 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
644 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
646 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
647 if ( temp & 0x01 ) /* DVI read GPIOH */
652 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
657 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
667 /* --------------------------------------------------------------------- */
668 /* Function : XGINew_Get310DRAMType */
672 /* --------------------------------------------------------------------- */
673 UCHAR XGINew_Get310DRAMType(PVB_DEVICE_INFO pVBInfo)
677 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
680 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
681 data = *pVBInfo->pSoftSetting & 0x03 ;
683 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
690 /* --------------------------------------------------------------------- */
691 /* Function : XGINew_Delay15us */
695 /* --------------------------------------------------------------------- */
697 void XGINew_Delay15us(ULONG ulMicrsoSec)
703 /* --------------------------------------------------------------------- */
704 /* Function : XGINew_SDR_MRS */
708 /* --------------------------------------------------------------------- */
709 void XGINew_SDR_MRS( PVB_DEVICE_INFO pVBInfo )
713 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
714 data &= 0x3F ; /* SR16 D7=0,D6=0 */
715 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
716 /* XGINew_Delay15us( 0x100 ) ; */
717 data |= 0x80 ; /* SR16 D7=1,D6=0 */
718 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
719 /* XGINew_Delay15us( 0x100 ) ; */
723 /* --------------------------------------------------------------------- */
724 /* Function : XGINew_DDR1x_MRS_340 */
728 /* --------------------------------------------------------------------- */
729 void XGINew_DDR1x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
731 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
732 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
733 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
734 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
736 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
738 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
739 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
740 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
741 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
742 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
746 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
747 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
748 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
749 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
751 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
753 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
754 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
755 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
756 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
757 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
761 /* --------------------------------------------------------------------- */
762 /* Function : XGINew_DDR2x_MRS_340 */
766 /* --------------------------------------------------------------------- */
767 void XGINew_DDR2x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
769 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
770 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
771 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
772 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
774 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
775 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
776 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
777 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
778 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
780 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
782 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
783 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
784 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
785 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
786 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
787 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
790 /* --------------------------------------------------------------------- */
791 /* Function : XGINew_DDRII_Bootup_XG27 */
795 /* --------------------------------------------------------------------- */
796 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
798 ULONG P3d4 = P3c4 + 0x10 ;
799 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
800 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
802 /* Set Double Frequency */
803 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
804 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
808 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
809 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
810 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
812 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
815 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
816 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
817 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
819 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
822 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
823 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
824 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
826 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
829 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
830 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
831 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
833 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
834 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
835 /* DelayUS( 15 ) ; */
837 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
839 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
841 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
842 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
843 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
846 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
849 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
850 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
851 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
853 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
856 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
857 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
858 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
860 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
863 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
868 /* --------------------------------------------------------------------- */
869 /* Function : XGINew_DDR2_MRS_XG20 */
873 /* --------------------------------------------------------------------- */
874 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
876 ULONG P3d4 = P3c4 + 0x10 ;
878 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
879 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
881 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
884 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
885 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
886 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
887 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
889 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
890 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
891 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
892 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
894 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
895 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
896 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
897 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
899 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
900 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
901 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
902 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
903 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
906 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
908 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
911 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
912 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
913 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
914 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
915 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
920 /* --------------------------------------------------------------------- */
921 /* Function : XGINew_DDR2_MRS_XG20 */
925 /* --------------------------------------------------------------------- */
926 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
928 ULONG P3d4 = P3c4 + 0x10 ;
930 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
931 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
933 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
935 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
936 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
938 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
939 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
940 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
942 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
943 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
945 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
946 DelayUS( 15 ) ; ////06/11/22 XG27 A0
947 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
950 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
951 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
953 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
954 DelayUS( 15 ) ; ////06/11/22 XG27 A0
955 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
957 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
958 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
960 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
961 DelayUS( 15 ) ; ////06/11/23 XG27 A0
962 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
964 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
965 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
967 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
970 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
971 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
973 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
975 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
977 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
978 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
980 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
982 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
984 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
985 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
987 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
989 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
991 DelayUS( 15 ) ; ////Start Auto-PreCharge
992 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
994 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
998 /* --------------------------------------------------------------------- */
999 /* Function : XGINew_DDR1x_DefaultRegister */
1003 /* --------------------------------------------------------------------- */
1004 void XGINew_DDR1x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1007 P3c4 = Port - 0x10 ;
1009 if ( HwDeviceExtension->jChipType >= XG20 )
1011 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1012 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1013 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1014 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1016 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1017 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1019 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
1023 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1025 switch( HwDeviceExtension->jChipType )
1029 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1030 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1031 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1034 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1035 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1036 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1037 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1038 XGINew_GetReg1( P3d4 , 0x86 ) ;
1039 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1040 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1041 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1042 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1043 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1044 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1045 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1046 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1050 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1051 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1052 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1053 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1058 /* --------------------------------------------------------------------- */
1059 /* Function : XGINew_DDR2x_DefaultRegister */
1063 /* --------------------------------------------------------------------- */
1064 void XGINew_DDR2x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port ,PVB_DEVICE_INFO pVBInfo)
1067 P3c4 = Port - 0x10 ;
1069 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1071 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1072 switch( HwDeviceExtension->jChipType )
1076 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1077 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1078 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1081 /* keep following setting sequence, each setting in the same reg insert idle */
1082 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1083 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1084 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1085 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1086 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1087 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1088 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1089 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1090 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1091 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1092 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1094 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1095 if ( HwDeviceExtension->jChipType == XG42 )
1097 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1101 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1103 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1105 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1109 /* --------------------------------------------------------------------- */
1110 /* Function : XGINew_DDR2_DefaultRegister */
1114 /* --------------------------------------------------------------------- */
1115 void XGINew_DDR2_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG Port , PVB_DEVICE_INFO pVBInfo)
1118 P3c4 = Port - 0x10 ;
1120 /* keep following setting sequence, each setting in the same reg insert idle */
1121 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1122 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1123 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1124 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1125 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1126 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1127 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1128 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1129 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1130 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1131 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1132 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1133 if ( HwDeviceExtension->jChipType == XG27 )
1134 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1136 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1138 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1139 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1140 if ( HwDeviceExtension->jChipType == XG27 )
1141 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1143 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1147 /* --------------------------------------------------------------------- */
1148 /* Function : XGINew_SetDRAMDefaultRegister340 */
1152 /* --------------------------------------------------------------------- */
1153 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1155 UCHAR temp , temp1 , temp2 , temp3 ,
1159 P3c4 = Port - 0x10 ;
1161 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1162 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1163 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1164 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1167 for( i = 0 ; i < 4 ; i++ )
1169 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1170 for( j = 0 ; j < 4 ; j++ )
1172 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1174 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1175 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1182 for( i = 0 ; i < 4 ; i++ )
1184 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1185 for( j = 0 ; j < 4 ; j++ )
1187 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1189 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1190 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1197 for( k = 0 ; k < 4 ; k++ )
1199 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1201 for( i = 0 ; i < 8 ; i++ )
1203 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1204 for( j = 0 ; j < 4 ; j++ )
1206 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1208 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1209 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1217 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1218 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1221 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1222 for( j = 0 ; j < 4 ; j++ )
1224 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1226 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1227 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1232 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1233 temp1 = temp & 0x03 ;
1235 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1237 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1238 temp1 = temp & 0x0F ;
1239 temp2 = ( temp >> 4 ) & 0x07 ;
1240 temp3 = temp & 0x80 ;
1241 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1242 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1243 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1244 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1246 if ( HwDeviceExtension->jChipType == XG27 )
1247 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1249 for( j = 0 ; j <= 6 ; j++ )
1250 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1252 for( j = 0 ; j <= 2 ; j++ )
1253 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1255 for( j = 0 ; j < 2 ; j++ )
1256 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1258 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1259 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1261 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1263 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1264 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1265 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1266 if ( XGINew_RAMType )
1268 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1269 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1270 if ( HwDeviceExtension->jChipType == XG27 )
1271 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1275 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1276 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1278 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1280 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1283 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1284 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1286 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1290 /* --------------------------------------------------------------------- */
1291 /* Function : XGINew_DDR_MRS */
1295 /* --------------------------------------------------------------------- */
1296 void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo)
1300 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
1302 /* SR16 <- 1F,DF,2F,AF */
1303 /* yriver modified SR16 <- 0F,DF,0F,AF */
1304 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1305 data = pVideoMemory[ 0xFB ] ;
1306 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1309 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1311 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1313 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1315 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1317 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1319 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1321 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1323 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1328 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1330 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1336 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1341 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1342 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1348 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1354 /* check if read cache pointer is correct */
1358 /* --------------------------------------------------------------------- */
1359 /* Function : XGINew_VerifyMclk */
1363 /* --------------------------------------------------------------------- */
1364 void XGINew_VerifyMclk( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1366 PUCHAR pVideoMemory = pVBInfo->FBAddr ;
1368 USHORT Temp , SR21 ;
1370 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1371 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1373 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1375 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1377 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1378 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1379 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1381 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1382 Temp |= 0x01 ; /* MCLK reset */
1385 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1386 Temp &= 0xFE ; /* MCLK normal operation */
1388 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1390 pVideoMemory[ 16 + j ] = j ;
1391 if ( pVideoMemory[ 16 + j ] == j )
1393 pVideoMemory[ j ] = j ;
1404 /* --------------------------------------------------------------------- */
1405 /* Function : XGINew_SetDRAMSize_340 */
1409 /* --------------------------------------------------------------------- */
1410 void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1414 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1415 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1417 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1420 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1421 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1422 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1424 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1426 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1427 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1428 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1429 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1434 /* --------------------------------------------------------------------- */
1439 /* --------------------------------------------------------------------- */
1440 void XGINew_SetDRAMSize_310( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1443 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1444 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1446 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1449 #ifdef XGI302 /* alan,should change value */
1450 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1451 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1452 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1455 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1457 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1458 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1460 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1462 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1464 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1467 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , ( USHORT )( data | 0x0F ) ) ; /* assume lowest speed DRAM */
1469 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1470 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1471 XGINew_CheckBusWidth_310( pVBInfo) ;
1472 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1476 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1478 XGINew_SDRSizing( pVBInfo ) ;
1482 XGINew_DDRSizing( pVBInfo) ;
1488 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , pVBInfo->SR15[ 1 ][ XGINew_RAMType ] ) ; /* restore SR16 */
1490 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1491 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1492 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1497 /* --------------------------------------------------------------------- */
1498 /* Function : XGINew_SetDRAMModeRegister340 */
1502 /* --------------------------------------------------------------------- */
1504 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension )
1507 VB_DEVICE_INFO VBINF;
1508 PVB_DEVICE_INFO pVBInfo = &VBINF;
1509 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1510 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1511 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
1512 pVBInfo->ISXPDOS = 0 ;
1514 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1515 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1516 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1517 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1518 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1519 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1520 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1521 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1522 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1523 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1524 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1525 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1526 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1527 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1528 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1529 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1530 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1531 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1532 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1534 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1536 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1538 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1540 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1542 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1544 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1547 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1549 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1552 /* --------------------------------------------------------------------- */
1553 /* Function : XGINew_SetDRAMModeRegister */
1557 /* --------------------------------------------------------------------- */
1558 void XGINew_SetDRAMModeRegister( PVB_DEVICE_INFO pVBInfo)
1560 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1562 XGINew_SDR_MRS(pVBInfo ) ;
1566 /* SR16 <- 0F,CF,0F,8F */
1567 XGINew_DDR_MRS( pVBInfo ) ;
1572 /* --------------------------------------------------------------------- */
1573 /* Function : XGINew_DisableRefresh */
1577 /* --------------------------------------------------------------------- */
1578 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1583 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1585 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1590 /* --------------------------------------------------------------------- */
1591 /* Function : XGINew_EnableRefresh */
1595 /* --------------------------------------------------------------------- */
1596 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1599 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1605 /* --------------------------------------------------------------------- */
1606 /* Function : XGINew_DisableChannelInterleaving */
1610 /* --------------------------------------------------------------------- */
1611 void XGINew_DisableChannelInterleaving( int index , USHORT XGINew_DDRDRAM_TYPE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1615 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1618 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1635 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1639 /* --------------------------------------------------------------------- */
1640 /* Function : XGINew_SetDRAMSizingType */
1644 /* --------------------------------------------------------------------- */
1645 void XGINew_SetDRAMSizingType( int index , USHORT DRAMTYPE_TABLE[][ 5 ] ,PVB_DEVICE_INFO pVBInfo)
1649 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1650 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1652 /* should delay 50 ns */
1656 /* --------------------------------------------------------------------- */
1657 /* Function : XGINew_CheckBusWidth_310 */
1661 /* --------------------------------------------------------------------- */
1662 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO pVBInfo)
1665 PULONG volatile pVideoMemory ;
1667 pVideoMemory = (PULONG) pVBInfo->FBAddr;
1669 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1671 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1672 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1674 XGINew_SDR_MRS( pVBInfo ) ;
1676 XGINew_ChannelAB = 0 ;
1677 XGINew_DataBusWidth = 128 ;
1678 pVideoMemory[ 0 ] = 0x01234567L ;
1679 pVideoMemory[ 1 ] = 0x456789ABL ;
1680 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1681 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1682 pVideoMemory[ 4 ] = 0x55555555L ;
1683 pVideoMemory[ 5 ] = 0x55555555L ;
1684 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1685 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1687 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1690 XGINew_DataBusWidth = 64 ;
1691 XGINew_ChannelAB = 0 ;
1692 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1693 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( data & 0xFD ) ) ;
1696 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1699 XGINew_DataBusWidth = 64 ;
1700 XGINew_ChannelAB = 1 ;
1701 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1702 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( ( data & 0xFD ) | 0x01 ) ) ;
1709 /* DDR Dual channel */
1710 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1711 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1713 XGINew_DDR_MRS( pVBInfo ) ;
1715 XGINew_ChannelAB = 0 ;
1716 XGINew_DataBusWidth = 64 ;
1717 pVideoMemory[ 0 ] = 0x01234567L ;
1718 pVideoMemory[ 1 ] = 0x456789ABL ;
1719 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1720 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1721 pVideoMemory[ 4 ] = 0x55555555L ;
1722 pVideoMemory[ 5 ] = 0x55555555L ;
1723 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1724 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1726 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1728 if ( pVideoMemory[ 0 ] == 0x01234567L )
1730 /* Channel A 64bit */
1736 if ( pVideoMemory[ 0 ] == 0x01234567L )
1738 /* Channel A 32bit */
1739 XGINew_DataBusWidth = 32 ;
1740 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1745 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1746 XGINew_DDR_MRS( pVBInfo);
1748 XGINew_ChannelAB = 1 ;
1749 XGINew_DataBusWidth = 64 ;
1750 pVideoMemory[ 0 ] = 0x01234567L ;
1751 pVideoMemory[ 1 ] = 0x456789ABL ;
1752 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1753 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1754 pVideoMemory[ 4 ] = 0x55555555L ;
1755 pVideoMemory[ 5 ] = 0x55555555L ;
1756 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1757 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1759 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1762 if ( pVideoMemory[ 0 ] == 0x01234567L )
1764 /* Channel B 64bit */
1774 if ( pVideoMemory[ 0 ] == 0x01234567L )
1777 XGINew_DataBusWidth = 32 ;
1778 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1789 /* --------------------------------------------------------------------- */
1790 /* Function : XGINew_SetRank */
1794 /* --------------------------------------------------------------------- */
1795 int XGINew_SetRank( int index , UCHAR RankNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1800 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1803 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1805 if ( ( RankNo * RankSize ) <= 128 )
1809 while( ( RankSize >>= 1 ) > 0 )
1813 data |= ( RankNo - 1 ) << 2 ;
1814 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1815 data |= XGINew_ChannelAB ;
1816 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1818 XGINew_SDR_MRS( pVBInfo ) ;
1826 /* --------------------------------------------------------------------- */
1827 /* Function : XGINew_SetDDRChannel */
1831 /* --------------------------------------------------------------------- */
1832 int XGINew_SetDDRChannel( int index , UCHAR ChannelNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1837 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1838 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1839 if ( ChannelNo * RankSize <= 128 )
1842 while( ( RankSize >>= 1 ) > 0 )
1847 if ( ChannelNo == 2 )
1850 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1851 data |= XGINew_ChannelAB ;
1852 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1854 XGINew_DDR_MRS( pVBInfo ) ;
1862 /* --------------------------------------------------------------------- */
1863 /* Function : XGINew_CheckColumn */
1867 /* --------------------------------------------------------------------- */
1868 int XGINew_CheckColumn( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1871 ULONG Increment , Position ;
1873 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1874 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1876 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1878 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1879 Position += Increment ;
1882 #ifdef WIN2000 /* chiawen for linux solution */
1886 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1888 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1889 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1891 Position += Increment ;
1897 /* --------------------------------------------------------------------- */
1898 /* Function : XGINew_CheckBanks */
1902 /* --------------------------------------------------------------------- */
1903 int XGINew_CheckBanks( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1906 ULONG Increment , Position ;
1908 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1910 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1912 /* pVBInfo->FBAddr[ Position ] = Position ; */
1913 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1914 Position += Increment ;
1917 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1919 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1920 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1922 Position += Increment ;
1928 /* --------------------------------------------------------------------- */
1929 /* Function : XGINew_CheckRank */
1933 /* --------------------------------------------------------------------- */
1934 int XGINew_CheckRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1937 ULONG Increment , Position ;
1939 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1940 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1942 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1944 /* pVBInfo->FBAddr[ Position ] = Position ; */
1945 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */
1946 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1947 Position += Increment ;
1950 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1952 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1953 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */
1954 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1956 Position += Increment ;
1962 /* --------------------------------------------------------------------- */
1963 /* Function : XGINew_CheckDDRRank */
1967 /* --------------------------------------------------------------------- */
1968 int XGINew_CheckDDRRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1970 ULONG Increment , Position ;
1973 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1974 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1976 Increment += Increment / 2 ;
1979 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ;
1980 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ;
1981 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ;
1982 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ;
1983 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ;
1984 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ;
1986 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB )
1989 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 )
1992 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1995 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1996 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1998 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
2004 /* --------------------------------------------------------------------- */
2005 /* Function : XGINew_CheckRanks */
2009 /* --------------------------------------------------------------------- */
2010 int XGINew_CheckRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2014 for( r = RankNo ; r >= 1 ; r-- )
2016 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2020 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2023 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2030 /* --------------------------------------------------------------------- */
2031 /* Function : XGINew_CheckDDRRanks */
2035 /* --------------------------------------------------------------------- */
2036 int XGINew_CheckDDRRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2040 for( r = RankNo ; r >= 1 ; r-- )
2042 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2046 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2049 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2056 /* --------------------------------------------------------------------- */
2061 /* --------------------------------------------------------------------- */
2062 int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo)
2067 for( i = 0 ; i < 13 ; i++ )
2069 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2071 for( j = 2 ; j > 0 ; j-- )
2073 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) )
2077 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2086 /* --------------------------------------------------------------------- */
2087 /* Function : XGINew_SetDRAMSizeReg */
2091 /* --------------------------------------------------------------------- */
2092 USHORT XGINew_SetDRAMSizeReg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2094 USHORT data = 0 , memsize = 0 ;
2098 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2099 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2107 if( XGINew_ChannelAB == 3 )
2110 ChannelNo = XGINew_ChannelAB ;
2112 if ( ChannelNo * RankSize <= 256 )
2114 while( ( RankSize >>= 1 ) > 0 )
2119 memsize = data >> 4 ;
2121 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2122 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2124 /* data |= XGINew_ChannelAB << 2 ; */
2125 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2126 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2129 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2135 /* --------------------------------------------------------------------- */
2136 /* Function : XGINew_SetDRAMSize20Reg */
2140 /* --------------------------------------------------------------------- */
2141 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2143 USHORT data = 0 , memsize = 0 ;
2147 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2148 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2156 if( XGINew_ChannelAB == 3 )
2159 ChannelNo = XGINew_ChannelAB ;
2161 if ( ChannelNo * RankSize <= 256 )
2163 while( ( RankSize >>= 1 ) > 0 )
2168 memsize = data >> 4 ;
2170 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2171 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2174 /* data |= XGINew_ChannelAB << 2 ; */
2175 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2176 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2179 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2185 /* --------------------------------------------------------------------- */
2186 /* Function : XGINew_ReadWriteRest */
2190 /* --------------------------------------------------------------------- */
2191 int XGINew_ReadWriteRest( USHORT StopAddr , USHORT StartAddr, PVB_DEVICE_INFO pVBInfo)
2194 ULONG Position = 0 ;
2196 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2198 for( i = StartAddr ; i <= StopAddr ; i++ )
2201 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2204 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2208 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2211 for( i = StartAddr ; i <= StopAddr ; i++ )
2214 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2221 /* --------------------------------------------------------------------- */
2222 /* Function : XGINew_CheckFrequence */
2226 /* --------------------------------------------------------------------- */
2227 UCHAR XGINew_CheckFrequence( PVB_DEVICE_INFO pVBInfo )
2231 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2233 if ( ( data & 0x10 ) == 0 )
2235 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2236 data = ( data & 0x02 ) >> 1 ;
2240 return( data & 0x01 ) ;
2244 /* --------------------------------------------------------------------- */
2245 /* Function : XGINew_CheckChannel */
2249 /* --------------------------------------------------------------------- */
2250 void XGINew_CheckChannel( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2254 switch( HwDeviceExtension->jChipType )
2258 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2260 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2262 if ( data == 0 ) /* Single_32_16 */
2265 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2268 XGINew_DataBusWidth = 32 ; /* 32 bits */
2269 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2270 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2273 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2276 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2279 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2282 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2287 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2289 XGINew_DataBusWidth = 16 ; /* 16 bits */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2291 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2294 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2297 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2302 else /* Dual_16_8 */
2304 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2307 XGINew_DataBusWidth = 16 ; /* 16 bits */
2308 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2309 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2312 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2315 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2317 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2318 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2321 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2327 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2329 XGINew_DataBusWidth = 8 ; /* 8 bits */
2330 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2331 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2334 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2337 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2344 XGINew_DataBusWidth = 16 ; /* 16 bits */
2345 XGINew_ChannelAB = 1 ; /* Single channel */
2346 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2349 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2351 XGINew_DataBusWidth = 32 ; /* 32 bits */
2352 XGINew_ChannelAB = 3 ; /* Quad Channel */
2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2354 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2356 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2359 XGINew_ChannelAB = 2 ; /* Dual channels */
2360 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2362 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2365 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2367 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2370 XGINew_ChannelAB = 3 ;
2371 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2372 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2374 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2377 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2379 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2382 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2386 XGINew_DataBusWidth = 64 ; /* 64 bits */
2387 XGINew_ChannelAB = 2 ; /* Dual channels */
2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2389 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2391 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2394 XGINew_ChannelAB = 1 ; /* Single channels */
2395 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2397 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2400 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2402 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2405 XGINew_ChannelAB = 2 ; /* Dual channels */
2406 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2407 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2409 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2412 XGINew_ChannelAB = 1 ; /* Single channels */
2413 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2415 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2418 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2425 XG42 SR14 D[3] Reserve
2426 D[2] = 1, Dual Channel
2429 It's Different from Other XG40 Series.
2431 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2433 XGINew_DataBusWidth = 32 ; /* 32 bits */
2434 XGINew_ChannelAB = 2 ; /* 2 Channel */
2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2436 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2438 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2441 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2442 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2443 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2446 XGINew_ChannelAB = 1 ; /* Single Channel */
2447 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2448 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2450 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2454 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2455 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2460 XGINew_DataBusWidth = 64 ; /* 64 bits */
2461 XGINew_ChannelAB = 1 ; /* 1 channels */
2462 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2463 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2465 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2469 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2478 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2480 XGINew_DataBusWidth = 32 ; /* 32 bits */
2481 XGINew_ChannelAB = 3 ;
2482 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2483 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2485 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2488 XGINew_ChannelAB = 2 ; /* 2 channels */
2489 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2491 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2494 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2495 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2497 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2498 XGINew_ChannelAB = 3 ; /* 4 channels */
2501 XGINew_ChannelAB = 2 ; /* 2 channels */
2502 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2507 XGINew_DataBusWidth = 64 ; /* 64 bits */
2508 XGINew_ChannelAB = 2 ; /* 2 channels */
2509 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2510 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2512 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2516 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2517 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2525 /* --------------------------------------------------------------------- */
2526 /* Function : XGINew_DDRSizing340 */
2530 /* --------------------------------------------------------------------- */
2531 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2534 USHORT memsize , addr ;
2536 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2537 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2538 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2541 if ( HwDeviceExtension->jChipType >= XG20 )
2543 for( i = 0 ; i < 12 ; i++ )
2545 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2546 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2550 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2551 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2554 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2560 for( i = 0 ; i < 4 ; i++ )
2562 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2563 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2568 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2569 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2572 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2580 /* --------------------------------------------------------------------- */
2581 /* Function : XGINew_DDRSizing */
2585 /* --------------------------------------------------------------------- */
2586 int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo)
2591 for( i = 0 ; i < 4 ; i++ )
2593 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2594 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2595 for( j = 2 ; j > 0 ; j-- )
2597 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2598 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2602 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2610 /* --------------------------------------------------------------------- */
2611 /* Function : XGINew_SetMemoryClock */
2615 /* --------------------------------------------------------------------- */
2616 void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2620 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2621 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2622 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2626 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2627 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2628 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2630 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2631 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2632 if ( HwDeviceExtension->jChipType == XG42 )
2634 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2635 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2636 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2638 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2644 /* --------------------------------------------------------------------- */
2645 /* Function : ChkLFB */
2649 /* --------------------------------------------------------------------- */
2650 BOOLEAN ChkLFB( PVB_DEVICE_INFO pVBInfo )
2652 if ( LFBDRAMTrap & XGINew_GetReg1( pVBInfo->P3d4 , 0x78 ) )
2659 /* --------------------------------------------------------------------- */
2660 /* input : dx ,valid value : CR or second chip's CR */
2662 /* SetPowerConsume : */
2663 /* Description: reduce 40/43 power consumption in first chip or */
2664 /* in second chip, assume CR A1 D[6]="1" in this case */
2666 /* --------------------------------------------------------------------- */
2667 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG XGI_P3d4Port )
2672 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2673 if ((lTemp&0xFF)==0)
2675 /* set CR58 D[5]=0 D[3]=0 */
2676 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2677 bTemp = (UCHAR) XGINew_GetReg1( XGI_P3d4Port , 0xCB ) ;
2682 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2686 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2696 #if defined(LINUX_XF86)||defined(LINUX_KERNEL)
2697 void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2700 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
2701 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2702 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2703 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
2704 pVBInfo->ISXPDOS = 0 ;
2706 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2707 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2708 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2709 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2710 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2711 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2712 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2713 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2714 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2715 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2716 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2717 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2718 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2719 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2720 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2721 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2722 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2723 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2724 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2726 switch(HwDeviceExtension->jChipType)
2734 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2739 #endif /* For Linux */
2741 /* --------------------------------------------------------------------- */
2742 /* Function : ReadVBIOSTablData */
2746 /* --------------------------------------------------------------------- */
2747 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo)
2749 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
2754 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */
2759 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2761 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ;
2762 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ;
2763 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ;
2764 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2769 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2771 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ;
2772 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ;
2773 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ;
2774 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2778 /* Volari customize data area start */
2779 /* if ( ChipType == XG40 ) */
2780 if ( ChipType >= XG40 )
2783 for( jj = 0x00 ; jj < 0x03 ; jj++ )
2785 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */
2786 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2787 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2788 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2789 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2790 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2791 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2792 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2797 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */
2798 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2799 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2800 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2801 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2802 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2803 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2804 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2806 *pVBInfo->pSR07 = pVideoMemory[ 0x74 ] ;
2807 *pVBInfo->pSR1F = pVideoMemory[ 0x75 ] ;
2808 *pVBInfo->pSR21 = pVideoMemory[ 0x76 ] ;
2809 *pVBInfo->pSR22 = pVideoMemory[ 0x77 ] ;
2810 *pVBInfo->pSR23 = pVideoMemory[ 0x78 ] ;
2811 *pVBInfo->pSR24 = pVideoMemory[ 0x79 ] ;
2812 pVBInfo->SR25[ 0 ] = pVideoMemory[ 0x7A ] ;
2813 *pVBInfo->pSR31 = pVideoMemory[ 0x7B ] ;
2814 *pVBInfo->pSR32 = pVideoMemory[ 0x7C ] ;
2815 *pVBInfo->pSR33 = pVideoMemory[ 0x7D ] ;
2818 for( jj = 0 ; jj < 3 ; jj++ )
2820 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ;
2821 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2822 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2823 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2824 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2825 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2826 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2827 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2832 for( j = 3 ; j < 24 ; j++ )
2834 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ;
2835 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2836 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2837 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2838 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2839 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2840 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2841 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2845 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ;
2847 for( j = 0 ; j < 8 ; j++ )
2849 for( k = 0 ; k < 4 ; k++ )
2850 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2853 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ;
2855 for( j = 0 ; j < 8 ; j++ )
2857 for( k = 0 ; k < 4 ; k++ )
2858 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2861 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ;
2862 for( j = 0 ; j < 8 ; j++ )
2864 for( k = 0 ; k < 32 ; k++ )
2865 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ;
2868 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ;
2870 for( j = 0 ; j < 8 ; j++ )
2872 for( k = 0 ; k < 2 ; k++ )
2873 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ;
2876 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ;
2877 for( j = 0 ; j < 12 ; j++ )
2878 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ;
2880 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ;
2881 for( j = 0 ; j < 4 ; j++ )
2882 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ;
2884 if ( ChipType == XG21 )
2886 if (pVideoMemory[ 0x67 ] & 0x80)
2888 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2890 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2892 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ;
2893 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ;
2894 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ;
2895 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ;
2899 if ( ChipType == XG27 )
2902 for( i = 0 ; i <= 0xB ; i++,jj++ )
2903 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ;
2904 for( i = 0x0 ; i <= 0x1 ; i++,jj++ )
2905 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ;
2907 *pVBInfo->pSR40 = pVideoMemory[ jj ] ;
2909 *pVBInfo->pSR41 = pVideoMemory[ jj ] ;
2911 if (pVideoMemory[ 0x67 ] & 0x80)
2913 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2915 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2918 *pVBInfo->pCR2E = pVideoMemory[ jj ] ;
2919 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ;
2920 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ;
2921 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ;
2926 *pVBInfo->pCRCF = pVideoMemory[ 0x1CA ] ;
2927 *pVBInfo->pXGINew_DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ;
2928 *pVBInfo->pXGINew_I2CDefinition = pVideoMemory[ 0x1D1 ] ;
2929 if ( ChipType >= XG20 )
2931 *pVBInfo->pXGINew_CR97 = pVideoMemory[ 0x1D2 ] ;
2932 if ( ChipType == XG27 )
2934 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ;
2935 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ;
2941 /* Volari customize data area end */
2943 if ( ChipType == XG21 )
2945 pVBInfo->IF_DEF_LVDS = 0 ;
2946 if (pVideoMemory[ 0x65 ] & 0x1)
2948 pVBInfo->IF_DEF_LVDS = 1 ;
2949 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2950 j = pVideoMemory[ i-1 ] ;
2956 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2957 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2958 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2959 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2960 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2961 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2962 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2963 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2964 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2965 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2966 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2967 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2968 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2969 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2970 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2971 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2975 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) );
2979 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2980 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2981 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2982 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2983 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2984 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2985 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2986 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2987 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2988 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2989 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2990 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2991 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2992 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2993 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2994 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
3000 /* --------------------------------------------------------------------- */
3001 /* Function : XGINew_DDR1x_MRS_XG20 */
3005 /* --------------------------------------------------------------------- */
3006 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
3009 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
3010 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
3011 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
3012 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3015 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
3016 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
3017 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
3018 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3020 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3021 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3022 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
3023 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3024 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3026 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
3028 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3029 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3030 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
3031 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3032 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3033 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
3036 /* --------------------------------------------------------------------- */
3037 /* Function : XGINew_SetDRAMModeRegister_XG20 */
3041 /* --------------------------------------------------------------------- */
3042 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3044 VB_DEVICE_INFO VBINF;
3045 PVB_DEVICE_INFO pVBInfo = &VBINF;
3046 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3047 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3048 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3049 pVBInfo->ISXPDOS = 0 ;
3051 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3052 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3053 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3054 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3055 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3056 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3057 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3058 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3059 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3060 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3061 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3062 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3063 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3064 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3065 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3066 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3067 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3069 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3071 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3073 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3074 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3076 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3078 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3081 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3083 VB_DEVICE_INFO VBINF;
3084 PVB_DEVICE_INFO pVBInfo = &VBINF;
3085 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3086 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3087 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3088 pVBInfo->ISXPDOS = 0 ;
3090 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3091 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3092 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3093 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3094 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3095 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3096 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3097 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3098 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3099 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3100 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3101 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3102 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3103 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3104 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3105 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3106 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3108 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3110 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3112 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3113 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3115 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3116 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3118 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3119 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
3123 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3128 VB_DEVICE_INFO VBINF;
3129 PVB_DEVICE_INFO pVBInfo = &VBINF;
3130 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3131 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3132 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
3133 pVBInfo->ISXPDOS = 0 ;
3135 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3136 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3137 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3138 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3139 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3140 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3141 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3142 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3143 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3144 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3145 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3146 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3147 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3148 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3149 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3150 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3151 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3153 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3155 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3157 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3158 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3160 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3162 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3165 /* -------------------------------------------------------- */
3166 /* Function : XGINew_ChkSenseStatus */
3170 /* -------------------------------------------------------- */
3171 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
3173 USHORT tempbx=0 , temp , tempcx , CR3CData;
3175 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
3177 if ( temp & Monitor1Sense )
3178 tempbx |= ActiveCRT1 ;
3179 if ( temp & LCDSense )
3180 tempbx |= ActiveLCD ;
3181 if ( temp & Monitor2Sense )
3182 tempbx |= ActiveCRT2 ;
3183 if ( temp & TVSense )
3185 tempbx |= ActiveTV ;
3186 if ( temp & AVIDEOSense )
3187 tempbx |= ( ActiveAVideo << 8 );
3188 if ( temp & SVIDEOSense )
3189 tempbx |= ( ActiveSVideo << 8 );
3190 if ( temp & SCARTSense )
3191 tempbx |= ( ActiveSCART << 8 );
3192 if ( temp & HiTVSense )
3193 tempbx |= ( ActiveHiTV << 8 );
3194 if ( temp & YPbPrSense )
3195 tempbx |= ( ActiveYPbPr << 8 );
3198 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3199 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3201 if ( tempbx & tempcx )
3203 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3204 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3207 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3216 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3223 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3224 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3226 /* -------------------------------------------------------- */
3227 /* Function : XGINew_SetModeScratch */
3231 /* -------------------------------------------------------- */
3232 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo )
3234 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3236 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3237 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3238 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3240 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3242 if ( temp & ActiveCRT2 )
3243 tempcl = SetCRT2ToRAMDAC ;
3246 if ( temp & ActiveLCD )
3248 tempcl |= SetCRT2ToLCD ;
3249 if ( temp & DriverMode )
3251 if ( temp & ActiveTV )
3253 tempch = SetToLCDA | EnableDualEdge ;
3254 temp ^= SetCRT2ToLCD ;
3256 if ( ( temp >> 8 ) & ActiveAVideo )
3257 tempcl |= SetCRT2ToAVIDEO ;
3258 if ( ( temp >> 8 ) & ActiveSVideo )
3259 tempcl |= SetCRT2ToSVIDEO ;
3260 if ( ( temp >> 8 ) & ActiveSCART )
3261 tempcl |= SetCRT2ToSCART ;
3263 if ( pVBInfo->IF_DEF_HiVision == 1 )
3265 if ( ( temp >> 8 ) & ActiveHiTV )
3266 tempcl |= SetCRT2ToHiVisionTV ;
3269 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3271 if ( ( temp >> 8 ) & ActiveYPbPr )
3272 tempch |= SetYPbPr ;
3279 if ( ( temp >> 8 ) & ActiveAVideo )
3280 tempcl |= SetCRT2ToAVIDEO ;
3281 if ( ( temp >> 8 ) & ActiveSVideo )
3282 tempcl |= SetCRT2ToSVIDEO ;
3283 if ( ( temp >> 8 ) & ActiveSCART )
3284 tempcl |= SetCRT2ToSCART ;
3286 if ( pVBInfo->IF_DEF_HiVision == 1 )
3288 if ( ( temp >> 8 ) & ActiveHiTV )
3289 tempcl |= SetCRT2ToHiVisionTV ;
3292 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3294 if ( ( temp >> 8 ) & ActiveYPbPr )
3295 tempch |= SetYPbPr ;
3300 tempcl |= SetSimuScanMode ;
3301 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3302 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3303 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3304 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3305 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3307 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3308 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3309 if ( !( temp & ActiveCRT1 ) )
3310 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3311 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3312 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3313 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3314 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3316 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3317 CR38Data &= ~SetYPbPr ;
3318 CR38Data |= tempch ;
3319 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3323 /* -------------------------------------------------------- */
3324 /* Function : XGINew_GetXG21Sense */
3328 /* -------------------------------------------------------- */
3329 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3332 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
3334 pVBInfo->IF_DEF_LVDS = 0 ;
3337 pVBInfo->IF_DEF_CH7007 = 0 ;
3338 if ( ( pVideoMemory[ 0x65 ] & 0x02 ) ) /* For XG21 CH7007 */
3340 /* VideoDebugPrint((0, "ReadVBIOSTablData: pVideoMemory[ 0x65 ] =%x\n",pVideoMemory[ 0x65 ])); */
3341 pVBInfo->IF_DEF_CH7007 = 1 ; /* [Billy] 07/05/03 */
3342 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x60 ) ; /* CH7007 on chip */
3347 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3349 pVBInfo->IF_DEF_LVDS = 1 ;
3350 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3351 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3356 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3357 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3359 { /* DVI & DVO GPIOA/B pull high */
3360 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3361 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3362 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3363 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3365 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3367 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3368 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3375 /* -------------------------------------------------------- */
3376 /* Function : XGINew_GetXG27Sense */
3380 /* -------------------------------------------------------- */
3381 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3385 pVBInfo->IF_DEF_LVDS = 0 ;
3386 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3387 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3388 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3389 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3393 pVBInfo->IF_DEF_LVDS = 1 ;
3394 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3395 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3399 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3401 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3405 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo)
3407 UCHAR CR38,CR4A,temp;
3409 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3410 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3411 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3413 if ( ( CR38 & 0xE0 ) > 0x80 )
3415 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3420 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3425 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo)
3429 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3430 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3431 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3438 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3440 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;