drivers/staging/xgifb/vb_init.c

   1 #include <linux/types.h>
   2 #include <linux/delay.h> /* udelay */
   3 #include <linux/pci.h>
   4 #include <linux/vmalloc.h>
   5
   6 #include "XGIfb.h"
   7 #include "vgatypes.h"
   8
   9 #include "vb_def.h"
  10 #include "vb_struct.h"
  11 #include "vb_util.h"
  12 #include "vb_setmode.h"
  13 #include "vb_init.h"
  14
  15
  16 #include <linux/io.h>
  17
  18 static const unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  19         { 2, 13, 9, 64, 0x45},
  20         { 2, 12, 9, 32, 0x35},
  21         { 2, 12, 8, 16, 0x31},
  22         { 2, 11, 8,  8, 0x21} };
  23
  24 static const unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  25         { 2, 14, 11, 128, 0x5D},
  26         { 2, 14, 10, 64, 0x59},
  27         { 2, 13, 11, 64, 0x4D},
  28         { 2, 14,  9, 32, 0x55},
  29         { 2, 13, 10, 32, 0x49},
  30         { 2, 12, 11, 32, 0x3D},
  31         { 2, 14,  8, 16, 0x51},
  32         { 2, 13,  9, 16, 0x45},
  33         { 2, 12, 10, 16, 0x39},
  34         { 2, 13,  8,  8, 0x41},
  35         { 2, 12,  9,  8, 0x35},
  36         { 2, 12,  8,  4, 0x31} };
  37
  38 #define XGIFB_ROM_SIZE  65536
  39
  40 static unsigned char
  41 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  42                        struct vb_device_info *pVBInfo)
  43 {
  44         unsigned char data, temp;
  45
  46         if (HwDeviceExtension->jChipType < XG20) {
  47                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  48                         data = *pVBInfo->pSoftSetting & 0x07;
  49                         return data;
  50                 } else {
  51                         data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  52                         if (data == 0)
  53                                 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  54                                        0x02) >> 1;
  55                         return data;
  56                 }
  57         } else if (HwDeviceExtension->jChipType == XG27) {
  58                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  59                         data = *pVBInfo->pSoftSetting & 0x07;
  60                         return data;
  61                 }
  62                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  63                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  64                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  65                         data = 0; /* DDR */
  66                 else
  67                         data = 1; /* DDRII */
  68                 return data;
  69         } else if (HwDeviceExtension->jChipType == XG21) {
  70                 /* Independent GPIO control */
  71                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  72                 udelay(800);
  73                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  74                 /* GPIOF 0:DVI 1:DVO */
  75                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  76                 /* HOTPLUG_SUPPORT */
  77                 /* for current XG20 & XG21, GPIOH is floating, driver will
  78                  * fix DDR temporarily */
  79                 if (temp & 0x01) /* DVI read GPIOH */
  80                         data = 1; /* DDRII */
  81                 else
  82                         data = 0; /* DDR */
  83                 /* ~HOTPLUG_SUPPORT */
  84                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  85                 return data;
  86         } else {
  87                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  88
  89                 if (data == 1)
  90                         data++;
  91
  92                 return data;
  93         }
  94 }
  95
  96 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  97                                  struct vb_device_info *pVBInfo)
  98 {
  99         xgifb_reg_set(P3c4, 0x18, 0x01);
 100         xgifb_reg_set(P3c4, 0x19, 0x20);
 101         xgifb_reg_set(P3c4, 0x16, 0x00);
 102         xgifb_reg_set(P3c4, 0x16, 0x80);
 103
 104         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
 105                 mdelay(3);
 106                 xgifb_reg_set(P3c4, 0x18, 0x00);
 107                 xgifb_reg_set(P3c4, 0x19, 0x20);
 108                 xgifb_reg_set(P3c4, 0x16, 0x00);
 109                 xgifb_reg_set(P3c4, 0x16, 0x80);
 110         }
 111
 112         udelay(60);
 113         xgifb_reg_set(P3c4,
 114                       0x18,
 115                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 116         xgifb_reg_set(P3c4, 0x19, 0x01);
 117         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
 118         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
 119         mdelay(1);
 120         xgifb_reg_set(P3c4, 0x1B, 0x03);
 121         udelay(500);
 122         xgifb_reg_set(P3c4,
 123                       0x18,
 124                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 125         xgifb_reg_set(P3c4, 0x19, 0x00);
 126         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
 127         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
 128         xgifb_reg_set(P3c4, 0x1B, 0x00);
 129 }
 130
 131 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 132                 struct vb_device_info *pVBInfo)
 133 {
 134
 135         xgifb_reg_set(pVBInfo->P3c4,
 136                       0x28,
 137                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 138         xgifb_reg_set(pVBInfo->P3c4,
 139                       0x29,
 140                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 141         xgifb_reg_set(pVBInfo->P3c4,
 142                       0x2A,
 143                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 144
 145         xgifb_reg_set(pVBInfo->P3c4,
 146                       0x2E,
 147                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
 148         xgifb_reg_set(pVBInfo->P3c4,
 149                       0x2F,
 150                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
 151         xgifb_reg_set(pVBInfo->P3c4,
 152                       0x30,
 153                       pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
 154
 155         /* [Vicent] 2004/07/07,
 156          * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 157         /* [Hsuan] 2004/08/20,
 158          * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 159          * Set SR32 D[1:0] = 10b */
 160         if (HwDeviceExtension->jChipType == XG42) {
 161                 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
 162                     (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
 163                     (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
 164                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
 165                      ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
 166                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
 167                         xgifb_reg_set(pVBInfo->P3c4,
 168                                       0x32,
 169                                       ((unsigned char) xgifb_reg_get(
 170                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 171         }
 172 }
 173
 174 static void XGINew_DDRII_Bootup_XG27(
 175                         struct xgi_hw_device_info *HwDeviceExtension,
 176                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 177 {
 178         unsigned long P3d4 = P3c4 + 0x10;
 179         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 180         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 181
 182         /* Set Double Frequency */
 183         /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
 184         xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 185
 186         udelay(200);
 187
 188         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 189         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 190         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 191         udelay(15);
 192         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 193         udelay(15);
 194
 195         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 196         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 197         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 198         udelay(15);
 199         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 200         udelay(15);
 201
 202         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 203         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 204         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 205         udelay(30);
 206         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 207         udelay(15);
 208
 209         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 210         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 211         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 212         udelay(30);
 213         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 214         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 215         /* udelay(15); */
 216
 217         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 218         udelay(60);
 219         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 220
 221         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 222         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 223         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 224
 225         udelay(30);
 226         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 227         udelay(15);
 228
 229         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 230         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 231         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 232         udelay(30);
 233         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 234         udelay(15);
 235
 236         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 237         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 238         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 239         udelay(30);
 240         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 241         udelay(15);
 242
 243         /* Set SR1B refresh control 000:close; 010:open */
 244         xgifb_reg_set(P3c4, 0x1B, 0x04);
 245         udelay(200);
 246
 247 }
 248
 249 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 250                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 251 {
 252         unsigned long P3d4 = P3c4 + 0x10;
 253
 254         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 255         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 256
 257         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 258
 259         udelay(200);
 260         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 261         xgifb_reg_set(P3c4, 0x19, 0x80);
 262         xgifb_reg_set(P3c4, 0x16, 0x05);
 263         xgifb_reg_set(P3c4, 0x16, 0x85);
 264
 265         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 266         xgifb_reg_set(P3c4, 0x19, 0xC0);
 267         xgifb_reg_set(P3c4, 0x16, 0x05);
 268         xgifb_reg_set(P3c4, 0x16, 0x85);
 269
 270         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 271         xgifb_reg_set(P3c4, 0x19, 0x40);
 272         xgifb_reg_set(P3c4, 0x16, 0x05);
 273         xgifb_reg_set(P3c4, 0x16, 0x85);
 274
 275         /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
 276         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 277         xgifb_reg_set(P3c4, 0x19, 0x02);
 278         xgifb_reg_set(P3c4, 0x16, 0x05);
 279         xgifb_reg_set(P3c4, 0x16, 0x85);
 280
 281         udelay(15);
 282         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 283         udelay(30);
 284         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 285         udelay(100);
 286
 287         /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
 288         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 289         xgifb_reg_set(P3c4, 0x19, 0x00);
 290         xgifb_reg_set(P3c4, 0x16, 0x05);
 291         xgifb_reg_set(P3c4, 0x16, 0x85);
 292
 293         udelay(200);
 294 }
 295
 296 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 297                                   struct vb_device_info *pVBInfo)
 298 {
 299         xgifb_reg_set(P3c4, 0x18, 0x01);
 300         xgifb_reg_set(P3c4, 0x19, 0x40);
 301         xgifb_reg_set(P3c4, 0x16, 0x00);
 302         xgifb_reg_set(P3c4, 0x16, 0x80);
 303         udelay(60);
 304
 305         xgifb_reg_set(P3c4, 0x18, 0x00);
 306         xgifb_reg_set(P3c4, 0x19, 0x40);
 307         xgifb_reg_set(P3c4, 0x16, 0x00);
 308         xgifb_reg_set(P3c4, 0x16, 0x80);
 309         udelay(60);
 310         xgifb_reg_set(P3c4,
 311                       0x18,
 312                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 313         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 314         xgifb_reg_set(P3c4, 0x19, 0x01);
 315         xgifb_reg_set(P3c4, 0x16, 0x03);
 316         xgifb_reg_set(P3c4, 0x16, 0x83);
 317         mdelay(1);
 318         xgifb_reg_set(P3c4, 0x1B, 0x03);
 319         udelay(500);
 320         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 321         xgifb_reg_set(P3c4,
 322                       0x18,
 323                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 324         xgifb_reg_set(P3c4, 0x19, 0x00);
 325         xgifb_reg_set(P3c4, 0x16, 0x03);
 326         xgifb_reg_set(P3c4, 0x16, 0x83);
 327         xgifb_reg_set(P3c4, 0x1B, 0x00);
 328 }
 329
 330 static void XGINew_DDR1x_DefaultRegister(
 331                 struct xgi_hw_device_info *HwDeviceExtension,
 332                 unsigned long Port, struct vb_device_info *pVBInfo)
 333 {
 334         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 335
 336         if (HwDeviceExtension->jChipType >= XG20) {
 337                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 338                 xgifb_reg_set(P3d4,
 339                               0x82,
 340                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 341                 xgifb_reg_set(P3d4,
 342                               0x85,
 343                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 344                 xgifb_reg_set(P3d4,
 345                               0x86,
 346                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 347
 348                 xgifb_reg_set(P3d4, 0x98, 0x01);
 349                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 350
 351                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 352         } else {
 353                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 354
 355                 switch (HwDeviceExtension->jChipType) {
 356                 case XG42:
 357                         /* CR82 */
 358                         xgifb_reg_set(P3d4,
 359                                       0x82,
 360                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 361                         /* CR85 */
 362                         xgifb_reg_set(P3d4,
 363                                       0x85,
 364                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 365                         /* CR86 */
 366                         xgifb_reg_set(P3d4,
 367                                       0x86,
 368                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 369                         break;
 370                 default:
 371                         xgifb_reg_set(P3d4, 0x82, 0x88);
 372                         xgifb_reg_set(P3d4, 0x86, 0x00);
 373                         /* Insert read command for delay */
 374                         xgifb_reg_get(P3d4, 0x86);
 375                         xgifb_reg_set(P3d4, 0x86, 0x88);
 376                         xgifb_reg_get(P3d4, 0x86);
 377                         xgifb_reg_set(P3d4,
 378                                       0x86,
 379                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 380                         xgifb_reg_set(P3d4, 0x82, 0x77);
 381                         xgifb_reg_set(P3d4, 0x85, 0x00);
 382
 383                         /* Insert read command for delay */
 384                         xgifb_reg_get(P3d4, 0x85);
 385                         xgifb_reg_set(P3d4, 0x85, 0x88);
 386
 387                         /* Insert read command for delay */
 388                         xgifb_reg_get(P3d4, 0x85);
 389                         /* CR85 */
 390                         xgifb_reg_set(P3d4,
 391                                       0x85,
 392                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 393                         /* CR82 */
 394                         xgifb_reg_set(P3d4,
 395                                       0x82,
 396                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 397                         break;
 398                 }
 399
 400                 xgifb_reg_set(P3d4, 0x97, 0x00);
 401                 xgifb_reg_set(P3d4, 0x98, 0x01);
 402                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 403                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 404         }
 405 }
 406
 407 static void XGINew_DDR2_DefaultRegister(
 408                 struct xgi_hw_device_info *HwDeviceExtension,
 409                 unsigned long Port, struct vb_device_info *pVBInfo)
 410 {
 411         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 412
 413         /* keep following setting sequence, each setting in
 414          * the same reg insert idle */
 415         xgifb_reg_set(P3d4, 0x82, 0x77);
 416         xgifb_reg_set(P3d4, 0x86, 0x00);
 417         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 418         xgifb_reg_set(P3d4, 0x86, 0x88);
 419         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 420         /* CR86 */
 421         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 422         xgifb_reg_set(P3d4, 0x82, 0x77);
 423         xgifb_reg_set(P3d4, 0x85, 0x00);
 424         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 425         xgifb_reg_set(P3d4, 0x85, 0x88);
 426         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 427         xgifb_reg_set(P3d4,
 428                       0x85,
 429                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 430         if (HwDeviceExtension->jChipType == XG27)
 431                 /* CR82 */
 432                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 433         else
 434                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 435
 436         xgifb_reg_set(P3d4, 0x98, 0x01);
 437         xgifb_reg_set(P3d4, 0x9A, 0x02);
 438         if (HwDeviceExtension->jChipType == XG27)
 439                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 440         else
 441                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 442 }
 443
 444 static void XGINew_SetDRAMDefaultRegister340(
 445                 struct xgi_hw_device_info *HwDeviceExtension,
 446                 unsigned long Port, struct vb_device_info *pVBInfo)
 447 {
 448         unsigned char temp, temp1, temp2, temp3, i, j, k;
 449
 450         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 451
 452         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 453         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 454         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 455         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 456
 457         temp2 = 0;
 458         for (i = 0; i < 4; i++) {
 459                 /* CR6B DQS fine tune delay */
 460                 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
 461                 for (j = 0; j < 4; j++) {
 462                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 463                         temp2 |= temp1;
 464                         xgifb_reg_set(P3d4, 0x6B, temp2);
 465                         /* Insert read command for delay */
 466                         xgifb_reg_get(P3d4, 0x6B);
 467                         temp2 &= 0xF0;
 468                         temp2 += 0x10;
 469                 }
 470         }
 471
 472         temp2 = 0;
 473         for (i = 0; i < 4; i++) {
 474                 /* CR6E DQM fine tune delay */
 475                 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
 476                 for (j = 0; j < 4; j++) {
 477                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 478                         temp2 |= temp1;
 479                         xgifb_reg_set(P3d4, 0x6E, temp2);
 480                         /* Insert read command for delay */
 481                         xgifb_reg_get(P3d4, 0x6E);
 482                         temp2 &= 0xF0;
 483                         temp2 += 0x10;
 484                 }
 485         }
 486
 487         temp3 = 0;
 488         for (k = 0; k < 4; k++) {
 489                 /* CR6E_D[1:0] select channel */
 490                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 491                 temp2 = 0;
 492                 for (i = 0; i < 8; i++) {
 493                         /* CR6F DQ fine tune delay */
 494                         temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
 495                         for (j = 0; j < 4; j++) {
 496                                 temp1 = (temp >> (2 * j)) & 0x03;
 497                                 temp2 |= temp1;
 498                                 xgifb_reg_set(P3d4, 0x6F, temp2);
 499                                 /* Insert read command for delay */
 500                                 xgifb_reg_get(P3d4, 0x6F);
 501                                 temp2 &= 0xF8;
 502                                 temp2 += 0x08;
 503                         }
 504                 }
 505                 temp3 += 0x01;
 506         }
 507
 508         xgifb_reg_set(P3d4,
 509                       0x80,
 510                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 511         xgifb_reg_set(P3d4,
 512                       0x81,
 513                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 514
 515         temp2 = 0x80;
 516         /* CR89 terminator type select */
 517         temp = pVBInfo->CR89[pVBInfo->ram_type][0];
 518         for (j = 0; j < 4; j++) {
 519                 temp1 = (temp >> (2 * j)) & 0x03;
 520                 temp2 |= temp1;
 521                 xgifb_reg_set(P3d4, 0x89, temp2);
 522                 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
 523                 temp2 &= 0xF0;
 524                 temp2 += 0x10;
 525         }
 526
 527         temp = pVBInfo->CR89[pVBInfo->ram_type][1];
 528         temp1 = temp & 0x03;
 529         temp2 |= temp1;
 530         xgifb_reg_set(P3d4, 0x89, temp2);
 531
 532         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 533         temp1 = temp & 0x0F;
 534         temp2 = (temp >> 4) & 0x07;
 535         temp3 = temp & 0x80;
 536         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 537         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 538         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 539         xgifb_reg_set(P3d4,
 540                       0x41,
 541                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 542
 543         if (HwDeviceExtension->jChipType == XG27)
 544                 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
 545
 546         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 547                 xgifb_reg_set(P3d4, (0x90 + j),
 548                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 549
 550         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 551                 xgifb_reg_set(P3d4, (0xC3 + j),
 552                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 553
 554         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 555                 xgifb_reg_set(P3d4, (0x8A + j),
 556                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 557
 558         if (HwDeviceExtension->jChipType == XG42)
 559                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 560
 561         xgifb_reg_set(P3d4,
 562                       0x59,
 563                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 564
 565         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 566         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 567         xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
 568         if (pVBInfo->ram_type) {
 569                 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
 570                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 571                 if (HwDeviceExtension->jChipType == XG27)
 572                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 573
 574         } else {
 575                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 576         }
 577         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 578
 579         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 580         if (temp == 0) {
 581                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 582         } else {
 583                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 584                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 585         }
 586         xgifb_reg_set(P3c4,
 587                       0x1B,
 588                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 589 }
 590
 591 static void XGINew_SetDRAMSizingType(int index,
 592                 const unsigned short DRAMTYPE_TABLE[][5],
 593                 struct vb_device_info *pVBInfo)
 594 {
 595         unsigned short data;
 596
 597         data = DRAMTYPE_TABLE[index][4];
 598         xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
 599         udelay(15);
 600         /* should delay 50 ns */
 601 }
 602
 603 static unsigned short XGINew_SetDRAMSizeReg(int index,
 604                 const unsigned short DRAMTYPE_TABLE[][5],
 605                 struct vb_device_info *pVBInfo)
 606 {
 607         unsigned short data = 0, memsize = 0;
 608         int RankSize;
 609         unsigned char ChannelNo;
 610
 611         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 32;
 612         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 613         data &= 0x80;
 614
 615         if (data == 0x80)
 616                 RankSize *= 2;
 617
 618         data = 0;
 619
 620         if (pVBInfo->ram_channel == 3)
 621                 ChannelNo = 4;
 622         else
 623                 ChannelNo = pVBInfo->ram_channel;
 624
 625         if (ChannelNo * RankSize <= 256) {
 626                 while ((RankSize >>= 1) > 0)
 627                         data += 0x10;
 628
 629                 memsize = data >> 4;
 630
 631                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 632                 xgifb_reg_set(pVBInfo->P3c4,
 633                               0x14,
 634                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 635                                (data & 0xF0));
 636
 637                 /* data |= pVBInfo->ram_channel << 2; */
 638                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 639                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 640
 641                 /* should delay */
 642                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 643         }
 644         return memsize;
 645 }
 646
 647 static unsigned short XGINew_SetDRAMSize20Reg(int index,
 648                 const unsigned short DRAMTYPE_TABLE[][5],
 649                 struct vb_device_info *pVBInfo)
 650 {
 651         unsigned short data = 0, memsize = 0;
 652         int RankSize;
 653         unsigned char ChannelNo;
 654
 655         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 8;
 656         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 657         data &= 0x80;
 658
 659         if (data == 0x80)
 660                 RankSize *= 2;
 661
 662         data = 0;
 663
 664         if (pVBInfo->ram_channel == 3)
 665                 ChannelNo = 4;
 666         else
 667                 ChannelNo = pVBInfo->ram_channel;
 668
 669         if (ChannelNo * RankSize <= 256) {
 670                 while ((RankSize >>= 1) > 0)
 671                         data += 0x10;
 672
 673                 memsize = data >> 4;
 674
 675                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 676                 xgifb_reg_set(pVBInfo->P3c4,
 677                               0x14,
 678                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 679                                 (data & 0xF0));
 680                 udelay(15);
 681
 682                 /* data |= pVBInfo->ram_channel << 2; */
 683                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 684                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 685
 686                 /* should delay */
 687                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 688         }
 689         return memsize;
 690 }
 691
 692 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 693                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 694 {
 695         int i;
 696         unsigned long Position = 0;
 697         void __iomem *fbaddr = pVBInfo->FBAddr;
 698
 699         writel(Position, fbaddr + Position);
 700
 701         for (i = StartAddr; i <= StopAddr; i++) {
 702                 Position = 1 << i;
 703                 writel(Position, fbaddr + Position);
 704         }
 705
 706         udelay(500); /* [Vicent] 2004/04/16.
 707                         Fix #1759 Memory Size error in Multi-Adapter. */
 708
 709         Position = 0;
 710
 711         if (readl(fbaddr + Position) != Position)
 712                 return 0;
 713
 714         for (i = StartAddr; i <= StopAddr; i++) {
 715                 Position = 1 << i;
 716                 if (readl(fbaddr + Position) != Position)
 717                         return 0;
 718         }
 719         return 1;
 720 }
 721
 722 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 723 {
 724         unsigned char data;
 725
 726         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 727
 728         if ((data & 0x10) == 0) {
 729                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 730                 data = (data & 0x02) >> 1;
 731                 return data;
 732         } else {
 733                 return data & 0x01;
 734         }
 735 }
 736
 737 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 738                 struct vb_device_info *pVBInfo)
 739 {
 740         unsigned char data;
 741
 742         switch (HwDeviceExtension->jChipType) {
 743         case XG20:
 744         case XG21:
 745                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 746                 data = data & 0x01;
 747                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 748
 749                 if (data == 0) { /* Single_32_16 */
 750
 751                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 752                                         > 0x1000000) {
 753
 754                                 pVBInfo->ram_bus = 32; /* 32 bits */
 755                                 /* 22bit + 2 rank + 32bit */
 756                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 757                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 758                                 udelay(15);
 759
 760                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 761                                         return;
 762
 763                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 764                                     0x800000) {
 765                                         /* 22bit + 1 rank + 32bit */
 766                                         xgifb_reg_set(pVBInfo->P3c4,
 767                                                       0x13,
 768                                                       0x31);
 769                                         xgifb_reg_set(pVBInfo->P3c4,
 770                                                       0x14,
 771                                                       0x42);
 772                                         udelay(15);
 773
 774                                         if (XGINew_ReadWriteRest(23,
 775                                                                  23,
 776                                                                  pVBInfo) == 1)
 777                                                 return;
 778                                 }
 779                         }
 780
 781                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 782                             0x800000) {
 783                                 pVBInfo->ram_bus = 16; /* 16 bits */
 784                                 /* 22bit + 2 rank + 16bit */
 785                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 786                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 787                                 udelay(15);
 788
 789                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 790                                         return;
 791                                 else
 792                                         xgifb_reg_set(pVBInfo->P3c4,
 793                                                       0x13,
 794                                                       0x31);
 795                                 udelay(15);
 796                         }
 797
 798                 } else { /* Dual_16_8 */
 799                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 800                             0x800000) {
 801                                 pVBInfo->ram_bus = 16; /* 16 bits */
 802                                 /* (0x31:12x8x2) 22bit + 2 rank */
 803                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 804                                 /* 0x41:16Mx16 bit*/
 805                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 806                                 udelay(15);
 807
 808                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 809                                         return;
 810
 811                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 812                                     0x400000) {
 813                                         /* (0x31:12x8x2) 22bit + 1 rank */
 814                                         xgifb_reg_set(pVBInfo->P3c4,
 815                                                       0x13,
 816                                                       0x31);
 817                                         /* 0x31:8Mx16 bit*/
 818                                         xgifb_reg_set(pVBInfo->P3c4,
 819                                                       0x14,
 820                                                       0x31);
 821                                         udelay(15);
 822
 823                                         if (XGINew_ReadWriteRest(22,
 824                                                                  22,
 825                                                                  pVBInfo) == 1)
 826                                                 return;
 827                                 }
 828                         }
 829
 830                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 831                             0x400000) {
 832                                 pVBInfo->ram_bus = 8; /* 8 bits */
 833                                 /* (0x31:12x8x2) 22bit + 2 rank */
 834                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 835                                 /* 0x30:8Mx8 bit*/
 836                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 837                                 udelay(15);
 838
 839                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 840                                         return;
 841                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 842                                         xgifb_reg_set(pVBInfo->P3c4,
 843                                                       0x13,
 844                                                       0x31);
 845                                 udelay(15);
 846                         }
 847                 }
 848                 break;
 849
 850         case XG27:
 851                 pVBInfo->ram_bus = 16; /* 16 bits */
 852                 pVBInfo->ram_channel = 1; /* Single channel */
 853                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 854                 break;
 855         case XG42:
 856                 /*
 857                  XG42 SR14 D[3] Reserve
 858                  D[2] = 1, Dual Channel
 859                  = 0, Single Channel
 860
 861                  It's Different from Other XG40 Series.
 862                  */
 863                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 864                         pVBInfo->ram_bus = 32; /* 32 bits */
 865                         pVBInfo->ram_channel = 2; /* 2 Channel */
 866                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 867                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 868
 869                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 870                                 return;
 871
 872                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 873                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 874                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 875                                 return;
 876
 877                         pVBInfo->ram_channel = 1; /* Single Channel */
 878                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 879                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 880
 881                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 882                                 return;
 883                         else {
 884                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 885                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 886                         }
 887                 } else { /* DDR */
 888                         pVBInfo->ram_bus = 64; /* 64 bits */
 889                         pVBInfo->ram_channel = 1; /* 1 channels */
 890                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 891                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 892
 893                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 894                                 return;
 895                         else {
 896                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 897                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 898                         }
 899                 }
 900
 901                 break;
 902
 903         default: /* XG40 */
 904
 905                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 906                         pVBInfo->ram_bus = 32; /* 32 bits */
 907                         pVBInfo->ram_channel = 3;
 908                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 909                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 910
 911                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 912                                 return;
 913
 914                         pVBInfo->ram_channel = 2; /* 2 channels */
 915                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 916
 917                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 918                                 return;
 919
 920                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 921                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 922
 923                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 924                                 pVBInfo->ram_channel = 3; /* 4 channels */
 925                         } else {
 926                                 pVBInfo->ram_channel = 2; /* 2 channels */
 927                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 928                         }
 929                 } else { /* DDR */
 930                         pVBInfo->ram_bus = 64; /* 64 bits */
 931                         pVBInfo->ram_channel = 2; /* 2 channels */
 932                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 933                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 934
 935                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 936                                 return;
 937                         } else {
 938                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 939                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 940                         }
 941                 }
 942                 break;
 943         }
 944 }
 945
 946 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 947                 struct vb_device_info *pVBInfo)
 948 {
 949         int i;
 950         unsigned short memsize, addr;
 951
 952         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 953         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 954         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 955
 956         if (HwDeviceExtension->jChipType >= XG20) {
 957                 for (i = 0; i < 12; i++) {
 958                         XGINew_SetDRAMSizingType(i,
 959                                                  XGINew_DDRDRAM_TYPE20,
 960                                                  pVBInfo);
 961                         memsize = XGINew_SetDRAMSize20Reg(i,
 962                                                           XGINew_DDRDRAM_TYPE20,
 963                                                           pVBInfo);
 964                         if (memsize == 0)
 965                                 continue;
 966
 967                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
 968                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 969                             (unsigned long) (1 << addr))
 970                                 continue;
 971
 972                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
 973                                 return 1;
 974                 }
 975         } else {
 976                 for (i = 0; i < 4; i++) {
 977                         XGINew_SetDRAMSizingType(i,
 978                                                  XGINew_DDRDRAM_TYPE340,
 979                                                  pVBInfo);
 980                         memsize = XGINew_SetDRAMSizeReg(i,
 981                                                         XGINew_DDRDRAM_TYPE340,
 982                                                         pVBInfo);
 983
 984                         if (memsize == 0)
 985                                 continue;
 986
 987                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
 988                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 989                             (unsigned long) (1 << addr))
 990                                 continue;
 991
 992                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
 993                                 return 1;
 994                 }
 995         }
 996         return 0;
 997 }
 998
 999 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
1000                 struct xgi_hw_device_info *HwDeviceExtension,
1001                 struct vb_device_info *pVBInfo)
1002 {
1003         unsigned short data;
1004
1005         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1006
1007         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
1008
1009         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1010         /* disable read cache */
1011         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1012         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
1013
1014         /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1015         /* data |= 0x20 ; */
1016         /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1017         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1018         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1019         /* enable read cache */
1020         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1021 }
1022
1023 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
1024 {
1025         void __iomem *rom_address;
1026         u8 *rom_copy;
1027
1028         rom_address = pci_map_rom(dev, rom_size);
1029         if (rom_address == NULL)
1030                 return NULL;
1031
1032         rom_copy = vzalloc(XGIFB_ROM_SIZE);
1033         if (rom_copy == NULL)
1034                 goto done;
1035
1036         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
1037         memcpy_fromio(rom_copy, rom_address, *rom_size);
1038
1039 done:
1040         pci_unmap_rom(dev, rom_address);
1041         return rom_copy;
1042 }
1043
1044 static void xgifb_read_vbios(struct pci_dev *pdev,
1045                               struct vb_device_info *pVBInfo)
1046 {
1047         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1048         u8 *vbios;
1049         unsigned long i;
1050         unsigned char j;
1051         struct XGI21_LVDSCapStruct *lvds;
1052         size_t vbios_size;
1053         int entry;
1054
1055         if (xgifb_info->chip != XG21)
1056                 return;
1057         pVBInfo->IF_DEF_LVDS = 0;
1058         vbios = xgifb_copy_rom(pdev, &vbios_size);
1059         if (vbios == NULL) {
1060                 dev_err(&pdev->dev, "video BIOS not available\n");
1061                 return;
1062         }
1063         if (vbios_size <= 0x65)
1064                 goto error;
1065         /*
1066          * The user can ignore the LVDS bit in the BIOS and force the display
1067          * type.
1068          */
1069         if (!(vbios[0x65] & 0x1) &&
1070             (!xgifb_info->display2_force ||
1071              xgifb_info->display2 != XGIFB_DISP_LCD)) {
1072                 vfree(vbios);
1073                 return;
1074         }
1075         if (vbios_size <= 0x317)
1076                 goto error;
1077         i = vbios[0x316] | (vbios[0x317] << 8);
1078         if (vbios_size <= i - 1)
1079                 goto error;
1080         j = vbios[i - 1];
1081         if (j == 0)
1082                 goto error;
1083         if (j == 0xff)
1084                 j = 1;
1085         /*
1086          * Read the LVDS table index scratch register set by the BIOS.
1087          */
1088         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
1089         if (entry >= j)
1090                 entry = 0;
1091         i += entry * 25;
1092         lvds = &xgifb_info->lvds_data;
1093         if (vbios_size <= i + 24)
1094                 goto error;
1095         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
1096         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
1097         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
1098         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
1099         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
1100         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
1101         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
1102         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
1103         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
1104         lvds->VCLKData1         = vbios[i + 18];
1105         lvds->VCLKData2         = vbios[i + 19];
1106         lvds->PSC_S1            = vbios[i + 20];
1107         lvds->PSC_S2            = vbios[i + 21];
1108         lvds->PSC_S3            = vbios[i + 22];
1109         lvds->PSC_S4            = vbios[i + 23];
1110         lvds->PSC_S5            = vbios[i + 24];
1111         vfree(vbios);
1112         pVBInfo->IF_DEF_LVDS = 1;
1113         return;
1114 error:
1115         dev_err(&pdev->dev, "video BIOS corrupted\n");
1116         vfree(vbios);
1117 }
1118
1119 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1120                 struct vb_device_info *pVBInfo)
1121 {
1122         unsigned short tempbx = 0, temp, tempcx, CR3CData;
1123
1124         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1125
1126         if (temp & Monitor1Sense)
1127                 tempbx |= ActiveCRT1;
1128         if (temp & LCDSense)
1129                 tempbx |= ActiveLCD;
1130         if (temp & Monitor2Sense)
1131                 tempbx |= ActiveCRT2;
1132         if (temp & TVSense) {
1133                 tempbx |= ActiveTV;
1134                 if (temp & AVIDEOSense)
1135                         tempbx |= (ActiveAVideo << 8);
1136                 if (temp & SVIDEOSense)
1137                         tempbx |= (ActiveSVideo << 8);
1138                 if (temp & SCARTSense)
1139                         tempbx |= (ActiveSCART << 8);
1140                 if (temp & HiTVSense)
1141                         tempbx |= (ActiveHiTV << 8);
1142                 if (temp & YPbPrSense)
1143                         tempbx |= (ActiveYPbPr << 8);
1144         }
1145
1146         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1147         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1148
1149         if (tempbx & tempcx) {
1150                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1151                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1152                         tempcx = 0x1FF0;
1153                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1154                                 tempbx = 0x1FF0;
1155                 }
1156         } else {
1157                 tempcx = 0x1FF0;
1158                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1159                         tempbx = 0x1FF0;
1160         }
1161
1162         tempbx &= tempcx;
1163         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1164         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1165 }
1166
1167 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1168                 struct vb_device_info *pVBInfo)
1169 {
1170         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1171
1172         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1173         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1174         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1175
1176         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1177                 if (temp & ActiveCRT2)
1178                         tempcl = SetCRT2ToRAMDAC;
1179         }
1180
1181         if (temp & ActiveLCD) {
1182                 tempcl |= SetCRT2ToLCD;
1183                 if (temp & DriverMode) {
1184                         if (temp & ActiveTV) {
1185                                 tempch = SetToLCDA | EnableDualEdge;
1186                                 temp ^= SetCRT2ToLCD;
1187
1188                                 if ((temp >> 8) & ActiveAVideo)
1189                                         tempcl |= SetCRT2ToAVIDEO;
1190                                 if ((temp >> 8) & ActiveSVideo)
1191                                         tempcl |= SetCRT2ToSVIDEO;
1192                                 if ((temp >> 8) & ActiveSCART)
1193                                         tempcl |= SetCRT2ToSCART;
1194
1195                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1196                                         if ((temp >> 8) & ActiveHiTV)
1197                                                 tempcl |= SetCRT2ToHiVision;
1198                                 }
1199
1200                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1201                                         if ((temp >> 8) & ActiveYPbPr)
1202                                                 tempch |= SetYPbPr;
1203                                 }
1204                         }
1205                 }
1206         } else {
1207                 if ((temp >> 8) & ActiveAVideo)
1208                         tempcl |= SetCRT2ToAVIDEO;
1209                 if ((temp >> 8) & ActiveSVideo)
1210                         tempcl |= SetCRT2ToSVIDEO;
1211                 if ((temp >> 8) & ActiveSCART)
1212                         tempcl |= SetCRT2ToSCART;
1213
1214                 if (pVBInfo->IF_DEF_HiVision == 1) {
1215                         if ((temp >> 8) & ActiveHiTV)
1216                                 tempcl |= SetCRT2ToHiVision;
1217                 }
1218
1219                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1220                         if ((temp >> 8) & ActiveYPbPr)
1221                                 tempch |= SetYPbPr;
1222                 }
1223         }
1224
1225         tempcl |= SetSimuScanMode;
1226         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1227                         || (temp & ActiveCRT2)))
1228                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1229         if ((temp & ActiveLCD) && (temp & ActiveTV))
1230                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1231         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1232
1233         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1234         CR31Data &= ~(SetNotSimuMode >> 8);
1235         if (!(temp & ActiveCRT1))
1236                 CR31Data |= (SetNotSimuMode >> 8);
1237         CR31Data &= ~(DisableCRT2Display >> 8);
1238         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1239                 CR31Data |= (DisableCRT2Display >> 8);
1240         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1241
1242         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1243         CR38Data &= ~SetYPbPr;
1244         CR38Data |= tempch;
1245         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1246
1247 }
1248
1249 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1250                                                         *HwDeviceExtension,
1251                                       struct vb_device_info *pVBInfo)
1252 {
1253         unsigned short temp;
1254
1255         /* add lcd sense */
1256         if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1257                 return 0;
1258         } else {
1259                 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1260                 switch (HwDeviceExtension->ulCRT2LCDType) {
1261                 case LCD_INVALID:
1262                 case LCD_800x600:
1263                 case LCD_1024x768:
1264                 case LCD_1280x1024:
1265                         break;
1266
1267                 case LCD_640x480:
1268                 case LCD_1024x600:
1269                 case LCD_1152x864:
1270                 case LCD_1280x960:
1271                 case LCD_1152x768:
1272                         temp = 0;
1273                         break;
1274
1275                 case LCD_1400x1050:
1276                 case LCD_1280x768:
1277                 case LCD_1600x1200:
1278                         break;
1279
1280                 case LCD_1920x1440:
1281                 case LCD_2048x1536:
1282                         temp = 0;
1283                         break;
1284
1285                 default:
1286                         break;
1287                 }
1288                 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1289                 return 1;
1290         }
1291 }
1292
1293 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1294                 struct vb_device_info *pVBInfo)
1295 {
1296         unsigned char Temp;
1297
1298 #if 1
1299         if (pVBInfo->IF_DEF_LVDS) { /* For XG21 LVDS */
1300                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1301                 /* LVDS on chip */
1302                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1303         } else {
1304 #endif
1305                 /* Enable GPIOA/B read  */
1306                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1307                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1308                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1309                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1310                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1311                         /* Enable read GPIOF */
1312                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1313                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1314                         if (!Temp)
1315                                 xgifb_reg_and_or(pVBInfo->P3d4,
1316                                                  0x38,
1317                                                  ~0xE0,
1318                                                  0x80); /* TMDS on chip */
1319                         else
1320                                 xgifb_reg_and_or(pVBInfo->P3d4,
1321                                                  0x38,
1322                                                  ~0xE0,
1323                                                  0xA0); /* Only DVO on chip */
1324                         /* Disable read GPIOF */
1325                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1326                 }
1327 #if 1
1328         }
1329 #endif
1330 }
1331
1332 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1333                 struct vb_device_info *pVBInfo)
1334 {
1335         unsigned char Temp, bCR4A;
1336
1337         pVBInfo->IF_DEF_LVDS = 0;
1338         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1339         /* Enable GPIOA/B/C read  */
1340         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1341         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1342         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1343
1344         if (Temp <= 0x02) {
1345                 /* LVDS setting */
1346                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1347                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1348         } else {
1349                 /* TMDS/DVO setting */
1350                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1351         }
1352         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1353
1354 }
1355
1356 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1357 {
1358         unsigned char CR38, CR4A, temp;
1359
1360         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1361         /* enable GPIOE read */
1362         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1363         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1364         temp = 0;
1365         if ((CR38 & 0xE0) > 0x80) {
1366                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1367                 temp &= 0x08;
1368                 temp >>= 3;
1369         }
1370
1371         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1372
1373         return temp;
1374 }
1375
1376 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1377 {
1378         unsigned char CR4A, temp;
1379
1380         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1381         /* enable GPIOA/B/C read */
1382         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1383         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1384         if (temp <= 2)
1385                 temp &= 0x03;
1386         else
1387                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1388
1389         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1390
1391         return temp;
1392 }
1393
1394 unsigned char XGIInitNew(struct pci_dev *pdev)
1395 {
1396         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1397         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1398         struct vb_device_info VBINF;
1399         struct vb_device_info *pVBInfo = &VBINF;
1400         unsigned char i, temp = 0, temp1;
1401         /* VBIOSVersion[5]; */
1402
1403         /* unsigned long j, k; */
1404
1405         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1406
1407         pVBInfo->BaseAddr = xgifb_info->vga_base;
1408
1409         /* Newdebugcode(0x99); */
1410
1411         if (pVBInfo->FBAddr == NULL) {
1412                 printk("\n pVBInfo->FBAddr == 0 ");
1413                 return 0;
1414         }
1415         printk("1");
1416         if (pVBInfo->BaseAddr == 0) {
1417                 printk("\npVBInfo->BaseAddr == 0 ");
1418                 return 0;
1419         }
1420         printk("2");
1421
1422         outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1423
1424         pVBInfo->ISXPDOS = 0;
1425         printk("3");
1426
1427         printk("4");
1428
1429         /* VBIOSVersion[4] = 0x0; */
1430
1431         /* 09/07/99 modify by domao */
1432
1433         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1434         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1435         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1436         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1437         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1438         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1439         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1440         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1441         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1442         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1443         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1444         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1445         pVBInfo->Part1Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_04;
1446         pVBInfo->Part2Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_10;
1447         pVBInfo->Part3Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_12;
1448         pVBInfo->Part4Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_14;
1449         pVBInfo->Part5Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_14 + 2;
1450         printk("5");
1451
1452         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1453                 /* Run XGI_GetVBType before InitTo330Pointer */
1454                 XGI_GetVBType(pVBInfo);
1455
1456         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1457
1458         xgifb_read_vbios(pdev, pVBInfo);
1459
1460         /* 1.Openkey */
1461         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1462         printk("6");
1463
1464         /* GetXG21Sense (GPIO) */
1465         if (HwDeviceExtension->jChipType == XG21)
1466                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1467
1468         if (HwDeviceExtension->jChipType == XG27)
1469                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1470
1471         printk("7");
1472
1473         /* 2.Reset Extended register */
1474
1475         for (i = 0x06; i < 0x20; i++)
1476                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1477
1478         for (i = 0x21; i <= 0x27; i++)
1479                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1480
1481         /* for(i = 0x06; i <= 0x27; i++) */
1482         /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1483
1484         printk("8");
1485
1486         for (i = 0x31; i <= 0x3B; i++)
1487                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1488         printk("9");
1489
1490         /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1491         if (HwDeviceExtension->jChipType == XG42)
1492                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1493
1494         /* for (i = 0x30; i <= 0x3F; i++) */
1495         /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1496
1497         for (i = 0x79; i <= 0x7C; i++)
1498                 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1499
1500         printk("10");
1501
1502         if (HwDeviceExtension->jChipType >= XG20)
1503                 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1504
1505         /* 3.SetMemoryClock
1506
1507         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1508         */
1509
1510         printk("11");
1511
1512         /* 4.SetDefExt1Regs begin */
1513         xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1514         if (HwDeviceExtension->jChipType == XG27) {
1515                 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1516                 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1517         }
1518         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1519         xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1520         /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1521         /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1522         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1523         /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1524         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1525         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1526                 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1527
1528         /* SR11 = 0x0F; */
1529         /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1530
1531         printk("12");
1532
1533         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1534                 u32 Temp;
1535
1536                 /* Set AGP Rate */
1537                 /*
1538                 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1539                 temp1 &= 0x02;
1540                 if (temp1 == 0x02) {
1541                         outl(0x80000000, 0xcf8);
1542                         ChipsetID = inl(0x0cfc);
1543                         outl(0x8000002C, 0xcf8);
1544                         VendorID = inl(0x0cfc);
1545                         VendorID &= 0x0000FFFF;
1546                         outl(0x8001002C, 0xcf8);
1547                         GraphicVendorID = inl(0x0cfc);
1548                         GraphicVendorID &= 0x0000FFFF;
1549
1550                         if (ChipsetID == 0x7301039)
1551                                 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1552
1553                         ChipsetID &= 0x0000FFFF;
1554
1555                         if ((ChipsetID == 0x700E) ||
1556                             (ChipsetID == 0x1022) ||
1557                             (ChipsetID == 0x1106) ||
1558                             (ChipsetID == 0x10DE)) {
1559                                 if (ChipsetID == 0x1106) {
1560                                         if ((VendorID == 0x1019) &&
1561                                             (GraphicVendorID == 0x1019))
1562                                                 xgifb_reg_set(pVBInfo->P3d4,
1563                                                               0x5F,
1564                                                               0x0D);
1565                                         else
1566                                                 xgifb_reg_set(pVBInfo->P3d4,
1567                                                               0x5F,
1568                                                               0x0B);
1569                                 } else {
1570                                         xgifb_reg_set(pVBInfo->P3d4,
1571                                                       0x5F,
1572                                                       0x0B);
1573                                 }
1574                         }
1575                 }
1576                 */
1577
1578                 printk("13");
1579
1580                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1581                 for (i = 0x47; i <= 0x4C; i++)
1582                         xgifb_reg_set(pVBInfo->P3d4,
1583                                       i,
1584                                       pVBInfo->AGPReg[i - 0x47]);
1585
1586                 for (i = 0x70; i <= 0x71; i++)
1587                         xgifb_reg_set(pVBInfo->P3d4,
1588                                       i,
1589                                       pVBInfo->AGPReg[6 + i - 0x70]);
1590
1591                 for (i = 0x74; i <= 0x77; i++)
1592                         xgifb_reg_set(pVBInfo->P3d4,
1593                                       i,
1594                                       pVBInfo->AGPReg[8 + i - 0x74]);
1595                 /* Set AGP customize registers (in SetDefAGPRegs) End */
1596                 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1597                 /*        outl(0x80000000, 0xcf8); */
1598                 /*        ChipsetID = inl(0x0cfc); */
1599                 /*        if (ChipsetID == 0x25308086) */
1600                 /*            xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1601
1602                 pci_read_config_dword(pdev, 0x50, &Temp);
1603                 Temp >>= 20;
1604                 Temp &= 0xF;
1605
1606                 if (Temp == 1)
1607                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1608                 printk("14");
1609         } /* != XG20 */
1610
1611         /* Set PCI */
1612         xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1613         xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1614         xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1615         printk("15");
1616
1617         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1618                 /* Set VB */
1619                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1620                 /* alan, disable VideoCapture */
1621                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1622                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1623                 /* chk if BCLK>=100MHz */
1624                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1625                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1626
1627                 xgifb_reg_set(pVBInfo->Part1Port,
1628                               0x02,
1629                               (*pVBInfo->pCRT2Data_1_2));
1630
1631                 printk("16");
1632
1633                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1634         } /* != XG20 */
1635
1636         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1637
1638         if ((HwDeviceExtension->jChipType == XG42) &&
1639             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1640                 /* Not DDR */
1641                 xgifb_reg_set(pVBInfo->P3c4,
1642                               0x31,
1643                               (*pVBInfo->pSR31 & 0x3F) | 0x40);
1644                 xgifb_reg_set(pVBInfo->P3c4,
1645                               0x32,
1646                               (*pVBInfo->pSR32 & 0xFC) | 0x01);
1647         } else {
1648                 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1649                 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1650         }
1651         xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1652         printk("17");
1653
1654         /*
1655          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
1656
1657         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1658                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1659                         if (pVBInfo->IF_DEF_LVDS == 0) {
1660                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1661                                 xgifb_reg_set(pVBInfo->Part4Port,
1662                                               0x0D,
1663                                               *pVBInfo->pCRT2Data_4_D);
1664                                 xgifb_reg_set(pVBInfo->Part4Port,
1665                                               0x0E,
1666                                               *pVBInfo->pCRT2Data_4_E);
1667                                 xgifb_reg_set(pVBInfo->Part4Port,
1668                                               0x10,
1669                                               *pVBInfo->pCRT2Data_4_10);
1670                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1671                         }
1672
1673                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1674                 }
1675         } /* != XG20 */
1676         printk("18");
1677
1678         printk("181");
1679
1680         printk("182");
1681
1682         XGI_SenseCRT1(pVBInfo);
1683
1684         printk("183");
1685         /* XGINew_DetectMonitor(HwDeviceExtension); */
1686         if (HwDeviceExtension->jChipType == XG21) {
1687                 printk("186");
1688
1689                 xgifb_reg_and_or(pVBInfo->P3d4,
1690                                  0x32,
1691                                  ~Monitor1Sense,
1692                                  Monitor1Sense); /* Z9 default has CRT */
1693                 temp = GetXG21FPBits(pVBInfo);
1694                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1695                 printk("187");
1696
1697         }
1698         if (HwDeviceExtension->jChipType == XG27) {
1699                 xgifb_reg_and_or(pVBInfo->P3d4,
1700                                  0x32,
1701                                  ~Monitor1Sense,
1702                                  Monitor1Sense); /* Z9 default has CRT */
1703                 temp = GetXG27FPBits(pVBInfo);
1704                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1705         }
1706         printk("19");
1707
1708         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1709
1710         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1711                                          pVBInfo->P3d4,
1712                                          pVBInfo);
1713
1714         printk("20");
1715         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1716         printk("21");
1717
1718         printk("22");
1719
1720         /* SetDefExt2Regs begin */
1721         /*
1722         AGP = 1;
1723         temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1724         temp &= 0x30;
1725         if (temp == 0x30)
1726                 AGP = 0;
1727
1728         if (AGP == 0)
1729                 *pVBInfo->pSR21 &= 0xEF;
1730
1731         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1732         if (AGP == 1)
1733                 *pVBInfo->pSR22 &= 0x20;
1734         xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1735         */
1736         /* base = 0x80000000; */
1737         /* OutPortLong(0xcf8, base); */
1738         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1739         /* if (Temp == 0x1039) { */
1740         xgifb_reg_set(pVBInfo->P3c4,
1741                       0x22,
1742                       (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1743         /* } else { */
1744         /*      xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1745         /* } */
1746
1747         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1748
1749         printk("23");
1750
1751         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1752         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1753
1754         printk("24");
1755
1756         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1757         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1758         printk("25");
1759
1760         return 1;
1761 } /* end of init */