2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
4 * Sascha Hauer <s.hauer@pengutronix.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/nvmem-consumer.h>
23 #include <linux/of_address.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include <linux/thermal.h>
28 #include <linux/reset.h>
29 #include <linux/types.h>
31 /* AUXADC Registers */
32 #define AUXADC_CON0_V 0x000
33 #define AUXADC_CON1_V 0x004
34 #define AUXADC_CON1_SET_V 0x008
35 #define AUXADC_CON1_CLR_V 0x00c
36 #define AUXADC_CON2_V 0x010
37 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
38 #define AUXADC_MISC_V 0x094
40 #define AUXADC_CON1_CHANNEL(x) BIT(x)
42 #define APMIXED_SYS_TS_CON1 0x604
44 /* Thermal Controller Registers */
45 #define TEMP_MONCTL0 0x000
46 #define TEMP_MONCTL1 0x004
47 #define TEMP_MONCTL2 0x008
48 #define TEMP_MONIDET0 0x014
49 #define TEMP_MONIDET1 0x018
50 #define TEMP_MSRCTL0 0x038
51 #define TEMP_AHBPOLL 0x040
52 #define TEMP_AHBTO 0x044
53 #define TEMP_ADCPNP0 0x048
54 #define TEMP_ADCPNP1 0x04c
55 #define TEMP_ADCPNP2 0x050
56 #define TEMP_ADCPNP3 0x0b4
58 #define TEMP_ADCMUX 0x054
59 #define TEMP_ADCEN 0x060
60 #define TEMP_PNPMUXADDR 0x064
61 #define TEMP_ADCMUXADDR 0x068
62 #define TEMP_ADCENADDR 0x074
63 #define TEMP_ADCVALIDADDR 0x078
64 #define TEMP_ADCVOLTADDR 0x07c
65 #define TEMP_RDCTRL 0x080
66 #define TEMP_ADCVALIDMASK 0x084
67 #define TEMP_ADCVOLTAGESHIFT 0x088
68 #define TEMP_ADCWRITECTRL 0x08c
69 #define TEMP_MSR0 0x090
70 #define TEMP_MSR1 0x094
71 #define TEMP_MSR2 0x098
72 #define TEMP_MSR3 0x0B8
74 #define TEMP_SPARE0 0x0f0
76 #define PTPCORESEL 0x400
78 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
80 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
81 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
83 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
85 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
86 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
88 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
89 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
95 #define MT8173_TSABB 4
97 /* AUXADC channel 11 is used for the temperature sensors */
98 #define MT8173_TEMP_AUXADC_CHANNEL 11
100 /* The total number of temperature sensors in the MT8173 */
101 #define MT8173_NUM_SENSORS 5
103 /* The number of banks in the MT8173 */
104 #define MT8173_NUM_ZONES 4
106 /* The number of sensing points per bank */
107 #define MT8173_NUM_SENSORS_PER_ZONE 4
109 /* Layout of the fuses providing the calibration data */
110 #define MT8173_CALIB_BUF0_VALID BIT(0)
111 #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
112 #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
113 #define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
114 #define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
115 #define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
116 #define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
117 #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
118 #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
120 #define THERMAL_NAME "mtk-thermal"
124 struct mtk_thermal_bank {
125 struct mtk_thermal *mt;
131 void __iomem *thermal_base;
133 struct clk *clk_peri_therm;
134 struct clk *clk_auxadc;
136 struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
138 /* lock: for getting and putting banks */
141 /* Calibration values */
145 s32 vts[MT8173_NUM_SENSORS];
149 struct mtk_thermal_bank_cfg {
150 unsigned int num_sensors;
151 unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
154 static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
157 * The MT8173 thermal controller has four banks. Each bank can read up to
158 * four temperature sensors simultaneously. The MT8173 has a total of 5
159 * temperature sensors. We use each bank to measure a certain area of the
160 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
161 * areas, hence is used in different banks.
163 * The thermal core only gets the maximum temperature of all banks, so
164 * the bank concept wouldn't be necessary here. However, the SVS (Smart
165 * Voltage Scaling) unit makes its decisions based on the same bank
166 * data, and this indeed needs the temperatures of the individual banks
167 * for making better decisions.
169 static const struct mtk_thermal_bank_cfg bank_data[] = {
172 .sensors = { MT8173_TS2, MT8173_TS3 },
175 .sensors = { MT8173_TS2, MT8173_TS4 },
178 .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
181 .sensors = { MT8173_TS2 },
185 struct mtk_thermal_sense_point {
190 static const struct mtk_thermal_sense_point
191 sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
194 .adcpnp = TEMP_ADCPNP0,
197 .adcpnp = TEMP_ADCPNP1,
200 .adcpnp = TEMP_ADCPNP2,
203 .adcpnp = TEMP_ADCPNP3,
208 * raw_to_mcelsius - convert a raw ADC value to mcelsius
209 * @mt: The thermal controller
210 * @raw: raw ADC value
212 * This converts the raw ADC value to mcelsius using the SoC specific
213 * calibration constants
215 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
221 tmp = 203450520 << 3;
222 tmp /= 165 + mt->o_slope;
223 tmp /= 10000 + mt->adc_ge;
224 tmp *= raw - mt->vts[sensno] - 3350;
227 return mt->degc_cali * 500 - tmp;
231 * mtk_thermal_get_bank - get bank
234 * The bank registers are banked, we have to select a bank in the
235 * PTPCORESEL register to access it.
237 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
239 struct mtk_thermal *mt = bank->mt;
242 mutex_lock(&mt->lock);
244 val = readl(mt->thermal_base + PTPCORESEL);
247 writel(val, mt->thermal_base + PTPCORESEL);
251 * mtk_thermal_put_bank - release bank
254 * release a bank previously taken with mtk_thermal_get_bank,
256 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
258 struct mtk_thermal *mt = bank->mt;
260 mutex_unlock(&mt->lock);
264 * mtk_thermal_bank_temperature - get the temperature of a bank
267 * The temperature of a bank is considered the maximum temperature of
268 * the sensors associated to the bank.
270 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
272 struct mtk_thermal *mt = bank->mt;
273 int i, temp = INT_MIN, max = INT_MIN;
276 for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
277 raw = readl(mt->thermal_base + sensing_points[i].msr);
279 temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);
282 * The first read of a sensor often contains very high bogus
283 * temperature value. Filter these out so that the system does
284 * not immediately shut down.
296 static int mtk_read_temp(void *data, int *temperature)
298 struct mtk_thermal *mt = data;
300 int tempmax = INT_MIN;
302 for (i = 0; i < MT8173_NUM_ZONES; i++) {
303 struct mtk_thermal_bank *bank = &mt->banks[i];
305 mtk_thermal_get_bank(bank);
307 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
309 mtk_thermal_put_bank(bank);
312 *temperature = tempmax;
317 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
318 .get_temp = mtk_read_temp,
321 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
322 u32 apmixed_phys_base, u32 auxadc_phys_base)
324 struct mtk_thermal_bank *bank = &mt->banks[num];
325 const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
331 mtk_thermal_get_bank(bank);
333 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
334 writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
337 * filt interval is 1 * 46.540us = 46.54us,
338 * sen interval is 429 * 46.540us = 19.96ms
340 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
341 TEMP_MONCTL2_SENSOR_INTERVAL(429),
342 mt->thermal_base + TEMP_MONCTL2);
344 /* poll is set to 10u */
345 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
346 mt->thermal_base + TEMP_AHBPOLL);
348 /* temperature sampling control, 1 sample */
349 writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
351 /* exceed this polling time, IRQ would be inserted */
352 writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
354 /* number of interrupts per event, 1 is enough */
355 writel(0x0, mt->thermal_base + TEMP_MONIDET0);
356 writel(0x0, mt->thermal_base + TEMP_MONIDET1);
359 * The MT8173 thermal controller does not have its own ADC. Instead it
360 * uses AHB bus accesses to control the AUXADC. To do this the thermal
361 * controller has to be programmed with the physical addresses of the
362 * AUXADC registers and with the various bit positions in the AUXADC.
363 * Also the thermal controller controls a mux in the APMIXEDSYS register
368 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
369 * automatically by hw
371 writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);
373 /* AHB address for auxadc mux selection */
374 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
375 mt->thermal_base + TEMP_ADCMUXADDR);
377 /* AHB address for pnp sensor mux selection */
378 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
379 mt->thermal_base + TEMP_PNPMUXADDR);
381 /* AHB value for auxadc enable */
382 writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
384 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
385 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
386 mt->thermal_base + TEMP_ADCENADDR);
388 /* AHB address for auxadc valid bit */
389 writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
390 mt->thermal_base + TEMP_ADCVALIDADDR);
392 /* AHB address for auxadc voltage output */
393 writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
394 mt->thermal_base + TEMP_ADCVOLTADDR);
396 /* read valid & voltage are at the same register */
397 writel(0x0, mt->thermal_base + TEMP_RDCTRL);
399 /* indicate where the valid bit is */
400 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
401 mt->thermal_base + TEMP_ADCVALIDMASK);
404 writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
406 /* enable auxadc mux write transaction */
407 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
408 mt->thermal_base + TEMP_ADCWRITECTRL);
410 for (i = 0; i < cfg->num_sensors; i++)
411 writel(sensor_mux_values[cfg->sensors[i]],
412 mt->thermal_base + sensing_points[i].adcpnp);
414 writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
416 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
417 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
418 mt->thermal_base + TEMP_ADCWRITECTRL);
420 mtk_thermal_put_bank(bank);
423 static u64 of_get_phys_base(struct device_node *np)
426 const __be32 *regaddr_p;
428 regaddr_p = of_get_address(np, 0, &size64, NULL);
432 return of_translate_address(np, regaddr_p);
435 static int mtk_thermal_get_calibration_data(struct device *dev,
436 struct mtk_thermal *mt)
438 struct nvmem_cell *cell;
443 /* Start with default values */
445 for (i = 0; i < MT8173_NUM_SENSORS; i++)
450 cell = nvmem_cell_get(dev, "calibration-data");
452 if (PTR_ERR(cell) == -EPROBE_DEFER)
453 return PTR_ERR(cell);
457 buf = (u32 *)nvmem_cell_read(cell, &len);
459 nvmem_cell_put(cell);
464 if (len < 3 * sizeof(u32)) {
465 dev_warn(dev, "invalid calibration data\n");
470 if (buf[0] & MT8173_CALIB_BUF0_VALID) {
471 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
472 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
473 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
474 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
475 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
476 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
477 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
478 mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
480 dev_info(dev, "Device not calibrated, using default calibration values\n");
489 static int mtk_thermal_probe(struct platform_device *pdev)
492 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
493 struct mtk_thermal *mt;
494 struct resource *res;
495 u64 auxadc_phys_base, apmixed_phys_base;
497 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
501 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
502 if (IS_ERR(mt->clk_peri_therm))
503 return PTR_ERR(mt->clk_peri_therm);
505 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
506 if (IS_ERR(mt->clk_auxadc))
507 return PTR_ERR(mt->clk_auxadc);
509 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
510 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
511 if (IS_ERR(mt->thermal_base))
512 return PTR_ERR(mt->thermal_base);
514 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
518 mutex_init(&mt->lock);
520 mt->dev = &pdev->dev;
522 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
524 dev_err(&pdev->dev, "missing auxadc node\n");
528 auxadc_phys_base = of_get_phys_base(auxadc);
532 if (auxadc_phys_base == OF_BAD_ADDR) {
533 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
537 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
539 dev_err(&pdev->dev, "missing apmixedsys node\n");
543 apmixed_phys_base = of_get_phys_base(apmixedsys);
545 of_node_put(apmixedsys);
547 if (apmixed_phys_base == OF_BAD_ADDR) {
548 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
552 ret = clk_prepare_enable(mt->clk_auxadc);
554 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
558 ret = device_reset(&pdev->dev);
560 goto err_disable_clk_auxadc;
562 ret = clk_prepare_enable(mt->clk_peri_therm);
564 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
565 goto err_disable_clk_auxadc;
568 for (i = 0; i < MT8173_NUM_ZONES; i++)
569 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
572 platform_set_drvdata(pdev, mt);
574 devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
579 err_disable_clk_auxadc:
580 clk_disable_unprepare(mt->clk_auxadc);
585 static int mtk_thermal_remove(struct platform_device *pdev)
587 struct mtk_thermal *mt = platform_get_drvdata(pdev);
589 clk_disable_unprepare(mt->clk_peri_therm);
590 clk_disable_unprepare(mt->clk_auxadc);
595 static const struct of_device_id mtk_thermal_of_match[] = {
597 .compatible = "mediatek,mt8173-thermal",
602 static struct platform_driver mtk_thermal_driver = {
603 .probe = mtk_thermal_probe,
604 .remove = mtk_thermal_remove,
606 .name = THERMAL_NAME,
607 .of_match_table = mtk_thermal_of_match,
611 module_platform_driver(mtk_thermal_driver);
613 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
614 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
615 MODULE_DESCRIPTION("Mediatek thermal driver");
616 MODULE_LICENSE("GPL v2");