2 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Caesar Wang <wxt@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/thermal.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/pinctrl/consumer.h>
31 * If the temperature over a period of time High,
32 * the resulting TSHUT gave CRU module,let it reset the entire chip,
33 * or via GPIO give PMIC.
41 * The system Temperature Sensors tshut(tshut) polarity
42 * the bit 8 is tshut polarity.
43 * 0: low active, 1: high active
51 * The system has two Temperature Sensors.
52 * sensor0 is for CPU, and sensor1 is for GPU.
60 * The conversion table has the adc value and temperature.
61 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
62 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
70 * The max sensors is two in rockchip SoCs.
71 * Two sensors: CPU and GPU sensor.
73 #define SOC_MAX_SENSORS 2
76 * struct chip_tsadc_table - hold information about chip-specific differences
77 * @id: conversion table
78 * @length: size of conversion table
79 * @data_mask: mask to apply on data inputs
80 * @mode: sort mode of this adc variant (incrementing or decrementing)
82 struct chip_tsadc_table {
83 const struct tsadc_table *id;
86 enum adc_sort_mode mode;
90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
91 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
92 * @chn_num: the channel number of tsadc chip
93 * @tshut_temp: the hardware-controlled shutdown temperature value
94 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
95 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
96 * @initialize: SoC special initialize tsadc controller method
97 * @irq_ack: clear the interrupt
98 * @get_temp: get the temperature
99 * @set_alarm_temp: set the high temperature interrupt
100 * @set_tshut_temp: set the hardware-controlled shutdown temperature
101 * @set_tshut_mode: set the hardware-controlled shutdown mode
102 * @table: the chip-specific conversion table
104 struct rockchip_tsadc_chip {
105 /* The sensor id of chip correspond to the ADC channel */
106 int chn_id[SOC_MAX_SENSORS];
109 /* The hardware-controlled tshut property */
111 enum tshut_mode tshut_mode;
112 enum tshut_polarity tshut_polarity;
114 /* Chip-wide methods */
115 void (*initialize)(struct regmap *grf,
116 void __iomem *reg, enum tshut_polarity p);
117 void (*irq_ack)(void __iomem *reg);
118 void (*control)(void __iomem *reg, bool on);
120 /* Per-sensor methods */
121 int (*get_temp)(struct chip_tsadc_table table,
122 int chn, void __iomem *reg, int *temp);
123 void (*set_alarm_temp)(struct chip_tsadc_table table,
124 int chn, void __iomem *reg, int temp);
125 void (*set_tshut_temp)(struct chip_tsadc_table table,
126 int chn, void __iomem *reg, int temp);
127 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
129 /* Per-table methods */
130 struct chip_tsadc_table table;
134 * struct rockchip_thermal_sensor - hold the information of thermal sensor
135 * @thermal: pointer to the platform/configuration data
136 * @tzd: pointer to a thermal zone
137 * @id: identifier of the thermal sensor
139 struct rockchip_thermal_sensor {
140 struct rockchip_thermal_data *thermal;
141 struct thermal_zone_device *tzd;
146 * struct rockchip_thermal_data - hold the private data of thermal driver
147 * @chip: pointer to the platform/configuration data
148 * @pdev: platform device of thermal
149 * @reset: the reset controller of tsadc
150 * @sensors[SOC_MAX_SENSORS]: the thermal sensor
151 * @clk: the controller clock is divided by the exteral 24MHz
152 * @pclk: the advanced peripherals bus clock
153 * @grf: the general register file will be used to do static set by software
154 * @regs: the base address of tsadc controller
155 * @tshut_temp: the hardware-controlled shutdown temperature value
156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
159 struct rockchip_thermal_data {
160 const struct rockchip_tsadc_chip *chip;
161 struct platform_device *pdev;
162 struct reset_control *reset;
164 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
173 enum tshut_mode tshut_mode;
174 enum tshut_polarity tshut_polarity;
178 * TSADC Sensor Register description:
180 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
181 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
184 #define TSADCV2_USER_CON 0x00
185 #define TSADCV2_AUTO_CON 0x04
186 #define TSADCV2_INT_EN 0x08
187 #define TSADCV2_INT_PD 0x0c
188 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
189 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
190 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
191 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
192 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
193 #define TSADCV2_AUTO_PERIOD 0x68
194 #define TSADCV2_AUTO_PERIOD_HT 0x6c
196 #define TSADCV2_AUTO_EN BIT(0)
197 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
198 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
200 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
202 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
203 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
204 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
206 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
207 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
209 #define TSADCV2_DATA_MASK 0xfff
210 #define TSADCV3_DATA_MASK 0x3ff
212 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
213 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
214 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
215 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
216 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
217 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
219 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
221 #define GRF_SARADC_TESTBIT 0x0e644
222 #define GRF_TSADC_TESTBIT_L 0x0e648
223 #define GRF_TSADC_TESTBIT_H 0x0e64c
225 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
226 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
227 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
228 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
231 * struct tsadc_table - code to temperature conversion table
232 * @code: the value of adc channel
233 * @temp: the temperature
235 * code to temperature mapping of the temperature sensor is a piece wise linear
236 * curve.Any temperature, code faling between to 2 give temperatures can be
237 * linearly interpolated.
238 * Code to Temperature mapping should be updated based on manufacturer results.
245 static const struct tsadc_table rk3228_code_table[] = {
281 {TSADCV2_DATA_MASK, 125000},
284 static const struct tsadc_table rk3288_code_table[] = {
285 {TSADCV2_DATA_MASK, -40000},
322 static const struct tsadc_table rk3368_code_table[] = {
358 {TSADCV3_DATA_MASK, 125000},
361 static const struct tsadc_table rk3399_code_table[] = {
397 {TSADCV3_DATA_MASK, 125000},
400 static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table,
407 high = table.length - 1;
408 mid = (high + low) / 2;
410 /* Return mask code data when the temp is over table range */
411 if (temp < table.id[low].temp || temp > table.id[high].temp) {
412 error = table.data_mask;
416 while (low <= high) {
417 if (temp == table.id[mid].temp)
418 return table.id[mid].code;
419 else if (temp < table.id[mid].temp)
423 mid = (low + high) / 2;
427 pr_err("Invalid the conversion, error=%d\n", error);
431 static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code,
434 unsigned int low = 1;
435 unsigned int high = table.length - 1;
436 unsigned int mid = (low + high) / 2;
440 WARN_ON(table.length < 2);
442 switch (table.mode) {
444 code &= table.data_mask;
445 if (code < table.id[high].code)
446 return -EAGAIN; /* Incorrect reading */
448 while (low <= high) {
449 if (code >= table.id[mid].code &&
450 code < table.id[mid - 1].code)
452 else if (code < table.id[mid].code)
457 mid = (low + high) / 2;
461 code &= table.data_mask;
462 if (code < table.id[low].code)
463 return -EAGAIN; /* Incorrect reading */
465 while (low <= high) {
466 if (code <= table.id[mid].code &&
467 code > table.id[mid - 1].code)
469 else if (code > table.id[mid].code)
474 mid = (low + high) / 2;
478 pr_err("Invalid the conversion table\n");
482 * The 5C granularity provided by the table is too much. Let's
483 * assume that the relationship between sensor readings and
484 * temperature between 2 table entries is linear and interpolate
485 * to produce less granular result.
487 num = table.id[mid].temp - table.id[mid - 1].temp;
488 num *= abs(table.id[mid - 1].code - code);
489 denom = abs(table.id[mid - 1].code - table.id[mid].code);
490 *temp = table.id[mid - 1].temp + (num / denom);
496 * rk_tsadcv2_initialize - initialize TASDC Controller.
498 * (1) Set TSADC_V2_AUTO_PERIOD:
499 * Configure the interleave between every two accessing of
500 * TSADC in normal operation.
502 * (2) Set TSADCV2_AUTO_PERIOD_HT:
503 * Configure the interleave between every two accessing of
504 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
506 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
507 * If the temperature is higher than COMP_INT or COMP_SHUT for
508 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
510 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
511 enum tshut_polarity tshut_polarity)
513 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
514 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
515 regs + TSADCV2_AUTO_CON);
517 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
518 regs + TSADCV2_AUTO_CON);
520 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
521 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
522 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
523 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
524 regs + TSADCV2_AUTO_PERIOD_HT);
525 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
526 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
530 * rk_tsadcv3_initialize - initialize TASDC Controller.
532 * (1) The tsadc control power sequence.
534 * (2) Set TSADC_V2_AUTO_PERIOD:
535 * Configure the interleave between every two accessing of
536 * TSADC in normal operation.
538 * (2) Set TSADCV2_AUTO_PERIOD_HT:
539 * Configure the interleave between every two accessing of
540 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
542 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
543 * If the temperature is higher than COMP_INT or COMP_SHUT for
544 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
546 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
547 enum tshut_polarity tshut_polarity)
549 /* The tsadc control power sequence */
551 /* Set interleave value to workround ic time sync issue */
552 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
555 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
556 regs + TSADCV2_AUTO_PERIOD);
557 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
558 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
559 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
560 regs + TSADCV2_AUTO_PERIOD_HT);
561 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
562 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
565 /* Enable the voltage common mode feature */
566 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
567 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
569 usleep_range(15, 100); /* The spec note says at least 15 us */
570 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
571 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
572 usleep_range(90, 200); /* The spec note says at least 90 us */
574 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
575 regs + TSADCV2_AUTO_PERIOD);
576 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
577 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
578 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
579 regs + TSADCV2_AUTO_PERIOD_HT);
580 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
581 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
584 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
585 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
586 regs + TSADCV2_AUTO_CON);
588 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
589 regs + TSADCV2_AUTO_CON);
592 static void rk_tsadcv2_irq_ack(void __iomem *regs)
596 val = readl_relaxed(regs + TSADCV2_INT_PD);
597 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
600 static void rk_tsadcv3_irq_ack(void __iomem *regs)
604 val = readl_relaxed(regs + TSADCV2_INT_PD);
605 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
608 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
612 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
614 val |= TSADCV2_AUTO_EN;
616 val &= ~TSADCV2_AUTO_EN;
618 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
622 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
624 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
625 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
626 * adc value if setting this bit to enable.
628 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
632 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
634 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
636 val &= ~TSADCV2_AUTO_EN;
638 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
641 static int rk_tsadcv2_get_temp(struct chip_tsadc_table table,
642 int chn, void __iomem *regs, int *temp)
646 val = readl_relaxed(regs + TSADCV2_DATA(chn));
648 return rk_tsadcv2_code_to_temp(table, val, temp);
651 static void rk_tsadcv2_alarm_temp(struct chip_tsadc_table table,
652 int chn, void __iomem *regs, int temp)
654 u32 alarm_value, int_en;
656 /* Make sure the value is valid */
657 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
658 if (alarm_value == table.data_mask)
661 writel_relaxed(alarm_value & table.data_mask,
662 regs + TSADCV2_COMP_INT(chn));
664 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
665 int_en |= TSADCV2_INT_SRC_EN(chn);
666 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
669 static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table,
670 int chn, void __iomem *regs, int temp)
672 u32 tshut_value, val;
674 /* Make sure the value is valid */
675 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
676 if (tshut_value == table.data_mask)
679 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
681 /* TSHUT will be valid */
682 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
683 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
686 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
687 enum tshut_mode mode)
691 val = readl_relaxed(regs + TSADCV2_INT_EN);
692 if (mode == TSHUT_MODE_GPIO) {
693 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
694 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
696 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
697 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
700 writel_relaxed(val, regs + TSADCV2_INT_EN);
703 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
704 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
705 .chn_num = 1, /* one channel for tsadc */
707 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
708 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
711 .initialize = rk_tsadcv2_initialize,
712 .irq_ack = rk_tsadcv3_irq_ack,
713 .control = rk_tsadcv3_control,
714 .get_temp = rk_tsadcv2_get_temp,
715 .set_alarm_temp = rk_tsadcv2_alarm_temp,
716 .set_tshut_temp = rk_tsadcv2_tshut_temp,
717 .set_tshut_mode = rk_tsadcv2_tshut_mode,
720 .id = rk3228_code_table,
721 .length = ARRAY_SIZE(rk3228_code_table),
722 .data_mask = TSADCV3_DATA_MASK,
723 .mode = ADC_INCREMENT,
727 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
728 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
729 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
730 .chn_num = 2, /* two channels for tsadc */
732 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
733 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
736 .initialize = rk_tsadcv2_initialize,
737 .irq_ack = rk_tsadcv2_irq_ack,
738 .control = rk_tsadcv2_control,
739 .get_temp = rk_tsadcv2_get_temp,
740 .set_alarm_temp = rk_tsadcv2_alarm_temp,
741 .set_tshut_temp = rk_tsadcv2_tshut_temp,
742 .set_tshut_mode = rk_tsadcv2_tshut_mode,
745 .id = rk3288_code_table,
746 .length = ARRAY_SIZE(rk3288_code_table),
747 .data_mask = TSADCV2_DATA_MASK,
748 .mode = ADC_DECREMENT,
752 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
753 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
754 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
755 .chn_num = 2, /* two channels for tsadc */
757 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
758 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
761 .initialize = rk_tsadcv3_initialize,
762 .irq_ack = rk_tsadcv3_irq_ack,
763 .control = rk_tsadcv3_control,
764 .get_temp = rk_tsadcv2_get_temp,
765 .set_alarm_temp = rk_tsadcv2_alarm_temp,
766 .set_tshut_temp = rk_tsadcv2_tshut_temp,
767 .set_tshut_mode = rk_tsadcv2_tshut_mode,
770 .id = rk3228_code_table,
771 .length = ARRAY_SIZE(rk3228_code_table),
772 .data_mask = TSADCV3_DATA_MASK,
773 .mode = ADC_INCREMENT,
777 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
778 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
779 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
780 .chn_num = 2, /* two channels for tsadc */
782 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
783 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
786 .initialize = rk_tsadcv2_initialize,
787 .irq_ack = rk_tsadcv2_irq_ack,
788 .control = rk_tsadcv2_control,
789 .get_temp = rk_tsadcv2_get_temp,
790 .set_alarm_temp = rk_tsadcv2_alarm_temp,
791 .set_tshut_temp = rk_tsadcv2_tshut_temp,
792 .set_tshut_mode = rk_tsadcv2_tshut_mode,
795 .id = rk3368_code_table,
796 .length = ARRAY_SIZE(rk3368_code_table),
797 .data_mask = TSADCV3_DATA_MASK,
798 .mode = ADC_INCREMENT,
802 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
803 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
804 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
805 .chn_num = 2, /* two channels for tsadc */
807 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
808 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
811 .initialize = rk_tsadcv3_initialize,
812 .irq_ack = rk_tsadcv3_irq_ack,
813 .control = rk_tsadcv3_control,
814 .get_temp = rk_tsadcv2_get_temp,
815 .set_alarm_temp = rk_tsadcv2_alarm_temp,
816 .set_tshut_temp = rk_tsadcv2_tshut_temp,
817 .set_tshut_mode = rk_tsadcv2_tshut_mode,
820 .id = rk3399_code_table,
821 .length = ARRAY_SIZE(rk3399_code_table),
822 .data_mask = TSADCV3_DATA_MASK,
823 .mode = ADC_INCREMENT,
827 static const struct of_device_id of_rockchip_thermal_match[] = {
829 .compatible = "rockchip,rk3228-tsadc",
830 .data = (void *)&rk3228_tsadc_data,
833 .compatible = "rockchip,rk3288-tsadc",
834 .data = (void *)&rk3288_tsadc_data,
837 .compatible = "rockchip,rk3366-tsadc",
838 .data = (void *)&rk3366_tsadc_data,
841 .compatible = "rockchip,rk3368-tsadc",
842 .data = (void *)&rk3368_tsadc_data,
845 .compatible = "rockchip,rk3399-tsadc",
846 .data = (void *)&rk3399_tsadc_data,
850 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
853 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
855 struct thermal_zone_device *tzd = sensor->tzd;
857 tzd->ops->set_mode(tzd,
858 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
861 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
863 struct rockchip_thermal_data *thermal = dev;
866 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
868 thermal->chip->irq_ack(thermal->regs);
870 for (i = 0; i < thermal->chip->chn_num; i++)
871 thermal_zone_device_update(thermal->sensors[i].tzd,
872 THERMAL_EVENT_UNSPECIFIED);
877 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
879 struct rockchip_thermal_sensor *sensor = _sensor;
880 struct rockchip_thermal_data *thermal = sensor->thermal;
881 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
883 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
884 __func__, sensor->id, low, high);
886 tsadc->set_alarm_temp(tsadc->table,
887 sensor->id, thermal->regs, high);
892 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
894 struct rockchip_thermal_sensor *sensor = _sensor;
895 struct rockchip_thermal_data *thermal = sensor->thermal;
896 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
899 retval = tsadc->get_temp(tsadc->table,
900 sensor->id, thermal->regs, out_temp);
901 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
902 sensor->id, *out_temp, retval);
907 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
908 .get_temp = rockchip_thermal_get_temp,
909 .set_trips = rockchip_thermal_set_trips,
912 static int rockchip_configure_from_dt(struct device *dev,
913 struct device_node *np,
914 struct rockchip_thermal_data *thermal)
916 u32 shut_temp, tshut_mode, tshut_polarity;
918 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
920 "Missing tshut temp property, using default %d\n",
921 thermal->chip->tshut_temp);
922 thermal->tshut_temp = thermal->chip->tshut_temp;
924 if (shut_temp > INT_MAX) {
925 dev_err(dev, "Invalid tshut temperature specified: %d\n",
929 thermal->tshut_temp = shut_temp;
932 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
934 "Missing tshut mode property, using default (%s)\n",
935 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
937 thermal->tshut_mode = thermal->chip->tshut_mode;
939 thermal->tshut_mode = tshut_mode;
942 if (thermal->tshut_mode > 1) {
943 dev_err(dev, "Invalid tshut mode specified: %d\n",
944 thermal->tshut_mode);
948 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
951 "Missing tshut-polarity property, using default (%s)\n",
952 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
954 thermal->tshut_polarity = thermal->chip->tshut_polarity;
956 thermal->tshut_polarity = tshut_polarity;
959 if (thermal->tshut_polarity > 1) {
960 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
961 thermal->tshut_polarity);
965 /* The tsadc wont to handle the error in here since some SoCs didn't
966 * need this property.
968 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
969 if (IS_ERR(thermal->grf))
970 dev_warn(dev, "Missing rockchip,grf property\n");
976 rockchip_thermal_register_sensor(struct platform_device *pdev,
977 struct rockchip_thermal_data *thermal,
978 struct rockchip_thermal_sensor *sensor,
981 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
984 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
985 tsadc->set_tshut_temp(tsadc->table, id, thermal->regs,
986 thermal->tshut_temp);
988 sensor->thermal = thermal;
990 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
991 sensor, &rockchip_of_thermal_ops);
992 if (IS_ERR(sensor->tzd)) {
993 error = PTR_ERR(sensor->tzd);
994 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1003 * Reset TSADC Controller, reset all tsadc registers.
1005 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1007 reset_control_assert(reset);
1008 usleep_range(10, 20);
1009 reset_control_deassert(reset);
1012 static int rockchip_thermal_probe(struct platform_device *pdev)
1014 struct device_node *np = pdev->dev.of_node;
1015 struct rockchip_thermal_data *thermal;
1016 const struct of_device_id *match;
1017 struct resource *res;
1022 match = of_match_node(of_rockchip_thermal_match, np);
1026 irq = platform_get_irq(pdev, 0);
1028 dev_err(&pdev->dev, "no irq resource?\n");
1032 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1037 thermal->pdev = pdev;
1039 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1044 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1045 if (IS_ERR(thermal->regs))
1046 return PTR_ERR(thermal->regs);
1048 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1049 if (IS_ERR(thermal->reset)) {
1050 error = PTR_ERR(thermal->reset);
1051 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1055 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1056 if (IS_ERR(thermal->clk)) {
1057 error = PTR_ERR(thermal->clk);
1058 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1062 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1063 if (IS_ERR(thermal->pclk)) {
1064 error = PTR_ERR(thermal->pclk);
1065 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1070 error = clk_prepare_enable(thermal->clk);
1072 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1077 error = clk_prepare_enable(thermal->pclk);
1079 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1080 goto err_disable_clk;
1083 rockchip_thermal_reset_controller(thermal->reset);
1085 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1087 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1089 goto err_disable_pclk;
1092 thermal->chip->initialize(thermal->grf, thermal->regs,
1093 thermal->tshut_polarity);
1095 for (i = 0; i < thermal->chip->chn_num; i++) {
1096 error = rockchip_thermal_register_sensor(pdev, thermal,
1097 &thermal->sensors[i],
1098 thermal->chip->chn_id[i]);
1101 "failed to register sensor[%d] : error = %d\n",
1103 goto err_disable_pclk;
1107 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1108 &rockchip_thermal_alarm_irq_thread,
1110 "rockchip_thermal", thermal);
1113 "failed to request tsadc irq: %d\n", error);
1114 goto err_disable_pclk;
1117 thermal->chip->control(thermal->regs, true);
1119 for (i = 0; i < thermal->chip->chn_num; i++)
1120 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1122 platform_set_drvdata(pdev, thermal);
1127 clk_disable_unprepare(thermal->pclk);
1129 clk_disable_unprepare(thermal->clk);
1134 static int rockchip_thermal_remove(struct platform_device *pdev)
1136 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1139 for (i = 0; i < thermal->chip->chn_num; i++) {
1140 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1142 rockchip_thermal_toggle_sensor(sensor, false);
1145 thermal->chip->control(thermal->regs, false);
1147 clk_disable_unprepare(thermal->pclk);
1148 clk_disable_unprepare(thermal->clk);
1153 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1155 struct platform_device *pdev = to_platform_device(dev);
1156 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1159 for (i = 0; i < thermal->chip->chn_num; i++)
1160 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1162 thermal->chip->control(thermal->regs, false);
1164 clk_disable(thermal->pclk);
1165 clk_disable(thermal->clk);
1167 pinctrl_pm_select_sleep_state(dev);
1172 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1174 struct platform_device *pdev = to_platform_device(dev);
1175 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1179 error = clk_enable(thermal->clk);
1183 error = clk_enable(thermal->pclk);
1185 clk_disable(thermal->clk);
1189 rockchip_thermal_reset_controller(thermal->reset);
1191 thermal->chip->initialize(thermal->grf, thermal->regs,
1192 thermal->tshut_polarity);
1194 for (i = 0; i < thermal->chip->chn_num; i++) {
1195 int id = thermal->sensors[i].id;
1197 thermal->chip->set_tshut_mode(id, thermal->regs,
1198 thermal->tshut_mode);
1199 thermal->chip->set_tshut_temp(thermal->chip->table,
1201 thermal->tshut_temp);
1204 thermal->chip->control(thermal->regs, true);
1206 for (i = 0; i < thermal->chip->chn_num; i++)
1207 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1209 pinctrl_pm_select_default_state(dev);
1214 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1215 rockchip_thermal_suspend, rockchip_thermal_resume);
1217 static struct platform_driver rockchip_thermal_driver = {
1219 .name = "rockchip-thermal",
1220 .pm = &rockchip_thermal_pm_ops,
1221 .of_match_table = of_rockchip_thermal_match,
1223 .probe = rockchip_thermal_probe,
1224 .remove = rockchip_thermal_remove,
1227 module_platform_driver(rockchip_thermal_driver);
1229 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1230 MODULE_AUTHOR("Rockchip, Inc.");
1231 MODULE_LICENSE("GPL v2");
1232 MODULE_ALIAS("platform:rockchip-thermal");