2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
8 * Copyright (C) 2011 Samsung Electronics
9 * Donggeun Kim <dg77.kim@samsung.com>
10 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/clk.h>
30 #include <linux/interrupt.h>
31 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/regulator/consumer.h>
38 #include "exynos_tmu.h"
39 #include "../thermal_core.h"
41 /* Exynos generic registers */
42 #define EXYNOS_TMU_REG_TRIMINFO 0x0
43 #define EXYNOS_TMU_REG_CONTROL 0x20
44 #define EXYNOS_TMU_REG_STATUS 0x28
45 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
46 #define EXYNOS_TMU_REG_INTEN 0x70
47 #define EXYNOS_TMU_REG_INTSTAT 0x74
48 #define EXYNOS_TMU_REG_INTCLEAR 0x78
50 #define EXYNOS_TMU_TEMP_MASK 0xff
51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
52 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
55 #define EXYNOS_TMU_CORE_EN_SHIFT 0
57 /* Exynos3250 specific registers */
58 #define EXYNOS_TMU_TRIMINFO_CON1 0x10
60 /* Exynos4210 specific registers */
61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
65 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
66 #define EXYNOS_THD_TEMP_RISE 0x50
67 #define EXYNOS_THD_TEMP_FALL 0x54
68 #define EXYNOS_EMUL_CON 0x80
70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
71 #define EXYNOS_TRIMINFO_25_SHIFT 0
72 #define EXYNOS_TRIMINFO_85_SHIFT 8
73 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
74 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
83 #define EXYNOS_EMUL_TIME 0x57F0
84 #define EXYNOS_EMUL_TIME_MASK 0xffff
85 #define EXYNOS_EMUL_TIME_SHIFT 16
86 #define EXYNOS_EMUL_DATA_SHIFT 8
87 #define EXYNOS_EMUL_DATA_MASK 0xFF
88 #define EXYNOS_EMUL_ENABLE 0x1
90 /* Exynos5260 specific */
91 #define EXYNOS5260_TMU_REG_INTEN 0xC0
92 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
93 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
94 #define EXYNOS5260_EMUL_CON 0x100
96 /* Exynos4412 specific */
97 #define EXYNOS4412_MUX_ADDR_VALUE 6
98 #define EXYNOS4412_MUX_ADDR_SHIFT 20
100 /*exynos5440 specific registers*/
101 #define EXYNOS5440_TMU_S0_7_TRIM 0x000
102 #define EXYNOS5440_TMU_S0_7_CTRL 0x020
103 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040
104 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
105 #define EXYNOS5440_TMU_S0_7_TH0 0x110
106 #define EXYNOS5440_TMU_S0_7_TH1 0x130
107 #define EXYNOS5440_TMU_S0_7_TH2 0x150
108 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210
109 #define EXYNOS5440_TMU_S0_7_IRQ 0x230
110 /* exynos5440 common registers */
111 #define EXYNOS5440_TMU_IRQ_STATUS 0x000
112 #define EXYNOS5440_TMU_PMIN 0x004
114 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
115 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
116 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
117 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
118 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
119 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
120 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8
122 #define MCELSIUS 1000
124 * struct exynos_tmu_data : A structure to hold the private data of the TMU
126 * @id: identifier of the one instance of the TMU controller.
127 * @pdata: pointer to the tmu platform/configuration data
128 * @base: base address of the single instance of the TMU controller.
129 * @base_second: base address of the common registers of the TMU controller.
130 * @irq: irq number of the TMU controller.
131 * @soc: id of the SOC type.
132 * @irq_work: pointer to the irq work structure.
133 * @lock: lock to implement synchronization.
134 * @clk: pointer to the clock structure.
135 * @clk_sec: pointer to the clock structure for accessing the base_second.
136 * @temp_error1: fused value of the first point trim.
137 * @temp_error2: fused value of the second point trim.
138 * @regulator: pointer to the TMU regulator structure.
139 * @reg_conf: pointer to structure to register with core thermal.
140 * @tmu_initialize: SoC specific TMU initialization method
141 * @tmu_control: SoC specific TMU control method
142 * @tmu_read: SoC specific TMU temperature read method
143 * @tmu_set_emulation: SoC specific TMU emulation setting method
144 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
146 struct exynos_tmu_data {
148 struct exynos_tmu_platform_data *pdata;
150 void __iomem *base_second;
153 struct work_struct irq_work;
155 struct clk *clk, *clk_sec;
156 u8 temp_error1, temp_error2;
157 struct regulator *regulator;
158 struct thermal_zone_device *tzd;
160 int (*tmu_initialize)(struct platform_device *pdev);
161 void (*tmu_control)(struct platform_device *pdev, bool on);
162 int (*tmu_read)(struct exynos_tmu_data *data);
163 void (*tmu_set_emulation)(struct exynos_tmu_data *data,
165 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
168 static void exynos_report_trigger(struct exynos_tmu_data *p)
170 char data[10], *envp[] = { data, NULL };
171 struct thermal_zone_device *tz = p->tzd;
176 pr_err("No thermal zone device defined\n");
180 thermal_zone_device_update(tz);
182 mutex_lock(&tz->lock);
183 /* Find the level for which trip happened */
184 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
185 tz->ops->get_trip_temp(tz, i, &temp);
186 if (tz->last_temperature < temp)
190 snprintf(data, sizeof(data), "%u", i);
191 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
192 mutex_unlock(&tz->lock);
196 * TMU treats temperature as a mapped temperature code.
197 * The temperature is converted differently depending on the calibration type.
199 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
201 struct exynos_tmu_platform_data *pdata = data->pdata;
204 switch (pdata->cal_type) {
205 case TYPE_TWO_POINT_TRIMMING:
206 temp_code = (temp - pdata->first_point_trim) *
207 (data->temp_error2 - data->temp_error1) /
208 (pdata->second_point_trim - pdata->first_point_trim) +
211 case TYPE_ONE_POINT_TRIMMING:
212 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
215 temp_code = temp + pdata->default_temp_offset;
223 * Calculate a temperature value from a temperature code.
224 * The unit of the temperature is degree Celsius.
226 static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
228 struct exynos_tmu_platform_data *pdata = data->pdata;
231 switch (pdata->cal_type) {
232 case TYPE_TWO_POINT_TRIMMING:
233 temp = (temp_code - data->temp_error1) *
234 (pdata->second_point_trim - pdata->first_point_trim) /
235 (data->temp_error2 - data->temp_error1) +
236 pdata->first_point_trim;
238 case TYPE_ONE_POINT_TRIMMING:
239 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
242 temp = temp_code - pdata->default_temp_offset;
249 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
251 struct exynos_tmu_platform_data *pdata = data->pdata;
253 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
254 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
255 EXYNOS_TMU_TEMP_MASK);
257 if (!data->temp_error1 ||
258 (pdata->min_efuse_value > data->temp_error1) ||
259 (data->temp_error1 > pdata->max_efuse_value))
260 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
262 if (!data->temp_error2)
264 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
265 EXYNOS_TMU_TEMP_MASK;
268 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
270 struct thermal_zone_device *tz = data->tzd;
271 const struct thermal_trip * const trips =
272 of_thermal_get_trip_points(tz);
277 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
282 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
283 if (trips[i].type == THERMAL_TRIP_CRITICAL)
286 temp = trips[i].temperature / MCELSIUS;
288 temp -= (trips[i].hysteresis / MCELSIUS);
290 threshold &= ~(0xff << 8 * i);
292 threshold |= temp_to_code(data, temp) << 8 * i;
298 static int exynos_tmu_initialize(struct platform_device *pdev)
300 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
303 mutex_lock(&data->lock);
304 clk_enable(data->clk);
305 if (!IS_ERR(data->clk_sec))
306 clk_enable(data->clk_sec);
307 ret = data->tmu_initialize(pdev);
308 clk_disable(data->clk);
309 mutex_unlock(&data->lock);
310 if (!IS_ERR(data->clk_sec))
311 clk_disable(data->clk_sec);
316 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
318 struct exynos_tmu_platform_data *pdata = data->pdata;
320 if (data->soc == SOC_ARCH_EXYNOS4412 ||
321 data->soc == SOC_ARCH_EXYNOS3250)
322 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
324 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
325 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
327 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
328 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
330 if (pdata->noise_cancel_mode) {
331 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
332 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
338 static void exynos_tmu_control(struct platform_device *pdev, bool on)
340 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
342 mutex_lock(&data->lock);
343 clk_enable(data->clk);
344 data->tmu_control(pdev, on);
345 clk_disable(data->clk);
346 mutex_unlock(&data->lock);
349 static int exynos4210_tmu_initialize(struct platform_device *pdev)
351 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
352 struct thermal_zone_device *tz = data->tzd;
353 const struct thermal_trip * const trips =
354 of_thermal_get_trip_points(tz);
355 int ret = 0, threshold_code, i;
356 unsigned long reference, temp;
360 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
366 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
372 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
374 /* Write temperature code for threshold */
375 reference = trips[0].temperature / MCELSIUS;
376 threshold_code = temp_to_code(data, reference);
377 if (threshold_code < 0) {
378 ret = threshold_code;
381 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
383 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
384 temp = trips[i].temperature / MCELSIUS;
385 writeb(temp - reference, data->base +
386 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
389 data->tmu_clear_irqs(data);
394 static int exynos4412_tmu_initialize(struct platform_device *pdev)
396 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
397 const struct thermal_trip * const trips =
398 of_thermal_get_trip_points(data->tzd);
399 unsigned int status, trim_info, con, ctrl, rising_threshold;
400 int ret = 0, threshold_code, i;
401 unsigned long crit_temp = 0;
403 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
409 if (data->soc == SOC_ARCH_EXYNOS3250 ||
410 data->soc == SOC_ARCH_EXYNOS4412 ||
411 data->soc == SOC_ARCH_EXYNOS5250) {
412 if (data->soc == SOC_ARCH_EXYNOS3250) {
413 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
414 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
415 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
417 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
418 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
419 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
422 /* On exynos5420 the triminfo register is in the shared space */
423 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
424 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
426 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
428 sanitize_temp_error(data, trim_info);
430 /* Write temperature code for rising and falling threshold */
431 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
432 rising_threshold = get_th_reg(data, rising_threshold, false);
433 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
434 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
436 data->tmu_clear_irqs(data);
438 /* if last threshold limit is also present */
439 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
440 if (trips[i].type == THERMAL_TRIP_CRITICAL) {
441 crit_temp = trips[i].temperature;
446 if (i == of_thermal_get_ntrips(data->tzd)) {
447 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
453 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
454 /* 1-4 level to be assigned in th0 reg */
455 rising_threshold &= ~(0xff << 8 * i);
456 rising_threshold |= threshold_code << 8 * i;
457 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
458 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
459 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
460 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
466 static int exynos5440_tmu_initialize(struct platform_device *pdev)
468 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
469 unsigned int trim_info = 0, con, rising_threshold;
470 int ret = 0, threshold_code;
471 unsigned long crit_temp = 0;
474 * For exynos5440 soc triminfo value is swapped between TMU0 and
475 * TMU2, so the below logic is needed.
479 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
480 EXYNOS5440_TMU_S0_7_TRIM);
483 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
486 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
487 EXYNOS5440_TMU_S0_7_TRIM);
489 sanitize_temp_error(data, trim_info);
491 /* Write temperature code for rising and falling threshold */
492 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
493 rising_threshold = get_th_reg(data, rising_threshold, false);
494 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
495 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
497 data->tmu_clear_irqs(data);
499 /* if last threshold limit is also present */
500 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
501 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
502 /* 5th level to be assigned in th2 reg */
504 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
505 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
506 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
507 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
508 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
510 /* Clear the PMIN in the common TMU register */
512 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
516 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
518 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
519 struct thermal_zone_device *tz = data->tzd;
520 unsigned int con, interrupt_en;
522 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
525 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
527 (of_thermal_is_trip_valid(tz, 3)
528 << EXYNOS_TMU_INTEN_RISE3_SHIFT) |
529 (of_thermal_is_trip_valid(tz, 2)
530 << EXYNOS_TMU_INTEN_RISE2_SHIFT) |
531 (of_thermal_is_trip_valid(tz, 1)
532 << EXYNOS_TMU_INTEN_RISE1_SHIFT) |
533 (of_thermal_is_trip_valid(tz, 0)
534 << EXYNOS_TMU_INTEN_RISE0_SHIFT);
536 if (data->soc != SOC_ARCH_EXYNOS4210)
538 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
540 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
541 interrupt_en = 0; /* Disable all interrupts */
543 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
544 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
547 static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
549 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
550 struct thermal_zone_device *tz = data->tzd;
551 unsigned int con, interrupt_en;
553 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
556 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
558 (of_thermal_is_trip_valid(tz, 3)
559 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
560 (of_thermal_is_trip_valid(tz, 2)
561 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
562 (of_thermal_is_trip_valid(tz, 1)
563 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
564 (of_thermal_is_trip_valid(tz, 0)
565 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
567 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
569 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
570 interrupt_en = 0; /* Disable all interrupts */
572 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
573 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
576 static int exynos_get_temp(void *p, long *temp)
578 struct exynos_tmu_data *data = p;
583 mutex_lock(&data->lock);
584 clk_enable(data->clk);
586 *temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS;
588 clk_disable(data->clk);
589 mutex_unlock(&data->lock);
594 #ifdef CONFIG_THERMAL_EMULATION
595 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
601 if (data->soc != SOC_ARCH_EXYNOS5440) {
602 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
603 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
605 val &= ~(EXYNOS_EMUL_DATA_MASK << EXYNOS_EMUL_DATA_SHIFT);
606 val |= (temp_to_code(data, temp) << EXYNOS_EMUL_DATA_SHIFT) |
609 val &= ~EXYNOS_EMUL_ENABLE;
615 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
621 if (data->soc == SOC_ARCH_EXYNOS5260)
622 emul_con = EXYNOS5260_EMUL_CON;
624 emul_con = EXYNOS_EMUL_CON;
626 val = readl(data->base + emul_con);
627 val = get_emul_con_reg(data, val, temp);
628 writel(val, data->base + emul_con);
631 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
636 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
637 val = get_emul_con_reg(data, val, temp);
638 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
641 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
643 struct exynos_tmu_data *data = drv_data;
646 if (data->soc == SOC_ARCH_EXYNOS4210)
649 if (temp && temp < MCELSIUS)
652 mutex_lock(&data->lock);
653 clk_enable(data->clk);
654 data->tmu_set_emulation(data, temp);
655 clk_disable(data->clk);
656 mutex_unlock(&data->lock);
662 #define exynos4412_tmu_set_emulation NULL
663 #define exynos5440_tmu_set_emulation NULL
664 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
666 #endif /* CONFIG_THERMAL_EMULATION */
668 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
670 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
672 /* "temp_code" should range between 75 and 175 */
673 return (ret < 75 || ret > 175) ? -ENODATA : ret;
676 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
678 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
681 static int exynos5440_tmu_read(struct exynos_tmu_data *data)
683 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
686 static void exynos_tmu_work(struct work_struct *work)
688 struct exynos_tmu_data *data = container_of(work,
689 struct exynos_tmu_data, irq_work);
690 unsigned int val_type;
692 if (!IS_ERR(data->clk_sec))
693 clk_enable(data->clk_sec);
694 /* Find which sensor generated this interrupt */
695 if (data->soc == SOC_ARCH_EXYNOS5440) {
696 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
697 if (!((val_type >> data->id) & 0x1))
700 if (!IS_ERR(data->clk_sec))
701 clk_disable(data->clk_sec);
703 exynos_report_trigger(data);
704 mutex_lock(&data->lock);
705 clk_enable(data->clk);
707 /* TODO: take action based on particular interrupt */
708 data->tmu_clear_irqs(data);
710 clk_disable(data->clk);
711 mutex_unlock(&data->lock);
713 enable_irq(data->irq);
716 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
718 unsigned int val_irq;
719 u32 tmu_intstat, tmu_intclear;
721 if (data->soc == SOC_ARCH_EXYNOS5260) {
722 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
723 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
725 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
726 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
729 val_irq = readl(data->base + tmu_intstat);
731 * Clear the interrupts. Please note that the documentation for
732 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
733 * states that INTCLEAR register has a different placing of bits
734 * responsible for FALL IRQs than INTSTAT register. Exynos5420
735 * and Exynos5440 documentation is correct (Exynos4210 doesn't
736 * support FALL IRQs at all).
738 writel(val_irq, data->base + tmu_intclear);
741 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
743 unsigned int val_irq;
745 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
746 /* clear the interrupts */
747 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
750 static irqreturn_t exynos_tmu_irq(int irq, void *id)
752 struct exynos_tmu_data *data = id;
754 disable_irq_nosync(irq);
755 schedule_work(&data->irq_work);
760 static const struct of_device_id exynos_tmu_match[] = {
762 .compatible = "samsung,exynos3250-tmu",
765 .compatible = "samsung,exynos4210-tmu",
768 .compatible = "samsung,exynos4412-tmu",
771 .compatible = "samsung,exynos5250-tmu",
774 .compatible = "samsung,exynos5260-tmu",
777 .compatible = "samsung,exynos5420-tmu",
780 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
783 .compatible = "samsung,exynos5440-tmu",
787 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
789 static int exynos_of_get_soc_type(struct device_node *np)
791 if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
792 return SOC_ARCH_EXYNOS3250;
793 else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
794 return SOC_ARCH_EXYNOS4210;
795 else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
796 return SOC_ARCH_EXYNOS4412;
797 else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
798 return SOC_ARCH_EXYNOS5250;
799 else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
800 return SOC_ARCH_EXYNOS5260;
801 else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
802 return SOC_ARCH_EXYNOS5420;
803 else if (of_device_is_compatible(np,
804 "samsung,exynos5420-tmu-ext-triminfo"))
805 return SOC_ARCH_EXYNOS5420_TRIMINFO;
806 else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
807 return SOC_ARCH_EXYNOS5440;
812 static int exynos_of_sensor_conf(struct device_node *np,
813 struct exynos_tmu_platform_data *pdata)
820 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
821 pdata->gain = (u8)value;
822 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
823 pdata->reference_voltage = (u8)value;
824 of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
825 pdata->noise_cancel_mode = (u8)value;
827 of_property_read_u32(np, "samsung,tmu_efuse_value",
828 &pdata->efuse_value);
829 of_property_read_u32(np, "samsung,tmu_min_efuse_value",
830 &pdata->min_efuse_value);
831 of_property_read_u32(np, "samsung,tmu_max_efuse_value",
832 &pdata->max_efuse_value);
834 of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
835 pdata->first_point_trim = (u8)value;
836 of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
837 pdata->second_point_trim = (u8)value;
838 of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
839 pdata->default_temp_offset = (u8)value;
841 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
842 of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode);
848 static int exynos_map_dt_data(struct platform_device *pdev)
850 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
851 struct exynos_tmu_platform_data *pdata;
855 if (!data || !pdev->dev.of_node)
859 * Try enabling the regulator if found
860 * TODO: Add regulator as an SOC feature, so that regulator enable
861 * is a compulsory call.
863 data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
864 if (!IS_ERR(data->regulator)) {
865 ret = regulator_enable(data->regulator);
867 dev_err(&pdev->dev, "failed to enable vtmu\n");
871 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
874 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
878 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
879 if (data->irq <= 0) {
880 dev_err(&pdev->dev, "failed to get IRQ\n");
884 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
885 dev_err(&pdev->dev, "failed to get Resource 0\n");
889 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
891 dev_err(&pdev->dev, "Failed to ioremap memory\n");
892 return -EADDRNOTAVAIL;
895 pdata = devm_kzalloc(&pdev->dev,
896 sizeof(struct exynos_tmu_platform_data),
901 exynos_of_sensor_conf(pdev->dev.of_node, pdata);
903 data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
906 case SOC_ARCH_EXYNOS4210:
907 data->tmu_initialize = exynos4210_tmu_initialize;
908 data->tmu_control = exynos4210_tmu_control;
909 data->tmu_read = exynos4210_tmu_read;
910 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
912 case SOC_ARCH_EXYNOS3250:
913 case SOC_ARCH_EXYNOS4412:
914 case SOC_ARCH_EXYNOS5250:
915 case SOC_ARCH_EXYNOS5260:
916 case SOC_ARCH_EXYNOS5420:
917 case SOC_ARCH_EXYNOS5420_TRIMINFO:
918 data->tmu_initialize = exynos4412_tmu_initialize;
919 data->tmu_control = exynos4210_tmu_control;
920 data->tmu_read = exynos4412_tmu_read;
921 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
922 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
924 case SOC_ARCH_EXYNOS5440:
925 data->tmu_initialize = exynos5440_tmu_initialize;
926 data->tmu_control = exynos5440_tmu_control;
927 data->tmu_read = exynos5440_tmu_read;
928 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
929 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
932 dev_err(&pdev->dev, "Platform not supported\n");
937 * Check if the TMU shares some registers and then try to map the
938 * memory of common registers.
940 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
941 data->soc != SOC_ARCH_EXYNOS5440)
944 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
945 dev_err(&pdev->dev, "failed to get Resource 1\n");
949 data->base_second = devm_ioremap(&pdev->dev, res.start,
950 resource_size(&res));
951 if (!data->base_second) {
952 dev_err(&pdev->dev, "Failed to ioremap memory\n");
959 static struct thermal_zone_of_device_ops exynos_sensor_ops = {
960 .get_temp = exynos_get_temp,
961 .set_emul_temp = exynos_tmu_set_emulation,
964 static int exynos_tmu_probe(struct platform_device *pdev)
966 struct exynos_tmu_platform_data *pdata;
967 struct exynos_tmu_data *data;
970 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
975 platform_set_drvdata(pdev, data);
976 mutex_init(&data->lock);
978 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
980 if (IS_ERR(data->tzd)) {
981 pr_err("thermal: tz: %p ERROR\n", data->tzd);
982 return PTR_ERR(data->tzd);
984 ret = exynos_map_dt_data(pdev);
990 INIT_WORK(&data->irq_work, exynos_tmu_work);
992 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
993 if (IS_ERR(data->clk)) {
994 dev_err(&pdev->dev, "Failed to get clock\n");
995 ret = PTR_ERR(data->clk);
999 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1000 if (IS_ERR(data->clk_sec)) {
1001 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1002 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
1003 ret = PTR_ERR(data->clk_sec);
1007 ret = clk_prepare(data->clk_sec);
1009 dev_err(&pdev->dev, "Failed to get clock\n");
1014 ret = clk_prepare(data->clk);
1016 dev_err(&pdev->dev, "Failed to get clock\n");
1020 ret = exynos_tmu_initialize(pdev);
1022 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1026 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1027 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1029 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1033 exynos_tmu_control(pdev, true);
1036 clk_unprepare(data->clk);
1038 if (!IS_ERR(data->clk_sec))
1039 clk_unprepare(data->clk_sec);
1041 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1046 static int exynos_tmu_remove(struct platform_device *pdev)
1048 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1049 struct thermal_zone_device *tzd = data->tzd;
1051 thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
1052 exynos_tmu_control(pdev, false);
1054 clk_unprepare(data->clk);
1055 if (!IS_ERR(data->clk_sec))
1056 clk_unprepare(data->clk_sec);
1058 if (!IS_ERR(data->regulator))
1059 regulator_disable(data->regulator);
1064 #ifdef CONFIG_PM_SLEEP
1065 static int exynos_tmu_suspend(struct device *dev)
1067 exynos_tmu_control(to_platform_device(dev), false);
1072 static int exynos_tmu_resume(struct device *dev)
1074 struct platform_device *pdev = to_platform_device(dev);
1076 exynos_tmu_initialize(pdev);
1077 exynos_tmu_control(pdev, true);
1082 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1083 exynos_tmu_suspend, exynos_tmu_resume);
1084 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
1086 #define EXYNOS_TMU_PM NULL
1089 static struct platform_driver exynos_tmu_driver = {
1091 .name = "exynos-tmu",
1092 .pm = EXYNOS_TMU_PM,
1093 .of_match_table = exynos_tmu_match,
1095 .probe = exynos_tmu_probe,
1096 .remove = exynos_tmu_remove,
1099 module_platform_driver(exynos_tmu_driver);
1101 MODULE_DESCRIPTION("EXYNOS TMU Driver");
1102 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1103 MODULE_LICENSE("GPL");
1104 MODULE_ALIAS("platform:exynos-tmu");