drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  30         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
  31         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
  32         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  33         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
  34         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
  35         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
  36         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
  37         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
  38         .tmu_status = EXYNOS_TMU_REG_STATUS,
  39         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  40         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
  41         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  42         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  43         .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
  44         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  45         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  46         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  47         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  48         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  49         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  50 };
  51
  52 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  53         .tmu_data = {
  54                 {
  55                 .threshold = 80,
  56                 .trigger_levels[0] = 5,
  57                 .trigger_levels[1] = 20,
  58                 .trigger_levels[2] = 30,
  59                 .trigger_enable[0] = true,
  60                 .trigger_enable[1] = true,
  61                 .trigger_enable[2] = true,
  62                 .trigger_enable[3] = false,
  63                 .trigger_type[0] = THROTTLE_ACTIVE,
  64                 .trigger_type[1] = THROTTLE_ACTIVE,
  65                 .trigger_type[2] = SW_TRIP,
  66                 .max_trigger_level = 4,
  67                 .gain = 15,
  68                 .reference_voltage = 7,
  69                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  70                 .min_efuse_value = 40,
  71                 .max_efuse_value = 100,
  72                 .first_point_trim = 25,
  73                 .second_point_trim = 85,
  74                 .default_temp_offset = 50,
  75                 .freq_tab[0] = {
  76                         .freq_clip_max = 800 * 1000,
  77                         .temp_level = 85,
  78                         },
  79                 .freq_tab[1] = {
  80                         .freq_clip_max = 200 * 1000,
  81                         .temp_level = 100,
  82                 },
  83                 .freq_tab_count = 2,
  84                 .type = SOC_ARCH_EXYNOS4210,
  85                 .registers = &exynos4210_tmu_registers,
  86                 .features = TMU_SUPPORT_READY_STATUS,
  87                 },
  88         },
  89         .tmu_count = 1,
  90 };
  91 #endif
  92
  93 #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
  94 static const struct exynos_tmu_registers exynos5250_tmu_registers = {
  95         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  96         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
  97         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
  98         .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
  99         .triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
 100         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 101         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
 102         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
 103         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 104         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 105         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 106         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
 107         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 108         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 109         .tmu_status = EXYNOS_TMU_REG_STATUS,
 110         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 111         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 112         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 113         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 114         .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 115         .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 116         .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 117         .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 118         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 119         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 120         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 121         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 122         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 123         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 124         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 125         .emul_con = EXYNOS_EMUL_CON,
 126         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 127         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 128         .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
 129 };
 130
 131 #define EXYNOS5250_TMU_DATA \
 132         .threshold_falling = 10, \
 133         .trigger_levels[0] = 85, \
 134         .trigger_levels[1] = 103, \
 135         .trigger_levels[2] = 110, \
 136         .trigger_levels[3] = 120, \
 137         .trigger_enable[0] = true, \
 138         .trigger_enable[1] = true, \
 139         .trigger_enable[2] = true, \
 140         .trigger_enable[3] = false, \
 141         .trigger_type[0] = THROTTLE_ACTIVE, \
 142         .trigger_type[1] = THROTTLE_ACTIVE, \
 143         .trigger_type[2] = SW_TRIP, \
 144         .trigger_type[3] = HW_TRIP, \
 145         .max_trigger_level = 4, \
 146         .gain = 8, \
 147         .reference_voltage = 16, \
 148         .noise_cancel_mode = 4, \
 149         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 150         .efuse_value = 55, \
 151         .min_efuse_value = 40, \
 152         .max_efuse_value = 100, \
 153         .first_point_trim = 25, \
 154         .second_point_trim = 85, \
 155         .default_temp_offset = 50, \
 156         .freq_tab[0] = { \
 157                 .freq_clip_max = 800 * 1000, \
 158                 .temp_level = 85, \
 159         }, \
 160         .freq_tab[1] = { \
 161                 .freq_clip_max = 200 * 1000, \
 162                 .temp_level = 103, \
 163         }, \
 164         .freq_tab_count = 2, \
 165         .type = SOC_ARCH_EXYNOS, \
 166         .registers = &exynos5250_tmu_registers, \
 167         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 168                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 169                         TMU_SUPPORT_EMUL_TIME)
 170
 171 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 172         .tmu_data = {
 173                 { EXYNOS5250_TMU_DATA },
 174         },
 175         .tmu_count = 1,
 176 };
 177 #endif
 178
 179 #if defined(CONFIG_SOC_EXYNOS5440)
 180 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 181         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
 182         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
 183         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
 184         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 185         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
 186         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
 187         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 188         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 189         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 190         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
 191         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 192         .calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
 193         .calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
 194         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 195         .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
 196         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 197         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 198         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 199         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 200         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 201         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 202         .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
 203         .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
 204         .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 205         .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
 206         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 207         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 208         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 209         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 210         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 211         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 212         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 213         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 214         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 215         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 216         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 217 };
 218
 219 #define EXYNOS5440_TMU_DATA \
 220         .trigger_levels[0] = 100, \
 221         .trigger_levels[4] = 105, \
 222         .trigger_enable[0] = 1, \
 223         .trigger_type[0] = SW_TRIP, \
 224         .trigger_type[4] = HW_TRIP, \
 225         .max_trigger_level = 5, \
 226         .gain = 5, \
 227         .reference_voltage = 16, \
 228         .noise_cancel_mode = 4, \
 229         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 230         .cal_mode = 0, \
 231         .efuse_value = 0x5b2d, \
 232         .min_efuse_value = 16, \
 233         .max_efuse_value = 76, \
 234         .first_point_trim = 25, \
 235         .second_point_trim = 70, \
 236         .default_temp_offset = 25, \
 237         .type = SOC_ARCH_EXYNOS5440, \
 238         .registers = &exynos5440_tmu_registers, \
 239         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 240                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
 241
 242 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 243         .tmu_data = {
 244                 { EXYNOS5440_TMU_DATA } ,
 245                 { EXYNOS5440_TMU_DATA } ,
 246                 { EXYNOS5440_TMU_DATA } ,
 247         },
 248         .tmu_count = 3,
 249 };
 250 #endif