2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <linux/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
92 /****** RocketPort includes ******/
94 #include "rocket_int.h"
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
100 /****** RocketPort Local Variables ******/
102 static void rp_do_poll(unsigned long dummy);
104 static struct tty_driver *rocket_driver;
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
160 static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
181 static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197 static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 static int sClockPrescale = 0x14;
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
223 static unsigned char lineNumbers[MAX_RP_PORTS];
224 static unsigned long nextLineNumber;
226 /***** RocketPort Static Prototypes *********/
227 static int __init init_ISA(int i);
228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229 static void rp_flush_buffer(struct tty_struct *tty);
230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233 static void rp_start(struct tty_struct *tty);
234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237 static void sFlushRxFIFO(CHANNEL_T * ChP);
238 static void sFlushTxFIFO(CHANNEL_T * ChP);
239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252 static int sReadAiopID(ByteIO_t io);
253 static int sReadAiopNumChan(WordIO_t io);
255 MODULE_AUTHOR("Theodore Ts'o");
256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
257 module_param(board1, ulong, 0);
258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259 module_param(board2, ulong, 0);
260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261 module_param(board3, ulong, 0);
262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263 module_param(board4, ulong, 0);
264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265 module_param(controller, ulong, 0);
266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267 module_param(support_low_speed, bool, 0);
268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269 module_param(modem1, ulong, 0);
270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271 module_param(modem2, ulong, 0);
272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273 module_param(modem3, ulong, 0);
274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275 module_param(modem4, ulong, 0);
276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277 module_param_array(pc104_1, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279 module_param_array(pc104_2, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281 module_param_array(pc104_3, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283 module_param_array(pc104_4, ulong, NULL, 0);
284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
286 static int rp_init(void);
287 static void rp_cleanup_module(void);
289 module_init(rp_init);
290 module_exit(rp_cleanup_module);
293 MODULE_LICENSE("Dual BSD/GPL");
295 /*************************************************************************/
296 /* Module code starts here */
298 static inline int rocket_paranoia_check(struct r_port *info,
301 #ifdef ROCKET_PARANOIA_CHECK
304 if (info->magic != RPORT_MAGIC) {
305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
314 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
318 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
319 unsigned int ChanStatus)
321 unsigned int CharNStat;
322 int ToRecv, wRecv, space;
325 ToRecv = sGetRxCnt(cp);
326 #ifdef ROCKET_DEBUG_INTR
327 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
333 * if status indicates there are errored characters in the
334 * FIFO, then enter status mode (a word in FIFO holds
335 * character and status).
337 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
338 if (!(ChanStatus & STATMODE)) {
339 #ifdef ROCKET_DEBUG_RECEIVE
340 printk(KERN_INFO "Entering STATMODE...\n");
342 ChanStatus |= STATMODE;
348 * if we previously entered status mode, then read down the
349 * FIFO one word at a time, pulling apart the character and
350 * the status. Update error counters depending on status
352 if (ChanStatus & STATMODE) {
353 #ifdef ROCKET_DEBUG_RECEIVE
354 printk(KERN_INFO "Ignore %x, read %x...\n",
355 info->ignore_status_mask, info->read_status_mask);
360 CharNStat = sInW(sGetTxRxDataIO(cp));
361 #ifdef ROCKET_DEBUG_RECEIVE
362 printk(KERN_INFO "%x...\n", CharNStat);
364 if (CharNStat & STMBREAKH)
365 CharNStat &= ~(STMFRAMEH | STMPARITYH);
366 if (CharNStat & info->ignore_status_mask) {
370 CharNStat &= info->read_status_mask;
371 if (CharNStat & STMBREAKH)
373 else if (CharNStat & STMPARITYH)
375 else if (CharNStat & STMFRAMEH)
377 else if (CharNStat & STMRCVROVRH)
381 tty_insert_flip_char(&info->port, CharNStat & 0xff,
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
390 if (sGetRxCnt(cp) == 0) {
391 #ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
394 sDisRxStatusMode(cp);
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
402 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
403 if (space < ToRecv) {
404 #ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
417 /* Push the data up to the tty layer */
418 tty_flip_buffer_push(&info->port);
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
427 static void rp_do_transmit(struct r_port *info)
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
434 #ifdef ROCKET_DEBUG_INTR
435 printk(KERN_DEBUG "%s\n", __func__);
439 tty = tty_port_tty_get(&info->port);
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
447 spin_lock_irqsave(&info->slock, flags);
448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
450 /* Loop sending data to FIFO until done or FIFO full */
454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
456 if (c <= 0 || info->xmit_fifo_room <= 0)
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
464 info->xmit_fifo_room -= c;
465 #ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...\n", c);
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
473 if (info->xmit_cnt < WAKEUP_CHARS) {
475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
480 spin_unlock_irqrestore(&info->slock, flags);
483 #ifdef ROCKET_DEBUG_INTR
484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
485 info->xmit_tail, info->xmit_fifo_room);
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
494 static void rp_handle_port(struct r_port *info)
497 unsigned int IntMask, ChanStatus;
502 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
503 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
504 "info->flags & NOT_INIT\n");
510 IntMask = sGetChanIntID(cp) & info->intmask;
511 #ifdef ROCKET_DEBUG_INTR
512 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
514 ChanStatus = sGetChanStatus(cp);
515 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
516 rp_do_receive(info, cp, ChanStatus);
518 if (IntMask & DELTA_CD) { /* CD change */
519 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
520 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
521 (ChanStatus & CD_ACT) ? "on" : "off");
523 if (!(ChanStatus & CD_ACT) && info->cd_status) {
524 #ifdef ROCKET_DEBUG_HANGUP
525 printk(KERN_INFO "CD drop, calling hangup.\n");
527 tty_port_tty_hangup(&info->port, false);
529 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
530 wake_up_interruptible(&info->port.open_wait);
532 #ifdef ROCKET_DEBUG_INTR
533 if (IntMask & DELTA_CTS) { /* CTS change */
534 printk(KERN_INFO "CTS change...\n");
536 if (IntMask & DELTA_DSR) { /* DSR change */
537 printk(KERN_INFO "DSR change...\n");
543 * The top level polling routine. Repeats every 1/100 HZ (10ms).
545 static void rp_do_poll(unsigned long dummy)
548 int ctrl, aiop, ch, line;
549 unsigned int xmitmask, i;
550 unsigned int CtlMask;
551 unsigned char AiopMask;
554 /* Walk through all the boards (ctrl's) */
555 for (ctrl = 0; ctrl < max_board; ctrl++) {
556 if (rcktpt_io_addr[ctrl] <= 0)
559 /* Get a ptr to the board's control struct */
560 ctlp = sCtlNumToCtlPtr(ctrl);
562 /* Get the interrupt status from the board */
564 if (ctlp->BusType == isPCI)
565 CtlMask = sPCIGetControllerIntStatus(ctlp);
568 CtlMask = sGetControllerIntStatus(ctlp);
570 /* Check if any AIOP read bits are set */
571 for (aiop = 0; CtlMask; aiop++) {
572 bit = ctlp->AiopIntrBits[aiop];
575 AiopMask = sGetAiopIntStatus(ctlp, aiop);
577 /* Check if any port read bits are set */
578 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
581 /* Get the line number (/dev/ttyRx number). */
582 /* Read the data from the port. */
583 line = GetLineNumber(ctrl, aiop, ch);
584 rp_handle_port(rp_table[line]);
590 xmitmask = xmit_flags[ctrl];
593 * xmit_flags contains bit-significant flags, indicating there is data
594 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
595 * 1, ... (32 total possible). The variable i has the aiop and ch
596 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
599 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
600 if (xmitmask & (1 << i)) {
601 aiop = (i & 0x18) >> 3;
603 line = GetLineNumber(ctrl, aiop, ch);
604 rp_do_transmit(rp_table[line]);
611 * Reset the timer so we get called at the next clock tick (10ms).
613 if (atomic_read(&rp_num_ports_open))
614 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
618 * Initializes the r_port structure for a port, as well as enabling the port on
620 * Inputs: board, aiop, chan numbers
622 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
629 /* Get the next available line number */
630 line = SetLineNumber(board, aiop, chan);
632 ctlp = sCtlNumToCtlPtr(board);
634 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
635 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
637 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
642 info->magic = RPORT_MAGIC;
648 tty_port_init(&info->port);
649 info->port.ops = &rocket_port_ops;
650 init_completion(&info->close_wait);
651 info->flags &= ~ROCKET_MODE_MASK;
652 switch (pc104[board][line]) {
654 info->flags |= ROCKET_MODE_RS422;
657 info->flags |= ROCKET_MODE_RS485;
661 info->flags |= ROCKET_MODE_RS232;
665 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
666 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
667 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
669 tty_port_destroy(&info->port);
674 rocketMode = info->flags & ROCKET_MODE_MASK;
676 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
677 sEnRTSToggle(&info->channel);
679 sDisRTSToggle(&info->channel);
681 if (ctlp->boardType == ROCKET_TYPE_PC104) {
682 switch (rocketMode) {
683 case ROCKET_MODE_RS485:
684 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
686 case ROCKET_MODE_RS422:
687 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
689 case ROCKET_MODE_RS232:
691 if (info->flags & ROCKET_RTS_TOGGLE)
692 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
698 spin_lock_init(&info->slock);
699 mutex_init(&info->write_mtx);
700 rp_table[line] = info;
701 tty_port_register_device(&info->port, rocket_driver, line,
702 pci_dev ? &pci_dev->dev : NULL);
706 * Configures a rocketport port according to its termio settings. Called from
707 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
709 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
710 struct ktermios *old_termios)
715 int bits, baud, divisor;
717 struct ktermios *t = &tty->termios;
722 /* Byte size and parity */
723 if ((cflag & CSIZE) == CS8) {
730 if (cflag & CSTOPB) {
737 if (cflag & PARENB) {
740 if (cflag & PARODD) {
750 baud = tty_get_baud_rate(tty);
753 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
754 if ((divisor >= 8192 || divisor < 0) && old_termios) {
755 baud = tty_termios_baud_rate(old_termios);
758 divisor = (rp_baud_base[info->board] / baud) - 1;
760 if (divisor >= 8192 || divisor < 0) {
762 divisor = (rp_baud_base[info->board] / baud) - 1;
764 info->cps = baud / bits;
765 sSetBaud(cp, divisor);
767 /* FIXME: Should really back compute a baud rate from the divisor */
768 tty_encode_baud_rate(tty, baud, baud);
770 if (cflag & CRTSCTS) {
771 info->intmask |= DELTA_CTS;
774 info->intmask &= ~DELTA_CTS;
777 if (cflag & CLOCAL) {
778 info->intmask &= ~DELTA_CD;
780 spin_lock_irqsave(&info->slock, flags);
781 if (sGetChanStatus(cp) & CD_ACT)
785 info->intmask |= DELTA_CD;
786 spin_unlock_irqrestore(&info->slock, flags);
790 * Handle software flow control in the board
792 #ifdef ROCKET_SOFT_FLOW
794 sEnTxSoftFlowCtl(cp);
800 sSetTxXONChar(cp, START_CHAR(tty));
801 sSetTxXOFFChar(cp, STOP_CHAR(tty));
803 sDisTxSoftFlowCtl(cp);
810 * Set up ignore/read mask words
812 info->read_status_mask = STMRCVROVRH | 0xFF;
814 info->read_status_mask |= STMFRAMEH | STMPARITYH;
815 if (I_BRKINT(tty) || I_PARMRK(tty))
816 info->read_status_mask |= STMBREAKH;
819 * Characters to ignore
821 info->ignore_status_mask = 0;
823 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
825 info->ignore_status_mask |= STMBREAKH;
827 * If we're ignoring parity and break indicators,
828 * ignore overruns too. (For real raw support).
831 info->ignore_status_mask |= STMRCVROVRH;
834 rocketMode = info->flags & ROCKET_MODE_MASK;
836 if ((info->flags & ROCKET_RTS_TOGGLE)
837 || (rocketMode == ROCKET_MODE_RS485))
842 sSetRTS(&info->channel);
844 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
845 switch (rocketMode) {
846 case ROCKET_MODE_RS485:
847 sSetInterfaceMode(cp, InterfaceModeRS485);
849 case ROCKET_MODE_RS422:
850 sSetInterfaceMode(cp, InterfaceModeRS422);
852 case ROCKET_MODE_RS232:
854 if (info->flags & ROCKET_RTS_TOGGLE)
855 sSetInterfaceMode(cp, InterfaceModeRS232T);
857 sSetInterfaceMode(cp, InterfaceModeRS232);
863 static int carrier_raised(struct tty_port *port)
865 struct r_port *info = container_of(port, struct r_port, port);
866 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
869 static void dtr_rts(struct tty_port *port, int on)
871 struct r_port *info = container_of(port, struct r_port, port);
873 sSetDTR(&info->channel);
874 sSetRTS(&info->channel);
876 sClrDTR(&info->channel);
877 sClrRTS(&info->channel);
882 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
883 * port's r_port struct. Initializes the port hardware.
885 static int rp_open(struct tty_struct *tty, struct file *filp)
888 struct tty_port *port;
893 info = rp_table[tty->index];
898 page = __get_free_page(GFP_KERNEL);
902 if (port->flags & ASYNC_CLOSING) {
903 retval = wait_for_completion_interruptible(&info->close_wait);
907 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
911 * We must not sleep from here until the port is marked fully in use.
916 info->xmit_buf = (unsigned char *) page;
918 tty->driver_data = info;
919 tty_port_tty_set(port, tty);
921 if (port->count++ == 0) {
922 atomic_inc(&rp_num_ports_open);
924 #ifdef ROCKET_DEBUG_OPEN
925 printk(KERN_INFO "rocket mod++ = %d...\n",
926 atomic_read(&rp_num_ports_open));
929 #ifdef ROCKET_DEBUG_OPEN
930 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
934 * Info->count is now 1; so it's safe to sleep now.
936 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
938 sSetRxTrigger(cp, TRIG_1);
939 if (sGetChanStatus(cp) & CD_ACT)
943 sDisRxStatusMode(cp);
947 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
948 sSetRxTrigger(cp, TRIG_1);
951 sDisRxStatusMode(cp);
955 sDisTxSoftFlowCtl(cp);
960 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
963 * Set up the tty->alt_speed kludge
965 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
966 tty->alt_speed = 57600;
967 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
968 tty->alt_speed = 115200;
969 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
970 tty->alt_speed = 230400;
971 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
972 tty->alt_speed = 460800;
974 configure_r_port(tty, info, NULL);
975 if (tty->termios.c_cflag & CBAUD) {
980 /* Starts (or resets) the maint polling loop */
981 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
983 retval = tty_port_block_til_ready(port, tty, filp);
985 #ifdef ROCKET_DEBUG_OPEN
986 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
994 * Exception handler that closes a serial port. info->port.count is considered critical.
996 static void rp_close(struct tty_struct *tty, struct file *filp)
998 struct r_port *info = tty->driver_data;
999 struct tty_port *port = &info->port;
1003 if (rocket_paranoia_check(info, "rp_close"))
1006 #ifdef ROCKET_DEBUG_OPEN
1007 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1010 if (tty_port_close_start(port, tty, filp) == 0)
1013 mutex_lock(&port->mutex);
1014 cp = &info->channel;
1016 * Before we drop DTR, make sure the UART transmitter
1017 * has completely drained; this is especially
1018 * important if there is a transmit FIFO!
1020 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1023 rp_wait_until_sent(tty, timeout);
1024 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1027 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1029 sDisTxSoftFlowCtl(cp);
1037 rp_flush_buffer(tty);
1039 tty_ldisc_flush(tty);
1041 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1043 /* We can't yet use tty_port_close_end as the buffer handling in this
1044 driver is a bit different to the usual */
1046 if (port->blocked_open) {
1047 if (port->close_delay) {
1048 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1050 wake_up_interruptible(&port->open_wait);
1052 if (info->xmit_buf) {
1053 free_page((unsigned long) info->xmit_buf);
1054 info->xmit_buf = NULL;
1057 spin_lock_irq(&port->lock);
1058 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1060 spin_unlock_irq(&port->lock);
1061 mutex_unlock(&port->mutex);
1062 tty_port_tty_set(port, NULL);
1064 wake_up_interruptible(&port->close_wait);
1065 complete_all(&info->close_wait);
1066 atomic_dec(&rp_num_ports_open);
1068 #ifdef ROCKET_DEBUG_OPEN
1069 printk(KERN_INFO "rocket mod-- = %d...\n",
1070 atomic_read(&rp_num_ports_open));
1071 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1076 static void rp_set_termios(struct tty_struct *tty,
1077 struct ktermios *old_termios)
1079 struct r_port *info = tty->driver_data;
1083 if (rocket_paranoia_check(info, "rp_set_termios"))
1086 cflag = tty->termios.c_cflag;
1089 * This driver doesn't support CS5 or CS6
1091 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1092 tty->termios.c_cflag =
1093 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1095 tty->termios.c_cflag &= ~CMSPAR;
1097 configure_r_port(tty, info, old_termios);
1099 cp = &info->channel;
1101 /* Handle transition to B0 status */
1102 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1107 /* Handle transition away from B0 status */
1108 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1113 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1117 static int rp_break(struct tty_struct *tty, int break_state)
1119 struct r_port *info = tty->driver_data;
1120 unsigned long flags;
1122 if (rocket_paranoia_check(info, "rp_break"))
1125 spin_lock_irqsave(&info->slock, flags);
1126 if (break_state == -1)
1127 sSendBreak(&info->channel);
1129 sClrBreak(&info->channel);
1130 spin_unlock_irqrestore(&info->slock, flags);
1135 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1136 * the UPCI boards was added, it was decided to make this a function because
1137 * the macro was getting too complicated. All cases except the first one
1138 * (UPCIRingInd) are taken directly from the original macro.
1140 static int sGetChanRI(CHANNEL_T * ChP)
1142 CONTROLLER_t *CtlP = ChP->CtlP;
1143 int ChanNum = ChP->ChanNum;
1146 if (CtlP->UPCIRingInd)
1147 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1148 else if (CtlP->AltChanRingIndicator)
1149 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1150 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1151 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1156 /********************************************************************************************/
1157 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1160 * Returns the state of the serial modem control lines. These next 2 functions
1161 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1163 static int rp_tiocmget(struct tty_struct *tty)
1165 struct r_port *info = tty->driver_data;
1166 unsigned int control, result, ChanStatus;
1168 ChanStatus = sGetChanStatusLo(&info->channel);
1169 control = info->channel.TxControl[3];
1170 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1171 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1172 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1173 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1174 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1175 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1181 * Sets the modem control lines
1183 static int rp_tiocmset(struct tty_struct *tty,
1184 unsigned int set, unsigned int clear)
1186 struct r_port *info = tty->driver_data;
1188 if (set & TIOCM_RTS)
1189 info->channel.TxControl[3] |= SET_RTS;
1190 if (set & TIOCM_DTR)
1191 info->channel.TxControl[3] |= SET_DTR;
1192 if (clear & TIOCM_RTS)
1193 info->channel.TxControl[3] &= ~SET_RTS;
1194 if (clear & TIOCM_DTR)
1195 info->channel.TxControl[3] &= ~SET_DTR;
1197 out32(info->channel.IndexAddr, info->channel.TxControl);
1201 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1203 struct rocket_config tmp;
1207 memset(&tmp, 0, sizeof (tmp));
1208 mutex_lock(&info->port.mutex);
1209 tmp.line = info->line;
1210 tmp.flags = info->flags;
1211 tmp.close_delay = info->port.close_delay;
1212 tmp.closing_wait = info->port.closing_wait;
1213 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1214 mutex_unlock(&info->port.mutex);
1216 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1221 static int set_config(struct tty_struct *tty, struct r_port *info,
1222 struct rocket_config __user *new_info)
1224 struct rocket_config new_serial;
1226 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1229 mutex_lock(&info->port.mutex);
1230 if (!capable(CAP_SYS_ADMIN))
1232 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1233 mutex_unlock(&info->port.mutex);
1236 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1237 configure_r_port(tty, info, NULL);
1238 mutex_unlock(&info->port.mutex);
1242 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1243 info->port.close_delay = new_serial.close_delay;
1244 info->port.closing_wait = new_serial.closing_wait;
1246 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1247 tty->alt_speed = 57600;
1248 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1249 tty->alt_speed = 115200;
1250 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1251 tty->alt_speed = 230400;
1252 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1253 tty->alt_speed = 460800;
1254 mutex_unlock(&info->port.mutex);
1256 configure_r_port(tty, info, NULL);
1261 * This function fills in a rocket_ports struct with information
1262 * about what boards/ports are in the system. This info is passed
1263 * to user space. See setrocket.c where the info is used to create
1264 * the /dev/ttyRx ports.
1266 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1268 struct rocket_ports tmp;
1273 memset(&tmp, 0, sizeof (tmp));
1274 tmp.tty_major = rocket_driver->major;
1276 for (board = 0; board < 4; board++) {
1277 tmp.rocketModel[board].model = rocketModel[board].model;
1278 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1279 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1280 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1281 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1283 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1288 static int reset_rm2(struct r_port *info, void __user *arg)
1292 if (!capable(CAP_SYS_ADMIN))
1295 if (copy_from_user(&reset, arg, sizeof (int)))
1300 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1301 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1304 if (info->ctlp->BusType == isISA)
1305 sModemReset(info->ctlp, info->chan, reset);
1307 sPCIModemReset(info->ctlp, info->chan, reset);
1312 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1314 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1319 /* IOCTL call handler into the driver */
1320 static int rp_ioctl(struct tty_struct *tty,
1321 unsigned int cmd, unsigned long arg)
1323 struct r_port *info = tty->driver_data;
1324 void __user *argp = (void __user *)arg;
1327 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1331 case RCKP_GET_STRUCT:
1332 if (copy_to_user(argp, info, sizeof (struct r_port)))
1335 case RCKP_GET_CONFIG:
1336 ret = get_config(info, argp);
1338 case RCKP_SET_CONFIG:
1339 ret = set_config(tty, info, argp);
1341 case RCKP_GET_PORTS:
1342 ret = get_ports(info, argp);
1344 case RCKP_RESET_RM2:
1345 ret = reset_rm2(info, argp);
1347 case RCKP_GET_VERSION:
1348 ret = get_version(info, argp);
1356 static void rp_send_xchar(struct tty_struct *tty, char ch)
1358 struct r_port *info = tty->driver_data;
1361 if (rocket_paranoia_check(info, "rp_send_xchar"))
1364 cp = &info->channel;
1366 sWriteTxPrioByte(cp, ch);
1368 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1371 static void rp_throttle(struct tty_struct *tty)
1373 struct r_port *info = tty->driver_data;
1375 #ifdef ROCKET_DEBUG_THROTTLE
1376 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1377 tty->ldisc.chars_in_buffer(tty));
1380 if (rocket_paranoia_check(info, "rp_throttle"))
1384 rp_send_xchar(tty, STOP_CHAR(tty));
1386 sClrRTS(&info->channel);
1389 static void rp_unthrottle(struct tty_struct *tty)
1391 struct r_port *info = tty->driver_data;
1392 #ifdef ROCKET_DEBUG_THROTTLE
1393 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1394 tty->ldisc.chars_in_buffer(tty));
1397 if (rocket_paranoia_check(info, "rp_throttle"))
1401 rp_send_xchar(tty, START_CHAR(tty));
1403 sSetRTS(&info->channel);
1407 * ------------------------------------------------------------
1408 * rp_stop() and rp_start()
1410 * This routines are called before setting or resetting tty->stopped.
1411 * They enable or disable transmitter interrupts, as necessary.
1412 * ------------------------------------------------------------
1414 static void rp_stop(struct tty_struct *tty)
1416 struct r_port *info = tty->driver_data;
1418 #ifdef ROCKET_DEBUG_FLOW
1419 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1420 info->xmit_cnt, info->xmit_fifo_room);
1423 if (rocket_paranoia_check(info, "rp_stop"))
1426 if (sGetTxCnt(&info->channel))
1427 sDisTransmit(&info->channel);
1430 static void rp_start(struct tty_struct *tty)
1432 struct r_port *info = tty->driver_data;
1434 #ifdef ROCKET_DEBUG_FLOW
1435 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1436 info->xmit_cnt, info->xmit_fifo_room);
1439 if (rocket_paranoia_check(info, "rp_stop"))
1442 sEnTransmit(&info->channel);
1443 set_bit((info->aiop * 8) + info->chan,
1444 (void *) &xmit_flags[info->board]);
1448 * rp_wait_until_sent() --- wait until the transmitter is empty
1450 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1452 struct r_port *info = tty->driver_data;
1454 unsigned long orig_jiffies;
1455 int check_time, exit_time;
1458 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1461 cp = &info->channel;
1463 orig_jiffies = jiffies;
1464 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1465 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1467 printk(KERN_INFO "cps=%d...\n", info->cps);
1470 txcnt = sGetTxCnt(cp);
1472 if (sGetChanStatusLo(cp) & TXSHRMT)
1474 check_time = (HZ / info->cps) / 5;
1476 check_time = HZ * txcnt / info->cps;
1479 exit_time = orig_jiffies + timeout - jiffies;
1482 if (exit_time < check_time)
1483 check_time = exit_time;
1485 if (check_time == 0)
1487 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1488 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1489 jiffies, check_time);
1491 msleep_interruptible(jiffies_to_msecs(check_time));
1492 if (signal_pending(current))
1495 __set_current_state(TASK_RUNNING);
1496 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1497 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1502 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1504 static void rp_hangup(struct tty_struct *tty)
1507 struct r_port *info = tty->driver_data;
1508 unsigned long flags;
1510 if (rocket_paranoia_check(info, "rp_hangup"))
1513 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1514 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1516 rp_flush_buffer(tty);
1517 spin_lock_irqsave(&info->port.lock, flags);
1518 if (info->port.flags & ASYNC_CLOSING) {
1519 spin_unlock_irqrestore(&info->port.lock, flags);
1522 if (info->port.count)
1523 atomic_dec(&rp_num_ports_open);
1524 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1525 spin_unlock_irqrestore(&info->port.lock, flags);
1527 tty_port_hangup(&info->port);
1529 cp = &info->channel;
1532 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1534 sDisTxSoftFlowCtl(cp);
1536 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1538 wake_up_interruptible(&info->port.open_wait);
1542 * Exception handler - write char routine. The RocketPort driver uses a
1543 * double-buffering strategy, with the twist that if the in-memory CPU
1544 * buffer is empty, and there's space in the transmit FIFO, the
1545 * writing routines will write directly to transmit FIFO.
1546 * Write buffer and counters protected by spinlocks
1548 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1550 struct r_port *info = tty->driver_data;
1552 unsigned long flags;
1554 if (rocket_paranoia_check(info, "rp_put_char"))
1558 * Grab the port write mutex, locking out other processes that try to
1559 * write to this port
1561 mutex_lock(&info->write_mtx);
1563 #ifdef ROCKET_DEBUG_WRITE
1564 printk(KERN_INFO "rp_put_char %c...\n", ch);
1567 spin_lock_irqsave(&info->slock, flags);
1568 cp = &info->channel;
1570 if (!tty->stopped && info->xmit_fifo_room == 0)
1571 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1573 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1574 info->xmit_buf[info->xmit_head++] = ch;
1575 info->xmit_head &= XMIT_BUF_SIZE - 1;
1577 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1579 sOutB(sGetTxRxDataIO(cp), ch);
1580 info->xmit_fifo_room--;
1582 spin_unlock_irqrestore(&info->slock, flags);
1583 mutex_unlock(&info->write_mtx);
1588 * Exception handler - write routine, called when user app writes to the device.
1589 * A per port write mutex is used to protect from another process writing to
1590 * this port at the same time. This other process could be running on the other CPU
1591 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1592 * Spinlocks protect the info xmit members.
1594 static int rp_write(struct tty_struct *tty,
1595 const unsigned char *buf, int count)
1597 struct r_port *info = tty->driver_data;
1599 const unsigned char *b;
1601 unsigned long flags;
1603 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1606 if (mutex_lock_interruptible(&info->write_mtx))
1607 return -ERESTARTSYS;
1609 #ifdef ROCKET_DEBUG_WRITE
1610 printk(KERN_INFO "rp_write %d chars...\n", count);
1612 cp = &info->channel;
1614 if (!tty->stopped && info->xmit_fifo_room < count)
1615 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1618 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1619 * into FIFO. Use the write queue for temp storage.
1621 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1622 c = min(count, info->xmit_fifo_room);
1625 /* Push data into FIFO, 2 bytes at a time */
1626 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1628 /* If there is a byte remaining, write it */
1630 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1636 spin_lock_irqsave(&info->slock, flags);
1637 info->xmit_fifo_room -= c;
1638 spin_unlock_irqrestore(&info->slock, flags);
1641 /* If count is zero, we wrote it all and are done */
1645 /* Write remaining data into the port's xmit_buf */
1648 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1650 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1651 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1656 memcpy(info->xmit_buf + info->xmit_head, b, c);
1658 spin_lock_irqsave(&info->slock, flags);
1660 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1661 info->xmit_cnt += c;
1662 spin_unlock_irqrestore(&info->slock, flags);
1669 if ((retval > 0) && !tty->stopped)
1670 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1673 if (info->xmit_cnt < WAKEUP_CHARS) {
1675 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1676 wake_up_interruptible(&tty->poll_wait);
1679 mutex_unlock(&info->write_mtx);
1684 * Return the number of characters that can be sent. We estimate
1685 * only using the in-memory transmit buffer only, and ignore the
1686 * potential space in the transmit FIFO.
1688 static int rp_write_room(struct tty_struct *tty)
1690 struct r_port *info = tty->driver_data;
1693 if (rocket_paranoia_check(info, "rp_write_room"))
1696 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1699 #ifdef ROCKET_DEBUG_WRITE
1700 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1706 * Return the number of characters in the buffer. Again, this only
1707 * counts those characters in the in-memory transmit buffer.
1709 static int rp_chars_in_buffer(struct tty_struct *tty)
1711 struct r_port *info = tty->driver_data;
1713 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1716 #ifdef ROCKET_DEBUG_WRITE
1717 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1719 return info->xmit_cnt;
1723 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1724 * r_port struct for the port. Note that spinlock are used to protect info members,
1725 * do not call this function if the spinlock is already held.
1727 static void rp_flush_buffer(struct tty_struct *tty)
1729 struct r_port *info = tty->driver_data;
1731 unsigned long flags;
1733 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1736 spin_lock_irqsave(&info->slock, flags);
1737 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1738 spin_unlock_irqrestore(&info->slock, flags);
1740 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1741 wake_up_interruptible(&tty->poll_wait);
1745 cp = &info->channel;
1751 static DEFINE_PCI_DEVICE_TABLE(rocket_pci_ids) = {
1752 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1753 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1754 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1755 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1756 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1757 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1758 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1759 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1760 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1761 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1762 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1763 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1764 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1765 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1766 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1767 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1768 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1769 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1770 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1771 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1772 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1773 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1776 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1779 * Called when a PCI card is found. Retrieves and stores model information,
1780 * init's aiopic and serial port hardware.
1781 * Inputs: i is the board number (0-n)
1783 static __init int register_PCI(int i, struct pci_dev *dev)
1785 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1786 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1790 int altChanRingIndicator = 0;
1791 int ports_per_aiop = 8;
1792 WordIO_t ConfigIO = 0;
1793 ByteIO_t UPCIRingInd = 0;
1795 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1796 pci_enable_device(dev))
1799 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1801 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1802 rocketModel[i].loadrm2 = 0;
1803 rocketModel[i].startingPortNumber = nextLineNumber;
1805 /* Depending on the model, set up some config variables */
1806 switch (dev->device) {
1807 case PCI_DEVICE_ID_RP4QUAD:
1810 rocketModel[i].model = MODEL_RP4QUAD;
1811 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1812 rocketModel[i].numPorts = 4;
1814 case PCI_DEVICE_ID_RP8OCTA:
1816 rocketModel[i].model = MODEL_RP8OCTA;
1817 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1818 rocketModel[i].numPorts = 8;
1820 case PCI_DEVICE_ID_URP8OCTA:
1822 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1823 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1824 rocketModel[i].numPorts = 8;
1826 case PCI_DEVICE_ID_RP8INTF:
1828 rocketModel[i].model = MODEL_RP8INTF;
1829 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1830 rocketModel[i].numPorts = 8;
1832 case PCI_DEVICE_ID_URP8INTF:
1834 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1835 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1836 rocketModel[i].numPorts = 8;
1838 case PCI_DEVICE_ID_RP8J:
1840 rocketModel[i].model = MODEL_RP8J;
1841 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1842 rocketModel[i].numPorts = 8;
1844 case PCI_DEVICE_ID_RP4J:
1847 rocketModel[i].model = MODEL_RP4J;
1848 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1849 rocketModel[i].numPorts = 4;
1851 case PCI_DEVICE_ID_RP8SNI:
1853 rocketModel[i].model = MODEL_RP8SNI;
1854 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1855 rocketModel[i].numPorts = 8;
1857 case PCI_DEVICE_ID_RP16SNI:
1859 rocketModel[i].model = MODEL_RP16SNI;
1860 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1861 rocketModel[i].numPorts = 16;
1863 case PCI_DEVICE_ID_RP16INTF:
1865 rocketModel[i].model = MODEL_RP16INTF;
1866 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1867 rocketModel[i].numPorts = 16;
1869 case PCI_DEVICE_ID_URP16INTF:
1871 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1872 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1873 rocketModel[i].numPorts = 16;
1875 case PCI_DEVICE_ID_CRP16INTF:
1877 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1878 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1879 rocketModel[i].numPorts = 16;
1881 case PCI_DEVICE_ID_RP32INTF:
1883 rocketModel[i].model = MODEL_RP32INTF;
1884 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1885 rocketModel[i].numPorts = 32;
1887 case PCI_DEVICE_ID_URP32INTF:
1889 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1890 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1891 rocketModel[i].numPorts = 32;
1893 case PCI_DEVICE_ID_RPP4:
1896 altChanRingIndicator++;
1898 rocketModel[i].model = MODEL_RPP4;
1899 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1900 rocketModel[i].numPorts = 4;
1902 case PCI_DEVICE_ID_RPP8:
1905 altChanRingIndicator++;
1907 rocketModel[i].model = MODEL_RPP8;
1908 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1909 rocketModel[i].numPorts = 8;
1911 case PCI_DEVICE_ID_RP2_232:
1914 altChanRingIndicator++;
1916 rocketModel[i].model = MODEL_RP2_232;
1917 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1918 rocketModel[i].numPorts = 2;
1920 case PCI_DEVICE_ID_RP2_422:
1923 altChanRingIndicator++;
1925 rocketModel[i].model = MODEL_RP2_422;
1926 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1927 rocketModel[i].numPorts = 2;
1929 case PCI_DEVICE_ID_RP6M:
1934 /* If revision is 1, the rocketmodem flash must be loaded.
1935 * If it is 2 it is a "socketed" version. */
1936 if (dev->revision == 1) {
1937 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1938 rocketModel[i].loadrm2 = 1;
1940 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1943 rocketModel[i].model = MODEL_RP6M;
1944 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1945 rocketModel[i].numPorts = 6;
1947 case PCI_DEVICE_ID_RP4M:
1950 if (dev->revision == 1) {
1951 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1952 rocketModel[i].loadrm2 = 1;
1954 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1957 rocketModel[i].model = MODEL_RP4M;
1958 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1959 rocketModel[i].numPorts = 4;
1967 * Check for UPCI boards.
1970 switch (dev->device) {
1971 case PCI_DEVICE_ID_URP32INTF:
1972 case PCI_DEVICE_ID_URP8INTF:
1973 case PCI_DEVICE_ID_URP16INTF:
1974 case PCI_DEVICE_ID_CRP16INTF:
1975 case PCI_DEVICE_ID_URP8OCTA:
1976 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1977 ConfigIO = pci_resource_start(dev, 1);
1978 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1979 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1982 * Check for octa or quad cable.
1985 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1986 PCI_GPIO_CTRL_8PORT)) {
1988 rocketModel[i].numPorts = 4;
1992 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1994 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
1995 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
1996 rocketModel[i].numPorts = 8;
1997 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1998 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1999 ConfigIO = pci_resource_start(dev, 1);
2000 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2002 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2004 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2005 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2006 rocketModel[i].numPorts = 4;
2007 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2008 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2009 ConfigIO = pci_resource_start(dev, 1);
2010 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2017 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2018 rp_baud_base[i] = 921600;
2021 * If support_low_speed is set, use the slow clock
2022 * prescale, which supports 50 bps
2024 if (support_low_speed) {
2025 /* mod 9 (divide by 10) prescale */
2026 sClockPrescale = 0x19;
2027 rp_baud_base[i] = 230400;
2029 /* mod 4 (divide by 5) prescale */
2030 sClockPrescale = 0x14;
2031 rp_baud_base[i] = 460800;
2035 for (aiop = 0; aiop < max_num_aiops; aiop++)
2036 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2037 ctlp = sCtlNumToCtlPtr(i);
2038 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2039 for (aiop = 0; aiop < max_num_aiops; aiop++)
2040 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2042 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2043 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2044 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2045 rocketModel[i].startingPortNumber,
2046 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2048 if (num_aiops <= 0) {
2049 rcktpt_io_addr[i] = 0;
2054 /* Reset the AIOPIC, init the serial ports */
2055 for (aiop = 0; aiop < num_aiops; aiop++) {
2056 sResetAiopByNum(ctlp, aiop);
2057 num_chan = ports_per_aiop;
2058 for (chan = 0; chan < num_chan; chan++)
2059 init_r_port(i, aiop, chan, dev);
2062 /* Rocket modems must be reset */
2063 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2064 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2065 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2066 num_chan = ports_per_aiop;
2067 for (chan = 0; chan < num_chan; chan++)
2068 sPCIModemReset(ctlp, chan, 1);
2070 for (chan = 0; chan < num_chan; chan++)
2071 sPCIModemReset(ctlp, chan, 0);
2073 rmSpeakerReset(ctlp, rocketModel[i].model);
2079 * Probes for PCI cards, inits them if found
2080 * Input: board_found = number of ISA boards already found, or the
2081 * starting board number
2082 * Returns: Number of PCI boards found
2084 static int __init init_PCI(int boards_found)
2086 struct pci_dev *dev = NULL;
2089 /* Work through the PCI device list, pulling out ours */
2090 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2091 if (register_PCI(count + boards_found, dev))
2097 #endif /* CONFIG_PCI */
2100 * Probes for ISA cards
2101 * Input: i = the board number to look for
2102 * Returns: 1 if board found, 0 else
2104 static int __init init_ISA(int i)
2106 int num_aiops, num_chan = 0, total_num_chan = 0;
2108 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2112 /* If io_addr is zero, no board configured */
2113 if (rcktpt_io_addr[i] == 0)
2116 /* Reserve the IO region */
2117 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2118 printk(KERN_ERR "Unable to reserve IO region for configured "
2119 "ISA RocketPort at address 0x%lx, board not "
2120 "installed...\n", rcktpt_io_addr[i]);
2121 rcktpt_io_addr[i] = 0;
2125 ctlp = sCtlNumToCtlPtr(i);
2127 ctlp->boardType = rcktpt_type[i];
2129 switch (rcktpt_type[i]) {
2130 case ROCKET_TYPE_PC104:
2131 type_string = "(PC104)";
2133 case ROCKET_TYPE_MODEM:
2134 type_string = "(RocketModem)";
2136 case ROCKET_TYPE_MODEMII:
2137 type_string = "(RocketModem II)";
2145 * If support_low_speed is set, use the slow clock prescale,
2146 * which supports 50 bps
2148 if (support_low_speed) {
2149 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2150 rp_baud_base[i] = 230400;
2152 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2153 rp_baud_base[i] = 460800;
2156 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2157 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2159 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2161 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2162 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2163 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2166 /* If something went wrong initing the AIOP's release the ISA IO memory */
2167 if (num_aiops <= 0) {
2168 release_region(rcktpt_io_addr[i], 64);
2169 rcktpt_io_addr[i] = 0;
2173 rocketModel[i].startingPortNumber = nextLineNumber;
2175 for (aiop = 0; aiop < num_aiops; aiop++) {
2176 sResetAiopByNum(ctlp, aiop);
2177 sEnAiop(ctlp, aiop);
2178 num_chan = sGetAiopNumChan(ctlp, aiop);
2179 total_num_chan += num_chan;
2180 for (chan = 0; chan < num_chan; chan++)
2181 init_r_port(i, aiop, chan, NULL);
2184 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2185 num_chan = sGetAiopNumChan(ctlp, 0);
2186 total_num_chan = num_chan;
2187 for (chan = 0; chan < num_chan; chan++)
2188 sModemReset(ctlp, chan, 1);
2190 for (chan = 0; chan < num_chan; chan++)
2191 sModemReset(ctlp, chan, 0);
2193 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2195 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2197 rocketModel[i].numPorts = total_num_chan;
2198 rocketModel[i].model = MODEL_ISA;
2200 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2201 i, rcktpt_io_addr[i], num_aiops, type_string);
2203 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2204 rocketModel[i].modelString,
2205 rocketModel[i].startingPortNumber,
2206 rocketModel[i].startingPortNumber +
2207 rocketModel[i].numPorts - 1);
2212 static const struct tty_operations rocket_ops = {
2216 .put_char = rp_put_char,
2217 .write_room = rp_write_room,
2218 .chars_in_buffer = rp_chars_in_buffer,
2219 .flush_buffer = rp_flush_buffer,
2221 .throttle = rp_throttle,
2222 .unthrottle = rp_unthrottle,
2223 .set_termios = rp_set_termios,
2226 .hangup = rp_hangup,
2227 .break_ctl = rp_break,
2228 .send_xchar = rp_send_xchar,
2229 .wait_until_sent = rp_wait_until_sent,
2230 .tiocmget = rp_tiocmget,
2231 .tiocmset = rp_tiocmset,
2234 static const struct tty_port_operations rocket_port_ops = {
2235 .carrier_raised = carrier_raised,
2240 * The module "startup" routine; it's run when the module is loaded.
2242 static int __init rp_init(void)
2244 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2246 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2247 ROCKET_VERSION, ROCKET_DATE);
2249 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2254 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2255 * zero, use the default controller IO address of board1 + 0x40.
2258 if (controller == 0)
2259 controller = board1 + 0x40;
2261 controller = 0; /* Used as a flag, meaning no ISA boards */
2264 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2265 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2266 printk(KERN_ERR "Unable to reserve IO region for first "
2267 "configured ISA RocketPort controller 0x%lx. "
2268 "Driver exiting\n", controller);
2273 /* Store ISA variable retrieved from command line or .conf file. */
2274 rcktpt_io_addr[0] = board1;
2275 rcktpt_io_addr[1] = board2;
2276 rcktpt_io_addr[2] = board3;
2277 rcktpt_io_addr[3] = board4;
2279 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2280 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2281 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2282 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2283 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2284 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2285 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2286 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2289 * Set up the tty driver structure and then register this
2290 * driver with the tty layer.
2293 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2294 rocket_driver->name = "ttyR";
2295 rocket_driver->driver_name = "Comtrol RocketPort";
2296 rocket_driver->major = TTY_ROCKET_MAJOR;
2297 rocket_driver->minor_start = 0;
2298 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2299 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2300 rocket_driver->init_termios = tty_std_termios;
2301 rocket_driver->init_termios.c_cflag =
2302 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2303 rocket_driver->init_termios.c_ispeed = 9600;
2304 rocket_driver->init_termios.c_ospeed = 9600;
2305 #ifdef ROCKET_SOFT_FLOW
2306 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2308 tty_set_operations(rocket_driver, &rocket_ops);
2310 ret = tty_register_driver(rocket_driver);
2312 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2313 goto err_controller;
2316 #ifdef ROCKET_DEBUG_OPEN
2317 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2321 * OK, let's probe each of the controllers looking for boards. Any boards found
2322 * will be initialized here.
2324 isa_boards_found = 0;
2325 pci_boards_found = 0;
2327 for (i = 0; i < NUM_BOARDS; i++) {
2333 if (isa_boards_found < NUM_BOARDS)
2334 pci_boards_found = init_PCI(isa_boards_found);
2337 max_board = pci_boards_found + isa_boards_found;
2339 if (max_board == 0) {
2340 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2347 tty_unregister_driver(rocket_driver);
2350 release_region(controller, 4);
2352 put_tty_driver(rocket_driver);
2358 static void rp_cleanup_module(void)
2363 del_timer_sync(&rocket_timer);
2365 retval = tty_unregister_driver(rocket_driver);
2367 printk(KERN_ERR "Error %d while trying to unregister "
2368 "rocketport driver\n", -retval);
2370 for (i = 0; i < MAX_RP_PORTS; i++)
2372 tty_unregister_device(rocket_driver, i);
2373 tty_port_destroy(&rp_table[i]->port);
2377 put_tty_driver(rocket_driver);
2379 for (i = 0; i < NUM_BOARDS; i++) {
2380 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2382 release_region(rcktpt_io_addr[i], 64);
2385 release_region(controller, 4);
2388 /***************************************************************************
2389 Function: sInitController
2390 Purpose: Initialization of controller global registers and controller
2392 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2393 IRQNum,Frequency,PeriodicOnly)
2394 CONTROLLER_T *CtlP; Ptr to controller structure
2395 int CtlNum; Controller number
2396 ByteIO_t MudbacIO; Mudbac base I/O address.
2397 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2398 This list must be in the order the AIOPs will be found on the
2399 controller. Once an AIOP in the list is not found, it is
2400 assumed that there are no more AIOPs on the controller.
2401 int AiopIOListSize; Number of addresses in AiopIOList
2402 int IRQNum; Interrupt Request number. Can be any of the following:
2403 0: Disable global interrupts
2412 Byte_t Frequency: A flag identifying the frequency
2413 of the periodic interrupt, can be any one of the following:
2414 FREQ_DIS - periodic interrupt disabled
2415 FREQ_137HZ - 137 Hertz
2416 FREQ_69HZ - 69 Hertz
2417 FREQ_34HZ - 34 Hertz
2418 FREQ_17HZ - 17 Hertz
2421 If IRQNum is set to 0 the Frequency parameter is
2422 overidden, it is forced to a value of FREQ_DIS.
2423 int PeriodicOnly: 1 if all interrupts except the periodic
2424 interrupt are to be blocked.
2425 0 is both the periodic interrupt and
2426 other channel interrupts are allowed.
2427 If IRQNum is set to 0 the PeriodicOnly parameter is
2428 overidden, it is forced to a value of 0.
2429 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2430 initialization failed.
2433 If periodic interrupts are to be disabled but AIOP interrupts
2434 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2436 If interrupts are to be completely disabled set IRQNum to 0.
2438 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2439 invalid combination.
2441 This function performs initialization of global interrupt modes,
2442 but it does not actually enable global interrupts. To enable
2443 and disable global interrupts use functions sEnGlobalInt() and
2444 sDisGlobalInt(). Enabling of global interrupts is normally not
2445 done until all other initializations are complete.
2447 Even if interrupts are globally enabled, they must also be
2448 individually enabled for each channel that is to generate
2451 Warnings: No range checking on any of the parameters is done.
2453 No context switches are allowed while executing this function.
2455 After this function all AIOPs on the controller are disabled,
2456 they can be enabled with sEnAiop().
2458 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2459 ByteIO_t * AiopIOList, int AiopIOListSize,
2460 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2466 CtlP->AiopIntrBits = aiop_intr_bits;
2467 CtlP->AltChanRingIndicator = 0;
2468 CtlP->CtlNum = CtlNum;
2469 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2470 CtlP->BusType = isISA;
2471 CtlP->MBaseIO = MudbacIO;
2472 CtlP->MReg1IO = MudbacIO + 1;
2473 CtlP->MReg2IO = MudbacIO + 2;
2474 CtlP->MReg3IO = MudbacIO + 3;
2476 CtlP->MReg2 = 0; /* interrupt disable */
2477 CtlP->MReg3 = 0; /* no periodic interrupts */
2479 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2480 CtlP->MReg2 = 0; /* interrupt disable */
2481 CtlP->MReg3 = 0; /* no periodic interrupts */
2483 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2484 CtlP->MReg3 = Frequency; /* set frequency */
2485 if (PeriodicOnly) { /* periodic interrupt only */
2486 CtlP->MReg3 |= PERIODIC_ONLY;
2490 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2491 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2492 sControllerEOI(CtlP); /* clear EOI if warm init */
2495 for (i = done = 0; i < AiopIOListSize; i++) {
2497 CtlP->AiopIO[i] = (WordIO_t) io;
2498 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2499 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2500 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2503 sEnAiop(CtlP, i); /* enable the AIOP */
2504 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2505 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2506 done = 1; /* done looking for AIOPs */
2508 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2509 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2510 sOutB(io + _INDX_DATA, sClockPrescale);
2511 CtlP->NumAiop++; /* bump count of AIOPs */
2513 sDisAiop(CtlP, i); /* disable AIOP */
2516 if (CtlP->NumAiop == 0)
2519 return (CtlP->NumAiop);
2522 /***************************************************************************
2523 Function: sPCIInitController
2524 Purpose: Initialization of controller global registers and controller
2526 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2527 IRQNum,Frequency,PeriodicOnly)
2528 CONTROLLER_T *CtlP; Ptr to controller structure
2529 int CtlNum; Controller number
2530 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2531 This list must be in the order the AIOPs will be found on the
2532 controller. Once an AIOP in the list is not found, it is
2533 assumed that there are no more AIOPs on the controller.
2534 int AiopIOListSize; Number of addresses in AiopIOList
2535 int IRQNum; Interrupt Request number. Can be any of the following:
2536 0: Disable global interrupts
2545 Byte_t Frequency: A flag identifying the frequency
2546 of the periodic interrupt, can be any one of the following:
2547 FREQ_DIS - periodic interrupt disabled
2548 FREQ_137HZ - 137 Hertz
2549 FREQ_69HZ - 69 Hertz
2550 FREQ_34HZ - 34 Hertz
2551 FREQ_17HZ - 17 Hertz
2554 If IRQNum is set to 0 the Frequency parameter is
2555 overidden, it is forced to a value of FREQ_DIS.
2556 int PeriodicOnly: 1 if all interrupts except the periodic
2557 interrupt are to be blocked.
2558 0 is both the periodic interrupt and
2559 other channel interrupts are allowed.
2560 If IRQNum is set to 0 the PeriodicOnly parameter is
2561 overidden, it is forced to a value of 0.
2562 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2563 initialization failed.
2566 If periodic interrupts are to be disabled but AIOP interrupts
2567 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2569 If interrupts are to be completely disabled set IRQNum to 0.
2571 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2572 invalid combination.
2574 This function performs initialization of global interrupt modes,
2575 but it does not actually enable global interrupts. To enable
2576 and disable global interrupts use functions sEnGlobalInt() and
2577 sDisGlobalInt(). Enabling of global interrupts is normally not
2578 done until all other initializations are complete.
2580 Even if interrupts are globally enabled, they must also be
2581 individually enabled for each channel that is to generate
2584 Warnings: No range checking on any of the parameters is done.
2586 No context switches are allowed while executing this function.
2588 After this function all AIOPs on the controller are disabled,
2589 they can be enabled with sEnAiop().
2591 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2592 ByteIO_t * AiopIOList, int AiopIOListSize,
2593 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2594 int PeriodicOnly, int altChanRingIndicator,
2600 CtlP->AltChanRingIndicator = altChanRingIndicator;
2601 CtlP->UPCIRingInd = UPCIRingInd;
2602 CtlP->CtlNum = CtlNum;
2603 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2604 CtlP->BusType = isPCI; /* controller release 1 */
2608 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2609 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2610 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2614 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2615 CtlP->AiopIntrBits = aiop_intr_bits;
2618 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2621 for (i = 0; i < AiopIOListSize; i++) {
2623 CtlP->AiopIO[i] = (WordIO_t) io;
2624 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2626 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2627 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2628 break; /* done looking for AIOPs */
2630 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2631 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2632 sOutB(io + _INDX_DATA, sClockPrescale);
2633 CtlP->NumAiop++; /* bump count of AIOPs */
2636 if (CtlP->NumAiop == 0)
2639 return (CtlP->NumAiop);
2642 /***************************************************************************
2643 Function: sReadAiopID
2644 Purpose: Read the AIOP idenfication number directly from an AIOP.
2645 Call: sReadAiopID(io)
2646 ByteIO_t io: AIOP base I/O address
2647 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2648 is replace by an identifying number.
2649 Flag AIOPID_NULL if no valid AIOP is found
2650 Warnings: No context switches are allowed while executing this function.
2653 static int sReadAiopID(ByteIO_t io)
2655 Byte_t AiopID; /* ID byte from AIOP */
2657 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2658 sOutB(io + _CMD_REG, 0x0);
2659 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2662 else /* AIOP does not exist */
2666 /***************************************************************************
2667 Function: sReadAiopNumChan
2668 Purpose: Read the number of channels available in an AIOP directly from
2670 Call: sReadAiopNumChan(io)
2671 WordIO_t io: AIOP base I/O address
2672 Return: int: The number of channels available
2673 Comments: The number of channels is determined by write/reads from identical
2674 offsets within the SRAM address spaces for channels 0 and 4.
2675 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2676 AIOP, otherwise it is an 8 channel.
2677 Warnings: No context switches are allowed while executing this function.
2679 static int sReadAiopNumChan(WordIO_t io)
2682 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2684 /* write to chan 0 SRAM */
2685 out32((DWordIO_t) io + _INDX_ADDR, R);
2686 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2687 x = sInW(io + _INDX_DATA);
2688 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2689 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2695 /***************************************************************************
2697 Purpose: Initialization of a channel and channel structure
2698 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2699 CONTROLLER_T *CtlP; Ptr to controller structure
2700 CHANNEL_T *ChP; Ptr to channel structure
2701 int AiopNum; AIOP number within controller
2702 int ChanNum; Channel number within AIOP
2703 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2704 number exceeds number of channels available in AIOP.
2705 Comments: This function must be called before a channel can be used.
2706 Warnings: No range checking on any of the parameters is done.
2708 No context switches are allowed while executing this function.
2710 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2721 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2722 return 0; /* exceeds num chans in AIOP */
2724 /* Channel, AIOP, and controller identifiers */
2726 ChP->ChanID = CtlP->AiopID[AiopNum];
2727 ChP->AiopNum = AiopNum;
2728 ChP->ChanNum = ChanNum;
2730 /* Global direct addresses */
2731 AiopIO = CtlP->AiopIO[AiopNum];
2732 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2733 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2734 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2735 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2736 ChP->IndexData = AiopIO + _INDX_DATA;
2738 /* Channel direct addresses */
2739 ChIOOff = AiopIO + ChP->ChanNum * 2;
2740 ChP->TxRxData = ChIOOff + _TD0;
2741 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2742 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2743 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2745 /* Initialize the channel from the RData array */
2746 for (i = 0; i < RDATASIZE; i += 4) {
2748 R[1] = RData[i + 1] + 0x10 * ChanNum;
2749 R[2] = RData[i + 2];
2750 R[3] = RData[i + 3];
2751 out32(ChP->IndexAddr, R);
2755 for (i = 0; i < RREGDATASIZE; i += 4) {
2756 ChR[i] = RRegData[i];
2757 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2758 ChR[i + 2] = RRegData[i + 2];
2759 ChR[i + 3] = RRegData[i + 3];
2762 /* Indexed registers */
2763 ChOff = (Word_t) ChanNum *0x1000;
2765 if (sClockPrescale == 0x14)
2770 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2771 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2772 ChP->BaudDiv[2] = (Byte_t) brd9600;
2773 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2774 out32(ChP->IndexAddr, ChP->BaudDiv);
2776 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2777 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2778 ChP->TxControl[2] = 0;
2779 ChP->TxControl[3] = 0;
2780 out32(ChP->IndexAddr, ChP->TxControl);
2782 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2783 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2784 ChP->RxControl[2] = 0;
2785 ChP->RxControl[3] = 0;
2786 out32(ChP->IndexAddr, ChP->RxControl);
2788 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2789 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2790 ChP->TxEnables[2] = 0;
2791 ChP->TxEnables[3] = 0;
2792 out32(ChP->IndexAddr, ChP->TxEnables);
2794 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2795 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2796 ChP->TxCompare[2] = 0;
2797 ChP->TxCompare[3] = 0;
2798 out32(ChP->IndexAddr, ChP->TxCompare);
2800 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2801 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2802 ChP->TxReplace1[2] = 0;
2803 ChP->TxReplace1[3] = 0;
2804 out32(ChP->IndexAddr, ChP->TxReplace1);
2806 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2807 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2808 ChP->TxReplace2[2] = 0;
2809 ChP->TxReplace2[3] = 0;
2810 out32(ChP->IndexAddr, ChP->TxReplace2);
2812 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2813 ChP->TxFIFO = ChOff + _TX_FIFO;
2815 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2816 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2817 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2818 sOutW(ChP->IndexData, 0);
2819 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2820 ChP->RxFIFO = ChOff + _RX_FIFO;
2822 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2823 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2824 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2825 sOutW(ChP->IndexData, 0);
2826 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2827 sOutW(ChP->IndexData, 0);
2828 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2829 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2830 sOutB(ChP->IndexData, 0);
2831 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2832 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2833 sOutB(ChP->IndexData, 0);
2834 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2835 sEnRxProcessor(ChP); /* start the Rx processor */
2840 /***************************************************************************
2841 Function: sStopRxProcessor
2842 Purpose: Stop the receive processor from processing a channel.
2843 Call: sStopRxProcessor(ChP)
2844 CHANNEL_T *ChP; Ptr to channel structure
2846 Comments: The receive processor can be started again with sStartRxProcessor().
2847 This function causes the receive processor to skip over the
2848 stopped channel. It does not stop it from processing other channels.
2850 Warnings: No context switches are allowed while executing this function.
2852 Do not leave the receive processor stopped for more than one
2855 After calling this function a delay of 4 uS is required to ensure
2856 that the receive processor is no longer processing this channel.
2858 static void sStopRxProcessor(CHANNEL_T * ChP)
2866 out32(ChP->IndexAddr, R);
2869 /***************************************************************************
2870 Function: sFlushRxFIFO
2871 Purpose: Flush the Rx FIFO
2872 Call: sFlushRxFIFO(ChP)
2873 CHANNEL_T *ChP; Ptr to channel structure
2875 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2876 while it is being flushed the receive processor is stopped
2877 and the transmitter is disabled. After these operations a
2878 4 uS delay is done before clearing the pointers to allow
2879 the receive processor to stop. These items are handled inside
2881 Warnings: No context switches are allowed while executing this function.
2883 static void sFlushRxFIFO(CHANNEL_T * ChP)
2886 Byte_t Ch; /* channel number within AIOP */
2887 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2889 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2890 return; /* don't need to flush */
2893 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2895 sDisRxFIFO(ChP); /* disable it */
2896 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2897 sInB(ChP->IntChan); /* depends on bus i/o timing */
2899 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2900 Ch = (Byte_t) sGetChanNum(ChP);
2901 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2902 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2903 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2904 sOutW(ChP->IndexData, 0);
2905 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2906 sOutW(ChP->IndexData, 0);
2908 sEnRxFIFO(ChP); /* enable Rx FIFO */
2911 /***************************************************************************
2912 Function: sFlushTxFIFO
2913 Purpose: Flush the Tx FIFO
2914 Call: sFlushTxFIFO(ChP)
2915 CHANNEL_T *ChP; Ptr to channel structure
2917 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2918 while it is being flushed the receive processor is stopped
2919 and the transmitter is disabled. After these operations a
2920 4 uS delay is done before clearing the pointers to allow
2921 the receive processor to stop. These items are handled inside
2923 Warnings: No context switches are allowed while executing this function.
2925 static void sFlushTxFIFO(CHANNEL_T * ChP)
2928 Byte_t Ch; /* channel number within AIOP */
2929 int TxEnabled; /* 1 if transmitter enabled */
2931 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2932 return; /* don't need to flush */
2935 if (ChP->TxControl[3] & TX_ENABLE) {
2937 sDisTransmit(ChP); /* disable transmitter */
2939 sStopRxProcessor(ChP); /* stop Rx processor */
2940 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2941 sInB(ChP->IntChan); /* depends on bus i/o timing */
2942 Ch = (Byte_t) sGetChanNum(ChP);
2943 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2944 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2945 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2946 sOutW(ChP->IndexData, 0);
2948 sEnTransmit(ChP); /* enable transmitter */
2949 sStartRxProcessor(ChP); /* restart Rx processor */
2952 /***************************************************************************
2953 Function: sWriteTxPrioByte
2954 Purpose: Write a byte of priority transmit data to a channel
2955 Call: sWriteTxPrioByte(ChP,Data)
2956 CHANNEL_T *ChP; Ptr to channel structure
2957 Byte_t Data; The transmit data byte
2959 Return: int: 1 if the bytes is successfully written, otherwise 0.
2961 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2963 Warnings: No context switches are allowed while executing this function.
2965 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2967 Byte_t DWBuf[4]; /* buffer for double word writes */
2968 Word_t *WordPtr; /* must be far because Win SS != DS */
2969 register DWordIO_t IndexAddr;
2971 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2972 IndexAddr = ChP->IndexAddr;
2973 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2974 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2975 return (0); /* nothing sent */
2977 WordPtr = (Word_t *) (&DWBuf[0]);
2978 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2980 DWBuf[2] = Data; /* data byte value */
2981 out32(IndexAddr, DWBuf); /* write it out */
2983 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2985 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2986 DWBuf[3] = 0; /* priority buffer pointer */
2987 out32(IndexAddr, DWBuf); /* write it out */
2988 } else { /* write it to Tx FIFO */
2990 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2992 return (1); /* 1 byte sent */
2995 /***************************************************************************
2996 Function: sEnInterrupts
2997 Purpose: Enable one or more interrupts for a channel
2998 Call: sEnInterrupts(ChP,Flags)
2999 CHANNEL_T *ChP; Ptr to channel structure
3000 Word_t Flags: Interrupt enable flags, can be any combination
3001 of the following flags:
3002 TXINT_EN: Interrupt on Tx FIFO empty
3003 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3005 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3006 MCINT_EN: Interrupt on modem input change
3007 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3008 Interrupt Channel Register.
3010 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3011 enabled. If an interrupt enable flag is not set in Flags, that
3012 interrupt will not be changed. Interrupts can be disabled with
3013 function sDisInterrupts().
3015 This function sets the appropriate bit for the channel in the AIOP's
3016 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3017 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3019 Interrupts must also be globally enabled before channel interrupts
3020 will be passed on to the host. This is done with function
3023 In some cases it may be desirable to disable interrupts globally but
3024 enable channel interrupts. This would allow the global interrupt
3025 status register to be used to determine which AIOPs need service.
3027 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3029 Byte_t Mask; /* Interrupt Mask Register */
3031 ChP->RxControl[2] |=
3032 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3034 out32(ChP->IndexAddr, ChP->RxControl);
3036 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3038 out32(ChP->IndexAddr, ChP->TxControl);
3040 if (Flags & CHANINT_EN) {
3041 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3042 sOutB(ChP->IntMask, Mask);
3046 /***************************************************************************
3047 Function: sDisInterrupts
3048 Purpose: Disable one or more interrupts for a channel
3049 Call: sDisInterrupts(ChP,Flags)
3050 CHANNEL_T *ChP; Ptr to channel structure
3051 Word_t Flags: Interrupt flags, can be any combination
3052 of the following flags:
3053 TXINT_EN: Interrupt on Tx FIFO empty
3054 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3056 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3057 MCINT_EN: Interrupt on modem input change
3058 CHANINT_EN: Disable channel interrupt signal to the
3059 AIOP's Interrupt Channel Register.
3061 Comments: If an interrupt flag is set in Flags, that interrupt will be
3062 disabled. If an interrupt flag is not set in Flags, that
3063 interrupt will not be changed. Interrupts can be enabled with
3064 function sEnInterrupts().
3066 This function clears the appropriate bit for the channel in the AIOP's
3067 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3068 this channel's bit from being set in the AIOP's Interrupt Channel
3071 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3073 Byte_t Mask; /* Interrupt Mask Register */
3075 ChP->RxControl[2] &=
3076 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3077 out32(ChP->IndexAddr, ChP->RxControl);
3078 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3079 out32(ChP->IndexAddr, ChP->TxControl);
3081 if (Flags & CHANINT_EN) {
3082 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3083 sOutB(ChP->IntMask, Mask);
3087 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3089 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3093 * Not an official SSCI function, but how to reset RocketModems.
3096 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3101 addr = CtlP->AiopIO[0] + 0x400;
3102 val = sInB(CtlP->MReg3IO);
3103 /* if AIOP[1] is not enabled, enable it */
3104 if ((val & 2) == 0) {
3105 val = sInB(CtlP->MReg2IO);
3106 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3107 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3113 sOutB(addr + chan, 0); /* apply or remove reset */
3118 * Not an official SSCI function, but how to reset RocketModems.
3121 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3125 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3128 sOutB(addr + chan, 0); /* apply or remove reset */
3131 /* Resets the speaker controller on RocketModem II and III devices */
3132 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3136 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3137 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3138 addr = CtlP->AiopIO[0] + 0x4F;
3142 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3143 if ((model == MODEL_UPCI_RM3_8PORT)
3144 || (model == MODEL_UPCI_RM3_4PORT)) {
3145 addr = CtlP->AiopIO[0] + 0x88;
3150 /* Returns the line number given the controller (board), aiop and channel number */
3151 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3153 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3157 * Stores the line number associated with a given controller (board), aiop
3158 * and channel number.
3159 * Returns: The line number assigned
3161 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3163 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3164 return (nextLineNumber - 1);