2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
42 #include <linux/sunserialcore.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 static struct uart_driver serial8250_reg;
61 static int serial_index(struct uart_port *port)
63 return (serial8250_reg.minor - 64) + port->line;
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
78 #define DEBUG_INTR(fmt...) printk(fmt)
80 #define DEBUG_INTR(fmt...) do { } while (0)
83 #define PASS_LIMIT 512
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
101 #include <asm/serial.h>
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
117 #ifdef CONFIG_SERIAL_8250_RSA
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
125 struct hlist_node node;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
136 * Here we define the default xmit fifo size used for each type of UART.
138 static const struct serial8250_config uart_config[] = {
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
199 .name = "16C950/954",
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
287 #if defined(CONFIG_MIPS_ALCHEMY)
289 /* Au1x00 UART hardware has a weird register layout */
290 static const u8 au_io_in_map[] = {
300 static const u8 au_io_out_map[] = {
308 /* sane hardware needs no mapping */
309 static inline int map_8250_in_reg(struct uart_port *p, int offset)
311 if (p->iotype != UPIO_AU)
313 return au_io_in_map[offset];
316 static inline int map_8250_out_reg(struct uart_port *p, int offset)
318 if (p->iotype != UPIO_AU)
320 return au_io_out_map[offset];
323 #elif defined(CONFIG_SERIAL_8250_RM9K)
347 static inline int map_8250_in_reg(struct uart_port *p, int offset)
349 if (p->iotype != UPIO_RM9000)
351 return regmap_in[offset];
354 static inline int map_8250_out_reg(struct uart_port *p, int offset)
356 if (p->iotype != UPIO_RM9000)
358 return regmap_out[offset];
363 /* sane hardware needs no mapping */
364 #define map_8250_in_reg(up, offset) (offset)
365 #define map_8250_out_reg(up, offset) (offset)
369 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
371 offset = map_8250_in_reg(p, offset) << p->regshift;
372 outb(p->hub6 - 1 + offset, p->iobase);
373 return inb(p->iobase + 1);
376 static void hub6_serial_out(struct uart_port *p, int offset, int value)
378 offset = map_8250_out_reg(p, offset) << p->regshift;
379 outb(p->hub6 - 1 + offset, p->iobase);
380 outb(value, p->iobase + 1);
383 static unsigned int mem_serial_in(struct uart_port *p, int offset)
385 offset = map_8250_in_reg(p, offset) << p->regshift;
386 return readb(p->membase + offset);
389 static void mem_serial_out(struct uart_port *p, int offset, int value)
391 offset = map_8250_out_reg(p, offset) << p->regshift;
392 writeb(value, p->membase + offset);
395 static void mem32_serial_out(struct uart_port *p, int offset, int value)
397 offset = map_8250_out_reg(p, offset) << p->regshift;
398 writel(value, p->membase + offset);
401 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
403 offset = map_8250_in_reg(p, offset) << p->regshift;
404 return readl(p->membase + offset);
407 static unsigned int au_serial_in(struct uart_port *p, int offset)
409 offset = map_8250_in_reg(p, offset) << p->regshift;
410 return __raw_readl(p->membase + offset);
413 static void au_serial_out(struct uart_port *p, int offset, int value)
415 offset = map_8250_out_reg(p, offset) << p->regshift;
416 __raw_writel(value, p->membase + offset);
419 static unsigned int io_serial_in(struct uart_port *p, int offset)
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return inb(p->iobase + offset);
425 static void io_serial_out(struct uart_port *p, int offset, int value)
427 offset = map_8250_out_reg(p, offset) << p->regshift;
428 outb(value, p->iobase + offset);
431 static int serial8250_default_handle_irq(struct uart_port *port);
433 static void set_io_from_upio(struct uart_port *p)
435 struct uart_8250_port *up =
436 container_of(p, struct uart_8250_port, port);
439 p->serial_in = hub6_serial_in;
440 p->serial_out = hub6_serial_out;
444 p->serial_in = mem_serial_in;
445 p->serial_out = mem_serial_out;
450 p->serial_in = mem32_serial_in;
451 p->serial_out = mem32_serial_out;
455 p->serial_in = au_serial_in;
456 p->serial_out = au_serial_out;
460 p->serial_in = io_serial_in;
461 p->serial_out = io_serial_out;
464 /* Remember loaded iotype */
465 up->cur_iotype = p->iotype;
466 p->handle_irq = serial8250_default_handle_irq;
470 serial_port_out_sync(struct uart_port *p, int offset, int value)
476 p->serial_out(p, offset, value);
477 p->serial_in(p, UART_LCR); /* safe, no side-effects */
480 p->serial_out(p, offset, value);
484 /* Uart divisor latch read */
485 static inline int _serial_dl_read(struct uart_8250_port *up)
487 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
490 /* Uart divisor latch write */
491 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
493 serial_out(up, UART_DLL, value & 0xff);
494 serial_out(up, UART_DLM, value >> 8 & 0xff);
497 #if defined(CONFIG_MIPS_ALCHEMY)
498 /* Au1x00 haven't got a standard divisor latch */
499 static int serial_dl_read(struct uart_8250_port *up)
501 if (up->port.iotype == UPIO_AU)
502 return __raw_readl(up->port.membase + 0x28);
504 return _serial_dl_read(up);
507 static void serial_dl_write(struct uart_8250_port *up, int value)
509 if (up->port.iotype == UPIO_AU)
510 __raw_writel(value, up->port.membase + 0x28);
512 _serial_dl_write(up, value);
514 #elif defined(CONFIG_SERIAL_8250_RM9K)
515 static int serial_dl_read(struct uart_8250_port *up)
517 return (up->port.iotype == UPIO_RM9000) ?
518 (((__raw_readl(up->port.membase + 0x10) << 8) |
519 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
523 static void serial_dl_write(struct uart_8250_port *up, int value)
525 if (up->port.iotype == UPIO_RM9000) {
526 __raw_writel(value, up->port.membase + 0x08);
527 __raw_writel(value >> 8, up->port.membase + 0x10);
529 _serial_dl_write(up, value);
533 #define serial_dl_read(up) _serial_dl_read(up)
534 #define serial_dl_write(up, value) _serial_dl_write(up, value)
540 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
542 serial_out(up, UART_SCR, offset);
543 serial_out(up, UART_ICR, value);
546 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
550 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
551 serial_out(up, UART_SCR, offset);
552 value = serial_in(up, UART_ICR);
553 serial_icr_write(up, UART_ACR, up->acr);
561 static void serial8250_clear_fifos(struct uart_8250_port *p)
563 if (p->capabilities & UART_CAP_FIFO) {
564 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
565 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
566 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
567 serial_out(p, UART_FCR, 0);
572 * IER sleep support. UARTs which have EFRs need the "extended
573 * capability" bit enabled. Note that on XR16C850s, we need to
574 * reset LCR to write to IER.
576 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
578 if (p->capabilities & UART_CAP_SLEEP) {
579 if (p->capabilities & UART_CAP_EFR) {
580 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
581 serial_out(p, UART_EFR, UART_EFR_ECB);
582 serial_out(p, UART_LCR, 0);
584 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
585 if (p->capabilities & UART_CAP_EFR) {
586 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
587 serial_out(p, UART_EFR, 0);
588 serial_out(p, UART_LCR, 0);
593 #ifdef CONFIG_SERIAL_8250_RSA
595 * Attempts to turn on the RSA FIFO. Returns zero on failure.
596 * We set the port uart clock rate if we succeed.
598 static int __enable_rsa(struct uart_8250_port *up)
603 mode = serial_in(up, UART_RSA_MSR);
604 result = mode & UART_RSA_MSR_FIFO;
607 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
608 mode = serial_in(up, UART_RSA_MSR);
609 result = mode & UART_RSA_MSR_FIFO;
613 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
618 static void enable_rsa(struct uart_8250_port *up)
620 if (up->port.type == PORT_RSA) {
621 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
622 spin_lock_irq(&up->port.lock);
624 spin_unlock_irq(&up->port.lock);
626 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
627 serial_out(up, UART_RSA_FRR, 0);
632 * Attempts to turn off the RSA FIFO. Returns zero on failure.
633 * It is unknown why interrupts were disabled in here. However,
634 * the caller is expected to preserve this behaviour by grabbing
635 * the spinlock before calling this function.
637 static void disable_rsa(struct uart_8250_port *up)
642 if (up->port.type == PORT_RSA &&
643 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
646 mode = serial_in(up, UART_RSA_MSR);
647 result = !(mode & UART_RSA_MSR_FIFO);
650 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
651 mode = serial_in(up, UART_RSA_MSR);
652 result = !(mode & UART_RSA_MSR_FIFO);
656 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
657 spin_unlock_irq(&up->port.lock);
660 #endif /* CONFIG_SERIAL_8250_RSA */
663 * This is a quickie test to see how big the FIFO is.
664 * It doesn't work at all the time, more's the pity.
666 static int size_fifo(struct uart_8250_port *up)
668 unsigned char old_fcr, old_mcr, old_lcr;
669 unsigned short old_dl;
672 old_lcr = serial_in(up, UART_LCR);
673 serial_out(up, UART_LCR, 0);
674 old_fcr = serial_in(up, UART_FCR);
675 old_mcr = serial_in(up, UART_MCR);
676 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
677 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
678 serial_out(up, UART_MCR, UART_MCR_LOOP);
679 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
680 old_dl = serial_dl_read(up);
681 serial_dl_write(up, 0x0001);
682 serial_out(up, UART_LCR, 0x03);
683 for (count = 0; count < 256; count++)
684 serial_out(up, UART_TX, count);
685 mdelay(20);/* FIXME - schedule_timeout */
686 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
687 (count < 256); count++)
688 serial_in(up, UART_RX);
689 serial_out(up, UART_FCR, old_fcr);
690 serial_out(up, UART_MCR, old_mcr);
691 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
692 serial_dl_write(up, old_dl);
693 serial_out(up, UART_LCR, old_lcr);
699 * Read UART ID using the divisor method - set DLL and DLM to zero
700 * and the revision will be in DLL and device type in DLM. We
701 * preserve the device state across this.
703 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
705 unsigned char old_dll, old_dlm, old_lcr;
708 old_lcr = serial_in(p, UART_LCR);
709 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
711 old_dll = serial_in(p, UART_DLL);
712 old_dlm = serial_in(p, UART_DLM);
714 serial_out(p, UART_DLL, 0);
715 serial_out(p, UART_DLM, 0);
717 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
719 serial_out(p, UART_DLL, old_dll);
720 serial_out(p, UART_DLM, old_dlm);
721 serial_out(p, UART_LCR, old_lcr);
727 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
728 * When this function is called we know it is at least a StarTech
729 * 16650 V2, but it might be one of several StarTech UARTs, or one of
730 * its clones. (We treat the broken original StarTech 16650 V1 as a
731 * 16550, and why not? Startech doesn't seem to even acknowledge its
734 * What evil have men's minds wrought...
736 static void autoconfig_has_efr(struct uart_8250_port *up)
738 unsigned int id1, id2, id3, rev;
741 * Everything with an EFR has SLEEP
743 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
746 * First we check to see if it's an Oxford Semiconductor UART.
748 * If we have to do this here because some non-National
749 * Semiconductor clone chips lock up if you try writing to the
750 * LSR register (which serial_icr_read does)
754 * Check for Oxford Semiconductor 16C950.
756 * EFR [4] must be set else this test fails.
758 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
759 * claims that it's needed for 952 dual UART's (which are not
760 * recommended for new designs).
763 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
764 serial_out(up, UART_EFR, UART_EFR_ECB);
765 serial_out(up, UART_LCR, 0x00);
766 id1 = serial_icr_read(up, UART_ID1);
767 id2 = serial_icr_read(up, UART_ID2);
768 id3 = serial_icr_read(up, UART_ID3);
769 rev = serial_icr_read(up, UART_REV);
771 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
773 if (id1 == 0x16 && id2 == 0xC9 &&
774 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
775 up->port.type = PORT_16C950;
778 * Enable work around for the Oxford Semiconductor 952 rev B
779 * chip which causes it to seriously miscalculate baud rates
782 if (id3 == 0x52 && rev == 0x01)
783 up->bugs |= UART_BUG_QUOT;
788 * We check for a XR16C850 by setting DLL and DLM to 0, and then
789 * reading back DLL and DLM. The chip type depends on the DLM
791 * 0x10 - XR16C850 and the DLL contains the chip revision.
795 id1 = autoconfig_read_divisor_id(up);
796 DEBUG_AUTOCONF("850id=%04x ", id1);
799 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
800 up->port.type = PORT_16850;
805 * It wasn't an XR16C850.
807 * We distinguish between the '654 and the '650 by counting
808 * how many bytes are in the FIFO. I'm using this for now,
809 * since that's the technique that was sent to me in the
810 * serial driver update, but I'm not convinced this works.
811 * I've had problems doing this in the past. -TYT
813 if (size_fifo(up) == 64)
814 up->port.type = PORT_16654;
816 up->port.type = PORT_16650V2;
820 * We detected a chip without a FIFO. Only two fall into
821 * this category - the original 8250 and the 16450. The
822 * 16450 has a scratch register (accessible with LCR=0)
824 static void autoconfig_8250(struct uart_8250_port *up)
826 unsigned char scratch, status1, status2;
828 up->port.type = PORT_8250;
830 scratch = serial_in(up, UART_SCR);
831 serial_out(up, UART_SCR, 0xa5);
832 status1 = serial_in(up, UART_SCR);
833 serial_out(up, UART_SCR, 0x5a);
834 status2 = serial_in(up, UART_SCR);
835 serial_out(up, UART_SCR, scratch);
837 if (status1 == 0xa5 && status2 == 0x5a)
838 up->port.type = PORT_16450;
841 static int broken_efr(struct uart_8250_port *up)
844 * Exar ST16C2550 "A2" devices incorrectly detect as
845 * having an EFR, and report an ID of 0x0201. See
846 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
848 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
854 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
856 unsigned char status;
858 status = serial_in(up, 0x04); /* EXCR2 */
859 #define PRESL(x) ((x) & 0x30)
860 if (PRESL(status) == 0x10) {
861 /* already in high speed mode */
864 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
865 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
866 serial_out(up, 0x04, status);
872 * We know that the chip has FIFOs. Does it have an EFR? The
873 * EFR is located in the same register position as the IIR and
874 * we know the top two bits of the IIR are currently set. The
875 * EFR should contain zero. Try to read the EFR.
877 static void autoconfig_16550a(struct uart_8250_port *up)
879 unsigned char status1, status2;
880 unsigned int iersave;
882 up->port.type = PORT_16550A;
883 up->capabilities |= UART_CAP_FIFO;
886 * Check for presence of the EFR when DLAB is set.
887 * Only ST16C650V1 UARTs pass this test.
889 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
890 if (serial_in(up, UART_EFR) == 0) {
891 serial_out(up, UART_EFR, 0xA8);
892 if (serial_in(up, UART_EFR) != 0) {
893 DEBUG_AUTOCONF("EFRv1 ");
894 up->port.type = PORT_16650;
895 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
897 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
899 serial_out(up, UART_EFR, 0);
904 * Maybe it requires 0xbf to be written to the LCR.
905 * (other ST16C650V2 UARTs, TI16C752A, etc)
907 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
908 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
909 DEBUG_AUTOCONF("EFRv2 ");
910 autoconfig_has_efr(up);
915 * Check for a National Semiconductor SuperIO chip.
916 * Attempt to switch to bank 2, read the value of the LOOP bit
917 * from EXCR1. Switch back to bank 0, change it in MCR. Then
918 * switch back to bank 2, read it from EXCR1 again and check
919 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
921 serial_out(up, UART_LCR, 0);
922 status1 = serial_in(up, UART_MCR);
923 serial_out(up, UART_LCR, 0xE0);
924 status2 = serial_in(up, 0x02); /* EXCR1 */
926 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
927 serial_out(up, UART_LCR, 0);
928 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
929 serial_out(up, UART_LCR, 0xE0);
930 status2 = serial_in(up, 0x02); /* EXCR1 */
931 serial_out(up, UART_LCR, 0);
932 serial_out(up, UART_MCR, status1);
934 if ((status2 ^ status1) & UART_MCR_LOOP) {
937 serial_out(up, UART_LCR, 0xE0);
939 quot = serial_dl_read(up);
942 if (ns16550a_goto_highspeed(up))
943 serial_dl_write(up, quot);
945 serial_out(up, UART_LCR, 0);
947 up->port.uartclk = 921600*16;
948 up->port.type = PORT_NS16550A;
949 up->capabilities |= UART_NATSEMI;
955 * No EFR. Try to detect a TI16750, which only sets bit 5 of
956 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
957 * Try setting it with and without DLAB set. Cheap clones
958 * set bit 5 without DLAB set.
960 serial_out(up, UART_LCR, 0);
961 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
962 status1 = serial_in(up, UART_IIR) >> 5;
963 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
964 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
965 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
966 status2 = serial_in(up, UART_IIR) >> 5;
967 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
968 serial_out(up, UART_LCR, 0);
970 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
972 if (status1 == 6 && status2 == 7) {
973 up->port.type = PORT_16750;
974 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
979 * Try writing and reading the UART_IER_UUE bit (b6).
980 * If it works, this is probably one of the Xscale platform's
982 * We're going to explicitly set the UUE bit to 0 before
983 * trying to write and read a 1 just to make sure it's not
984 * already a 1 and maybe locked there before we even start start.
986 iersave = serial_in(up, UART_IER);
987 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
988 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
990 * OK it's in a known zero state, try writing and reading
991 * without disturbing the current state of the other bits.
993 serial_out(up, UART_IER, iersave | UART_IER_UUE);
994 if (serial_in(up, UART_IER) & UART_IER_UUE) {
997 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
999 DEBUG_AUTOCONF("Xscale ");
1000 up->port.type = PORT_XSCALE;
1001 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1006 * If we got here we couldn't force the IER_UUE bit to 0.
1007 * Log it and continue.
1009 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1011 serial_out(up, UART_IER, iersave);
1014 * Exar uarts have EFR in a weird location
1016 if (up->port.flags & UPF_EXAR_EFR) {
1017 up->port.type = PORT_XR17D15X;
1018 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1022 * We distinguish between 16550A and U6 16550A by counting
1023 * how many bytes are in the FIFO.
1025 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1026 up->port.type = PORT_U6_16550A;
1027 up->capabilities |= UART_CAP_AFE;
1032 * This routine is called by rs_init() to initialize a specific serial
1033 * port. It determines what type of UART chip this serial port is
1034 * using: 8250, 16450, 16550, 16550A. The important question is
1035 * whether or not this UART is a 16550A or not, since this will
1036 * determine whether or not we can use its FIFO features or not.
1038 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1040 unsigned char status1, scratch, scratch2, scratch3;
1041 unsigned char save_lcr, save_mcr;
1042 struct uart_port *port = &up->port;
1043 unsigned long flags;
1045 if (!port->iobase && !port->mapbase && !port->membase)
1048 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1049 serial_index(port), port->iobase, port->membase);
1052 * We really do need global IRQs disabled here - we're going to
1053 * be frobbing the chips IRQ enable register to see if it exists.
1055 spin_lock_irqsave(&port->lock, flags);
1057 up->capabilities = 0;
1060 if (!(port->flags & UPF_BUGGY_UART)) {
1062 * Do a simple existence test first; if we fail this,
1063 * there's no point trying anything else.
1065 * 0x80 is used as a nonsense port to prevent against
1066 * false positives due to ISA bus float. The
1067 * assumption is that 0x80 is a non-existent port;
1068 * which should be safe since include/asm/io.h also
1069 * makes this assumption.
1071 * Note: this is safe as long as MCR bit 4 is clear
1072 * and the device is in "PC" mode.
1074 scratch = serial_in(up, UART_IER);
1075 serial_out(up, UART_IER, 0);
1080 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1081 * 16C754B) allow only to modify them if an EFR bit is set.
1083 scratch2 = serial_in(up, UART_IER) & 0x0f;
1084 serial_out(up, UART_IER, 0x0F);
1088 scratch3 = serial_in(up, UART_IER) & 0x0f;
1089 serial_out(up, UART_IER, scratch);
1090 if (scratch2 != 0 || scratch3 != 0x0F) {
1092 * We failed; there's nothing here
1094 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1095 scratch2, scratch3);
1100 save_mcr = serial_in(up, UART_MCR);
1101 save_lcr = serial_in(up, UART_LCR);
1104 * Check to see if a UART is really there. Certain broken
1105 * internal modems based on the Rockwell chipset fail this
1106 * test, because they apparently don't implement the loopback
1107 * test mode. So this test is skipped on the COM 1 through
1108 * COM 4 ports. This *should* be safe, since no board
1109 * manufacturer would be stupid enough to design a board
1110 * that conflicts with COM 1-4 --- we hope!
1112 if (!(port->flags & UPF_SKIP_TEST)) {
1113 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1114 status1 = serial_in(up, UART_MSR) & 0xF0;
1115 serial_out(up, UART_MCR, save_mcr);
1116 if (status1 != 0x90) {
1117 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1124 * We're pretty sure there's a port here. Lets find out what
1125 * type of port it is. The IIR top two bits allows us to find
1126 * out if it's 8250 or 16450, 16550, 16550A or later. This
1127 * determines what we test for next.
1129 * We also initialise the EFR (if any) to zero for later. The
1130 * EFR occupies the same register location as the FCR and IIR.
1132 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1133 serial_out(up, UART_EFR, 0);
1134 serial_out(up, UART_LCR, 0);
1136 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1137 scratch = serial_in(up, UART_IIR) >> 6;
1139 DEBUG_AUTOCONF("iir=%d ", scratch);
1143 autoconfig_8250(up);
1146 port->type = PORT_UNKNOWN;
1149 port->type = PORT_16550;
1152 autoconfig_16550a(up);
1156 #ifdef CONFIG_SERIAL_8250_RSA
1158 * Only probe for RSA ports if we got the region.
1160 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1163 for (i = 0 ; i < probe_rsa_count; ++i) {
1164 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1165 port->type = PORT_RSA;
1172 serial_out(up, UART_LCR, save_lcr);
1174 if (up->capabilities != uart_config[port->type].flags) {
1176 "ttyS%d: detected caps %08x should be %08x\n",
1177 serial_index(port), up->capabilities,
1178 uart_config[port->type].flags);
1181 port->fifosize = uart_config[up->port.type].fifo_size;
1182 up->capabilities = uart_config[port->type].flags;
1183 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1185 if (port->type == PORT_UNKNOWN)
1191 #ifdef CONFIG_SERIAL_8250_RSA
1192 if (port->type == PORT_RSA)
1193 serial_out(up, UART_RSA_FRR, 0);
1195 serial_out(up, UART_MCR, save_mcr);
1196 serial8250_clear_fifos(up);
1197 serial_in(up, UART_RX);
1198 if (up->capabilities & UART_CAP_UUE)
1199 serial_out(up, UART_IER, UART_IER_UUE);
1201 serial_out(up, UART_IER, 0);
1204 spin_unlock_irqrestore(&port->lock, flags);
1205 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1208 static void autoconfig_irq(struct uart_8250_port *up)
1210 struct uart_port *port = &up->port;
1211 unsigned char save_mcr, save_ier;
1212 unsigned char save_ICP = 0;
1213 unsigned int ICP = 0;
1217 if (port->flags & UPF_FOURPORT) {
1218 ICP = (port->iobase & 0xfe0) | 0x1f;
1219 save_ICP = inb_p(ICP);
1224 /* forget possible initially masked and pending IRQ */
1225 probe_irq_off(probe_irq_on());
1226 save_mcr = serial_in(up, UART_MCR);
1227 save_ier = serial_in(up, UART_IER);
1228 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1230 irqs = probe_irq_on();
1231 serial_out(up, UART_MCR, 0);
1233 if (port->flags & UPF_FOURPORT) {
1234 serial_out(up, UART_MCR,
1235 UART_MCR_DTR | UART_MCR_RTS);
1237 serial_out(up, UART_MCR,
1238 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1240 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1241 serial_in(up, UART_LSR);
1242 serial_in(up, UART_RX);
1243 serial_in(up, UART_IIR);
1244 serial_in(up, UART_MSR);
1245 serial_out(up, UART_TX, 0xFF);
1247 irq = probe_irq_off(irqs);
1249 serial_out(up, UART_MCR, save_mcr);
1250 serial_out(up, UART_IER, save_ier);
1252 if (port->flags & UPF_FOURPORT)
1253 outb_p(save_ICP, ICP);
1255 port->irq = (irq > 0) ? irq : 0;
1258 static inline void __stop_tx(struct uart_8250_port *p)
1260 if (p->ier & UART_IER_THRI) {
1261 p->ier &= ~UART_IER_THRI;
1262 serial_out(p, UART_IER, p->ier);
1266 static void serial8250_stop_tx(struct uart_port *port)
1268 struct uart_8250_port *up =
1269 container_of(port, struct uart_8250_port, port);
1274 * We really want to stop the transmitter from sending.
1276 if (port->type == PORT_16C950) {
1277 up->acr |= UART_ACR_TXDIS;
1278 serial_icr_write(up, UART_ACR, up->acr);
1282 static void serial8250_start_tx(struct uart_port *port)
1284 struct uart_8250_port *up =
1285 container_of(port, struct uart_8250_port, port);
1287 if (!(up->ier & UART_IER_THRI)) {
1288 up->ier |= UART_IER_THRI;
1289 serial_port_out(port, UART_IER, up->ier);
1291 if (up->bugs & UART_BUG_TXEN) {
1293 lsr = serial_in(up, UART_LSR);
1294 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1295 if ((port->type == PORT_RM9000) ?
1296 (lsr & UART_LSR_THRE) :
1297 (lsr & UART_LSR_TEMT))
1298 serial8250_tx_chars(up);
1303 * Re-enable the transmitter if we disabled it.
1305 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1306 up->acr &= ~UART_ACR_TXDIS;
1307 serial_icr_write(up, UART_ACR, up->acr);
1311 static void serial8250_stop_rx(struct uart_port *port)
1313 struct uart_8250_port *up =
1314 container_of(port, struct uart_8250_port, port);
1316 up->ier &= ~UART_IER_RLSI;
1317 up->port.read_status_mask &= ~UART_LSR_DR;
1318 serial_port_out(port, UART_IER, up->ier);
1321 static void serial8250_enable_ms(struct uart_port *port)
1323 struct uart_8250_port *up =
1324 container_of(port, struct uart_8250_port, port);
1326 /* no MSR capabilities */
1327 if (up->bugs & UART_BUG_NOMSR)
1330 up->ier |= UART_IER_MSI;
1331 serial_port_out(port, UART_IER, up->ier);
1335 * Clear the Tegra rx fifo after a break
1337 * FIXME: This needs to become a port specific callback once we have a
1338 * framework for this
1340 static void clear_rx_fifo(struct uart_8250_port *up)
1342 unsigned int status, tmout = 10000;
1344 status = serial_in(up, UART_LSR);
1345 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1346 status = serial_in(up, UART_RX);
1356 * serial8250_rx_chars: processes according to the passed in LSR
1357 * value, and returns the remaining LSR bits not handled
1358 * by this Rx routine.
1361 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1363 struct uart_port *port = &up->port;
1364 struct tty_struct *tty = port->state->port.tty;
1366 int max_count = 256;
1370 if (likely(lsr & UART_LSR_DR))
1371 ch = serial_in(up, UART_RX);
1374 * Intel 82571 has a Serial Over Lan device that will
1375 * set UART_LSR_BI without setting UART_LSR_DR when
1376 * it receives a break. To avoid reading from the
1377 * receive buffer without UART_LSR_DR bit set, we
1378 * just force the read character to be 0
1385 lsr |= up->lsr_saved_flags;
1386 up->lsr_saved_flags = 0;
1388 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1390 * For statistics only
1392 if (lsr & UART_LSR_BI) {
1393 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1396 * If tegra port then clear the rx fifo to
1397 * accept another break/character.
1399 if (port->type == PORT_TEGRA)
1403 * We do the SysRQ and SAK checking
1404 * here because otherwise the break
1405 * may get masked by ignore_status_mask
1406 * or read_status_mask.
1408 if (uart_handle_break(port))
1410 } else if (lsr & UART_LSR_PE)
1411 port->icount.parity++;
1412 else if (lsr & UART_LSR_FE)
1413 port->icount.frame++;
1414 if (lsr & UART_LSR_OE)
1415 port->icount.overrun++;
1418 * Mask off conditions which should be ignored.
1420 lsr &= port->read_status_mask;
1422 if (lsr & UART_LSR_BI) {
1423 DEBUG_INTR("handling break....");
1425 } else if (lsr & UART_LSR_PE)
1427 else if (lsr & UART_LSR_FE)
1430 if (uart_handle_sysrq_char(port, ch))
1433 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1436 lsr = serial_in(up, UART_LSR);
1437 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1438 spin_unlock(&port->lock);
1439 tty_flip_buffer_push(tty);
1440 spin_lock(&port->lock);
1443 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1445 void serial8250_tx_chars(struct uart_8250_port *up)
1447 struct uart_port *port = &up->port;
1448 struct circ_buf *xmit = &port->state->xmit;
1452 serial_out(up, UART_TX, port->x_char);
1457 if (uart_tx_stopped(port)) {
1458 serial8250_stop_tx(port);
1461 if (uart_circ_empty(xmit)) {
1466 count = up->tx_loadsz;
1468 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1471 if (uart_circ_empty(xmit))
1473 } while (--count > 0);
1475 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1476 uart_write_wakeup(port);
1478 DEBUG_INTR("THRE...");
1480 if (uart_circ_empty(xmit))
1483 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1485 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1487 struct uart_port *port = &up->port;
1488 unsigned int status = serial_in(up, UART_MSR);
1490 status |= up->msr_saved_flags;
1491 up->msr_saved_flags = 0;
1492 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1493 port->state != NULL) {
1494 if (status & UART_MSR_TERI)
1496 if (status & UART_MSR_DDSR)
1498 if (status & UART_MSR_DDCD)
1499 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1500 if (status & UART_MSR_DCTS)
1501 uart_handle_cts_change(port, status & UART_MSR_CTS);
1503 wake_up_interruptible(&port->state->port.delta_msr_wait);
1508 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1511 * This handles the interrupt from one port.
1513 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1515 unsigned char status;
1516 unsigned long flags;
1517 struct uart_8250_port *up =
1518 container_of(port, struct uart_8250_port, port);
1520 if (iir & UART_IIR_NO_INT)
1523 spin_lock_irqsave(&port->lock, flags);
1525 status = serial_port_in(port, UART_LSR);
1527 DEBUG_INTR("status = %x...", status);
1529 if (status & (UART_LSR_DR | UART_LSR_BI))
1530 status = serial8250_rx_chars(up, status);
1531 serial8250_modem_status(up);
1532 if (status & UART_LSR_THRE)
1533 serial8250_tx_chars(up);
1535 spin_unlock_irqrestore(&port->lock, flags);
1538 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1540 static int serial8250_default_handle_irq(struct uart_port *port)
1542 unsigned int iir = serial_port_in(port, UART_IIR);
1544 return serial8250_handle_irq(port, iir);
1548 * This is the serial driver's interrupt routine.
1550 * Arjan thinks the old way was overly complex, so it got simplified.
1551 * Alan disagrees, saying that need the complexity to handle the weird
1552 * nature of ISA shared interrupts. (This is a special exception.)
1554 * In order to handle ISA shared interrupts properly, we need to check
1555 * that all ports have been serviced, and therefore the ISA interrupt
1556 * line has been de-asserted.
1558 * This means we need to loop through all ports. checking that they
1559 * don't have an interrupt pending.
1561 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1563 struct irq_info *i = dev_id;
1564 struct list_head *l, *end = NULL;
1565 int pass_counter = 0, handled = 0;
1567 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1569 spin_lock(&i->lock);
1573 struct uart_8250_port *up;
1574 struct uart_port *port;
1577 up = list_entry(l, struct uart_8250_port, list);
1579 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1581 if (!skip && port->handle_irq(port)) {
1584 } else if (end == NULL)
1589 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1590 /* If we hit this, we're dead. */
1591 printk_ratelimited(KERN_ERR
1592 "serial8250: too much work for irq%d\n", irq);
1597 spin_unlock(&i->lock);
1599 DEBUG_INTR("end.\n");
1601 return IRQ_RETVAL(handled);
1605 * To support ISA shared interrupts, we need to have one interrupt
1606 * handler that ensures that the IRQ line has been deasserted
1607 * before returning. Failing to do this will result in the IRQ
1608 * line being stuck active, and, since ISA irqs are edge triggered,
1609 * no more IRQs will be seen.
1611 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1613 spin_lock_irq(&i->lock);
1615 if (!list_empty(i->head)) {
1616 if (i->head == &up->list)
1617 i->head = i->head->next;
1618 list_del(&up->list);
1620 BUG_ON(i->head != &up->list);
1623 spin_unlock_irq(&i->lock);
1624 /* List empty so throw away the hash node */
1625 if (i->head == NULL) {
1626 hlist_del(&i->node);
1631 static int serial_link_irq_chain(struct uart_8250_port *up)
1633 struct hlist_head *h;
1634 struct hlist_node *n;
1636 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1638 mutex_lock(&hash_mutex);
1640 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1642 hlist_for_each(n, h) {
1643 i = hlist_entry(n, struct irq_info, node);
1644 if (i->irq == up->port.irq)
1649 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1651 mutex_unlock(&hash_mutex);
1654 spin_lock_init(&i->lock);
1655 i->irq = up->port.irq;
1656 hlist_add_head(&i->node, h);
1658 mutex_unlock(&hash_mutex);
1660 spin_lock_irq(&i->lock);
1663 list_add(&up->list, i->head);
1664 spin_unlock_irq(&i->lock);
1668 INIT_LIST_HEAD(&up->list);
1669 i->head = &up->list;
1670 spin_unlock_irq(&i->lock);
1671 irq_flags |= up->port.irqflags;
1672 ret = request_irq(up->port.irq, serial8250_interrupt,
1673 irq_flags, "serial", i);
1675 serial_do_unlink(i, up);
1681 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1684 struct hlist_node *n;
1685 struct hlist_head *h;
1687 mutex_lock(&hash_mutex);
1689 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1691 hlist_for_each(n, h) {
1692 i = hlist_entry(n, struct irq_info, node);
1693 if (i->irq == up->port.irq)
1698 BUG_ON(i->head == NULL);
1700 if (list_empty(i->head))
1701 free_irq(up->port.irq, i);
1703 serial_do_unlink(i, up);
1704 mutex_unlock(&hash_mutex);
1708 * This function is used to handle ports that do not have an
1709 * interrupt. This doesn't work very well for 16450's, but gives
1710 * barely passable results for a 16550A. (Although at the expense
1711 * of much CPU overhead).
1713 static void serial8250_timeout(unsigned long data)
1715 struct uart_8250_port *up = (struct uart_8250_port *)data;
1717 up->port.handle_irq(&up->port);
1718 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1721 static void serial8250_backup_timeout(unsigned long data)
1723 struct uart_8250_port *up = (struct uart_8250_port *)data;
1724 unsigned int iir, ier = 0, lsr;
1725 unsigned long flags;
1727 spin_lock_irqsave(&up->port.lock, flags);
1730 * Must disable interrupts or else we risk racing with the interrupt
1734 ier = serial_in(up, UART_IER);
1735 serial_out(up, UART_IER, 0);
1738 iir = serial_in(up, UART_IIR);
1741 * This should be a safe test for anyone who doesn't trust the
1742 * IIR bits on their UART, but it's specifically designed for
1743 * the "Diva" UART used on the management processor on many HP
1744 * ia64 and parisc boxes.
1746 lsr = serial_in(up, UART_LSR);
1747 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1748 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1749 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1750 (lsr & UART_LSR_THRE)) {
1751 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1752 iir |= UART_IIR_THRI;
1755 if (!(iir & UART_IIR_NO_INT))
1756 serial8250_tx_chars(up);
1759 serial_out(up, UART_IER, ier);
1761 spin_unlock_irqrestore(&up->port.lock, flags);
1763 /* Standard timer interval plus 0.2s to keep the port running */
1764 mod_timer(&up->timer,
1765 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1768 static unsigned int serial8250_tx_empty(struct uart_port *port)
1770 struct uart_8250_port *up =
1771 container_of(port, struct uart_8250_port, port);
1772 unsigned long flags;
1775 spin_lock_irqsave(&port->lock, flags);
1776 lsr = serial_port_in(port, UART_LSR);
1777 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1778 spin_unlock_irqrestore(&port->lock, flags);
1780 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1783 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1785 struct uart_8250_port *up =
1786 container_of(port, struct uart_8250_port, port);
1787 unsigned int status;
1790 status = serial8250_modem_status(up);
1793 if (status & UART_MSR_DCD)
1795 if (status & UART_MSR_RI)
1797 if (status & UART_MSR_DSR)
1799 if (status & UART_MSR_CTS)
1804 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1806 struct uart_8250_port *up =
1807 container_of(port, struct uart_8250_port, port);
1808 unsigned char mcr = 0;
1810 if (mctrl & TIOCM_RTS)
1811 mcr |= UART_MCR_RTS;
1812 if (mctrl & TIOCM_DTR)
1813 mcr |= UART_MCR_DTR;
1814 if (mctrl & TIOCM_OUT1)
1815 mcr |= UART_MCR_OUT1;
1816 if (mctrl & TIOCM_OUT2)
1817 mcr |= UART_MCR_OUT2;
1818 if (mctrl & TIOCM_LOOP)
1819 mcr |= UART_MCR_LOOP;
1821 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1823 serial_port_out(port, UART_MCR, mcr);
1826 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1828 struct uart_8250_port *up =
1829 container_of(port, struct uart_8250_port, port);
1830 unsigned long flags;
1832 spin_lock_irqsave(&port->lock, flags);
1833 if (break_state == -1)
1834 up->lcr |= UART_LCR_SBC;
1836 up->lcr &= ~UART_LCR_SBC;
1837 serial_port_out(port, UART_LCR, up->lcr);
1838 spin_unlock_irqrestore(&port->lock, flags);
1842 * Wait for transmitter & holding register to empty
1844 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1846 unsigned int status, tmout = 10000;
1848 /* Wait up to 10ms for the character(s) to be sent. */
1850 status = serial_in(up, UART_LSR);
1852 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1854 if ((status & bits) == bits)
1861 /* Wait up to 1s for flow control if necessary */
1862 if (up->port.flags & UPF_CONS_FLOW) {
1864 for (tmout = 1000000; tmout; tmout--) {
1865 unsigned int msr = serial_in(up, UART_MSR);
1866 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1867 if (msr & UART_MSR_CTS)
1870 touch_nmi_watchdog();
1875 #ifdef CONFIG_CONSOLE_POLL
1877 * Console polling routines for writing and reading from the uart while
1878 * in an interrupt or debug context.
1881 static int serial8250_get_poll_char(struct uart_port *port)
1883 unsigned char lsr = serial_port_in(port, UART_LSR);
1885 if (!(lsr & UART_LSR_DR))
1886 return NO_POLL_CHAR;
1888 return serial_port_in(port, UART_RX);
1892 static void serial8250_put_poll_char(struct uart_port *port,
1896 struct uart_8250_port *up =
1897 container_of(port, struct uart_8250_port, port);
1900 * First save the IER then disable the interrupts
1902 ier = serial_port_in(port, UART_IER);
1903 if (up->capabilities & UART_CAP_UUE)
1904 serial_port_out(port, UART_IER, UART_IER_UUE);
1906 serial_port_out(port, UART_IER, 0);
1908 wait_for_xmitr(up, BOTH_EMPTY);
1910 * Send the character out.
1911 * If a LF, also do CR...
1913 serial_port_out(port, UART_TX, c);
1915 wait_for_xmitr(up, BOTH_EMPTY);
1916 serial_port_out(port, UART_TX, 13);
1920 * Finally, wait for transmitter to become empty
1921 * and restore the IER
1923 wait_for_xmitr(up, BOTH_EMPTY);
1924 serial_port_out(port, UART_IER, ier);
1927 #endif /* CONFIG_CONSOLE_POLL */
1929 static int serial8250_startup(struct uart_port *port)
1931 struct uart_8250_port *up =
1932 container_of(port, struct uart_8250_port, port);
1933 unsigned long flags;
1934 unsigned char lsr, iir;
1937 port->fifosize = uart_config[up->port.type].fifo_size;
1938 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1939 up->capabilities = uart_config[up->port.type].flags;
1942 if (port->iotype != up->cur_iotype)
1943 set_io_from_upio(port);
1945 if (port->type == PORT_16C950) {
1946 /* Wake up and initialize UART */
1948 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1949 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1950 serial_port_out(port, UART_IER, 0);
1951 serial_port_out(port, UART_LCR, 0);
1952 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1953 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1954 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1955 serial_port_out(port, UART_LCR, 0);
1958 #ifdef CONFIG_SERIAL_8250_RSA
1960 * If this is an RSA port, see if we can kick it up to the
1961 * higher speed clock.
1967 * Clear the FIFO buffers and disable them.
1968 * (they will be reenabled in set_termios())
1970 serial8250_clear_fifos(up);
1973 * Clear the interrupt registers.
1975 serial_port_in(port, UART_LSR);
1976 serial_port_in(port, UART_RX);
1977 serial_port_in(port, UART_IIR);
1978 serial_port_in(port, UART_MSR);
1981 * At this point, there's no way the LSR could still be 0xff;
1982 * if it is, then bail out, because there's likely no UART
1985 if (!(port->flags & UPF_BUGGY_UART) &&
1986 (serial_port_in(port, UART_LSR) == 0xff)) {
1987 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1988 serial_index(port));
1993 * For a XR16C850, we need to set the trigger levels
1995 if (port->type == PORT_16850) {
1998 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2000 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2001 serial_port_out(port, UART_FCTR,
2002 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2003 serial_port_out(port, UART_TRG, UART_TRG_96);
2004 serial_port_out(port, UART_FCTR,
2005 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2006 serial_port_out(port, UART_TRG, UART_TRG_96);
2008 serial_port_out(port, UART_LCR, 0);
2014 * Test for UARTs that do not reassert THRE when the
2015 * transmitter is idle and the interrupt has already
2016 * been cleared. Real 16550s should always reassert
2017 * this interrupt whenever the transmitter is idle and
2018 * the interrupt is enabled. Delays are necessary to
2019 * allow register changes to become visible.
2021 spin_lock_irqsave(&port->lock, flags);
2022 if (up->port.irqflags & IRQF_SHARED)
2023 disable_irq_nosync(port->irq);
2025 wait_for_xmitr(up, UART_LSR_THRE);
2026 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2027 udelay(1); /* allow THRE to set */
2028 iir1 = serial_port_in(port, UART_IIR);
2029 serial_port_out(port, UART_IER, 0);
2030 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2031 udelay(1); /* allow a working UART time to re-assert THRE */
2032 iir = serial_port_in(port, UART_IIR);
2033 serial_port_out(port, UART_IER, 0);
2035 if (port->irqflags & IRQF_SHARED)
2036 enable_irq(port->irq);
2037 spin_unlock_irqrestore(&port->lock, flags);
2040 * If the interrupt is not reasserted, setup a timer to
2041 * kick the UART on a regular basis.
2043 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2044 up->bugs |= UART_BUG_THRE;
2045 pr_debug("ttyS%d - using backup timer\n",
2046 serial_index(port));
2051 * The above check will only give an accurate result the first time
2052 * the port is opened so this value needs to be preserved.
2054 if (up->bugs & UART_BUG_THRE) {
2055 up->timer.function = serial8250_backup_timeout;
2056 up->timer.data = (unsigned long)up;
2057 mod_timer(&up->timer, jiffies +
2058 uart_poll_timeout(port) + HZ / 5);
2062 * If the "interrupt" for this port doesn't correspond with any
2063 * hardware interrupt, we use a timer-based system. The original
2064 * driver used to do this with IRQ0.
2067 up->timer.data = (unsigned long)up;
2068 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2070 retval = serial_link_irq_chain(up);
2076 * Now, initialize the UART
2078 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2080 spin_lock_irqsave(&port->lock, flags);
2081 if (up->port.flags & UPF_FOURPORT) {
2083 up->port.mctrl |= TIOCM_OUT1;
2086 * Most PC uarts need OUT2 raised to enable interrupts.
2089 up->port.mctrl |= TIOCM_OUT2;
2091 serial8250_set_mctrl(port, port->mctrl);
2093 /* Serial over Lan (SoL) hack:
2094 Intel 8257x Gigabit ethernet chips have a
2095 16550 emulation, to be used for Serial Over Lan.
2096 Those chips take a longer time than a normal
2097 serial device to signalize that a transmission
2098 data was queued. Due to that, the above test generally
2099 fails. One solution would be to delay the reading of
2100 iir. However, this is not reliable, since the timeout
2101 is variable. So, let's just don't test if we receive
2102 TX irq. This way, we'll never enable UART_BUG_TXEN.
2104 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2105 goto dont_test_tx_en;
2108 * Do a quick test to see if we receive an
2109 * interrupt when we enable the TX irq.
2111 serial_port_out(port, UART_IER, UART_IER_THRI);
2112 lsr = serial_port_in(port, UART_LSR);
2113 iir = serial_port_in(port, UART_IIR);
2114 serial_port_out(port, UART_IER, 0);
2116 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2117 if (!(up->bugs & UART_BUG_TXEN)) {
2118 up->bugs |= UART_BUG_TXEN;
2119 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2120 serial_index(port));
2123 up->bugs &= ~UART_BUG_TXEN;
2127 spin_unlock_irqrestore(&port->lock, flags);
2130 * Clear the interrupt registers again for luck, and clear the
2131 * saved flags to avoid getting false values from polling
2132 * routines or the previous session.
2134 serial_port_in(port, UART_LSR);
2135 serial_port_in(port, UART_RX);
2136 serial_port_in(port, UART_IIR);
2137 serial_port_in(port, UART_MSR);
2138 up->lsr_saved_flags = 0;
2139 up->msr_saved_flags = 0;
2142 * Finally, enable interrupts. Note: Modem status interrupts
2143 * are set via set_termios(), which will be occurring imminently
2144 * anyway, so we don't enable them here.
2146 up->ier = UART_IER_RLSI | UART_IER_RDI;
2147 serial_port_out(port, UART_IER, up->ier);
2149 if (port->flags & UPF_FOURPORT) {
2152 * Enable interrupts on the AST Fourport board
2154 icp = (port->iobase & 0xfe0) | 0x01f;
2162 static void serial8250_shutdown(struct uart_port *port)
2164 struct uart_8250_port *up =
2165 container_of(port, struct uart_8250_port, port);
2166 unsigned long flags;
2169 * Disable interrupts from this port
2172 serial_port_out(port, UART_IER, 0);
2174 spin_lock_irqsave(&port->lock, flags);
2175 if (port->flags & UPF_FOURPORT) {
2176 /* reset interrupts on the AST Fourport board */
2177 inb((port->iobase & 0xfe0) | 0x1f);
2178 port->mctrl |= TIOCM_OUT1;
2180 port->mctrl &= ~TIOCM_OUT2;
2182 serial8250_set_mctrl(port, port->mctrl);
2183 spin_unlock_irqrestore(&port->lock, flags);
2186 * Disable break condition and FIFOs
2188 serial_port_out(port, UART_LCR,
2189 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2190 serial8250_clear_fifos(up);
2192 #ifdef CONFIG_SERIAL_8250_RSA
2194 * Reset the RSA board back to 115kbps compat mode.
2200 * Read data port to reset things, and then unlink from
2203 serial_port_in(port, UART_RX);
2205 del_timer_sync(&up->timer);
2206 up->timer.function = serial8250_timeout;
2208 serial_unlink_irq_chain(up);
2211 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2216 * Handle magic divisors for baud rates above baud_base on
2217 * SMSC SuperIO chips.
2219 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2220 baud == (port->uartclk/4))
2222 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2223 baud == (port->uartclk/8))
2226 quot = uart_get_divisor(port, baud);
2232 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2233 struct ktermios *old)
2235 struct uart_8250_port *up =
2236 container_of(port, struct uart_8250_port, port);
2237 unsigned char cval, fcr = 0;
2238 unsigned long flags;
2239 unsigned int baud, quot;
2241 switch (termios->c_cflag & CSIZE) {
2243 cval = UART_LCR_WLEN5;
2246 cval = UART_LCR_WLEN6;
2249 cval = UART_LCR_WLEN7;
2253 cval = UART_LCR_WLEN8;
2257 if (termios->c_cflag & CSTOPB)
2258 cval |= UART_LCR_STOP;
2259 if (termios->c_cflag & PARENB)
2260 cval |= UART_LCR_PARITY;
2261 if (!(termios->c_cflag & PARODD))
2262 cval |= UART_LCR_EPAR;
2264 if (termios->c_cflag & CMSPAR)
2265 cval |= UART_LCR_SPAR;
2269 * Ask the core to calculate the divisor for us.
2271 baud = uart_get_baud_rate(port, termios, old,
2272 port->uartclk / 16 / 0xffff,
2273 port->uartclk / 16);
2274 quot = serial8250_get_divisor(port, baud);
2277 * Oxford Semi 952 rev B workaround
2279 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2282 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2284 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2286 fcr = uart_config[port->type].fcr;
2290 * MCR-based auto flow control. When AFE is enabled, RTS will be
2291 * deasserted when the receive FIFO contains more characters than
2292 * the trigger, or the MCR RTS bit is cleared. In the case where
2293 * the remote UART is not using CTS auto flow control, we must
2294 * have sufficient FIFO entries for the latency of the remote
2295 * UART to respond. IOW, at least 32 bytes of FIFO.
2297 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2298 up->mcr &= ~UART_MCR_AFE;
2299 if (termios->c_cflag & CRTSCTS)
2300 up->mcr |= UART_MCR_AFE;
2304 * Ok, we're now changing the port state. Do it with
2305 * interrupts disabled.
2307 spin_lock_irqsave(&port->lock, flags);
2310 * Update the per-port timeout.
2312 uart_update_timeout(port, termios->c_cflag, baud);
2314 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2315 if (termios->c_iflag & INPCK)
2316 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2317 if (termios->c_iflag & (BRKINT | PARMRK))
2318 port->read_status_mask |= UART_LSR_BI;
2321 * Characteres to ignore
2323 port->ignore_status_mask = 0;
2324 if (termios->c_iflag & IGNPAR)
2325 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2326 if (termios->c_iflag & IGNBRK) {
2327 port->ignore_status_mask |= UART_LSR_BI;
2329 * If we're ignoring parity and break indicators,
2330 * ignore overruns too (for real raw support).
2332 if (termios->c_iflag & IGNPAR)
2333 port->ignore_status_mask |= UART_LSR_OE;
2337 * ignore all characters if CREAD is not set
2339 if ((termios->c_cflag & CREAD) == 0)
2340 port->ignore_status_mask |= UART_LSR_DR;
2343 * CTS flow control flag and modem status interrupts
2345 up->ier &= ~UART_IER_MSI;
2346 if (!(up->bugs & UART_BUG_NOMSR) &&
2347 UART_ENABLE_MS(&up->port, termios->c_cflag))
2348 up->ier |= UART_IER_MSI;
2349 if (up->capabilities & UART_CAP_UUE)
2350 up->ier |= UART_IER_UUE;
2351 if (up->capabilities & UART_CAP_RTOIE)
2352 up->ier |= UART_IER_RTOIE;
2354 serial_port_out(port, UART_IER, up->ier);
2356 if (up->capabilities & UART_CAP_EFR) {
2357 unsigned char efr = 0;
2359 * TI16C752/Startech hardware flow control. FIXME:
2360 * - TI16C752 requires control thresholds to be set.
2361 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2363 if (termios->c_cflag & CRTSCTS)
2364 efr |= UART_EFR_CTS;
2366 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2367 if (port->flags & UPF_EXAR_EFR)
2368 serial_port_out(port, UART_XR_EFR, efr);
2370 serial_port_out(port, UART_EFR, efr);
2373 #ifdef CONFIG_ARCH_OMAP
2374 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2375 if (cpu_is_omap1510() && is_omap_port(up)) {
2376 if (baud == 115200) {
2378 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2380 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2385 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2386 * otherwise just set DLAB
2388 if (up->capabilities & UART_NATSEMI)
2389 serial_port_out(port, UART_LCR, 0xe0);
2391 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2393 serial_dl_write(up, quot);
2396 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2397 * is written without DLAB set, this mode will be disabled.
2399 if (port->type == PORT_16750)
2400 serial_port_out(port, UART_FCR, fcr);
2402 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2403 up->lcr = cval; /* Save LCR */
2404 if (port->type != PORT_16750) {
2405 /* emulated UARTs (Lucent Venus 167x) need two steps */
2406 if (fcr & UART_FCR_ENABLE_FIFO)
2407 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2408 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2410 serial8250_set_mctrl(port, port->mctrl);
2411 spin_unlock_irqrestore(&port->lock, flags);
2412 /* Don't rewrite B0 */
2413 if (tty_termios_baud_rate(termios))
2414 tty_termios_encode_baud_rate(termios, baud, baud);
2416 EXPORT_SYMBOL(serial8250_do_set_termios);
2419 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2420 struct ktermios *old)
2422 if (port->set_termios)
2423 port->set_termios(port, termios, old);
2425 serial8250_do_set_termios(port, termios, old);
2429 serial8250_set_ldisc(struct uart_port *port, int new)
2432 port->flags |= UPF_HARDPPS_CD;
2433 serial8250_enable_ms(port);
2435 port->flags &= ~UPF_HARDPPS_CD;
2439 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2440 unsigned int oldstate)
2442 struct uart_8250_port *p =
2443 container_of(port, struct uart_8250_port, port);
2445 serial8250_set_sleep(p, state != 0);
2447 EXPORT_SYMBOL(serial8250_do_pm);
2450 serial8250_pm(struct uart_port *port, unsigned int state,
2451 unsigned int oldstate)
2454 port->pm(port, state, oldstate);
2456 serial8250_do_pm(port, state, oldstate);
2459 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2461 if (pt->port.iotype == UPIO_AU)
2463 #ifdef CONFIG_ARCH_OMAP
2464 if (is_omap_port(pt))
2465 return 0x16 << pt->port.regshift;
2467 return 8 << pt->port.regshift;
2471 * Resource handling.
2473 static int serial8250_request_std_resource(struct uart_8250_port *up)
2475 unsigned int size = serial8250_port_size(up);
2476 struct uart_port *port = &up->port;
2479 switch (port->iotype) {
2487 if (!request_mem_region(port->mapbase, size, "serial")) {
2492 if (port->flags & UPF_IOREMAP) {
2493 port->membase = ioremap_nocache(port->mapbase, size);
2494 if (!port->membase) {
2495 release_mem_region(port->mapbase, size);
2503 if (!request_region(port->iobase, size, "serial"))
2510 static void serial8250_release_std_resource(struct uart_8250_port *up)
2512 unsigned int size = serial8250_port_size(up);
2513 struct uart_port *port = &up->port;
2515 switch (port->iotype) {
2523 if (port->flags & UPF_IOREMAP) {
2524 iounmap(port->membase);
2525 port->membase = NULL;
2528 release_mem_region(port->mapbase, size);
2533 release_region(port->iobase, size);
2538 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2540 unsigned long start = UART_RSA_BASE << up->port.regshift;
2541 unsigned int size = 8 << up->port.regshift;
2542 struct uart_port *port = &up->port;
2545 switch (port->iotype) {
2548 start += port->iobase;
2549 if (request_region(start, size, "serial-rsa"))
2559 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2561 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2562 unsigned int size = 8 << up->port.regshift;
2563 struct uart_port *port = &up->port;
2565 switch (port->iotype) {
2568 release_region(port->iobase + offset, size);
2573 static void serial8250_release_port(struct uart_port *port)
2575 struct uart_8250_port *up =
2576 container_of(port, struct uart_8250_port, port);
2578 serial8250_release_std_resource(up);
2579 if (port->type == PORT_RSA)
2580 serial8250_release_rsa_resource(up);
2583 static int serial8250_request_port(struct uart_port *port)
2585 struct uart_8250_port *up =
2586 container_of(port, struct uart_8250_port, port);
2589 ret = serial8250_request_std_resource(up);
2590 if (ret == 0 && port->type == PORT_RSA) {
2591 ret = serial8250_request_rsa_resource(up);
2593 serial8250_release_std_resource(up);
2599 static void serial8250_config_port(struct uart_port *port, int flags)
2601 struct uart_8250_port *up =
2602 container_of(port, struct uart_8250_port, port);
2603 int probeflags = PROBE_ANY;
2607 * Find the region that we can probe for. This in turn
2608 * tells us whether we can probe for the type of port.
2610 ret = serial8250_request_std_resource(up);
2614 ret = serial8250_request_rsa_resource(up);
2616 probeflags &= ~PROBE_RSA;
2618 if (port->iotype != up->cur_iotype)
2619 set_io_from_upio(port);
2621 if (flags & UART_CONFIG_TYPE)
2622 autoconfig(up, probeflags);
2624 /* if access method is AU, it is a 16550 with a quirk */
2625 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2626 up->bugs |= UART_BUG_NOMSR;
2628 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2631 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2632 serial8250_release_rsa_resource(up);
2633 if (port->type == PORT_UNKNOWN)
2634 serial8250_release_std_resource(up);
2638 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2640 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2641 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2642 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2643 ser->type == PORT_STARTECH)
2649 serial8250_type(struct uart_port *port)
2651 int type = port->type;
2653 if (type >= ARRAY_SIZE(uart_config))
2655 return uart_config[type].name;
2658 static struct uart_ops serial8250_pops = {
2659 .tx_empty = serial8250_tx_empty,
2660 .set_mctrl = serial8250_set_mctrl,
2661 .get_mctrl = serial8250_get_mctrl,
2662 .stop_tx = serial8250_stop_tx,
2663 .start_tx = serial8250_start_tx,
2664 .stop_rx = serial8250_stop_rx,
2665 .enable_ms = serial8250_enable_ms,
2666 .break_ctl = serial8250_break_ctl,
2667 .startup = serial8250_startup,
2668 .shutdown = serial8250_shutdown,
2669 .set_termios = serial8250_set_termios,
2670 .set_ldisc = serial8250_set_ldisc,
2671 .pm = serial8250_pm,
2672 .type = serial8250_type,
2673 .release_port = serial8250_release_port,
2674 .request_port = serial8250_request_port,
2675 .config_port = serial8250_config_port,
2676 .verify_port = serial8250_verify_port,
2677 #ifdef CONFIG_CONSOLE_POLL
2678 .poll_get_char = serial8250_get_poll_char,
2679 .poll_put_char = serial8250_put_poll_char,
2683 static struct uart_8250_port serial8250_ports[UART_NR];
2685 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2686 unsigned short *capabilities);
2688 void serial8250_set_isa_configurator(
2689 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2691 serial8250_isa_config = v;
2693 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2695 static void __init serial8250_isa_init_ports(void)
2697 struct uart_8250_port *up;
2698 static int first = 1;
2705 for (i = 0; i < nr_uarts; i++) {
2706 struct uart_8250_port *up = &serial8250_ports[i];
2707 struct uart_port *port = &up->port;
2710 spin_lock_init(&port->lock);
2712 init_timer(&up->timer);
2713 up->timer.function = serial8250_timeout;
2716 * ALPHA_KLUDGE_MCR needs to be killed.
2718 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2719 up->mcr_force = ALPHA_KLUDGE_MCR;
2721 port->ops = &serial8250_pops;
2725 irqflag = IRQF_SHARED;
2727 for (i = 0, up = serial8250_ports;
2728 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2730 struct uart_port *port = &up->port;
2732 port->iobase = old_serial_port[i].port;
2733 port->irq = irq_canonicalize(old_serial_port[i].irq);
2734 port->irqflags = old_serial_port[i].irqflags;
2735 port->uartclk = old_serial_port[i].baud_base * 16;
2736 port->flags = old_serial_port[i].flags;
2737 port->hub6 = old_serial_port[i].hub6;
2738 port->membase = old_serial_port[i].iomem_base;
2739 port->iotype = old_serial_port[i].io_type;
2740 port->regshift = old_serial_port[i].iomem_reg_shift;
2741 set_io_from_upio(port);
2742 port->irqflags |= irqflag;
2743 if (serial8250_isa_config != NULL)
2744 serial8250_isa_config(i, &up->port, &up->capabilities);
2750 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2752 up->port.type = type;
2753 up->port.fifosize = uart_config[type].fifo_size;
2754 up->capabilities = uart_config[type].flags;
2755 up->tx_loadsz = uart_config[type].tx_loadsz;
2759 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2763 for (i = 0; i < nr_uarts; i++) {
2764 struct uart_8250_port *up = &serial8250_ports[i];
2765 up->cur_iotype = 0xFF;
2768 serial8250_isa_init_ports();
2770 for (i = 0; i < nr_uarts; i++) {
2771 struct uart_8250_port *up = &serial8250_ports[i];
2775 if (up->port.flags & UPF_FIXED_TYPE)
2776 serial8250_init_fixed_type_port(up, up->port.type);
2778 uart_add_one_port(drv, &up->port);
2782 #ifdef CONFIG_SERIAL_8250_CONSOLE
2784 static void serial8250_console_putchar(struct uart_port *port, int ch)
2786 struct uart_8250_port *up =
2787 container_of(port, struct uart_8250_port, port);
2789 wait_for_xmitr(up, UART_LSR_THRE);
2790 serial_port_out(port, UART_TX, ch);
2794 * Print a string to the serial port trying not to disturb
2795 * any possible real use of the port...
2797 * The console_lock must be held when we get here.
2800 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2802 struct uart_8250_port *up = &serial8250_ports[co->index];
2803 struct uart_port *port = &up->port;
2804 unsigned long flags;
2808 touch_nmi_watchdog();
2810 local_irq_save(flags);
2812 /* serial8250_handle_irq() already took the lock */
2814 } else if (oops_in_progress) {
2815 locked = spin_trylock(&port->lock);
2817 spin_lock(&port->lock);
2820 * First save the IER then disable the interrupts
2822 ier = serial_port_in(port, UART_IER);
2824 if (up->capabilities & UART_CAP_UUE)
2825 serial_port_out(port, UART_IER, UART_IER_UUE);
2827 serial_port_out(port, UART_IER, 0);
2829 uart_console_write(port, s, count, serial8250_console_putchar);
2832 * Finally, wait for transmitter to become empty
2833 * and restore the IER
2835 wait_for_xmitr(up, BOTH_EMPTY);
2836 serial_port_out(port, UART_IER, ier);
2839 * The receive handling will happen properly because the
2840 * receive ready bit will still be set; it is not cleared
2841 * on read. However, modem control will not, we must
2842 * call it if we have saved something in the saved flags
2843 * while processing with interrupts off.
2845 if (up->msr_saved_flags)
2846 serial8250_modem_status(up);
2849 spin_unlock(&port->lock);
2850 local_irq_restore(flags);
2853 static int __init serial8250_console_setup(struct console *co, char *options)
2855 struct uart_port *port;
2862 * Check whether an invalid uart number has been specified, and
2863 * if so, search for the first available port that does have
2866 if (co->index >= nr_uarts)
2868 port = &serial8250_ports[co->index].port;
2869 if (!port->iobase && !port->membase)
2873 uart_parse_options(options, &baud, &parity, &bits, &flow);
2875 return uart_set_options(port, co, baud, parity, bits, flow);
2878 static int serial8250_console_early_setup(void)
2880 return serial8250_find_port_for_earlycon();
2883 static struct console serial8250_console = {
2885 .write = serial8250_console_write,
2886 .device = uart_console_device,
2887 .setup = serial8250_console_setup,
2888 .early_setup = serial8250_console_early_setup,
2889 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2891 .data = &serial8250_reg,
2894 static int __init serial8250_console_init(void)
2896 if (nr_uarts > UART_NR)
2899 serial8250_isa_init_ports();
2900 register_console(&serial8250_console);
2903 console_initcall(serial8250_console_init);
2905 int serial8250_find_port(struct uart_port *p)
2908 struct uart_port *port;
2910 for (line = 0; line < nr_uarts; line++) {
2911 port = &serial8250_ports[line].port;
2912 if (uart_match_port(p, port))
2918 #define SERIAL8250_CONSOLE &serial8250_console
2920 #define SERIAL8250_CONSOLE NULL
2923 static struct uart_driver serial8250_reg = {
2924 .owner = THIS_MODULE,
2925 .driver_name = "serial",
2929 .cons = SERIAL8250_CONSOLE,
2933 * early_serial_setup - early registration for 8250 ports
2935 * Setup an 8250 port structure prior to console initialisation. Use
2936 * after console initialisation will cause undefined behaviour.
2938 int __init early_serial_setup(struct uart_port *port)
2940 struct uart_port *p;
2942 if (port->line >= ARRAY_SIZE(serial8250_ports))
2945 serial8250_isa_init_ports();
2946 p = &serial8250_ports[port->line].port;
2947 p->iobase = port->iobase;
2948 p->membase = port->membase;
2950 p->irqflags = port->irqflags;
2951 p->uartclk = port->uartclk;
2952 p->fifosize = port->fifosize;
2953 p->regshift = port->regshift;
2954 p->iotype = port->iotype;
2955 p->flags = port->flags;
2956 p->mapbase = port->mapbase;
2957 p->private_data = port->private_data;
2958 p->type = port->type;
2959 p->line = port->line;
2961 set_io_from_upio(p);
2962 if (port->serial_in)
2963 p->serial_in = port->serial_in;
2964 if (port->serial_out)
2965 p->serial_out = port->serial_out;
2966 if (port->handle_irq)
2967 p->handle_irq = port->handle_irq;
2969 p->handle_irq = serial8250_default_handle_irq;
2975 * serial8250_suspend_port - suspend one serial port
2976 * @line: serial line number
2978 * Suspend one serial port.
2980 void serial8250_suspend_port(int line)
2982 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2986 * serial8250_resume_port - resume one serial port
2987 * @line: serial line number
2989 * Resume one serial port.
2991 void serial8250_resume_port(int line)
2993 struct uart_8250_port *up = &serial8250_ports[line];
2994 struct uart_port *port = &up->port;
2996 if (up->capabilities & UART_NATSEMI) {
2997 /* Ensure it's still in high speed mode */
2998 serial_port_out(port, UART_LCR, 0xE0);
3000 ns16550a_goto_highspeed(up);
3002 serial_port_out(port, UART_LCR, 0);
3003 port->uartclk = 921600*16;
3005 uart_resume_port(&serial8250_reg, port);
3009 * Register a set of serial devices attached to a platform device. The
3010 * list is terminated with a zero flags entry, which means we expect
3011 * all entries to have at least UPF_BOOT_AUTOCONF set.
3013 static int __devinit serial8250_probe(struct platform_device *dev)
3015 struct plat_serial8250_port *p = dev->dev.platform_data;
3016 struct uart_port port;
3017 int ret, i, irqflag = 0;
3019 memset(&port, 0, sizeof(struct uart_port));
3022 irqflag = IRQF_SHARED;
3024 for (i = 0; p && p->flags != 0; p++, i++) {
3025 port.iobase = p->iobase;
3026 port.membase = p->membase;
3028 port.irqflags = p->irqflags;
3029 port.uartclk = p->uartclk;
3030 port.regshift = p->regshift;
3031 port.iotype = p->iotype;
3032 port.flags = p->flags;
3033 port.mapbase = p->mapbase;
3034 port.hub6 = p->hub6;
3035 port.private_data = p->private_data;
3036 port.type = p->type;
3037 port.serial_in = p->serial_in;
3038 port.serial_out = p->serial_out;
3039 port.handle_irq = p->handle_irq;
3040 port.set_termios = p->set_termios;
3042 port.dev = &dev->dev;
3043 port.irqflags |= irqflag;
3044 ret = serial8250_register_port(&port);
3046 dev_err(&dev->dev, "unable to register port at index %d "
3047 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3048 p->iobase, (unsigned long long)p->mapbase,
3056 * Remove serial ports registered against a platform device.
3058 static int __devexit serial8250_remove(struct platform_device *dev)
3062 for (i = 0; i < nr_uarts; i++) {
3063 struct uart_8250_port *up = &serial8250_ports[i];
3065 if (up->port.dev == &dev->dev)
3066 serial8250_unregister_port(i);
3071 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3075 for (i = 0; i < UART_NR; i++) {
3076 struct uart_8250_port *up = &serial8250_ports[i];
3078 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3079 uart_suspend_port(&serial8250_reg, &up->port);
3085 static int serial8250_resume(struct platform_device *dev)
3089 for (i = 0; i < UART_NR; i++) {
3090 struct uart_8250_port *up = &serial8250_ports[i];
3092 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3093 serial8250_resume_port(i);
3099 static struct platform_driver serial8250_isa_driver = {
3100 .probe = serial8250_probe,
3101 .remove = __devexit_p(serial8250_remove),
3102 .suspend = serial8250_suspend,
3103 .resume = serial8250_resume,
3105 .name = "serial8250",
3106 .owner = THIS_MODULE,
3111 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3112 * in the table in include/asm/serial.h
3114 static struct platform_device *serial8250_isa_devs;
3117 * serial8250_register_port and serial8250_unregister_port allows for
3118 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3119 * modems and PCI multiport cards.
3121 static DEFINE_MUTEX(serial_mutex);
3123 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3128 * First, find a port entry which matches.
3130 for (i = 0; i < nr_uarts; i++)
3131 if (uart_match_port(&serial8250_ports[i].port, port))
3132 return &serial8250_ports[i];
3135 * We didn't find a matching entry, so look for the first
3136 * free entry. We look for one which hasn't been previously
3137 * used (indicated by zero iobase).
3139 for (i = 0; i < nr_uarts; i++)
3140 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3141 serial8250_ports[i].port.iobase == 0)
3142 return &serial8250_ports[i];
3145 * That also failed. Last resort is to find any entry which
3146 * doesn't have a real port associated with it.
3148 for (i = 0; i < nr_uarts; i++)
3149 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3150 return &serial8250_ports[i];
3156 * serial8250_register_port - register a serial port
3157 * @port: serial port template
3159 * Configure the serial port specified by the request. If the
3160 * port exists and is in use, it is hung up and unregistered
3163 * The port is then probed and if necessary the IRQ is autodetected
3164 * If this fails an error is returned.
3166 * On success the port is ready to use and the line number is returned.
3168 int serial8250_register_port(struct uart_port *port)
3170 struct uart_8250_port *uart;
3173 if (port->uartclk == 0)
3176 mutex_lock(&serial_mutex);
3178 uart = serial8250_find_match_or_unused(port);
3180 uart_remove_one_port(&serial8250_reg, &uart->port);
3182 uart->port.iobase = port->iobase;
3183 uart->port.membase = port->membase;
3184 uart->port.irq = port->irq;
3185 uart->port.irqflags = port->irqflags;
3186 uart->port.uartclk = port->uartclk;
3187 uart->port.fifosize = port->fifosize;
3188 uart->port.regshift = port->regshift;
3189 uart->port.iotype = port->iotype;
3190 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3191 uart->port.mapbase = port->mapbase;
3192 uart->port.private_data = port->private_data;
3194 uart->port.dev = port->dev;
3196 if (port->flags & UPF_FIXED_TYPE)
3197 serial8250_init_fixed_type_port(uart, port->type);
3199 set_io_from_upio(&uart->port);
3200 /* Possibly override default I/O functions. */
3201 if (port->serial_in)
3202 uart->port.serial_in = port->serial_in;
3203 if (port->serial_out)
3204 uart->port.serial_out = port->serial_out;
3205 if (port->handle_irq)
3206 uart->port.handle_irq = port->handle_irq;
3207 /* Possibly override set_termios call */
3208 if (port->set_termios)
3209 uart->port.set_termios = port->set_termios;
3211 uart->port.pm = port->pm;
3213 if (serial8250_isa_config != NULL)
3214 serial8250_isa_config(0, &uart->port,
3215 &uart->capabilities);
3217 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3219 ret = uart->port.line;
3221 mutex_unlock(&serial_mutex);
3225 EXPORT_SYMBOL(serial8250_register_port);
3228 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3229 * @line: serial line number
3231 * Remove one serial port. This may not be called from interrupt
3232 * context. We hand the port back to the our control.
3234 void serial8250_unregister_port(int line)
3236 struct uart_8250_port *uart = &serial8250_ports[line];
3238 mutex_lock(&serial_mutex);
3239 uart_remove_one_port(&serial8250_reg, &uart->port);
3240 if (serial8250_isa_devs) {
3241 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3242 uart->port.type = PORT_UNKNOWN;
3243 uart->port.dev = &serial8250_isa_devs->dev;
3244 uart->capabilities = uart_config[uart->port.type].flags;
3245 uart_add_one_port(&serial8250_reg, &uart->port);
3247 uart->port.dev = NULL;
3249 mutex_unlock(&serial_mutex);
3251 EXPORT_SYMBOL(serial8250_unregister_port);
3253 static int __init serial8250_init(void)
3257 if (nr_uarts > UART_NR)
3260 printk(KERN_INFO "Serial: 8250/16550 driver, "
3261 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3262 share_irqs ? "en" : "dis");
3265 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3267 serial8250_reg.nr = UART_NR;
3268 ret = uart_register_driver(&serial8250_reg);
3273 serial8250_isa_devs = platform_device_alloc("serial8250",
3274 PLAT8250_DEV_LEGACY);
3275 if (!serial8250_isa_devs) {
3277 goto unreg_uart_drv;
3280 ret = platform_device_add(serial8250_isa_devs);
3284 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3286 ret = platform_driver_register(&serial8250_isa_driver);
3290 platform_device_del(serial8250_isa_devs);
3292 platform_device_put(serial8250_isa_devs);
3295 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3297 uart_unregister_driver(&serial8250_reg);
3303 static void __exit serial8250_exit(void)
3305 struct platform_device *isa_dev = serial8250_isa_devs;
3308 * This tells serial8250_unregister_port() not to re-register
3309 * the ports (thereby making serial8250_isa_driver permanently
3312 serial8250_isa_devs = NULL;
3314 platform_driver_unregister(&serial8250_isa_driver);
3315 platform_device_unregister(isa_dev);
3318 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3320 uart_unregister_driver(&serial8250_reg);
3324 module_init(serial8250_init);
3325 module_exit(serial8250_exit);
3327 EXPORT_SYMBOL(serial8250_suspend_port);
3328 EXPORT_SYMBOL(serial8250_resume_port);
3330 MODULE_LICENSE("GPL");
3331 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3333 module_param(share_irqs, uint, 0644);
3334 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3337 module_param(nr_uarts, uint, 0644);
3338 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3340 module_param(skip_txen_test, uint, 0644);
3341 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3343 #ifdef CONFIG_SERIAL_8250_RSA
3344 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3345 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3347 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);