2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
42 #include <linux/sunserialcore.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 static struct uart_driver serial8250_reg;
61 static int serial_index(struct uart_port *port)
63 return (serial8250_reg.minor - 64) + port->line;
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
78 #define DEBUG_INTR(fmt...) printk(fmt)
80 #define DEBUG_INTR(fmt...) do { } while (0)
83 #define PASS_LIMIT 512
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
101 #include <asm/serial.h>
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
117 #ifdef CONFIG_SERIAL_8250_RSA
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
125 struct hlist_node node;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
136 * Here we define the default xmit fifo size used for each type of UART.
138 static const struct serial8250_config uart_config[] = {
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
199 .name = "16C950/954",
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
292 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
299 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
300 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
301 .flags = UART_CAP_FIFO,
303 [PORT_BRCM_TRUMANAGE] = {
307 .flags = UART_CAP_HFIFO,
314 /* Uart divisor latch read */
315 static int default_serial_dl_read(struct uart_8250_port *up)
317 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
320 /* Uart divisor latch write */
321 static void default_serial_dl_write(struct uart_8250_port *up, int value)
323 serial_out(up, UART_DLL, value & 0xff);
324 serial_out(up, UART_DLM, value >> 8 & 0xff);
327 #ifdef CONFIG_MIPS_ALCHEMY
329 /* Au1x00 UART hardware has a weird register layout */
330 static const u8 au_io_in_map[] = {
340 static const u8 au_io_out_map[] = {
348 static unsigned int au_serial_in(struct uart_port *p, int offset)
350 offset = au_io_in_map[offset] << p->regshift;
351 return __raw_readl(p->membase + offset);
354 static void au_serial_out(struct uart_port *p, int offset, int value)
356 offset = au_io_out_map[offset] << p->regshift;
357 __raw_writel(value, p->membase + offset);
360 /* Au1x00 haven't got a standard divisor latch */
361 static int au_serial_dl_read(struct uart_8250_port *up)
363 return __raw_readl(up->port.membase + 0x28);
366 static void au_serial_dl_write(struct uart_8250_port *up, int value)
368 __raw_writel(value, up->port.membase + 0x28);
373 #ifdef CONFIG_SERIAL_8250_RM9K
397 static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
399 offset = regmap_in[offset] << p->regshift;
400 return readl(p->membase + offset);
403 static void rm9k_serial_out(struct uart_port *p, int offset, int value)
405 offset = regmap_out[offset] << p->regshift;
406 writel(value, p->membase + offset);
409 static int rm9k_serial_dl_read(struct uart_8250_port *up)
411 return ((__raw_readl(up->port.membase + 0x10) << 8) |
412 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
415 static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
417 __raw_writel(value, up->port.membase + 0x08);
418 __raw_writel(value >> 8, up->port.membase + 0x10);
423 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
425 offset = offset << p->regshift;
426 outb(p->hub6 - 1 + offset, p->iobase);
427 return inb(p->iobase + 1);
430 static void hub6_serial_out(struct uart_port *p, int offset, int value)
432 offset = offset << p->regshift;
433 outb(p->hub6 - 1 + offset, p->iobase);
434 outb(value, p->iobase + 1);
437 static unsigned int mem_serial_in(struct uart_port *p, int offset)
439 offset = offset << p->regshift;
440 return readb(p->membase + offset);
443 static void mem_serial_out(struct uart_port *p, int offset, int value)
445 offset = offset << p->regshift;
446 writeb(value, p->membase + offset);
449 static void mem32_serial_out(struct uart_port *p, int offset, int value)
451 offset = offset << p->regshift;
452 writel(value, p->membase + offset);
455 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
457 offset = offset << p->regshift;
458 return readl(p->membase + offset);
461 static unsigned int io_serial_in(struct uart_port *p, int offset)
463 offset = offset << p->regshift;
464 return inb(p->iobase + offset);
467 static void io_serial_out(struct uart_port *p, int offset, int value)
469 offset = offset << p->regshift;
470 outb(value, p->iobase + offset);
473 static int serial8250_default_handle_irq(struct uart_port *port);
474 static int exar_handle_irq(struct uart_port *port);
476 static void set_io_from_upio(struct uart_port *p)
478 struct uart_8250_port *up =
479 container_of(p, struct uart_8250_port, port);
481 up->dl_read = default_serial_dl_read;
482 up->dl_write = default_serial_dl_write;
486 p->serial_in = hub6_serial_in;
487 p->serial_out = hub6_serial_out;
491 p->serial_in = mem_serial_in;
492 p->serial_out = mem_serial_out;
496 p->serial_in = mem32_serial_in;
497 p->serial_out = mem32_serial_out;
500 #ifdef CONFIG_SERIAL_8250_RM9K
502 p->serial_in = rm9k_serial_in;
503 p->serial_out = rm9k_serial_out;
504 up->dl_read = rm9k_serial_dl_read;
505 up->dl_write = rm9k_serial_dl_write;
509 #ifdef CONFIG_MIPS_ALCHEMY
511 p->serial_in = au_serial_in;
512 p->serial_out = au_serial_out;
513 up->dl_read = au_serial_dl_read;
514 up->dl_write = au_serial_dl_write;
519 p->serial_in = io_serial_in;
520 p->serial_out = io_serial_out;
523 /* Remember loaded iotype */
524 up->cur_iotype = p->iotype;
525 p->handle_irq = serial8250_default_handle_irq;
529 serial_port_out_sync(struct uart_port *p, int offset, int value)
535 p->serial_out(p, offset, value);
536 p->serial_in(p, UART_LCR); /* safe, no side-effects */
539 p->serial_out(p, offset, value);
546 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
548 serial_out(up, UART_SCR, offset);
549 serial_out(up, UART_ICR, value);
552 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
556 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
557 serial_out(up, UART_SCR, offset);
558 value = serial_in(up, UART_ICR);
559 serial_icr_write(up, UART_ACR, up->acr);
567 static void serial8250_clear_fifos(struct uart_8250_port *p)
569 if (p->capabilities & UART_CAP_FIFO) {
570 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
571 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
572 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
573 serial_out(p, UART_FCR, 0);
577 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
581 serial8250_clear_fifos(p);
582 fcr = uart_config[p->port.type].fcr;
583 serial_out(p, UART_FCR, fcr);
585 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
588 * IER sleep support. UARTs which have EFRs need the "extended
589 * capability" bit enabled. Note that on XR16C850s, we need to
590 * reset LCR to write to IER.
592 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
595 * Exar UARTs have a SLEEP register that enables or disables
596 * each UART to enter sleep mode separately. On the XR17V35x the
597 * register is accessible to each UART at the UART_EXAR_SLEEP
598 * offset but the UART channel may only write to the corresponding
601 if ((p->port.type == PORT_XR17V35X) ||
602 (p->port.type == PORT_XR17D15X)) {
603 serial_out(p, UART_EXAR_SLEEP, 0xff);
607 if (p->capabilities & UART_CAP_SLEEP) {
608 if (p->capabilities & UART_CAP_EFR) {
609 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
610 serial_out(p, UART_EFR, UART_EFR_ECB);
611 serial_out(p, UART_LCR, 0);
613 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
614 if (p->capabilities & UART_CAP_EFR) {
615 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
616 serial_out(p, UART_EFR, 0);
617 serial_out(p, UART_LCR, 0);
622 #ifdef CONFIG_SERIAL_8250_RSA
624 * Attempts to turn on the RSA FIFO. Returns zero on failure.
625 * We set the port uart clock rate if we succeed.
627 static int __enable_rsa(struct uart_8250_port *up)
632 mode = serial_in(up, UART_RSA_MSR);
633 result = mode & UART_RSA_MSR_FIFO;
636 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
637 mode = serial_in(up, UART_RSA_MSR);
638 result = mode & UART_RSA_MSR_FIFO;
642 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
647 static void enable_rsa(struct uart_8250_port *up)
649 if (up->port.type == PORT_RSA) {
650 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
651 spin_lock_irq(&up->port.lock);
653 spin_unlock_irq(&up->port.lock);
655 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
656 serial_out(up, UART_RSA_FRR, 0);
661 * Attempts to turn off the RSA FIFO. Returns zero on failure.
662 * It is unknown why interrupts were disabled in here. However,
663 * the caller is expected to preserve this behaviour by grabbing
664 * the spinlock before calling this function.
666 static void disable_rsa(struct uart_8250_port *up)
671 if (up->port.type == PORT_RSA &&
672 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
673 spin_lock_irq(&up->port.lock);
675 mode = serial_in(up, UART_RSA_MSR);
676 result = !(mode & UART_RSA_MSR_FIFO);
679 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
680 mode = serial_in(up, UART_RSA_MSR);
681 result = !(mode & UART_RSA_MSR_FIFO);
685 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
686 spin_unlock_irq(&up->port.lock);
689 #endif /* CONFIG_SERIAL_8250_RSA */
692 * This is a quickie test to see how big the FIFO is.
693 * It doesn't work at all the time, more's the pity.
695 static int size_fifo(struct uart_8250_port *up)
697 unsigned char old_fcr, old_mcr, old_lcr;
698 unsigned short old_dl;
701 old_lcr = serial_in(up, UART_LCR);
702 serial_out(up, UART_LCR, 0);
703 old_fcr = serial_in(up, UART_FCR);
704 old_mcr = serial_in(up, UART_MCR);
705 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
706 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
707 serial_out(up, UART_MCR, UART_MCR_LOOP);
708 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
709 old_dl = serial_dl_read(up);
710 serial_dl_write(up, 0x0001);
711 serial_out(up, UART_LCR, 0x03);
712 for (count = 0; count < 256; count++)
713 serial_out(up, UART_TX, count);
714 mdelay(20);/* FIXME - schedule_timeout */
715 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
716 (count < 256); count++)
717 serial_in(up, UART_RX);
718 serial_out(up, UART_FCR, old_fcr);
719 serial_out(up, UART_MCR, old_mcr);
720 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
721 serial_dl_write(up, old_dl);
722 serial_out(up, UART_LCR, old_lcr);
728 * Read UART ID using the divisor method - set DLL and DLM to zero
729 * and the revision will be in DLL and device type in DLM. We
730 * preserve the device state across this.
732 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
734 unsigned char old_dll, old_dlm, old_lcr;
737 old_lcr = serial_in(p, UART_LCR);
738 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
740 old_dll = serial_in(p, UART_DLL);
741 old_dlm = serial_in(p, UART_DLM);
743 serial_out(p, UART_DLL, 0);
744 serial_out(p, UART_DLM, 0);
746 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
748 serial_out(p, UART_DLL, old_dll);
749 serial_out(p, UART_DLM, old_dlm);
750 serial_out(p, UART_LCR, old_lcr);
756 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
757 * When this function is called we know it is at least a StarTech
758 * 16650 V2, but it might be one of several StarTech UARTs, or one of
759 * its clones. (We treat the broken original StarTech 16650 V1 as a
760 * 16550, and why not? Startech doesn't seem to even acknowledge its
763 * What evil have men's minds wrought...
765 static void autoconfig_has_efr(struct uart_8250_port *up)
767 unsigned int id1, id2, id3, rev;
770 * Everything with an EFR has SLEEP
772 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
775 * First we check to see if it's an Oxford Semiconductor UART.
777 * If we have to do this here because some non-National
778 * Semiconductor clone chips lock up if you try writing to the
779 * LSR register (which serial_icr_read does)
783 * Check for Oxford Semiconductor 16C950.
785 * EFR [4] must be set else this test fails.
787 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
788 * claims that it's needed for 952 dual UART's (which are not
789 * recommended for new designs).
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
793 serial_out(up, UART_EFR, UART_EFR_ECB);
794 serial_out(up, UART_LCR, 0x00);
795 id1 = serial_icr_read(up, UART_ID1);
796 id2 = serial_icr_read(up, UART_ID2);
797 id3 = serial_icr_read(up, UART_ID3);
798 rev = serial_icr_read(up, UART_REV);
800 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
802 if (id1 == 0x16 && id2 == 0xC9 &&
803 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
804 up->port.type = PORT_16C950;
807 * Enable work around for the Oxford Semiconductor 952 rev B
808 * chip which causes it to seriously miscalculate baud rates
811 if (id3 == 0x52 && rev == 0x01)
812 up->bugs |= UART_BUG_QUOT;
817 * We check for a XR16C850 by setting DLL and DLM to 0, and then
818 * reading back DLL and DLM. The chip type depends on the DLM
820 * 0x10 - XR16C850 and the DLL contains the chip revision.
824 id1 = autoconfig_read_divisor_id(up);
825 DEBUG_AUTOCONF("850id=%04x ", id1);
828 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
829 up->port.type = PORT_16850;
834 * It wasn't an XR16C850.
836 * We distinguish between the '654 and the '650 by counting
837 * how many bytes are in the FIFO. I'm using this for now,
838 * since that's the technique that was sent to me in the
839 * serial driver update, but I'm not convinced this works.
840 * I've had problems doing this in the past. -TYT
842 if (size_fifo(up) == 64)
843 up->port.type = PORT_16654;
845 up->port.type = PORT_16650V2;
849 * We detected a chip without a FIFO. Only two fall into
850 * this category - the original 8250 and the 16450. The
851 * 16450 has a scratch register (accessible with LCR=0)
853 static void autoconfig_8250(struct uart_8250_port *up)
855 unsigned char scratch, status1, status2;
857 up->port.type = PORT_8250;
859 scratch = serial_in(up, UART_SCR);
860 serial_out(up, UART_SCR, 0xa5);
861 status1 = serial_in(up, UART_SCR);
862 serial_out(up, UART_SCR, 0x5a);
863 status2 = serial_in(up, UART_SCR);
864 serial_out(up, UART_SCR, scratch);
866 if (status1 == 0xa5 && status2 == 0x5a)
867 up->port.type = PORT_16450;
870 static int broken_efr(struct uart_8250_port *up)
873 * Exar ST16C2550 "A2" devices incorrectly detect as
874 * having an EFR, and report an ID of 0x0201. See
875 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
877 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
883 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
885 unsigned char status;
887 status = serial_in(up, 0x04); /* EXCR2 */
888 #define PRESL(x) ((x) & 0x30)
889 if (PRESL(status) == 0x10) {
890 /* already in high speed mode */
893 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
894 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
895 serial_out(up, 0x04, status);
901 * We know that the chip has FIFOs. Does it have an EFR? The
902 * EFR is located in the same register position as the IIR and
903 * we know the top two bits of the IIR are currently set. The
904 * EFR should contain zero. Try to read the EFR.
906 static void autoconfig_16550a(struct uart_8250_port *up)
908 unsigned char status1, status2;
909 unsigned int iersave;
911 up->port.type = PORT_16550A;
912 up->capabilities |= UART_CAP_FIFO;
915 * XR17V35x UARTs have an extra divisor register, DLD
916 * that gets enabled with when DLAB is set which will
917 * cause the device to incorrectly match and assign
918 * port type to PORT_16650. The EFR for this UART is
919 * found at offset 0x09. Instead check the Deice ID (DVID)
920 * register for a 2, 4 or 8 port UART.
922 if (up->port.flags & UPF_EXAR_EFR) {
923 status1 = serial_in(up, UART_EXAR_DVID);
924 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
925 DEBUG_AUTOCONF("Exar XR17V35x ");
926 up->port.type = PORT_XR17V35X;
927 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
936 * Check for presence of the EFR when DLAB is set.
937 * Only ST16C650V1 UARTs pass this test.
939 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
940 if (serial_in(up, UART_EFR) == 0) {
941 serial_out(up, UART_EFR, 0xA8);
942 if (serial_in(up, UART_EFR) != 0) {
943 DEBUG_AUTOCONF("EFRv1 ");
944 up->port.type = PORT_16650;
945 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
947 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
949 serial_out(up, UART_EFR, 0);
954 * Maybe it requires 0xbf to be written to the LCR.
955 * (other ST16C650V2 UARTs, TI16C752A, etc)
957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
958 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
959 DEBUG_AUTOCONF("EFRv2 ");
960 autoconfig_has_efr(up);
965 * Check for a National Semiconductor SuperIO chip.
966 * Attempt to switch to bank 2, read the value of the LOOP bit
967 * from EXCR1. Switch back to bank 0, change it in MCR. Then
968 * switch back to bank 2, read it from EXCR1 again and check
969 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
971 serial_out(up, UART_LCR, 0);
972 status1 = serial_in(up, UART_MCR);
973 serial_out(up, UART_LCR, 0xE0);
974 status2 = serial_in(up, 0x02); /* EXCR1 */
976 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
977 serial_out(up, UART_LCR, 0);
978 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
979 serial_out(up, UART_LCR, 0xE0);
980 status2 = serial_in(up, 0x02); /* EXCR1 */
981 serial_out(up, UART_LCR, 0);
982 serial_out(up, UART_MCR, status1);
984 if ((status2 ^ status1) & UART_MCR_LOOP) {
987 serial_out(up, UART_LCR, 0xE0);
989 quot = serial_dl_read(up);
992 if (ns16550a_goto_highspeed(up))
993 serial_dl_write(up, quot);
995 serial_out(up, UART_LCR, 0);
997 up->port.uartclk = 921600*16;
998 up->port.type = PORT_NS16550A;
999 up->capabilities |= UART_NATSEMI;
1005 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1006 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1007 * Try setting it with and without DLAB set. Cheap clones
1008 * set bit 5 without DLAB set.
1010 serial_out(up, UART_LCR, 0);
1011 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1012 status1 = serial_in(up, UART_IIR) >> 5;
1013 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1014 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1015 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1016 status2 = serial_in(up, UART_IIR) >> 5;
1017 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1018 serial_out(up, UART_LCR, 0);
1020 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1022 if (status1 == 6 && status2 == 7) {
1023 up->port.type = PORT_16750;
1024 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1029 * Try writing and reading the UART_IER_UUE bit (b6).
1030 * If it works, this is probably one of the Xscale platform's
1032 * We're going to explicitly set the UUE bit to 0 before
1033 * trying to write and read a 1 just to make sure it's not
1034 * already a 1 and maybe locked there before we even start start.
1036 iersave = serial_in(up, UART_IER);
1037 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1038 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1040 * OK it's in a known zero state, try writing and reading
1041 * without disturbing the current state of the other bits.
1043 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1044 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1047 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1049 DEBUG_AUTOCONF("Xscale ");
1050 up->port.type = PORT_XSCALE;
1051 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1056 * If we got here we couldn't force the IER_UUE bit to 0.
1057 * Log it and continue.
1059 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1061 serial_out(up, UART_IER, iersave);
1064 * Exar uarts have EFR in a weird location
1066 if (up->port.flags & UPF_EXAR_EFR) {
1067 DEBUG_AUTOCONF("Exar XR17D15x ");
1068 up->port.type = PORT_XR17D15X;
1069 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1076 * We distinguish between 16550A and U6 16550A by counting
1077 * how many bytes are in the FIFO.
1079 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1080 up->port.type = PORT_U6_16550A;
1081 up->capabilities |= UART_CAP_AFE;
1086 * This routine is called by rs_init() to initialize a specific serial
1087 * port. It determines what type of UART chip this serial port is
1088 * using: 8250, 16450, 16550, 16550A. The important question is
1089 * whether or not this UART is a 16550A or not, since this will
1090 * determine whether or not we can use its FIFO features or not.
1092 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1094 unsigned char status1, scratch, scratch2, scratch3;
1095 unsigned char save_lcr, save_mcr;
1096 struct uart_port *port = &up->port;
1097 unsigned long flags;
1098 unsigned int old_capabilities;
1100 if (!port->iobase && !port->mapbase && !port->membase)
1103 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1104 serial_index(port), port->iobase, port->membase);
1107 * We really do need global IRQs disabled here - we're going to
1108 * be frobbing the chips IRQ enable register to see if it exists.
1110 spin_lock_irqsave(&port->lock, flags);
1112 up->capabilities = 0;
1115 if (!(port->flags & UPF_BUGGY_UART)) {
1117 * Do a simple existence test first; if we fail this,
1118 * there's no point trying anything else.
1120 * 0x80 is used as a nonsense port to prevent against
1121 * false positives due to ISA bus float. The
1122 * assumption is that 0x80 is a non-existent port;
1123 * which should be safe since include/asm/io.h also
1124 * makes this assumption.
1126 * Note: this is safe as long as MCR bit 4 is clear
1127 * and the device is in "PC" mode.
1129 scratch = serial_in(up, UART_IER);
1130 serial_out(up, UART_IER, 0);
1135 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1136 * 16C754B) allow only to modify them if an EFR bit is set.
1138 scratch2 = serial_in(up, UART_IER) & 0x0f;
1139 serial_out(up, UART_IER, 0x0F);
1143 scratch3 = serial_in(up, UART_IER) & 0x0f;
1144 serial_out(up, UART_IER, scratch);
1145 if (scratch2 != 0 || scratch3 != 0x0F) {
1147 * We failed; there's nothing here
1149 spin_unlock_irqrestore(&port->lock, flags);
1150 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1151 scratch2, scratch3);
1156 save_mcr = serial_in(up, UART_MCR);
1157 save_lcr = serial_in(up, UART_LCR);
1160 * Check to see if a UART is really there. Certain broken
1161 * internal modems based on the Rockwell chipset fail this
1162 * test, because they apparently don't implement the loopback
1163 * test mode. So this test is skipped on the COM 1 through
1164 * COM 4 ports. This *should* be safe, since no board
1165 * manufacturer would be stupid enough to design a board
1166 * that conflicts with COM 1-4 --- we hope!
1168 if (!(port->flags & UPF_SKIP_TEST)) {
1169 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1170 status1 = serial_in(up, UART_MSR) & 0xF0;
1171 serial_out(up, UART_MCR, save_mcr);
1172 if (status1 != 0x90) {
1173 spin_unlock_irqrestore(&port->lock, flags);
1174 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1181 * We're pretty sure there's a port here. Lets find out what
1182 * type of port it is. The IIR top two bits allows us to find
1183 * out if it's 8250 or 16450, 16550, 16550A or later. This
1184 * determines what we test for next.
1186 * We also initialise the EFR (if any) to zero for later. The
1187 * EFR occupies the same register location as the FCR and IIR.
1189 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1190 serial_out(up, UART_EFR, 0);
1191 serial_out(up, UART_LCR, 0);
1193 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1194 scratch = serial_in(up, UART_IIR) >> 6;
1198 autoconfig_8250(up);
1201 port->type = PORT_UNKNOWN;
1204 port->type = PORT_16550;
1207 autoconfig_16550a(up);
1211 #ifdef CONFIG_SERIAL_8250_RSA
1213 * Only probe for RSA ports if we got the region.
1215 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1218 for (i = 0 ; i < probe_rsa_count; ++i) {
1219 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1220 port->type = PORT_RSA;
1227 serial_out(up, UART_LCR, save_lcr);
1229 port->fifosize = uart_config[up->port.type].fifo_size;
1230 old_capabilities = up->capabilities;
1231 up->capabilities = uart_config[port->type].flags;
1232 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1234 if (port->type == PORT_UNKNOWN)
1240 #ifdef CONFIG_SERIAL_8250_RSA
1241 if (port->type == PORT_RSA)
1242 serial_out(up, UART_RSA_FRR, 0);
1244 serial_out(up, UART_MCR, save_mcr);
1245 serial8250_clear_fifos(up);
1246 serial_in(up, UART_RX);
1247 if (up->capabilities & UART_CAP_UUE)
1248 serial_out(up, UART_IER, UART_IER_UUE);
1250 serial_out(up, UART_IER, 0);
1253 spin_unlock_irqrestore(&port->lock, flags);
1254 if (up->capabilities != old_capabilities) {
1256 "ttyS%d: detected caps %08x should be %08x\n",
1257 serial_index(port), old_capabilities,
1261 DEBUG_AUTOCONF("iir=%d ", scratch);
1262 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1265 static void autoconfig_irq(struct uart_8250_port *up)
1267 struct uart_port *port = &up->port;
1268 unsigned char save_mcr, save_ier;
1269 unsigned char save_ICP = 0;
1270 unsigned int ICP = 0;
1274 if (port->flags & UPF_FOURPORT) {
1275 ICP = (port->iobase & 0xfe0) | 0x1f;
1276 save_ICP = inb_p(ICP);
1281 /* forget possible initially masked and pending IRQ */
1282 probe_irq_off(probe_irq_on());
1283 save_mcr = serial_in(up, UART_MCR);
1284 save_ier = serial_in(up, UART_IER);
1285 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1287 irqs = probe_irq_on();
1288 serial_out(up, UART_MCR, 0);
1290 if (port->flags & UPF_FOURPORT) {
1291 serial_out(up, UART_MCR,
1292 UART_MCR_DTR | UART_MCR_RTS);
1294 serial_out(up, UART_MCR,
1295 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1297 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1298 serial_in(up, UART_LSR);
1299 serial_in(up, UART_RX);
1300 serial_in(up, UART_IIR);
1301 serial_in(up, UART_MSR);
1302 serial_out(up, UART_TX, 0xFF);
1304 irq = probe_irq_off(irqs);
1306 serial_out(up, UART_MCR, save_mcr);
1307 serial_out(up, UART_IER, save_ier);
1309 if (port->flags & UPF_FOURPORT)
1310 outb_p(save_ICP, ICP);
1312 port->irq = (irq > 0) ? irq : 0;
1315 static inline void __stop_tx(struct uart_8250_port *p)
1317 if (p->ier & UART_IER_THRI) {
1318 p->ier &= ~UART_IER_THRI;
1319 serial_out(p, UART_IER, p->ier);
1323 static void serial8250_stop_tx(struct uart_port *port)
1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1331 * We really want to stop the transmitter from sending.
1333 if (port->type == PORT_16C950) {
1334 up->acr |= UART_ACR_TXDIS;
1335 serial_icr_write(up, UART_ACR, up->acr);
1339 static void serial8250_start_tx(struct uart_port *port)
1341 struct uart_8250_port *up =
1342 container_of(port, struct uart_8250_port, port);
1344 if (!(up->ier & UART_IER_THRI)) {
1345 up->ier |= UART_IER_THRI;
1346 serial_port_out(port, UART_IER, up->ier);
1348 if (up->bugs & UART_BUG_TXEN) {
1350 lsr = serial_in(up, UART_LSR);
1351 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1352 if ((port->type == PORT_RM9000) ?
1353 (lsr & UART_LSR_THRE) :
1354 (lsr & UART_LSR_TEMT))
1355 serial8250_tx_chars(up);
1360 * Re-enable the transmitter if we disabled it.
1362 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1363 up->acr &= ~UART_ACR_TXDIS;
1364 serial_icr_write(up, UART_ACR, up->acr);
1368 static void serial8250_stop_rx(struct uart_port *port)
1370 struct uart_8250_port *up =
1371 container_of(port, struct uart_8250_port, port);
1373 up->ier &= ~UART_IER_RLSI;
1374 up->port.read_status_mask &= ~UART_LSR_DR;
1375 serial_port_out(port, UART_IER, up->ier);
1378 static void serial8250_enable_ms(struct uart_port *port)
1380 struct uart_8250_port *up =
1381 container_of(port, struct uart_8250_port, port);
1383 /* no MSR capabilities */
1384 if (up->bugs & UART_BUG_NOMSR)
1387 up->ier |= UART_IER_MSI;
1388 serial_port_out(port, UART_IER, up->ier);
1392 * serial8250_rx_chars: processes according to the passed in LSR
1393 * value, and returns the remaining LSR bits not handled
1394 * by this Rx routine.
1397 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1399 struct uart_port *port = &up->port;
1400 struct tty_struct *tty = port->state->port.tty;
1402 int max_count = 256;
1406 if (likely(lsr & UART_LSR_DR))
1407 ch = serial_in(up, UART_RX);
1410 * Intel 82571 has a Serial Over Lan device that will
1411 * set UART_LSR_BI without setting UART_LSR_DR when
1412 * it receives a break. To avoid reading from the
1413 * receive buffer without UART_LSR_DR bit set, we
1414 * just force the read character to be 0
1421 lsr |= up->lsr_saved_flags;
1422 up->lsr_saved_flags = 0;
1424 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1425 if (lsr & UART_LSR_BI) {
1426 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1429 * We do the SysRQ and SAK checking
1430 * here because otherwise the break
1431 * may get masked by ignore_status_mask
1432 * or read_status_mask.
1434 if (uart_handle_break(port))
1436 } else if (lsr & UART_LSR_PE)
1437 port->icount.parity++;
1438 else if (lsr & UART_LSR_FE)
1439 port->icount.frame++;
1440 if (lsr & UART_LSR_OE)
1441 port->icount.overrun++;
1444 * Mask off conditions which should be ignored.
1446 lsr &= port->read_status_mask;
1448 if (lsr & UART_LSR_BI) {
1449 DEBUG_INTR("handling break....");
1451 } else if (lsr & UART_LSR_PE)
1453 else if (lsr & UART_LSR_FE)
1456 if (uart_handle_sysrq_char(port, ch))
1459 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1462 lsr = serial_in(up, UART_LSR);
1463 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1464 spin_unlock(&port->lock);
1465 tty_flip_buffer_push(tty);
1466 spin_lock(&port->lock);
1469 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1471 void serial8250_tx_chars(struct uart_8250_port *up)
1473 struct uart_port *port = &up->port;
1474 struct circ_buf *xmit = &port->state->xmit;
1478 serial_out(up, UART_TX, port->x_char);
1483 if (uart_tx_stopped(port)) {
1484 serial8250_stop_tx(port);
1487 if (uart_circ_empty(xmit)) {
1492 count = up->tx_loadsz;
1494 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1495 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1497 if (uart_circ_empty(xmit))
1499 if (up->capabilities & UART_CAP_HFIFO) {
1500 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1504 } while (--count > 0);
1506 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1507 uart_write_wakeup(port);
1509 DEBUG_INTR("THRE...");
1511 if (uart_circ_empty(xmit))
1514 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1516 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1518 struct uart_port *port = &up->port;
1519 unsigned int status = serial_in(up, UART_MSR);
1521 status |= up->msr_saved_flags;
1522 up->msr_saved_flags = 0;
1523 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1524 port->state != NULL) {
1525 if (status & UART_MSR_TERI)
1527 if (status & UART_MSR_DDSR)
1529 if (status & UART_MSR_DDCD)
1530 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1531 if (status & UART_MSR_DCTS)
1532 uart_handle_cts_change(port, status & UART_MSR_CTS);
1534 wake_up_interruptible(&port->state->port.delta_msr_wait);
1539 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1542 * This handles the interrupt from one port.
1544 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1546 unsigned char status;
1547 unsigned long flags;
1548 struct uart_8250_port *up =
1549 container_of(port, struct uart_8250_port, port);
1551 if (iir & UART_IIR_NO_INT)
1554 spin_lock_irqsave(&port->lock, flags);
1556 status = serial_port_in(port, UART_LSR);
1558 DEBUG_INTR("status = %x...", status);
1560 if (status & (UART_LSR_DR | UART_LSR_BI))
1561 status = serial8250_rx_chars(up, status);
1562 serial8250_modem_status(up);
1563 if (status & UART_LSR_THRE)
1564 serial8250_tx_chars(up);
1566 spin_unlock_irqrestore(&port->lock, flags);
1569 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1571 static int serial8250_default_handle_irq(struct uart_port *port)
1573 unsigned int iir = serial_port_in(port, UART_IIR);
1575 return serial8250_handle_irq(port, iir);
1579 * These Exar UARTs have an extra interrupt indicator that could
1580 * fire for a few unimplemented interrupts. One of which is a
1581 * wakeup event when coming out of sleep. Put this here just
1582 * to be on the safe side that these interrupts don't go unhandled.
1584 static int exar_handle_irq(struct uart_port *port)
1586 unsigned char int0, int1, int2, int3;
1587 unsigned int iir = serial_port_in(port, UART_IIR);
1590 ret = serial8250_handle_irq(port, iir);
1592 if ((port->type == PORT_XR17V35X) ||
1593 (port->type == PORT_XR17D15X)) {
1594 int0 = serial_port_in(port, 0x80);
1595 int1 = serial_port_in(port, 0x81);
1596 int2 = serial_port_in(port, 0x82);
1597 int3 = serial_port_in(port, 0x83);
1604 * This is the serial driver's interrupt routine.
1606 * Arjan thinks the old way was overly complex, so it got simplified.
1607 * Alan disagrees, saying that need the complexity to handle the weird
1608 * nature of ISA shared interrupts. (This is a special exception.)
1610 * In order to handle ISA shared interrupts properly, we need to check
1611 * that all ports have been serviced, and therefore the ISA interrupt
1612 * line has been de-asserted.
1614 * This means we need to loop through all ports. checking that they
1615 * don't have an interrupt pending.
1617 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1619 struct irq_info *i = dev_id;
1620 struct list_head *l, *end = NULL;
1621 int pass_counter = 0, handled = 0;
1623 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1625 spin_lock(&i->lock);
1629 struct uart_8250_port *up;
1630 struct uart_port *port;
1632 up = list_entry(l, struct uart_8250_port, list);
1635 if (port->handle_irq(port)) {
1638 } else if (end == NULL)
1643 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1644 /* If we hit this, we're dead. */
1645 printk_ratelimited(KERN_ERR
1646 "serial8250: too much work for irq%d\n", irq);
1651 spin_unlock(&i->lock);
1653 DEBUG_INTR("end.\n");
1655 return IRQ_RETVAL(handled);
1659 * To support ISA shared interrupts, we need to have one interrupt
1660 * handler that ensures that the IRQ line has been deasserted
1661 * before returning. Failing to do this will result in the IRQ
1662 * line being stuck active, and, since ISA irqs are edge triggered,
1663 * no more IRQs will be seen.
1665 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1667 spin_lock_irq(&i->lock);
1669 if (!list_empty(i->head)) {
1670 if (i->head == &up->list)
1671 i->head = i->head->next;
1672 list_del(&up->list);
1674 BUG_ON(i->head != &up->list);
1677 spin_unlock_irq(&i->lock);
1678 /* List empty so throw away the hash node */
1679 if (i->head == NULL) {
1680 hlist_del(&i->node);
1685 static int serial_link_irq_chain(struct uart_8250_port *up)
1687 struct hlist_head *h;
1688 struct hlist_node *n;
1690 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1692 mutex_lock(&hash_mutex);
1694 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1696 hlist_for_each(n, h) {
1697 i = hlist_entry(n, struct irq_info, node);
1698 if (i->irq == up->port.irq)
1703 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1705 mutex_unlock(&hash_mutex);
1708 spin_lock_init(&i->lock);
1709 i->irq = up->port.irq;
1710 hlist_add_head(&i->node, h);
1712 mutex_unlock(&hash_mutex);
1714 spin_lock_irq(&i->lock);
1717 list_add(&up->list, i->head);
1718 spin_unlock_irq(&i->lock);
1722 INIT_LIST_HEAD(&up->list);
1723 i->head = &up->list;
1724 spin_unlock_irq(&i->lock);
1725 irq_flags |= up->port.irqflags;
1726 ret = request_irq(up->port.irq, serial8250_interrupt,
1727 irq_flags, "serial", i);
1729 serial_do_unlink(i, up);
1735 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1738 struct hlist_node *n;
1739 struct hlist_head *h;
1741 mutex_lock(&hash_mutex);
1743 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1745 hlist_for_each(n, h) {
1746 i = hlist_entry(n, struct irq_info, node);
1747 if (i->irq == up->port.irq)
1752 BUG_ON(i->head == NULL);
1754 if (list_empty(i->head))
1755 free_irq(up->port.irq, i);
1757 serial_do_unlink(i, up);
1758 mutex_unlock(&hash_mutex);
1762 * This function is used to handle ports that do not have an
1763 * interrupt. This doesn't work very well for 16450's, but gives
1764 * barely passable results for a 16550A. (Although at the expense
1765 * of much CPU overhead).
1767 static void serial8250_timeout(unsigned long data)
1769 struct uart_8250_port *up = (struct uart_8250_port *)data;
1771 up->port.handle_irq(&up->port);
1772 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1775 static void serial8250_backup_timeout(unsigned long data)
1777 struct uart_8250_port *up = (struct uart_8250_port *)data;
1778 unsigned int iir, ier = 0, lsr;
1779 unsigned long flags;
1781 spin_lock_irqsave(&up->port.lock, flags);
1784 * Must disable interrupts or else we risk racing with the interrupt
1788 ier = serial_in(up, UART_IER);
1789 serial_out(up, UART_IER, 0);
1792 iir = serial_in(up, UART_IIR);
1795 * This should be a safe test for anyone who doesn't trust the
1796 * IIR bits on their UART, but it's specifically designed for
1797 * the "Diva" UART used on the management processor on many HP
1798 * ia64 and parisc boxes.
1800 lsr = serial_in(up, UART_LSR);
1801 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1802 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1803 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1804 (lsr & UART_LSR_THRE)) {
1805 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1806 iir |= UART_IIR_THRI;
1809 if (!(iir & UART_IIR_NO_INT))
1810 serial8250_tx_chars(up);
1813 serial_out(up, UART_IER, ier);
1815 spin_unlock_irqrestore(&up->port.lock, flags);
1817 /* Standard timer interval plus 0.2s to keep the port running */
1818 mod_timer(&up->timer,
1819 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1822 static unsigned int serial8250_tx_empty(struct uart_port *port)
1824 struct uart_8250_port *up =
1825 container_of(port, struct uart_8250_port, port);
1826 unsigned long flags;
1829 spin_lock_irqsave(&port->lock, flags);
1830 lsr = serial_port_in(port, UART_LSR);
1831 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1832 spin_unlock_irqrestore(&port->lock, flags);
1834 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1837 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1839 struct uart_8250_port *up =
1840 container_of(port, struct uart_8250_port, port);
1841 unsigned int status;
1844 status = serial8250_modem_status(up);
1847 if (status & UART_MSR_DCD)
1849 if (status & UART_MSR_RI)
1851 if (status & UART_MSR_DSR)
1853 if (status & UART_MSR_CTS)
1858 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1860 struct uart_8250_port *up =
1861 container_of(port, struct uart_8250_port, port);
1862 unsigned char mcr = 0;
1864 if (mctrl & TIOCM_RTS)
1865 mcr |= UART_MCR_RTS;
1866 if (mctrl & TIOCM_DTR)
1867 mcr |= UART_MCR_DTR;
1868 if (mctrl & TIOCM_OUT1)
1869 mcr |= UART_MCR_OUT1;
1870 if (mctrl & TIOCM_OUT2)
1871 mcr |= UART_MCR_OUT2;
1872 if (mctrl & TIOCM_LOOP)
1873 mcr |= UART_MCR_LOOP;
1875 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1877 serial_port_out(port, UART_MCR, mcr);
1880 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1882 struct uart_8250_port *up =
1883 container_of(port, struct uart_8250_port, port);
1884 unsigned long flags;
1886 spin_lock_irqsave(&port->lock, flags);
1887 if (break_state == -1)
1888 up->lcr |= UART_LCR_SBC;
1890 up->lcr &= ~UART_LCR_SBC;
1891 serial_port_out(port, UART_LCR, up->lcr);
1892 spin_unlock_irqrestore(&port->lock, flags);
1896 * Wait for transmitter & holding register to empty
1898 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1900 unsigned int status, tmout = 10000;
1902 /* Wait up to 10ms for the character(s) to be sent. */
1904 status = serial_in(up, UART_LSR);
1906 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1908 if ((status & bits) == bits)
1915 /* Wait up to 1s for flow control if necessary */
1916 if (up->port.flags & UPF_CONS_FLOW) {
1918 for (tmout = 1000000; tmout; tmout--) {
1919 unsigned int msr = serial_in(up, UART_MSR);
1920 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1921 if (msr & UART_MSR_CTS)
1924 touch_nmi_watchdog();
1929 #ifdef CONFIG_CONSOLE_POLL
1931 * Console polling routines for writing and reading from the uart while
1932 * in an interrupt or debug context.
1935 static int serial8250_get_poll_char(struct uart_port *port)
1937 unsigned char lsr = serial_port_in(port, UART_LSR);
1939 if (!(lsr & UART_LSR_DR))
1940 return NO_POLL_CHAR;
1942 return serial_port_in(port, UART_RX);
1946 static void serial8250_put_poll_char(struct uart_port *port,
1950 struct uart_8250_port *up =
1951 container_of(port, struct uart_8250_port, port);
1954 * First save the IER then disable the interrupts
1956 ier = serial_port_in(port, UART_IER);
1957 if (up->capabilities & UART_CAP_UUE)
1958 serial_port_out(port, UART_IER, UART_IER_UUE);
1960 serial_port_out(port, UART_IER, 0);
1962 wait_for_xmitr(up, BOTH_EMPTY);
1964 * Send the character out.
1965 * If a LF, also do CR...
1967 serial_port_out(port, UART_TX, c);
1969 wait_for_xmitr(up, BOTH_EMPTY);
1970 serial_port_out(port, UART_TX, 13);
1974 * Finally, wait for transmitter to become empty
1975 * and restore the IER
1977 wait_for_xmitr(up, BOTH_EMPTY);
1978 serial_port_out(port, UART_IER, ier);
1981 #endif /* CONFIG_CONSOLE_POLL */
1983 static int serial8250_startup(struct uart_port *port)
1985 struct uart_8250_port *up =
1986 container_of(port, struct uart_8250_port, port);
1987 unsigned long flags;
1988 unsigned char lsr, iir;
1991 if (port->type == PORT_8250_CIR)
1994 port->fifosize = uart_config[up->port.type].fifo_size;
1995 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1996 up->capabilities = uart_config[up->port.type].flags;
1999 if (port->iotype != up->cur_iotype)
2000 set_io_from_upio(port);
2002 if (port->type == PORT_16C950) {
2003 /* Wake up and initialize UART */
2005 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2006 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2007 serial_port_out(port, UART_IER, 0);
2008 serial_port_out(port, UART_LCR, 0);
2009 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2010 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2011 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2012 serial_port_out(port, UART_LCR, 0);
2015 #ifdef CONFIG_SERIAL_8250_RSA
2017 * If this is an RSA port, see if we can kick it up to the
2018 * higher speed clock.
2024 * Clear the FIFO buffers and disable them.
2025 * (they will be reenabled in set_termios())
2027 serial8250_clear_fifos(up);
2030 * Clear the interrupt registers.
2032 serial_port_in(port, UART_LSR);
2033 serial_port_in(port, UART_RX);
2034 serial_port_in(port, UART_IIR);
2035 serial_port_in(port, UART_MSR);
2038 * At this point, there's no way the LSR could still be 0xff;
2039 * if it is, then bail out, because there's likely no UART
2042 if (!(port->flags & UPF_BUGGY_UART) &&
2043 (serial_port_in(port, UART_LSR) == 0xff)) {
2044 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2045 serial_index(port));
2050 * For a XR16C850, we need to set the trigger levels
2052 if (port->type == PORT_16850) {
2055 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2057 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2058 serial_port_out(port, UART_FCTR,
2059 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2060 serial_port_out(port, UART_TRG, UART_TRG_96);
2061 serial_port_out(port, UART_FCTR,
2062 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2063 serial_port_out(port, UART_TRG, UART_TRG_96);
2065 serial_port_out(port, UART_LCR, 0);
2071 * Test for UARTs that do not reassert THRE when the
2072 * transmitter is idle and the interrupt has already
2073 * been cleared. Real 16550s should always reassert
2074 * this interrupt whenever the transmitter is idle and
2075 * the interrupt is enabled. Delays are necessary to
2076 * allow register changes to become visible.
2078 spin_lock_irqsave(&port->lock, flags);
2079 if (up->port.irqflags & IRQF_SHARED)
2080 disable_irq_nosync(port->irq);
2082 wait_for_xmitr(up, UART_LSR_THRE);
2083 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2084 udelay(1); /* allow THRE to set */
2085 iir1 = serial_port_in(port, UART_IIR);
2086 serial_port_out(port, UART_IER, 0);
2087 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2088 udelay(1); /* allow a working UART time to re-assert THRE */
2089 iir = serial_port_in(port, UART_IIR);
2090 serial_port_out(port, UART_IER, 0);
2092 if (port->irqflags & IRQF_SHARED)
2093 enable_irq(port->irq);
2094 spin_unlock_irqrestore(&port->lock, flags);
2097 * If the interrupt is not reasserted, or we otherwise
2098 * don't trust the iir, setup a timer to kick the UART
2099 * on a regular basis.
2101 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2102 up->port.flags & UPF_BUG_THRE) {
2103 up->bugs |= UART_BUG_THRE;
2104 pr_debug("ttyS%d - using backup timer\n",
2105 serial_index(port));
2110 * The above check will only give an accurate result the first time
2111 * the port is opened so this value needs to be preserved.
2113 if (up->bugs & UART_BUG_THRE) {
2114 up->timer.function = serial8250_backup_timeout;
2115 up->timer.data = (unsigned long)up;
2116 mod_timer(&up->timer, jiffies +
2117 uart_poll_timeout(port) + HZ / 5);
2121 * If the "interrupt" for this port doesn't correspond with any
2122 * hardware interrupt, we use a timer-based system. The original
2123 * driver used to do this with IRQ0.
2126 up->timer.data = (unsigned long)up;
2127 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2129 retval = serial_link_irq_chain(up);
2135 * Now, initialize the UART
2137 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2139 spin_lock_irqsave(&port->lock, flags);
2140 if (up->port.flags & UPF_FOURPORT) {
2142 up->port.mctrl |= TIOCM_OUT1;
2145 * Most PC uarts need OUT2 raised to enable interrupts.
2148 up->port.mctrl |= TIOCM_OUT2;
2150 serial8250_set_mctrl(port, port->mctrl);
2152 /* Serial over Lan (SoL) hack:
2153 Intel 8257x Gigabit ethernet chips have a
2154 16550 emulation, to be used for Serial Over Lan.
2155 Those chips take a longer time than a normal
2156 serial device to signalize that a transmission
2157 data was queued. Due to that, the above test generally
2158 fails. One solution would be to delay the reading of
2159 iir. However, this is not reliable, since the timeout
2160 is variable. So, let's just don't test if we receive
2161 TX irq. This way, we'll never enable UART_BUG_TXEN.
2163 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2164 goto dont_test_tx_en;
2167 * Do a quick test to see if we receive an
2168 * interrupt when we enable the TX irq.
2170 serial_port_out(port, UART_IER, UART_IER_THRI);
2171 lsr = serial_port_in(port, UART_LSR);
2172 iir = serial_port_in(port, UART_IIR);
2173 serial_port_out(port, UART_IER, 0);
2175 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2176 if (!(up->bugs & UART_BUG_TXEN)) {
2177 up->bugs |= UART_BUG_TXEN;
2178 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2179 serial_index(port));
2182 up->bugs &= ~UART_BUG_TXEN;
2186 spin_unlock_irqrestore(&port->lock, flags);
2189 * Clear the interrupt registers again for luck, and clear the
2190 * saved flags to avoid getting false values from polling
2191 * routines or the previous session.
2193 serial_port_in(port, UART_LSR);
2194 serial_port_in(port, UART_RX);
2195 serial_port_in(port, UART_IIR);
2196 serial_port_in(port, UART_MSR);
2197 up->lsr_saved_flags = 0;
2198 up->msr_saved_flags = 0;
2201 * Finally, enable interrupts. Note: Modem status interrupts
2202 * are set via set_termios(), which will be occurring imminently
2203 * anyway, so we don't enable them here.
2205 up->ier = UART_IER_RLSI | UART_IER_RDI;
2206 serial_port_out(port, UART_IER, up->ier);
2208 if (port->flags & UPF_FOURPORT) {
2211 * Enable interrupts on the AST Fourport board
2213 icp = (port->iobase & 0xfe0) | 0x01f;
2221 static void serial8250_shutdown(struct uart_port *port)
2223 struct uart_8250_port *up =
2224 container_of(port, struct uart_8250_port, port);
2225 unsigned long flags;
2228 * Disable interrupts from this port
2231 serial_port_out(port, UART_IER, 0);
2233 spin_lock_irqsave(&port->lock, flags);
2234 if (port->flags & UPF_FOURPORT) {
2235 /* reset interrupts on the AST Fourport board */
2236 inb((port->iobase & 0xfe0) | 0x1f);
2237 port->mctrl |= TIOCM_OUT1;
2239 port->mctrl &= ~TIOCM_OUT2;
2241 serial8250_set_mctrl(port, port->mctrl);
2242 spin_unlock_irqrestore(&port->lock, flags);
2245 * Disable break condition and FIFOs
2247 serial_port_out(port, UART_LCR,
2248 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2249 serial8250_clear_fifos(up);
2251 #ifdef CONFIG_SERIAL_8250_RSA
2253 * Reset the RSA board back to 115kbps compat mode.
2259 * Read data port to reset things, and then unlink from
2262 serial_port_in(port, UART_RX);
2264 del_timer_sync(&up->timer);
2265 up->timer.function = serial8250_timeout;
2267 serial_unlink_irq_chain(up);
2270 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2275 * Handle magic divisors for baud rates above baud_base on
2276 * SMSC SuperIO chips.
2278 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2279 baud == (port->uartclk/4))
2281 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2282 baud == (port->uartclk/8))
2285 quot = uart_get_divisor(port, baud);
2291 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2292 struct ktermios *old)
2294 struct uart_8250_port *up =
2295 container_of(port, struct uart_8250_port, port);
2296 unsigned char cval, fcr = 0;
2297 unsigned long flags;
2298 unsigned int baud, quot;
2301 switch (termios->c_cflag & CSIZE) {
2303 cval = UART_LCR_WLEN5;
2306 cval = UART_LCR_WLEN6;
2309 cval = UART_LCR_WLEN7;
2313 cval = UART_LCR_WLEN8;
2317 if (termios->c_cflag & CSTOPB)
2318 cval |= UART_LCR_STOP;
2319 if (termios->c_cflag & PARENB) {
2320 cval |= UART_LCR_PARITY;
2321 if (up->bugs & UART_BUG_PARITY)
2324 if (!(termios->c_cflag & PARODD))
2325 cval |= UART_LCR_EPAR;
2327 if (termios->c_cflag & CMSPAR)
2328 cval |= UART_LCR_SPAR;
2332 * Ask the core to calculate the divisor for us.
2334 baud = uart_get_baud_rate(port, termios, old,
2335 port->uartclk / 16 / 0xffff,
2336 port->uartclk / 16);
2337 quot = serial8250_get_divisor(port, baud);
2340 * Oxford Semi 952 rev B workaround
2342 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2345 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2346 fcr = uart_config[port->type].fcr;
2347 if (baud < 2400 || fifo_bug) {
2348 fcr &= ~UART_FCR_TRIGGER_MASK;
2349 fcr |= UART_FCR_TRIGGER_1;
2354 * MCR-based auto flow control. When AFE is enabled, RTS will be
2355 * deasserted when the receive FIFO contains more characters than
2356 * the trigger, or the MCR RTS bit is cleared. In the case where
2357 * the remote UART is not using CTS auto flow control, we must
2358 * have sufficient FIFO entries for the latency of the remote
2359 * UART to respond. IOW, at least 32 bytes of FIFO.
2361 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2362 up->mcr &= ~UART_MCR_AFE;
2363 if (termios->c_cflag & CRTSCTS)
2364 up->mcr |= UART_MCR_AFE;
2368 * Ok, we're now changing the port state. Do it with
2369 * interrupts disabled.
2371 spin_lock_irqsave(&port->lock, flags);
2374 * Update the per-port timeout.
2376 uart_update_timeout(port, termios->c_cflag, baud);
2378 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2379 if (termios->c_iflag & INPCK)
2380 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2381 if (termios->c_iflag & (BRKINT | PARMRK))
2382 port->read_status_mask |= UART_LSR_BI;
2385 * Characteres to ignore
2387 port->ignore_status_mask = 0;
2388 if (termios->c_iflag & IGNPAR)
2389 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2390 if (termios->c_iflag & IGNBRK) {
2391 port->ignore_status_mask |= UART_LSR_BI;
2393 * If we're ignoring parity and break indicators,
2394 * ignore overruns too (for real raw support).
2396 if (termios->c_iflag & IGNPAR)
2397 port->ignore_status_mask |= UART_LSR_OE;
2401 * ignore all characters if CREAD is not set
2403 if ((termios->c_cflag & CREAD) == 0)
2404 port->ignore_status_mask |= UART_LSR_DR;
2407 * CTS flow control flag and modem status interrupts
2409 up->ier &= ~UART_IER_MSI;
2410 if (!(up->bugs & UART_BUG_NOMSR) &&
2411 UART_ENABLE_MS(&up->port, termios->c_cflag))
2412 up->ier |= UART_IER_MSI;
2413 if (up->capabilities & UART_CAP_UUE)
2414 up->ier |= UART_IER_UUE;
2415 if (up->capabilities & UART_CAP_RTOIE)
2416 up->ier |= UART_IER_RTOIE;
2418 serial_port_out(port, UART_IER, up->ier);
2420 if (up->capabilities & UART_CAP_EFR) {
2421 unsigned char efr = 0;
2423 * TI16C752/Startech hardware flow control. FIXME:
2424 * - TI16C752 requires control thresholds to be set.
2425 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2427 if (termios->c_cflag & CRTSCTS)
2428 efr |= UART_EFR_CTS;
2430 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2431 if (port->flags & UPF_EXAR_EFR)
2432 serial_port_out(port, UART_XR_EFR, efr);
2434 serial_port_out(port, UART_EFR, efr);
2437 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2438 if (is_omap1510_8250(up)) {
2439 if (baud == 115200) {
2441 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2443 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2447 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2448 * otherwise just set DLAB
2450 if (up->capabilities & UART_NATSEMI)
2451 serial_port_out(port, UART_LCR, 0xe0);
2453 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2455 serial_dl_write(up, quot);
2458 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2459 * is written without DLAB set, this mode will be disabled.
2461 if (port->type == PORT_16750)
2462 serial_port_out(port, UART_FCR, fcr);
2464 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2465 up->lcr = cval; /* Save LCR */
2466 if (port->type != PORT_16750) {
2467 /* emulated UARTs (Lucent Venus 167x) need two steps */
2468 if (fcr & UART_FCR_ENABLE_FIFO)
2469 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2470 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2472 serial8250_set_mctrl(port, port->mctrl);
2473 spin_unlock_irqrestore(&port->lock, flags);
2474 /* Don't rewrite B0 */
2475 if (tty_termios_baud_rate(termios))
2476 tty_termios_encode_baud_rate(termios, baud, baud);
2478 EXPORT_SYMBOL(serial8250_do_set_termios);
2481 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2482 struct ktermios *old)
2484 if (port->set_termios)
2485 port->set_termios(port, termios, old);
2487 serial8250_do_set_termios(port, termios, old);
2491 serial8250_set_ldisc(struct uart_port *port, int new)
2494 port->flags |= UPF_HARDPPS_CD;
2495 serial8250_enable_ms(port);
2497 port->flags &= ~UPF_HARDPPS_CD;
2501 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2502 unsigned int oldstate)
2504 struct uart_8250_port *p =
2505 container_of(port, struct uart_8250_port, port);
2507 serial8250_set_sleep(p, state != 0);
2509 EXPORT_SYMBOL(serial8250_do_pm);
2512 serial8250_pm(struct uart_port *port, unsigned int state,
2513 unsigned int oldstate)
2516 port->pm(port, state, oldstate);
2518 serial8250_do_pm(port, state, oldstate);
2521 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2523 if (pt->port.iotype == UPIO_AU)
2525 if (is_omap1_8250(pt))
2526 return 0x16 << pt->port.regshift;
2528 return 8 << pt->port.regshift;
2532 * Resource handling.
2534 static int serial8250_request_std_resource(struct uart_8250_port *up)
2536 unsigned int size = serial8250_port_size(up);
2537 struct uart_port *port = &up->port;
2540 switch (port->iotype) {
2548 if (!request_mem_region(port->mapbase, size, "serial")) {
2553 if (port->flags & UPF_IOREMAP) {
2554 port->membase = ioremap_nocache(port->mapbase, size);
2555 if (!port->membase) {
2556 release_mem_region(port->mapbase, size);
2564 if (!request_region(port->iobase, size, "serial"))
2571 static void serial8250_release_std_resource(struct uart_8250_port *up)
2573 unsigned int size = serial8250_port_size(up);
2574 struct uart_port *port = &up->port;
2576 switch (port->iotype) {
2584 if (port->flags & UPF_IOREMAP) {
2585 iounmap(port->membase);
2586 port->membase = NULL;
2589 release_mem_region(port->mapbase, size);
2594 release_region(port->iobase, size);
2599 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2601 unsigned long start = UART_RSA_BASE << up->port.regshift;
2602 unsigned int size = 8 << up->port.regshift;
2603 struct uart_port *port = &up->port;
2606 switch (port->iotype) {
2609 start += port->iobase;
2610 if (request_region(start, size, "serial-rsa"))
2620 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2622 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2623 unsigned int size = 8 << up->port.regshift;
2624 struct uart_port *port = &up->port;
2626 switch (port->iotype) {
2629 release_region(port->iobase + offset, size);
2634 static void serial8250_release_port(struct uart_port *port)
2636 struct uart_8250_port *up =
2637 container_of(port, struct uart_8250_port, port);
2639 serial8250_release_std_resource(up);
2640 if (port->type == PORT_RSA)
2641 serial8250_release_rsa_resource(up);
2644 static int serial8250_request_port(struct uart_port *port)
2646 struct uart_8250_port *up =
2647 container_of(port, struct uart_8250_port, port);
2650 if (port->type == PORT_8250_CIR)
2653 ret = serial8250_request_std_resource(up);
2654 if (ret == 0 && port->type == PORT_RSA) {
2655 ret = serial8250_request_rsa_resource(up);
2657 serial8250_release_std_resource(up);
2663 static void serial8250_config_port(struct uart_port *port, int flags)
2665 struct uart_8250_port *up =
2666 container_of(port, struct uart_8250_port, port);
2667 int probeflags = PROBE_ANY;
2670 if (port->type == PORT_8250_CIR)
2674 * Find the region that we can probe for. This in turn
2675 * tells us whether we can probe for the type of port.
2677 ret = serial8250_request_std_resource(up);
2681 ret = serial8250_request_rsa_resource(up);
2683 probeflags &= ~PROBE_RSA;
2685 if (port->iotype != up->cur_iotype)
2686 set_io_from_upio(port);
2688 if (flags & UART_CONFIG_TYPE)
2689 autoconfig(up, probeflags);
2691 /* if access method is AU, it is a 16550 with a quirk */
2692 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2693 up->bugs |= UART_BUG_NOMSR;
2695 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2698 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2699 serial8250_release_rsa_resource(up);
2700 if (port->type == PORT_UNKNOWN)
2701 serial8250_release_std_resource(up);
2703 /* Fixme: probably not the best place for this */
2704 if ((port->type == PORT_XR17V35X) ||
2705 (port->type == PORT_XR17D15X))
2706 port->handle_irq = exar_handle_irq;
2710 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2712 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2713 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2714 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2715 ser->type == PORT_STARTECH)
2721 serial8250_type(struct uart_port *port)
2723 int type = port->type;
2725 if (type >= ARRAY_SIZE(uart_config))
2727 return uart_config[type].name;
2730 static struct uart_ops serial8250_pops = {
2731 .tx_empty = serial8250_tx_empty,
2732 .set_mctrl = serial8250_set_mctrl,
2733 .get_mctrl = serial8250_get_mctrl,
2734 .stop_tx = serial8250_stop_tx,
2735 .start_tx = serial8250_start_tx,
2736 .stop_rx = serial8250_stop_rx,
2737 .enable_ms = serial8250_enable_ms,
2738 .break_ctl = serial8250_break_ctl,
2739 .startup = serial8250_startup,
2740 .shutdown = serial8250_shutdown,
2741 .set_termios = serial8250_set_termios,
2742 .set_ldisc = serial8250_set_ldisc,
2743 .pm = serial8250_pm,
2744 .type = serial8250_type,
2745 .release_port = serial8250_release_port,
2746 .request_port = serial8250_request_port,
2747 .config_port = serial8250_config_port,
2748 .verify_port = serial8250_verify_port,
2749 #ifdef CONFIG_CONSOLE_POLL
2750 .poll_get_char = serial8250_get_poll_char,
2751 .poll_put_char = serial8250_put_poll_char,
2755 static struct uart_8250_port serial8250_ports[UART_NR];
2757 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2758 unsigned short *capabilities);
2760 void serial8250_set_isa_configurator(
2761 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2763 serial8250_isa_config = v;
2765 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2767 static void __init serial8250_isa_init_ports(void)
2769 struct uart_8250_port *up;
2770 static int first = 1;
2777 if (nr_uarts > UART_NR)
2780 for (i = 0; i < nr_uarts; i++) {
2781 struct uart_8250_port *up = &serial8250_ports[i];
2782 struct uart_port *port = &up->port;
2785 spin_lock_init(&port->lock);
2787 init_timer(&up->timer);
2788 up->timer.function = serial8250_timeout;
2789 up->cur_iotype = 0xFF;
2792 * ALPHA_KLUDGE_MCR needs to be killed.
2794 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2795 up->mcr_force = ALPHA_KLUDGE_MCR;
2797 port->ops = &serial8250_pops;
2801 irqflag = IRQF_SHARED;
2803 for (i = 0, up = serial8250_ports;
2804 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2806 struct uart_port *port = &up->port;
2808 port->iobase = old_serial_port[i].port;
2809 port->irq = irq_canonicalize(old_serial_port[i].irq);
2810 port->irqflags = old_serial_port[i].irqflags;
2811 port->uartclk = old_serial_port[i].baud_base * 16;
2812 port->flags = old_serial_port[i].flags;
2813 port->hub6 = old_serial_port[i].hub6;
2814 port->membase = old_serial_port[i].iomem_base;
2815 port->iotype = old_serial_port[i].io_type;
2816 port->regshift = old_serial_port[i].iomem_reg_shift;
2817 set_io_from_upio(port);
2818 port->irqflags |= irqflag;
2819 if (serial8250_isa_config != NULL)
2820 serial8250_isa_config(i, &up->port, &up->capabilities);
2826 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2828 up->port.type = type;
2829 up->port.fifosize = uart_config[type].fifo_size;
2830 up->capabilities = uart_config[type].flags;
2831 up->tx_loadsz = uart_config[type].tx_loadsz;
2835 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2839 for (i = 0; i < nr_uarts; i++) {
2840 struct uart_8250_port *up = &serial8250_ports[i];
2847 if (up->port.flags & UPF_FIXED_TYPE)
2848 serial8250_init_fixed_type_port(up, up->port.type);
2850 uart_add_one_port(drv, &up->port);
2854 #ifdef CONFIG_SERIAL_8250_CONSOLE
2856 static void serial8250_console_putchar(struct uart_port *port, int ch)
2858 struct uart_8250_port *up =
2859 container_of(port, struct uart_8250_port, port);
2861 wait_for_xmitr(up, UART_LSR_THRE);
2862 serial_port_out(port, UART_TX, ch);
2866 * Print a string to the serial port trying not to disturb
2867 * any possible real use of the port...
2869 * The console_lock must be held when we get here.
2872 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2874 struct uart_8250_port *up = &serial8250_ports[co->index];
2875 struct uart_port *port = &up->port;
2876 unsigned long flags;
2880 touch_nmi_watchdog();
2882 local_irq_save(flags);
2884 /* serial8250_handle_irq() already took the lock */
2886 } else if (oops_in_progress) {
2887 locked = spin_trylock(&port->lock);
2889 spin_lock(&port->lock);
2892 * First save the IER then disable the interrupts
2894 ier = serial_port_in(port, UART_IER);
2896 if (up->capabilities & UART_CAP_UUE)
2897 serial_port_out(port, UART_IER, UART_IER_UUE);
2899 serial_port_out(port, UART_IER, 0);
2901 uart_console_write(port, s, count, serial8250_console_putchar);
2904 * Finally, wait for transmitter to become empty
2905 * and restore the IER
2907 wait_for_xmitr(up, BOTH_EMPTY);
2908 serial_port_out(port, UART_IER, ier);
2911 * The receive handling will happen properly because the
2912 * receive ready bit will still be set; it is not cleared
2913 * on read. However, modem control will not, we must
2914 * call it if we have saved something in the saved flags
2915 * while processing with interrupts off.
2917 if (up->msr_saved_flags)
2918 serial8250_modem_status(up);
2921 spin_unlock(&port->lock);
2922 local_irq_restore(flags);
2925 static int __init serial8250_console_setup(struct console *co, char *options)
2927 struct uart_port *port;
2934 * Check whether an invalid uart number has been specified, and
2935 * if so, search for the first available port that does have
2938 if (co->index >= nr_uarts)
2940 port = &serial8250_ports[co->index].port;
2941 if (!port->iobase && !port->membase)
2945 uart_parse_options(options, &baud, &parity, &bits, &flow);
2947 return uart_set_options(port, co, baud, parity, bits, flow);
2950 static int serial8250_console_early_setup(void)
2952 return serial8250_find_port_for_earlycon();
2955 static struct console serial8250_console = {
2957 .write = serial8250_console_write,
2958 .device = uart_console_device,
2959 .setup = serial8250_console_setup,
2960 .early_setup = serial8250_console_early_setup,
2961 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2963 .data = &serial8250_reg,
2966 static int __init serial8250_console_init(void)
2968 serial8250_isa_init_ports();
2969 register_console(&serial8250_console);
2972 console_initcall(serial8250_console_init);
2974 int serial8250_find_port(struct uart_port *p)
2977 struct uart_port *port;
2979 for (line = 0; line < nr_uarts; line++) {
2980 port = &serial8250_ports[line].port;
2981 if (uart_match_port(p, port))
2987 #define SERIAL8250_CONSOLE &serial8250_console
2989 #define SERIAL8250_CONSOLE NULL
2992 static struct uart_driver serial8250_reg = {
2993 .owner = THIS_MODULE,
2994 .driver_name = "serial",
2998 .cons = SERIAL8250_CONSOLE,
3002 * early_serial_setup - early registration for 8250 ports
3004 * Setup an 8250 port structure prior to console initialisation. Use
3005 * after console initialisation will cause undefined behaviour.
3007 int __init early_serial_setup(struct uart_port *port)
3009 struct uart_port *p;
3011 if (port->line >= ARRAY_SIZE(serial8250_ports))
3014 serial8250_isa_init_ports();
3015 p = &serial8250_ports[port->line].port;
3016 p->iobase = port->iobase;
3017 p->membase = port->membase;
3019 p->irqflags = port->irqflags;
3020 p->uartclk = port->uartclk;
3021 p->fifosize = port->fifosize;
3022 p->regshift = port->regshift;
3023 p->iotype = port->iotype;
3024 p->flags = port->flags;
3025 p->mapbase = port->mapbase;
3026 p->private_data = port->private_data;
3027 p->type = port->type;
3028 p->line = port->line;
3030 set_io_from_upio(p);
3031 if (port->serial_in)
3032 p->serial_in = port->serial_in;
3033 if (port->serial_out)
3034 p->serial_out = port->serial_out;
3035 if (port->handle_irq)
3036 p->handle_irq = port->handle_irq;
3038 p->handle_irq = serial8250_default_handle_irq;
3044 * serial8250_suspend_port - suspend one serial port
3045 * @line: serial line number
3047 * Suspend one serial port.
3049 void serial8250_suspend_port(int line)
3051 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3055 * serial8250_resume_port - resume one serial port
3056 * @line: serial line number
3058 * Resume one serial port.
3060 void serial8250_resume_port(int line)
3062 struct uart_8250_port *up = &serial8250_ports[line];
3063 struct uart_port *port = &up->port;
3065 if (up->capabilities & UART_NATSEMI) {
3066 /* Ensure it's still in high speed mode */
3067 serial_port_out(port, UART_LCR, 0xE0);
3069 ns16550a_goto_highspeed(up);
3071 serial_port_out(port, UART_LCR, 0);
3072 port->uartclk = 921600*16;
3074 uart_resume_port(&serial8250_reg, port);
3078 * Register a set of serial devices attached to a platform device. The
3079 * list is terminated with a zero flags entry, which means we expect
3080 * all entries to have at least UPF_BOOT_AUTOCONF set.
3082 static int serial8250_probe(struct platform_device *dev)
3084 struct plat_serial8250_port *p = dev->dev.platform_data;
3085 struct uart_8250_port uart;
3086 int ret, i, irqflag = 0;
3088 memset(&uart, 0, sizeof(uart));
3091 irqflag = IRQF_SHARED;
3093 for (i = 0; p && p->flags != 0; p++, i++) {
3094 uart.port.iobase = p->iobase;
3095 uart.port.membase = p->membase;
3096 uart.port.irq = p->irq;
3097 uart.port.irqflags = p->irqflags;
3098 uart.port.uartclk = p->uartclk;
3099 uart.port.regshift = p->regshift;
3100 uart.port.iotype = p->iotype;
3101 uart.port.flags = p->flags;
3102 uart.port.mapbase = p->mapbase;
3103 uart.port.hub6 = p->hub6;
3104 uart.port.private_data = p->private_data;
3105 uart.port.type = p->type;
3106 uart.port.serial_in = p->serial_in;
3107 uart.port.serial_out = p->serial_out;
3108 uart.port.handle_irq = p->handle_irq;
3109 uart.port.handle_break = p->handle_break;
3110 uart.port.set_termios = p->set_termios;
3111 uart.port.pm = p->pm;
3112 uart.port.dev = &dev->dev;
3113 uart.port.irqflags |= irqflag;
3114 ret = serial8250_register_8250_port(&uart);
3116 dev_err(&dev->dev, "unable to register port at index %d "
3117 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3118 p->iobase, (unsigned long long)p->mapbase,
3126 * Remove serial ports registered against a platform device.
3128 static int serial8250_remove(struct platform_device *dev)
3132 for (i = 0; i < nr_uarts; i++) {
3133 struct uart_8250_port *up = &serial8250_ports[i];
3135 if (up->port.dev == &dev->dev)
3136 serial8250_unregister_port(i);
3141 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3145 for (i = 0; i < UART_NR; i++) {
3146 struct uart_8250_port *up = &serial8250_ports[i];
3148 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3149 uart_suspend_port(&serial8250_reg, &up->port);
3155 static int serial8250_resume(struct platform_device *dev)
3159 for (i = 0; i < UART_NR; i++) {
3160 struct uart_8250_port *up = &serial8250_ports[i];
3162 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3163 serial8250_resume_port(i);
3169 static struct platform_driver serial8250_isa_driver = {
3170 .probe = serial8250_probe,
3171 .remove = serial8250_remove,
3172 .suspend = serial8250_suspend,
3173 .resume = serial8250_resume,
3175 .name = "serial8250",
3176 .owner = THIS_MODULE,
3181 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3182 * in the table in include/asm/serial.h
3184 static struct platform_device *serial8250_isa_devs;
3187 * serial8250_register_8250_port and serial8250_unregister_port allows for
3188 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3189 * modems and PCI multiport cards.
3191 static DEFINE_MUTEX(serial_mutex);
3193 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3198 * First, find a port entry which matches.
3200 for (i = 0; i < nr_uarts; i++)
3201 if (uart_match_port(&serial8250_ports[i].port, port))
3202 return &serial8250_ports[i];
3205 * We didn't find a matching entry, so look for the first
3206 * free entry. We look for one which hasn't been previously
3207 * used (indicated by zero iobase).
3209 for (i = 0; i < nr_uarts; i++)
3210 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3211 serial8250_ports[i].port.iobase == 0)
3212 return &serial8250_ports[i];
3215 * That also failed. Last resort is to find any entry which
3216 * doesn't have a real port associated with it.
3218 for (i = 0; i < nr_uarts; i++)
3219 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3220 return &serial8250_ports[i];
3226 * serial8250_register_8250_port - register a serial port
3227 * @up: serial port template
3229 * Configure the serial port specified by the request. If the
3230 * port exists and is in use, it is hung up and unregistered
3233 * The port is then probed and if necessary the IRQ is autodetected
3234 * If this fails an error is returned.
3236 * On success the port is ready to use and the line number is returned.
3238 int serial8250_register_8250_port(struct uart_8250_port *up)
3240 struct uart_8250_port *uart;
3243 if (up->port.uartclk == 0)
3246 mutex_lock(&serial_mutex);
3248 uart = serial8250_find_match_or_unused(&up->port);
3249 if (uart && uart->port.type != PORT_8250_CIR) {
3251 uart_remove_one_port(&serial8250_reg, &uart->port);
3253 uart->port.iobase = up->port.iobase;
3254 uart->port.membase = up->port.membase;
3255 uart->port.irq = up->port.irq;
3256 uart->port.irqflags = up->port.irqflags;
3257 uart->port.uartclk = up->port.uartclk;
3258 uart->port.fifosize = up->port.fifosize;
3259 uart->port.regshift = up->port.regshift;
3260 uart->port.iotype = up->port.iotype;
3261 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3262 uart->bugs = up->bugs;
3263 uart->port.mapbase = up->port.mapbase;
3264 uart->port.private_data = up->port.private_data;
3266 uart->port.dev = up->port.dev;
3268 if (up->port.flags & UPF_FIXED_TYPE)
3269 serial8250_init_fixed_type_port(uart, up->port.type);
3271 set_io_from_upio(&uart->port);
3272 /* Possibly override default I/O functions. */
3273 if (up->port.serial_in)
3274 uart->port.serial_in = up->port.serial_in;
3275 if (up->port.serial_out)
3276 uart->port.serial_out = up->port.serial_out;
3277 if (up->port.handle_irq)
3278 uart->port.handle_irq = up->port.handle_irq;
3279 /* Possibly override set_termios call */
3280 if (up->port.set_termios)
3281 uart->port.set_termios = up->port.set_termios;
3283 uart->port.pm = up->port.pm;
3284 if (up->port.handle_break)
3285 uart->port.handle_break = up->port.handle_break;
3287 uart->dl_read = up->dl_read;
3289 uart->dl_write = up->dl_write;
3291 if (serial8250_isa_config != NULL)
3292 serial8250_isa_config(0, &uart->port,
3293 &uart->capabilities);
3295 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3297 ret = uart->port.line;
3299 mutex_unlock(&serial_mutex);
3303 EXPORT_SYMBOL(serial8250_register_8250_port);
3306 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3307 * @line: serial line number
3309 * Remove one serial port. This may not be called from interrupt
3310 * context. We hand the port back to the our control.
3312 void serial8250_unregister_port(int line)
3314 struct uart_8250_port *uart = &serial8250_ports[line];
3316 mutex_lock(&serial_mutex);
3317 uart_remove_one_port(&serial8250_reg, &uart->port);
3318 if (serial8250_isa_devs) {
3319 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3320 uart->port.type = PORT_UNKNOWN;
3321 uart->port.dev = &serial8250_isa_devs->dev;
3322 uart->capabilities = uart_config[uart->port.type].flags;
3323 uart_add_one_port(&serial8250_reg, &uart->port);
3325 uart->port.dev = NULL;
3327 mutex_unlock(&serial_mutex);
3329 EXPORT_SYMBOL(serial8250_unregister_port);
3331 static int __init serial8250_init(void)
3335 serial8250_isa_init_ports();
3337 printk(KERN_INFO "Serial: 8250/16550 driver, "
3338 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3339 share_irqs ? "en" : "dis");
3342 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3344 serial8250_reg.nr = UART_NR;
3345 ret = uart_register_driver(&serial8250_reg);
3350 ret = serial8250_pnp_init();
3352 goto unreg_uart_drv;
3354 serial8250_isa_devs = platform_device_alloc("serial8250",
3355 PLAT8250_DEV_LEGACY);
3356 if (!serial8250_isa_devs) {
3361 ret = platform_device_add(serial8250_isa_devs);
3365 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3367 ret = platform_driver_register(&serial8250_isa_driver);
3371 platform_device_del(serial8250_isa_devs);
3373 platform_device_put(serial8250_isa_devs);
3375 serial8250_pnp_exit();
3378 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3380 uart_unregister_driver(&serial8250_reg);
3386 static void __exit serial8250_exit(void)
3388 struct platform_device *isa_dev = serial8250_isa_devs;
3391 * This tells serial8250_unregister_port() not to re-register
3392 * the ports (thereby making serial8250_isa_driver permanently
3395 serial8250_isa_devs = NULL;
3397 platform_driver_unregister(&serial8250_isa_driver);
3398 platform_device_unregister(isa_dev);
3400 serial8250_pnp_exit();
3403 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3405 uart_unregister_driver(&serial8250_reg);
3409 module_init(serial8250_init);
3410 module_exit(serial8250_exit);
3412 EXPORT_SYMBOL(serial8250_suspend_port);
3413 EXPORT_SYMBOL(serial8250_resume_port);
3415 MODULE_LICENSE("GPL");
3416 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3418 module_param(share_irqs, uint, 0644);
3419 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3422 module_param(nr_uarts, uint, 0644);
3423 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3425 module_param(skip_txen_test, uint, 0644);
3426 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3428 #ifdef CONFIG_SERIAL_8250_RSA
3429 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3430 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3432 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);