2 * 8250_dma.c - DMA Engine API support for 8250.c
4 * Copyright (C) 2013 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #include <linux/tty.h>
12 #include <linux/tty_flip.h>
13 #include <linux/serial_reg.h>
14 #include <linux/dma-mapping.h>
18 static void __dma_tx_complete(void *param)
20 struct uart_8250_port *p = param;
21 struct uart_8250_dma *dma = p->dma;
22 struct circ_buf *xmit = &p->port.state->xmit;
26 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
27 UART_XMIT_SIZE, DMA_TO_DEVICE);
29 spin_lock_irqsave(&p->port.lock, flags);
33 xmit->tail += dma->tx_size;
34 xmit->tail &= UART_XMIT_SIZE - 1;
35 p->port.icount.tx += dma->tx_size;
37 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
38 uart_write_wakeup(&p->port);
40 ret = serial8250_tx_dma(p);
42 p->ier |= UART_IER_THRI;
43 serial_port_out(&p->port, UART_IER, p->ier);
46 spin_unlock_irqrestore(&p->port.lock, flags);
49 static void __dma_rx_complete(void *param)
51 struct uart_8250_port *p = param;
52 struct uart_8250_dma *dma = p->dma;
53 struct tty_port *tty_port = &p->port.state->port;
54 struct dma_tx_state state;
58 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
60 count = dma->rx_size - state.residue;
62 tty_insert_flip_string(tty_port, dma->rx_buf, count);
63 p->port.icount.rx += count;
65 tty_flip_buffer_push(tty_port);
68 int serial8250_tx_dma(struct uart_8250_port *p)
70 struct uart_8250_dma *dma = p->dma;
71 struct circ_buf *xmit = &p->port.state->xmit;
72 struct dma_async_tx_descriptor *desc;
75 if (uart_tx_stopped(&p->port) || dma->tx_running ||
76 uart_circ_empty(xmit))
79 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
81 desc = dmaengine_prep_slave_single(dma->txchan,
82 dma->tx_addr + xmit->tail,
83 dma->tx_size, DMA_MEM_TO_DEV,
84 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
91 desc->callback = __dma_tx_complete;
92 desc->callback_param = p;
94 dma->tx_cookie = dmaengine_submit(desc);
96 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
97 UART_XMIT_SIZE, DMA_TO_DEVICE);
99 dma_async_issue_pending(dma->txchan);
102 if (p->ier & UART_IER_THRI) {
103 p->ier &= ~UART_IER_THRI;
104 serial_out(p, UART_IER, p->ier);
113 int serial8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
115 struct uart_8250_dma *dma = p->dma;
116 struct dma_async_tx_descriptor *desc;
118 switch (iir & 0x3f) {
120 /* 8250_core handles errors and break interrupts */
122 case UART_IIR_RX_TIMEOUT:
124 * If RCVR FIFO trigger level was not reached, complete the
125 * transfer and let 8250_core copy the remaining data.
127 if (dma->rx_running) {
128 dmaengine_pause(dma->rxchan);
129 __dma_rx_complete(p);
130 dmaengine_terminate_all(dma->rxchan);
140 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
141 dma->rx_size, DMA_DEV_TO_MEM,
142 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
147 desc->callback = __dma_rx_complete;
148 desc->callback_param = p;
150 dma->rx_cookie = dmaengine_submit(desc);
152 dma_async_issue_pending(dma->rxchan);
157 int serial8250_request_dma(struct uart_8250_port *p)
159 struct uart_8250_dma *dma = p->dma;
162 /* Default slave configuration parameters */
163 dma->rxconf.direction = DMA_DEV_TO_MEM;
164 dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
165 dma->rxconf.src_addr = p->port.mapbase + UART_RX;
167 dma->txconf.direction = DMA_MEM_TO_DEV;
168 dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
169 dma->txconf.dst_addr = p->port.mapbase + UART_TX;
172 dma_cap_set(DMA_SLAVE, mask);
174 /* Get a channel for RX */
175 dma->rxchan = dma_request_slave_channel_compat(mask,
176 dma->fn, dma->rx_param,
181 dmaengine_slave_config(dma->rxchan, &dma->rxconf);
183 /* Get a channel for TX */
184 dma->txchan = dma_request_slave_channel_compat(mask,
185 dma->fn, dma->tx_param,
188 dma_release_channel(dma->rxchan);
192 dmaengine_slave_config(dma->txchan, &dma->txconf);
196 dma->rx_size = PAGE_SIZE;
198 dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
199 &dma->rx_addr, GFP_KERNEL);
204 dma->tx_addr = dma_map_single(dma->txchan->device->dev,
205 p->port.state->xmit.buf,
208 if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) {
209 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size,
210 dma->rx_buf, dma->rx_addr);
214 dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
218 dma_release_channel(dma->rxchan);
219 dma_release_channel(dma->txchan);
223 EXPORT_SYMBOL_GPL(serial8250_request_dma);
225 void serial8250_release_dma(struct uart_8250_port *p)
227 struct uart_8250_dma *dma = p->dma;
232 /* Release RX resources */
233 dmaengine_terminate_all(dma->rxchan);
234 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
236 dma_release_channel(dma->rxchan);
239 /* Release TX resources */
240 dmaengine_terminate_all(dma->txchan);
241 dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
242 UART_XMIT_SIZE, DMA_TO_DEVICE);
243 dma_release_channel(dma->txchan);
247 dev_dbg_ratelimited(p->port.dev, "dma channels released\n");
249 EXPORT_SYMBOL_GPL(serial8250_release_dma);