2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/acpi.h>
27 #include <linux/clk.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
31 #include <asm/byteorder.h>
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
38 #define DW_UART_UCV 0xf8 /* UART Component Version */
40 /* Component Parameter Register bits */
41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42 #define DW_UART_CPR_AFCE_MODE (1 << 4)
43 #define DW_UART_CPR_THRE_MODE (1 << 5)
44 #define DW_UART_CPR_SIR_MODE (1 << 6)
45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48 #define DW_UART_CPR_FIFO_STAT (1 << 10)
49 #define DW_UART_CPR_SHADOW (1 << 11)
50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
52 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
53 /* Helper for fifo size calculation */
54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
67 unsigned int skip_autocfg:1;
68 unsigned int uart_16550_compatible:1;
71 #define BYT_PRV_CLK 0x800
72 #define BYT_PRV_CLK_EN (1 << 0)
73 #define BYT_PRV_CLK_M_VAL_SHIFT 1
74 #define BYT_PRV_CLK_N_VAL_SHIFT 16
75 #define BYT_PRV_CLK_UPDATE (1 << 31)
77 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
79 struct dw8250_data *d = p->private_data;
81 /* Override any modem control signals if needed */
82 if (offset == UART_MSR) {
83 value |= d->msr_mask_on;
84 value &= ~d->msr_mask_off;
90 static void dw8250_force_idle(struct uart_port *p)
92 struct uart_8250_port *up = up_to_u8250p(p);
94 serial8250_clear_and_reinit_fifos(up);
95 (void)p->serial_in(p, UART_RX);
98 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
100 writeb(value, p->membase + (offset << p->regshift));
102 /* Make sure LCR write wasn't ignored */
103 if (offset == UART_LCR) {
106 unsigned int lcr = p->serial_in(p, UART_LCR);
107 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
109 dw8250_force_idle(p);
110 writeb(value, p->membase + (UART_LCR << p->regshift));
113 * FIXME: this deadlocks if port->lock is already held
114 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
119 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
121 unsigned int value = readb(p->membase + (offset << p->regshift));
123 return dw8250_modify_msr(p, offset, value);
127 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
131 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
133 return dw8250_modify_msr(p, offset, value);
136 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
139 __raw_writeq(value, p->membase + (offset << p->regshift));
140 /* Read back to ensure register write ordering. */
141 __raw_readq(p->membase + (UART_LCR << p->regshift));
143 /* Make sure LCR write wasn't ignored */
144 if (offset == UART_LCR) {
147 unsigned int lcr = p->serial_in(p, UART_LCR);
148 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
150 dw8250_force_idle(p);
151 __raw_writeq(value & 0xff,
152 p->membase + (UART_LCR << p->regshift));
155 * FIXME: this deadlocks if port->lock is already held
156 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
160 #endif /* CONFIG_64BIT */
162 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
164 writel(value, p->membase + (offset << p->regshift));
166 /* Make sure LCR write wasn't ignored */
167 if (offset == UART_LCR) {
170 unsigned int lcr = p->serial_in(p, UART_LCR);
171 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
173 dw8250_force_idle(p);
174 writel(value, p->membase + (UART_LCR << p->regshift));
177 * FIXME: this deadlocks if port->lock is already held
178 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
183 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
185 unsigned int value = readl(p->membase + (offset << p->regshift));
187 return dw8250_modify_msr(p, offset, value);
190 static int dw8250_handle_irq(struct uart_port *p)
192 struct dw8250_data *d = p->private_data;
193 unsigned int iir = p->serial_in(p, UART_IIR);
195 if (serial8250_handle_irq(p, iir)) {
197 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
199 (void)p->serial_in(p, d->usr_reg);
208 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
211 pm_runtime_get_sync(port->dev);
213 serial8250_do_pm(port, state, old);
216 pm_runtime_put_sync_suspend(port->dev);
219 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
220 struct ktermios *old)
222 unsigned int baud = tty_termios_baud_rate(termios);
223 struct dw8250_data *d = p->private_data;
227 if (IS_ERR(d->clk) || !old)
230 /* Not requesting clock rates below 1.8432Mhz */
234 clk_disable_unprepare(d->clk);
235 rate = clk_round_rate(d->clk, baud * 16);
236 ret = clk_set_rate(d->clk, rate);
237 clk_prepare_enable(d->clk);
242 p->status &= ~UPSTAT_AUTOCTS;
243 if (termios->c_cflag & CRTSCTS)
244 p->status |= UPSTAT_AUTOCTS;
247 serial8250_do_set_termios(p, termios, old);
250 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
255 static void dw8250_setup_port(struct uart_8250_port *up)
257 struct uart_port *p = &up->port;
258 u32 reg = readl(p->membase + DW_UART_UCV);
261 * If the Component Version Register returns zero, we know that
262 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
267 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
268 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
270 reg = readl(p->membase + DW_UART_CPR);
274 /* Select the type based on fifo */
275 if (reg & DW_UART_CPR_FIFO_MODE) {
276 p->type = PORT_16550A;
277 p->flags |= UPF_FIXED_TYPE;
278 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
279 up->tx_loadsz = p->fifosize;
280 up->capabilities = UART_CAP_FIFO;
283 if (reg & DW_UART_CPR_AFCE_MODE)
284 up->capabilities |= UART_CAP_AFE;
287 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
289 struct device *dev = param;
291 if (dev != chan->device->dev->parent)
297 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
299 if (p->dev->of_node) {
300 struct device_node *np = p->dev->of_node;
303 /* get index of serial line, if found in DT aliases */
304 id = of_alias_get_id(np, "serial");
308 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
309 p->serial_in = dw8250_serial_inq;
310 p->serial_out = dw8250_serial_outq;
311 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
312 p->type = PORT_OCTEON;
313 data->usr_reg = 0x27;
314 data->skip_autocfg = true;
317 } else if (has_acpi_companion(p->dev)) {
318 p->iotype = UPIO_MEM32;
320 p->serial_in = dw8250_serial_in32;
321 p->set_termios = dw8250_set_termios;
322 /* So far none of there implement the Busy Functionality */
323 data->uart_16550_compatible = true;
326 /* Platforms with iDMA */
327 if (platform_get_resource_byname(to_platform_device(p->dev),
328 IORESOURCE_MEM, "lpss_priv")) {
329 p->set_termios = dw8250_set_termios;
330 data->dma.rx_param = p->dev->parent;
331 data->dma.tx_param = p->dev->parent;
332 data->dma.fn = dw8250_idma_filter;
336 static int dw8250_probe(struct platform_device *pdev)
338 struct uart_8250_port uart = {};
339 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340 int irq = platform_get_irq(pdev, 0);
341 struct uart_port *p = &uart.port;
342 struct dw8250_data *data;
347 dev_err(&pdev->dev, "no registers defined\n");
352 if (irq != -EPROBE_DEFER)
353 dev_err(&pdev->dev, "cannot get irq\n");
357 spin_lock_init(&p->lock);
358 p->mapbase = regs->start;
360 p->handle_irq = dw8250_handle_irq;
361 p->pm = dw8250_do_pm;
363 p->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
365 p->iotype = UPIO_MEM;
366 p->serial_in = dw8250_serial_in;
367 p->serial_out = dw8250_serial_out;
369 p->membase = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
373 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
377 data->usr_reg = DW_UART_USR;
378 p->private_data = data;
380 data->uart_16550_compatible = device_property_read_bool(p->dev,
381 "snps,uart-16550-compatible");
383 err = device_property_read_u32(p->dev, "reg-shift", &val);
387 err = device_property_read_u32(p->dev, "reg-io-width", &val);
388 if (!err && val == 4) {
389 p->iotype = UPIO_MEM32;
390 p->serial_in = dw8250_serial_in32;
391 p->serial_out = dw8250_serial_out32;
394 if (device_property_read_bool(p->dev, "dcd-override")) {
395 /* Always report DCD as active */
396 data->msr_mask_on |= UART_MSR_DCD;
397 data->msr_mask_off |= UART_MSR_DDCD;
400 if (device_property_read_bool(p->dev, "dsr-override")) {
401 /* Always report DSR as active */
402 data->msr_mask_on |= UART_MSR_DSR;
403 data->msr_mask_off |= UART_MSR_DDSR;
406 if (device_property_read_bool(p->dev, "cts-override")) {
407 /* Always report CTS as active */
408 data->msr_mask_on |= UART_MSR_CTS;
409 data->msr_mask_off |= UART_MSR_DCTS;
412 if (device_property_read_bool(p->dev, "ri-override")) {
413 /* Always report Ring indicator as inactive */
414 data->msr_mask_off |= UART_MSR_RI;
415 data->msr_mask_off |= UART_MSR_TERI;
418 /* Always ask for fixed clock rate from a property. */
419 device_property_read_u32(p->dev, "clock-frequency", &p->uartclk);
421 /* If there is separate baudclk, get the rate from it. */
422 data->clk = devm_clk_get(&pdev->dev, "baudclk");
423 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
424 data->clk = devm_clk_get(&pdev->dev, NULL);
425 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
426 return -EPROBE_DEFER;
427 if (!IS_ERR_OR_NULL(data->clk)) {
428 err = clk_prepare_enable(data->clk);
430 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
433 p->uartclk = clk_get_rate(data->clk);
436 /* If no clock rate is defined, fail. */
438 dev_err(&pdev->dev, "clock rate not defined\n");
442 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
443 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
447 if (!IS_ERR(data->pclk)) {
448 err = clk_prepare_enable(data->pclk);
450 dev_err(&pdev->dev, "could not enable apb_pclk\n");
455 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
456 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
460 if (!IS_ERR(data->rst))
461 reset_control_deassert(data->rst);
463 data->dma.rx_param = data;
464 data->dma.tx_param = data;
465 data->dma.fn = dw8250_dma_filter;
467 dw8250_quirks(p, data);
469 /* If the Busy Functionality is not implemented, don't handle it */
470 if (data->uart_16550_compatible) {
471 p->serial_out = NULL;
472 p->handle_irq = NULL;
475 if (!data->skip_autocfg)
476 dw8250_setup_port(&uart);
478 /* If we have a valid fifosize, try hooking up DMA */
480 data->dma.rxconf.src_maxburst = p->fifosize / 4;
481 data->dma.txconf.dst_maxburst = p->fifosize / 4;
482 uart.dma = &data->dma;
485 data->line = serial8250_register_8250_port(&uart);
486 if (data->line < 0) {
491 platform_set_drvdata(pdev, data);
493 pm_runtime_set_active(&pdev->dev);
494 pm_runtime_enable(&pdev->dev);
499 if (!IS_ERR(data->rst))
500 reset_control_assert(data->rst);
503 if (!IS_ERR(data->pclk))
504 clk_disable_unprepare(data->pclk);
507 if (!IS_ERR(data->clk))
508 clk_disable_unprepare(data->clk);
513 static int dw8250_remove(struct platform_device *pdev)
515 struct dw8250_data *data = platform_get_drvdata(pdev);
517 pm_runtime_get_sync(&pdev->dev);
519 serial8250_unregister_port(data->line);
521 if (!IS_ERR(data->rst))
522 reset_control_assert(data->rst);
524 if (!IS_ERR(data->pclk))
525 clk_disable_unprepare(data->pclk);
527 if (!IS_ERR(data->clk))
528 clk_disable_unprepare(data->clk);
530 pm_runtime_disable(&pdev->dev);
531 pm_runtime_put_noidle(&pdev->dev);
536 #ifdef CONFIG_PM_SLEEP
537 static int dw8250_suspend(struct device *dev)
539 struct dw8250_data *data = dev_get_drvdata(dev);
541 serial8250_suspend_port(data->line);
546 static int dw8250_resume(struct device *dev)
548 struct dw8250_data *data = dev_get_drvdata(dev);
550 serial8250_resume_port(data->line);
554 #endif /* CONFIG_PM_SLEEP */
557 static int dw8250_runtime_suspend(struct device *dev)
559 struct dw8250_data *data = dev_get_drvdata(dev);
561 if (!IS_ERR(data->clk))
562 clk_disable_unprepare(data->clk);
564 if (!IS_ERR(data->pclk))
565 clk_disable_unprepare(data->pclk);
570 static int dw8250_runtime_resume(struct device *dev)
572 struct dw8250_data *data = dev_get_drvdata(dev);
574 if (!IS_ERR(data->pclk))
575 clk_prepare_enable(data->pclk);
577 if (!IS_ERR(data->clk))
578 clk_prepare_enable(data->clk);
584 static const struct dev_pm_ops dw8250_pm_ops = {
585 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
586 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
589 static const struct of_device_id dw8250_of_match[] = {
590 { .compatible = "snps,dw-apb-uart" },
591 { .compatible = "cavium,octeon-3860-uart" },
594 MODULE_DEVICE_TABLE(of, dw8250_of_match);
596 static const struct acpi_device_id dw8250_acpi_match[] = {
607 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
609 static struct platform_driver dw8250_platform_driver = {
611 .name = "dw-apb-uart",
612 .pm = &dw8250_pm_ops,
613 .of_match_table = dw8250_of_match,
614 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
616 .probe = dw8250_probe,
617 .remove = dw8250_remove,
620 module_platform_driver(dw8250_platform_driver);
622 MODULE_AUTHOR("Jamie Iles");
623 MODULE_LICENSE("GPL");
624 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
625 MODULE_ALIAS("platform:dw-apb-uart");